JP3965323B2 - Memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory device and a manufacturing method thereof, and more particularly to a memory device having a 蔽層 shielding on the memory cell region.
[0002]
[Prior art]
In the current semiconductor manufacturing technology, the ionization technology is an important technology that is often used in the subsequent processes of semiconductors. For example, an ionization technology is used to perform an etching process, physical vapor deposition (PVD), or the like.
[0003]
However, when performing the ionization process, a large amount of plasma is generated in the reaction chamber of the manufacturing apparatus, and since these plasmas generally have a large amount of charge, the semiconductor device is charged, and the stability and reliability of the semiconductor device are increased. Affect.
[0004]
Taking a memory device as an example, particularly more advanced flash memory (flashRAM) and silicon nitride memory (NROM) form each memory cell of the memory using floating gate technology. As described above, when performing a post process of the memory device, a large amount of charge is generated by the generated large amount of plasma, and these plasma charges further impact the memory cells of the memory device, that is, the plasma charge is Since it is trapped in the memory cell, it affects the programming, writing and reading of the memory device, thereby degrading the stability and reliability of the semiconductor device.
[0005]
[Problems to be solved by the invention]
Here, how to prevent the large amount of plasma generated in the semiconductor post-process from being trapped in the memory cell of the memory device and further improve the stability and reliability of the memory device is a big problem in the current semiconductor process technology. It has become a challenge.
[0006]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a memory device that avoids trapping in a memory cell by shielding plasma charges and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
To achieve the above object, a memory device according to the present invention comprises a memory substrate, an insulating layer, a 蔽層 shielding, a second dielectric layer, a second metal layer. The memory substrate includes a substrate, a memory cell region, a peripheral circuit region, a first dielectric layer, and a first metal layer. The memory cell region and the peripheral circuit region are formed on the substrate. The first dielectric layer is formed in the memory cell region and the peripheral circuit region. The first metal layer is formed on the first dielectric layer. The insulating layer is formed on the first dielectric layer that is not covered by the first metal layer. Shielding 蔽層 it is formed on the insulating layer above the memory cell region. And蔽層 barrier, an insulating layer which is not covered with the 蔽層 shielding, the first metal layer not covered with the shield 蔽層and the insulating layer, the second dielectric layer is formed. The second metal layer is formed on the second dielectric layer.
[0008]
Furthermore, in another embodiment of the present invention, the memory substrate further includes a spacer formed on a side of the first metal layer, an upper side of the first dielectric layer, and the first metal layer. And a barrier layer formed below the spacer .
[0009]
Furthermore, a method of manufacturing the memory device according to the present invention, the preparing step of the memory substrate, the step of depositing the insulating layer, and the deposition step of the shielding 蔽層, the etching process of the insulating layer and shielding 蔽層, second dielectric A layer forming step and a second metal layer forming step.
[0010]
As described above, according to the memory device and a manufacturing method thereof according to the present invention, because it forms a 蔽層 barrier insulating layer above the memory cell area, a large amount generated in step after the semiconductor utilizing shielding 蔽層 Therefore, the stability and reliability of the memory device can be improved by preventing the plasma charge from being trapped by the gate of the memory cell.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a memory device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.
[0012]
Referring to FIG. 1, memory device 1 according to the embodiment of the present invention, the memory substrate 11, an insulating layer 12, a barrier 蔽層 13, a second dielectric layer 14 and the second metal layer 15, a Prepare.
[0013]
In the present embodiment, the memory substrate 11 includes a substrate 111, a memory cell 112, a peripheral circuit region 113, a first dielectric layer 114, and a first metal layer 115. The memory cell region 112 and the peripheral circuit region 113 are formed in the substrate 111, the first dielectric layer 114 is formed in the memory cell region 112 and the peripheral circuit region 113, and the first metal layer 115 is the first dielectric layer. 114 is formed. The memory cell region 112 includes a plurality of memory cells, and these memory cells are electrically connected to a plurality of word lines and a plurality of bit lines, respectively. These word lines and bit lines are constituted by the respective metal layers (first metal layer 115 and second metal layer 15) of the memory device 1. The peripheral circuit region 113 controls access to each memory cell. The first dielectric layer 114 is, for example, an interlayer dielectric (ILD), and a plurality of contact holes 116 are formed in the first dielectric layer 114, so that the first metal layer 115 is connected to the memory cell via the contact holes 116. 112 and the peripheral circuit region 113 are electrically connected to each other to form a necessary circuit design by design.
[0014]
Furthermore, in another embodiment of the present invention, the memory substrate 11 further includes a spacer 117 and a barrier layer 118. As shown in FIG. 2, the spacer 117 is formed on the side of the first metal layer 115, and the barrier layer 118 is formed between the first dielectric layer 114 and the first metal layer 115 and the spacer 117. Note that the barrier layer 118 is made of, for example, titanium nitride or titanium, thereby shielding a large amount of plasma charges generated in a subsequent process of the semiconductor.
[0015]
Referring back to FIG. 1, the insulating layer 12 is formed on the first dielectric layer 114 that is formed on the memory substrate 11 and is not covered by the first metal layer 115.
[0016]
Shielding 蔽層 13 is formed in the memory cell region 112 above the insulating layer 12. In the present embodiment, shielding 蔽層 is for example silicon nitride, titanium nitride, or consists of titanium.
[0017]
As shown in FIG. 1, shielding 蔽層 13, the first metal layer 115 not covered with the shield 蔽層 13 not covered with the insulating layer 12, and barrier 蔽層 13 and the insulating layer 12, second dielectric layer 14 is formed. In the present embodiment, the second dielectric layer 14 is a metal wiring interlayer insulating film (IMD).
[0018]
Finally, the second metal layer 15 is formed on the second dielectric layer 14. The second metal layer 15 is electrically connected to the first metal layer 115 through a plurality of contact holes 141 formed in the second dielectric layer 14, thereby forming a necessary circuit design by design. To do.
[0019]
In order to understand the contents of the present invention in more detail, the steps of the method for manufacturing the memory device according to the embodiment of the present invention will be described below with reference to examples.
[0020]
Referring to FIGS. 3A to 3C, a method of manufacturing a memory device according to an embodiment of the present invention includes the following steps.
[0021]
First, as shown in FIG. 3A, a memory substrate 11 is prepared. The memory cell 11 includes, for example, a spacer 117 and a barrier layer 118 (shown in FIG. 2), thereby enhancing the ability of the memory device 1 to shield plasma charges.
[0022]
Next, the insulating layer 12 is deposited on the first metal layer 115 and the first dielectric layer 114 (shown in FIG. 3A) that is not covered by the first metal layer 115. In the present embodiment, the insulating layer 12 is formed using , for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD).
[0023]
Then, depositing a 蔽層 13 barrier insulating layer 12 (shown in FIG. 3A). Incidentally, shielding 蔽層 13 is formed, for example, using a physical vapor deposition or chemical vapor deposition.
[0024]
Referring to Figure 3B, by etching the 蔽層 13 barrier and the insulating layer 12, 蔽層 13 barrier and the insulating layer 12 on the first metal layer 115, and the peripheral circuit region 113 above the insulating layer 12 and the蔽層 13 Remove. In the present embodiment, since etching a 蔽層 13 barrier and the insulating layer 12 by dry etching process, after the dry etching process, on both sides of the first metal layer 115 spacer 131 is formed. Further, the dry etching process described above, a sub-step of forming a photoresist layer 16 having a specific pattern in 蔽層 13 barrier before performing the dry etching (FIG. 3B), photoresist after dry etching A sub-step of peeling the layer 16 is included.
[0025]
Next, as shown in FIG. 3C, shielding 蔽層and 13, shielding the insulating layer 12 not covered with the 蔽層 13, to cover the first metal layer 115 not covered with the shield 蔽層 13 and the insulating layer 12 Next, the second dielectric layer 14 is formed. Here, after the second dielectric layer 14 is formed, a plurality of contact holes 141 for conducting the first metal layer 115 are formed in the second dielectric layer 14.
[0026]
Finally, the second metal layer 15 is formed on the second dielectric layer 14. As described above, control signals can be input to the memory cells in the memory cell region 112 from the first metal layer 115 and the second metal layer 15 through the contact hole 141 and the contact hole 116, respectively. Control memory cell access. Furthermore, control signals can be input to the peripheral circuit region 113 from the first metal layer 115 and the second metal layer 15 through the contact hole 141 and the contact hole 116, respectively, and the circuit in the peripheral circuit region 113 is operated, for example, logic Perform analysis.
[0027]
Further, the material of 蔽層 13 barrier and the barrier layer 118, with silicon nitride described in this embodiment, titanium nitride is not limited only to such as titanium, can be applied to semiconductor manufacturing processes, and the function of blocking the plasma charge Any metallic or non-metallic material.
[0028]
【The invention's effect】
Above, a memory device and a manufacturing method thereof according to an embodiment of the present invention, because it forms a 蔽層 barrier above the insulating layer of the memory cell area, a large amount generated in step after the semiconductor utilizing shielding 蔽層 Therefore, the stability and reliability of the memory device can be improved by preventing the plasma charge from being trapped by the gate of the memory cell.
[0029]
The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. However, it is included in the present invention.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a memory device according to an embodiment of the present invention.
FIG. 2 is a schematic diagram showing a memory substrate of the memory device shown in FIG. 1;
FIGS. 3A to 3B are schematic views showing a method for manufacturing a memory device according to an embodiment of the present invention. FIGS.
[Explanation of symbols]
1 memory device 11 memory board 111 substrate 112 memory cell region 113 peripheral region 114 first dielectric layer 115 first metal layer 116 a contact hole 117 spacer 118 barrier layer 12 insulating layer 13 barrier 蔽層 131 spacer 14 second dielectric layer 141 Contact hole 15 Second metal layer 16 Photoresist layer

Claims (21)

A substrate, a memory cell region, a peripheral circuit region, a first dielectric layer, and a first metal layer, wherein the memory cell and the peripheral circuit region are formed on the substrate, and the first dielectric layer Is formed in the memory cell and the peripheral circuit region, the first metal layer is formed in the first dielectric layer, a plurality of contact holes are formed in the first dielectric layer, and the first metal layer is formed Preparing a memory substrate electrically connected to each of the memory cell and the peripheral circuit region through the plurality of contact holes ;
Depositing an insulating layer on the first metal layer and the first dielectric layer not covered by the first metal layer;
Depositing a plasma charge shielding layer on the insulating layer ;
Wherein by etching the plasma charge blocking layer and the insulating layer, the plasma charge blocking layer and the insulating layer of the first metal layer above, and removing the plasma charge blocking layer and the insulating layer of the peripheral circuit region above Process,
And the plasma charge blocking layer above said insulating layer above which is not covered with the plasma charge blocking layer, the said plasma charge blocking layer and said not covered with the insulating layer the first metal layer above the second dielectric Forming a body layer;
A second metal layer is formed on the second dielectric layer, a plurality of contact holes are formed in the second dielectric layer , and the second metal layer is formed in the second dielectric layer. Electrically connecting to each of the first metal layers via contact holes ;
A method for manufacturing a memory device, comprising:   The method according to claim 1, wherein the first dielectric layer is an interlayer insulating film.   2. The method of manufacturing a memory device according to claim 1, wherein the second dielectric layer is a metal wiring interlayer insulating film. 2. The method of manufacturing a memory device according to claim 1, wherein the method of etching the insulating layer and the plasma charge shielding layer is dry etching. The method of manufacturing a memory device according to claim 1, wherein the plasma charge shielding layer is made of silicon nitride. The method of manufacturing a memory device according to claim 1, wherein the plasma charge shielding layer is made of titanium nitride. The method of manufacturing a memory device according to claim 1, wherein the plasma charge shielding layer is made of titanium. The method of manufacturing a memory device according to claim 1, wherein the step of preparing the memory substrate further includes a step of forming a spacer on a side of the first metal layer. The step of preparing the memory substrate, the memory of claim 8, further comprising the step of barrier layer is formed between the first said dielectric layer a first metal layer and the spacer Device manufacturing method. The method of manufacturing a memory device according to claim 9 , wherein the barrier layer is made of titanium nitride. The method of manufacturing a memory device according to claim 9 , wherein the barrier layer is made of titanium. A substrate, a memory cell region, a peripheral circuit region, a first dielectric layer, and a first metal layer, wherein the memory cell region and the peripheral circuit region are formed on the substrate; A memory substrate in which a layer is formed in the memory cell region and the peripheral circuit region, and the first metal layer is formed on the first dielectric layer ;
An insulating layer formed on the first dielectric layer not covered by the first metal layer;
A plasma charge shielding layer formed on the insulating layer above the memory cell region;
And the plasma charge blocking layer above the plasma charge and shielding layer not covered with the insulating layer above the plasma charge blocking layer and the second formed in said first metal layer on which is not covered with the insulating layer A dielectric layer;
A second metal layer formed on the second dielectric layer ,
The memory substrate includes a plurality of contact holes formed in the first dielectric layer, and the first metal layer is electrically connected to the memory cell region and the peripheral circuit region through the plurality of contact holes,
Wherein the second dielectric layer a plurality of contact holes are formed, the memory device the second metal layer is characterized that you have been respectively electrically connected to the first metal layer via a plurality of contact holes . The memory device of claim 12 , wherein the first dielectric layer is an interlayer insulating film. 13. The memory device according to claim 12 , wherein the second dielectric layer is a metal wiring interlayer insulating film. The memory device of claim 12 , wherein the plasma charge shielding layer is made of silicon nitride. The memory device according to claim 12 , wherein the plasma charge shielding layer is made of titanium nitride. The memory device according to claim 12 , wherein the plasma charge shielding layer is made of titanium. The memory board is a memory device according to claim 12, further comprising a space Sa formed on the sides of the first metal layer. The memory device of claim 18 , wherein the memory substrate further includes a barrier layer between the first dielectric layer , the first metal layer, and the spacer. The method of manufacturing a memory device according to claim 19 , wherein the barrier layer is made of titanium nitride. 20. The method of manufacturing a memory device according to claim 19 , wherein the barrier layer is made of titanium.

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