JP3963177B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device that generates a reference voltage.

  Conventionally, as this type of semiconductor device, for example, there is a semiconductor device described in Patent Document 1. Hereinafter, the configuration and operation of this apparatus will be briefly described with reference to FIG. FIG. 17 is a circuit diagram showing a circuit configuration of this semiconductor device.

  As shown in FIG. 17, this circuit is a reference voltage generation circuit called a band gap reference circuit, and mainly includes an output unit P1, a voltage compensation unit P2, and a current mirror unit. CM.

  Among these, the output part P1 includes an output NPN transistor Tr1 and voltage dividing resistors R1 and R2. Here, the current supplied from the power supply terminal TE1 connected to the power supply flows into the ground through the transistor Tr1 and the voltage dividing resistors R1 and R2. The power supply voltage (power supply potential) of the power supply terminal TE1 is divided by the resistance between the emitter and collector of the transistor Tr1 and the voltage dividing resistors R1 and R2, and the potential is output to the output terminal TE2.

The voltage compensation unit P2 includes a transformer (constant current source) TS, a PNP transistor Tr2 and a diode DI for voltage control, NPN transistors Tr3 and Tr4, and resistors R3 and R4. Here, a current having a constant current _Io is supplied from the power supply terminal TE1 to the emitter of the transistor Tr2 and the base of the transistor Tr1 through the transformer TS. For this reason, the output potential of the output terminal TE2 corresponds to the emitter current of the transistor Tr2. The resistance value of the resistor R3 is set so that the emitter currents of the transistors Tr3 and Tr4 are equal. The area ratio of the emitter size of the transistor Tr4 to the emitter size of the transistor Tr3 is set to N (natural number) times.

  On the other hand, the current mirror unit CM is configured to include transistors Tr2a to Tr4a. And these transistors Tr2a-Tr4a are arrange | positioned in the aspect which negates the thermal voltage of the said transistors Tr2-Tr4, and suppresses the voltage fluctuation accompanying a temperature change.

  In such a circuit, for example, when the output potential of the output terminal TE2 decreases or increases, the potential of the contact PC located between the voltage dividing resistor R1 and the voltage dividing resistor R2 also decreases or increases. Along with this, the collector current of the transistor Tr3 and the emitter current of the transistor Tr2 decrease or increase, and the emitter current of the transistor Tr1 increases or decreases. Eventually, the output potential at the output terminal TE2 rises or falls to return to the original potential, and the output potential at the output terminal TE2 is kept constant.

Further, the resistance value of the resistor R3 is Re3, the resistance value of the resistor R4 is Re4, the Boltzmann constant is k, the absolute temperature is T, the charge amount is q, the area ratio of the emitter size of the transistor Tr4 to the transistor Tr3 is Nr, and the transistor Tr3 When the base-emitter voltage is indicated as V _BE 3, the potential V _{BG of the} contact PC is
V _BG = 2 (Re4 / Re3) × (kT / q) lnNr + V _BE 3
It can be expressed as.

Here, V _BE 3 has a negative temperature coefficient. For this reason, by selecting appropriate values as the values of Re3, Re4, and Nr, the temperature characteristic of the potential output to the output terminal TE2 can be made constant, and as a result, a reference voltage having good temperature characteristics can be obtained. It becomes possible to output.
JP 7-325637 A

  Thus, according to the semiconductor device, it is possible to output a reference voltage having a good temperature characteristic. However, in such a semiconductor device, an increase in circuit scale and an increase in power consumption are inevitable. Specifically, in the output unit P1 of this semiconductor device, as shown in FIG. 17, the power supply voltage (power supply potential) of the power supply terminal TE1 is divided by resistors R1 and R2, and this is divided into the output terminal TE2. Output potential (reference voltage). However, with only such a circuit (output unit P1), it is difficult to obtain a stable reference voltage against fluctuations in power supply voltage and changes in temperature environment. Therefore, in the conventional semiconductor device, in order to generate a reference voltage with good temperature characteristics, the voltage compensation unit P2 and the current mirror unit CM, or a circuit corresponding to these circuits, is indispensable. An increase in circuit scale and an increase in power consumption are inevitable.

  In general, in a semiconductor device that generates such a reference voltage, not only the temperature characteristics of the reference voltage but also noise wrapping affects the performance. Therefore, it is necessary to stabilize the temperature characteristics of the reference voltage, which is a particularly important parameter for the semiconductor device, in consideration of these requirements. In order to satisfy such a requirement in the conventional semiconductor device, the voltage compensation unit P2 and the current mirror unit CM must be arranged on the chip in a well-balanced manner, and the degree of design freedom regarding the element arrangement on the chip is greatly limited. Will be. Such a restriction on the degree of freedom of design becomes particularly noticeable in a mixed circuit with a heat source element such as a power element or a circuit that requires high-speed operation.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device capable of generating a reference voltage having stable temperature characteristics even with a simple circuit configuration.

  In order to achieve these objects, in the semiconductor device according to claim 1, at least one diode is formed in each of the two semiconductor regions separated by the trench, and the cathode of the diode formed in each of the semiconductor regions. The terminals or anode terminals are electrically connected in series, and the anode terminal or cathode terminal at the other end of the diodes connected in series are at different potentials, so that they are connected in series. The reference voltage is generated in such a manner that the forward voltage and breakdown voltage of the diode are included.

Diodes respectively formed in two adjacent semiconductor regions separated by the trench have a so-called pair property. That is, these diodes can be formed under substantially the same manufacturing conditions, and the environment in use including the temperature environment can be made uniform. If the cathode terminals or the anode terminals of the diodes having such a pair property are connected in series, the diodes cancel out the temperature characteristics of the forward voltage and the breakdown voltage (reverse voltage). Will fit. Therefore, by generating a reference voltage that includes at least the forward voltage and breakdown voltage of the diodes, a reference voltage having excellent temperature characteristics can be obtained. Thus, according to the above structure as a semiconductor device, a reference voltage having stable temperature characteristics can be generated even with a simple circuit configuration.
Further, in the semiconductor device according to claim 1, a plurality of diodes electrically connected in parallel via a plurality of trimmable wirings are formed in one of the two semiconductor regions, and in parallel therewith. A connected diode is electrically connected in series with a diode formed on the other side of the semiconductor region.
In the semiconductor device having such a structure, the temperature characteristics of the forward voltage and breakdown voltage of the diodes electrically connected in series (particularly the temperature characteristics of the breakdown voltage) are electrically connected in parallel. It correlates with the pn junction area formed in each of the plurality of diodes. The temperature characteristic of the reference voltage output from the semiconductor device correlates with the sum of the pn junction areas formed in each of the plurality of diodes electrically connected in parallel. Therefore, according to the above structure, since these diodes are electrically connected in parallel via a plurality of trimmable wirings, the trimming wirings are selectively trimmed to correlate with the temperature characteristics. The total pn junction area can be adjusted to a desired value. That is, according to the structure as a semiconductor device, the reference voltage output from the semiconductor device and its temperature characteristics can be easily adjusted.

  In the semiconductor device according to claim 2, the two semiconductor regions each have a diffusion layer having an increased impurity concentration on a sidewall of the trench, and the electrically connected diodes are A structure in which the cathode terminals or the anode terminals are connected to each other through a wiring forming a contact in the diffusion layer.

  In such a structure, the diffusion layer can be easily formed by introducing impurities into the side walls of the trench using the mask used when forming the trench separating the two semiconductor regions as it is. it can. For this reason, according to the said structure, manufacture of the said semiconductor device can be made easier now.

  Further, in this case, as the wiring for forming the contact in the diffusion layer, as described in claim 3, the wiring is buried in the trench in a manner of short-circuiting the diffusion layer formed in each of the two semiconductor regions. It is particularly effective to use a conductive film. By doing so, the diffusion layer is short-circuited by the conductor film embedded in the trench. As a result, the diodes formed in each of the semiconductor regions are electrically connected in series by wiring having a simple structure, and as a result, the structure of the semiconductor device itself can be simplified. Incidentally, as the trench in which the conductor film is embedded, either a trench separating the two semiconductor regions or a trench formed for the wiring may be used.

  Further, in the invention according to any one of claims 1 to 3, as described in claim 4, the two semiconductor regions are surrounded by an insulating layer and other than those regions. It is particularly effective to have a structure that is electrically insulated from the region.

  By adopting such a structure, noise to the two semiconductor regions, that is, the regions where the diodes connected in series are formed is cut, and the noise resistance of the semiconductor device is also improved. Become. Further, according to such a structure, a parasitic diode which is formed when the pn junction is separated is not formed, so that it is possible to increase the resistance against a leakage current as a semiconductor device. become.

  In this case, as described in claim 5, it is effective that the two semiconductor regions have a structure in which the other regions are electrically isolated from each other by trench isolation on an SOI substrate.

  Generally, an SOI substrate and trench isolation are used in a semiconductor process. For this reason, it becomes possible to implement | achieve the structure of Claim 4 more easily and suitably by setting it as such a structure.

  Further, in the semiconductor device according to claim 6, in the invention according to any one of claims 1 to 5, one diode is formed in each of the two semiconductor regions, and each of the semiconductor regions is provided. The diodes formed one by one are formed in such a manner that the impurity concentration of at least two semiconductor layers of P-type and N-type constituting the diode and the area of the pn junction formed by these semiconductor layers are the same. The structure is as follows.

  When one diode is formed in each of the two semiconductor regions as the diodes connected in series, the temperature characteristics of the forward voltage and the breakdown voltage of these diodes can be obtained by aligning the structures of the diodes. Will preferably cancel each other out. Among the parameters as the structure of the diode, parameters that particularly affect the temperature characteristics of the forward voltage and the breakdown voltage have two semiconductor layers (P-type semiconductor layer and N-type) constituting the diode. The impurity concentration of the semiconductor layer) and the area of the pn junction formed by these semiconductor layers. That is, the above structure is particularly effective in improving the temperature characteristics of the reference voltage output from the semiconductor device.

  Further, in the semiconductor device according to claim 7, in the invention according to any one of claims 1 to 6, one diode is formed in each of the two semiconductor regions, and each of these semiconductor regions The reverse breakdown voltage of the diodes formed one by one is set to “5V”.

  With this structure, the diodes connected in series cancel out the temperature characteristics of the forward voltage and the breakdown voltage almost completely, and as a result, the reference voltage output from the semiconductor device is reduced. The temperature characteristic can be optimized.

In this case, as described in claim 8, each of the two diodes having a reverse breakdown voltage of 5 V includes an N-type semiconductor layer having an impurity concentration of “5.8 × 10 ¹⁸ cm ⁻³ ” or more; It is effective to have a structure constituted by a P-type semiconductor layer having an impurity concentration higher than that of the N-type semiconductor layer.

By adopting such a structure, the functions as the two diodes having the reverse withstand voltage of 5 V are properly maintained. However, when the impurity concentration of the N-type semiconductor layer is increased, the leakage current resistance is decreased. Therefore, it is preferable that the impurity concentration of the N-type semiconductor layer is set in a range in which desired leakage current resistance is ensured while taking this into consideration. For example, if setting the impurity concentration of the semiconductor layer made of the N-type to the "8.1 × 10 ¹⁸ cm ^-3", a high specification of requirements in the market, "1.0 × 10 ^-6 A The leakage current can be suppressed below. Further, it is desirable that the impurity concentration of the P-type semiconductor layer is set high enough to form wiring and ohmic contact.

In the invention according to any one of claims 1 to 8, as described in claim 9 , each of the plurality of trimmable wirings may have a structure including a trimming resistor. It is particularly effective.
With such a structure, the trimming can be performed more easily and appropriately, and as a result, the reference voltage output from the semiconductor device and its temperature characteristics can be adjusted more easily. Become.

Further in this case, as the material of the trimmable resistor, as claimed in claim 1 0, it is particularly effective to use a CrSiN.
CrSiN is a material having excellent temperature characteristics. Therefore, with the above structure, deterioration of the temperature characteristics of the reference voltage, which is a concern due to the provision of the resistor, is suppressed.

Further, as described in claim 1 1, in the invention described in any one of the preceding claims 1 to 1 0, a plurality of diodes connected in the parallel each semiconductor of a first conductivity type And a plurality of semiconductor layers of the second conductivity type formed on the surface of the semiconductor layer of the first conductivity type so as to be electrically isolated from each other by the insulating layer for element isolation. In this case, it is particularly effective to have a structure in which the element isolation insulating layer is formed deeper than the semiconductor layer of the second conductivity type.

  According to such a structure, each pn junction formed by the two types of semiconductor layers that respectively constitute the plurality of diodes connected in parallel is formed at a position shallower than the element isolation insulating layer. become. The semiconductor layer of the second conductivity type is formed in such a manner that the periphery of the semiconductor layer of the first conductivity type is surrounded by an insulating layer for element isolation. For this reason, the area of each pn junction formed by the diodes connected in parallel is the area of each region surrounded by the element isolation insulating layer, that is, the size of each semiconductor layer (substrate) of the second conductivity type. (Cross-sectional area in the horizontal direction). This makes it possible to easily obtain the desired pn junction area by setting the size of the semiconductor layer of the second conductivity type to an appropriate value at the design stage. The temperature characteristics can be adjusted more suitably.

Also in this case, as the insulating layer for the element isolation, as described in claim 1 2, it is possible to use an insulating film to take S TI structure.

Generally, the insulating film take S TI structure was Hiroshi is intended to be used for inter-element isolation (isolation) in a semiconductor process, it is also well known a method of forming the same. Therefore, when realizing the structure according to claim 1 1, it is particularly effective as such a structure.

In the semiconductor device according to claim 1 3, in the above-described invention according to any one of claims 1 to 1 2, which is connected to a plurality of diodes and the diodes in series connected in the parallel the The diode has a reverse breakdown voltage set to “5V”.

  With such a structure, the electrically connected diodes preferably cancel each other out of the temperature characteristics of the forward voltage and the breakdown voltage, and as a result, the reference output from the semiconductor device. The temperature characteristic of the voltage can be optimized.

Also in this case, as described in claim 1 4, wherein the plurality connected in parallel diodes and the diodes connected in series with said diode are each impurity concentration "5.8 × 10 ¹⁸ cm ^-3 It is particularly effective to have a structure constituted by the above-described semiconductor layer made of N-type and a semiconductor layer made of P-type having a higher impurity concentration than the semiconductor layer made of N-type.

  By adopting such a structure, the functions as the two diodes having the reverse withstand voltage of 5 V are properly maintained. Also in this case, it is preferable that the impurity concentration of the N-type semiconductor layer is set within a range in which desired leakage current resistance is ensured. Also, it is desirable that the impurity concentration of the P-type semiconductor layer be set high enough to form wiring and ohmic contact.

(First embodiment)
1 to 7 show a first embodiment of a semiconductor device according to the present invention.
The semiconductor device according to this embodiment is also a reference voltage generation circuit that outputs a reference voltage, like the semiconductor device illustrated in FIG. However, in the semiconductor device of this embodiment, the structure shown in FIGS. 1 and 2 is used to generate a reference voltage having a stable temperature characteristic with a simple circuit configuration.

The structure of the semiconductor device according to this embodiment will be described in detail below with reference to FIGS.
First, the circuit configuration of this semiconductor device will be described with reference to FIG. In FIG. 1, the same elements as those shown in FIG. 17 are denoted by the same reference numerals, and redundant description of these elements is omitted.

As shown in FIG. 1, in this circuit, a constant current _{Io of} , for example, “100 μA to 1 mA” from the power supply terminal TE1 through the transformer TS is converted into a diode TD11 connected in series between the cathode terminals and It flows into the ground via TD12. An output terminal TE2 is provided on the upstream side of the diodes TD11 and TD12. A reference voltage is output to the output terminal TE2 as the sum of the forward voltage and breakdown voltage (reverse voltage) of the diodes TD11 and TD12. Incidentally, the diode TD12 functions as a so-called Zener diode.

  Next, the structure of this semiconductor device will be described with reference to FIG. 2A is a plan view of the semiconductor device, and FIG. 2B is a cross-sectional view taken along line BB in FIG. 2A. Incidentally, FIGS. 2A and 2B correspond to a plan view and a cross-sectional view of a region P10 indicated by a one-dot chain line in FIG.

As shown in FIGS. 2A and 2B, this semiconductor device is roughly composed of a semiconductor substrate 11 made of, for example, silicon, an insulating layer 12 made of, for example, silicon oxide, and made of, for example, N-type silicon. The semiconductor layer 13 is laminated in order. Here, the semiconductor substrate 11, the insulating layer 12, and the semiconductor layer 13 are formed as an SOI (Silicon On Insulator) substrate. The impurity concentration (surface concentration) of the semiconductor layer 13 is set to “5.8 × 10 ¹⁸ cm ^{−3 to} 8.1 × 10 ¹⁸ cm ⁻³ ”. Further, the thickness of the semiconductor layer 13 is, for example, “10 μm to 16 μm”.

  Then, the semiconductor layer 13 is partitioned in a form surrounded by the field oxide film I13 having the LOCOS structure and the trench T1, and two adjacent semiconductor regions SA11 and SA12 separated by the trench T1 are formed. Yes. The trench T1 includes an insulating film 13a made of, for example, silicon oxide formed on the inner wall of the trench T1 and a dielectric film 13b made of, for example, polycrystalline silicon formed inside the insulating film 13a. Buried. The semiconductor regions SA11 and SA12 are completely surrounded by the trench T1 and the insulating layer 12, and are electrically isolated from other regions other than these regions. Incidentally, LOCOS here is an abbreviation for “LOCal Oxidation of Silicon”.

  Further, impurities of higher concentration than the semiconductor layer 13 are introduced into the surfaces of the semiconductor regions SA11 and SA12 to form P-type semiconductor layers D11b and D12b. Then, N-type semiconductor layers D11a and D12a having a higher concentration than the semiconductor layer 13 are formed so as to surround the semiconductor layers D11b and D12b, respectively. The semiconductor layers D11a and D12a and the semiconductor layers D11b and D12b are electrically separated by field oxide films I11 and I12 having a LOCOS structure, respectively.

Here, pn junctions are formed between the N-type semiconductor layer 13 and the P-type semiconductor layers D11b and D12b, respectively. As a result, diodes TD11 and TD12 are formed in the semiconductor regions SA11 and SA12, respectively. The impurity concentrations of the semiconductor layers D11a and D12a and the semiconductor layers D11b and D12b are, for example, “1.0 × 10 ²⁰ cm ⁻³ ” or more in order to form ohmic contacts with wirings connected to these semiconductor layers. Concentration.

  The semiconductor regions SA11 and SA12 have a line-symmetric relationship with a line perpendicular to the line BB in FIG. That is, the diodes TD11 and TD12 are formed as diodes having a reverse breakdown voltage of “5V” by making the impurity concentrations of the semiconductor layers D11b and D12b and the areas of the pn junctions formed by these semiconductor layers and the semiconductor layer 13 equal. Is formed.

  Further, an insulating film 14 is formed on the semiconductor layer 13, and the insulating film 14 is appropriately patterned to form contact holes, and a wiring material is formed so as to fill the contact holes. And wiring M11-M13 is formed by patterning this wiring material suitably. Among these, the wiring M11 is a power supply wiring connected to the power supply terminal TE1 (FIG. 1), and forms a contact with the semiconductor layer D11b corresponding to the anode terminal of the diode TD11. The wiring M12 is a ground wiring connected to the ground (FIG. 1), and forms a contact with the semiconductor layer D12b corresponding to the anode terminal of the diode TD12. The wiring M13 is a wiring for connecting the diode TD11 and the diode TD12 in series, and forms a contact with both the semiconductor layers D11a and D12a corresponding to the cathode terminals of these diodes. In the semiconductor device according to this embodiment, by applying a voltage to the diodes TD11 and TD12 through the wirings M11 to M13, the forward voltage and the break of the diodes TD11 and TD12 connected in series are broken. The reference voltage is generated as the sum total with the down voltage.

  Next, with reference to FIGS. 3 to 5, the temperature characteristic of the reference voltage output by the semiconductor device according to this embodiment will be described. Each of these figures is a graph showing various characteristics measured using a semiconductor device having a basic structure substantially similar to that of the semiconductor device according to this embodiment as a sample. Here, also about each semiconductor device used as these samples, the element corresponding to the element shown in previous FIG. 2 is attached | subjected and demonstrated in the code | symbol in FIG.

First, in FIG. 3, for each of the semiconductor devices used as with Sample, the diode TD11 (TD12 and also if the same) voltage V _Z which is applied in the opposite direction to and the reverse current I _Z flowing at that time The relationship is shown as a graph. In FIG. 3, FIG. 3A corresponds to a graph in which the region A indicated by the alternate long and short dash line in FIG. 3B is enlarged.

  As shown in FIG. 3, the reverse breakdown voltage cannot be clearly confirmed for the samples indicated by the characteristic line L1 and the characteristic line L2. On the other hand, the samples indicated by the characteristic lines L3 to L8 have reverse breakdown voltages of about “5V”, “6V”, “8V”, “8.5V”, “17V”, and “22.5V”, respectively. It can be read from this graph that it has.

  4 (a) and 4 (b) show the forward voltage and breakdown voltage (reverse voltage) of the diodes TD11 and TD12 and the temperature characteristics of the reference voltage output as the sum of these voltages. The measurement results are shown as a graph. Here, only the measurement results for the samples on the characteristic lines L3 and L5 in FIG. 3 are shown as representatives. In these figures, characteristic lines L32 and L52, characteristic lines L31 and L51, characteristic lines L30 and L50 are the forward voltage of diode TD11, the breakdown voltage (reverse voltage) of diode TD12, and the sum of these voltages. The temperature characteristics of the output reference voltage are shown.

  As a result of measuring the above samples by the inventors, the temperature characteristic of the reference voltage output as the sum of the forward voltage and breakdown voltage of the diodes TD11 and TD12 becomes constant. It was only the sample concerning the characteristic line L3 in the inside, that is, the semiconductor device provided with the diodes TD11 and TD12 having the reverse breakdown voltage “5V”.

FIG. 4A shows the temperature characteristics of this semiconductor device (the sample according to the characteristic line L3 in FIG. 3). As shown in FIG. 4A, in this semiconductor device, the temperature characteristic of the forward voltage (V _f ) of the diode TD11 indicated by the characteristic line L32 has a negative slope, whereas the characteristic line L31. The temperature characteristic of the breakdown voltage (V _Z ) of the diode TD12 indicated by ## EQU2 ## has a positive slope. The temperature characteristic of the reference voltage (V _Z + V _f ) output as the sum of these voltages is constant (temperature coefficient is substantially zero) because both of these temperature characteristics cancel each other out almost completely.

  On the other hand, in the other samples, the diodes TD11 and TD12 cancel the temperature characteristics of the forward voltage and the breakdown voltage to improve the temperature characteristics of the reference voltage, but the temperature characteristics of the reference voltage are constant (temperature The temperature characteristic with a coefficient of approximately zero) was not achieved.

For example, FIG. 4B shows the measurement results for the sample according to the characteristic line L5 in FIG. As shown in FIG. 4B, the temperature characteristic of the reference voltage (V _Z + V _f ) (see the characteristic line L50) is improved over the temperature characteristic of the breakdown voltage (V _Z ) (see the characteristic line L51). Although it has been done, it is still not constant with a positive slope.

  Here, in the semiconductor device according to this embodiment, the reverse breakdown voltages of the diodes TD11 and TD12 are each set to “5V”. By doing so, as is clear from the graph shown in FIG. 4A, the diodes TD11 and TD12 almost completely cancel out the temperature characteristics of the forward voltage and the breakdown voltage. As a result, the temperature characteristics of the reference voltage output from the semiconductor device can be made substantially constant.

Next, in FIGS. 5A and 5B, for two types of semiconductor devices as samples, the impurity concentration (surface concentration) of the semiconductor layer 13 and the reverse breakdown voltage of the diode TD11 (same as TD12), In addition, the relationship between the impurity concentration (surface concentration) of the semiconductor layer 13 and the leakage current of the semiconductor device is shown as a graph. In these figures, the data indicated by A11 and B11 are obtained from the P-type semiconductor layer D11b (D12b) having an impurity concentration of “2.0 × 10 ²⁰ cm ⁻³ ” and the N-type having a lower concentration than this. This is data relating to the semiconductor device in which the diode TD11 (TD12) is constituted by the semiconductor layer (thin side semiconductor layer) 13 to be formed. On the other hand, the data indicated by A12 and B12 in the figure are the measurement results of a sample having a structure substantially similar to the structure in which the conductivity type of each semiconductor layer is replaced in the semiconductor device according to this embodiment. Is shown. More specifically, an N-type semiconductor layer D11b (D12b) having an impurity concentration of “2.0 × 10 ²⁰ cm ⁻³ ” and a P-type semiconductor layer (thin side semiconductor layer) 13 having a lower concentration than this are used. Data relating to the semiconductor device in which the diode TD11 (TD12) is configured. FIG. 5A shows the measurement result when the constant current supplied to the diode TD11 (TD12) is “1 mA”. On the other hand, FIG. 5B shows the measurement result when the voltage applied to the diode TD11 (TD12) is “(Reverse breakdown voltage of the diode) −1V”.

Here, of the two types of semiconductor devices (samples), a semiconductor device in which the semiconductor layer 13 is N-type will be mainly described.
As can be seen from the data indicated by A11 in FIG. 5A, in the semiconductor device in which the semiconductor layer 13 is an N-type, when the impurity concentration of the semiconductor layer 13 is increased, this is accompanied by this. the reverse breakdown voltage Te (V _Z) is saturated in the place that became to continue to decline "5V". At this time, the saturation point is when the impurity concentration of the semiconductor layer 13 becomes “5.8 × 10 ¹⁸ cm ⁻³ ”.

Here, in the semiconductor device according to this embodiment, the impurity concentration of the semiconductor layer 13 is set to “5.8 × 10 ¹⁸ cm ⁻³ ” or more. As a result, as is clear from the graph shown in FIG. 5A, the reverse breakdown voltage of the diodes TD11 and TD12 is set to “5V”, so that the functions of the diodes TD11 and TD12 are properly maintained. Will come to be.

On the other hand, when the impurity concentration of the semiconductor layer 13 is increased, the leakage current resistance decreases conversely as seen in the data indicated by B11 in FIG. 5B. For this reason, it is preferable that the impurity concentration of the semiconductor layer 13 is set in a range in which desired leakage current resistance is ensured while taking this into consideration. In this respect, in the semiconductor device according to this embodiment, the impurity concentration (surface concentration) of the semiconductor layer 13 is set to “5.8 × 10 ¹⁸ cm ^{−3 to} 8.1 × 10 ¹⁸ cm ⁻³ ”. ing. As a result, the leakage current can be suppressed to “1.0 × 10 ⁻⁶ A” or less, which is a highly demanded specification in the market, as is apparent from the graph shown in FIG. become.

  Incidentally, such a tendency is seen in the data indicated by A12 and B12 in FIGS. 5A and 5B, among the two types of semiconductor devices (samples), the semiconductor layer 13 is P. The semiconductor devices made up of molds are also generally common.

Next, with reference to FIGS. 6 and 7, a method for manufacturing the semiconductor device according to this embodiment will be described in detail. Each of these figures is a cross-sectional view showing the manufacturing process of this semiconductor device.
In this manufacturing, first, as shown in FIG. 6A, an SOI substrate in which an insulating layer 12 and a semiconductor layer 13 are sequentially formed on the semiconductor substrate 11 is prepared, and a film thickness of, for example, “1 μm” is prepared thereon. A resist RE1 made of NSG (Non Dope Silicate Glass) of “˜2 μm” is applied.

  Next, as shown in FIG. 6B, necessary patterning is performed on the resist RE1 by, for example, photolithography, and the semiconductor layer 13 is selectively etched by, for example, RIE using the patterned resist RE1 as a mask. This is removed to form a trench T1.

  Then, after removing the resist RE1, for example, an appropriate heat treatment is performed to oxidize the side wall of the trench T1 so as to obtain the structure shown in FIG. 6C, thereby forming the insulating film 13a. Subsequently, the dielectric film 13b is formed so as to completely fill the trench T1, and then subjected to an appropriate flattening process, whereby the structure shown in FIG. 6C is obtained.

Then, as shown in FIG. 7A, the impurity concentration of the semiconductor layer 13 is adjusted by ion implantation of N-type impurities such as phosphorus into the semiconductor layer 13, for example. Thereafter, an appropriate heat treatment is performed. Thereby, the impurity concentration (surface concentration) of the semiconductor layer 13 is set to “5.8 × 10 ¹⁸ cm ^{−3 to} 8.1 × 10 ¹⁸ cm ⁻³ ”.

  Next, as shown in FIG. 7B, field oxide films I11 to I13 having the LOCOS structure are formed by a known selective oxidation method, for example, in the manner shown in FIG. That is, a silicon oxide film (pad oxide film) and a silicon nitride film are sequentially formed, and the silicon nitride film is selectively removed by, for example, photolithography to form an opening at a desired location. Then, only the openings not covered with the silicon nitride film are locally thermally oxidized to form the field oxide films I11 to I13, and the formed silicon oxide film (pad oxide film) and silicon nitride film are formed. Remove.

  Thereafter, ion implantation of P-type impurities such as boron is selectively performed to form the semiconductor layers D11b and D12b, and ion implantation of N-type impurities such as phosphorus is selectively performed to perform the semiconductor layers D11a and D12b. D12a is formed to have a structure as shown in FIG. At this time, the semiconductor layers D11a and D12a, and D11b and D12b are formed in a self-aligned manner using the field oxide films I11 to I13 as a mask.

  Subsequently, an appropriate heat treatment is performed to form a desired diode profile, and the impurity regions are activated. On this, the insulating film 14 and the wirings M11 to M13 are patterned in the manner shown in FIG. 2 to complete the semiconductor device.

  In the semiconductor device according to this embodiment, the diodes TD11 and TD12 are formed in two adjacent semiconductor regions SA11 and SA12 separated by the trench T1, respectively. Therefore, the diodes TD11 and TD12 have a so-called pair property. It becomes like this. That is, the diodes TD11 and TD12 can be formed under substantially the same manufacturing conditions, and the environment in use including the temperature environment can be made uniform. By connecting the cathode terminals of the diodes TD11 and TD12 in series, the diodes cancel out the temperature characteristics of the forward voltage and the breakdown voltage. For this reason, a reference voltage having excellent temperature characteristics can be obtained by generating a reference voltage that includes the forward voltage and breakdown voltage of the diodes TD11 and TD12. As a result, the semiconductor device according to this embodiment can generate a reference voltage having stable temperature characteristics even with a simple circuit configuration.

As described above, according to the semiconductor device of this embodiment, the following excellent effects can be obtained.
(1) The cathode terminals of the diodes TD11 and TD12 respectively formed in the two semiconductor regions SA11 and SA12 separated by the trench T1 are connected in series via the wiring M13. On the other hand, the anode terminals at the other ends of the diodes TD11 and TD12 connected in series are respectively connected to a wiring (power supply wiring) M11 connected to the power supply terminal and a wiring (ground wiring) M12 connected to the ground. . Then, by applying a voltage to the diodes TD11 and TD12 through the wirings M11 to M13, a reference voltage is generated as the sum of the forward voltage and the breakdown voltage of the diodes TD11 and TD12 connected in series. I did it. As a result, a reference voltage having stable temperature characteristics can be generated even with a simple circuit configuration.

  (2) Further, by simplifying the circuit configuration as the reference voltage generation circuit, the restriction on the degree of freedom in design due to the above-described noise wraparound is eased, and the integrated IC of the semiconductor device is also provided. This also makes it possible to reduce the size of the chip. Further, by simplifying the circuit configuration, the manufacture becomes easy, and as a result, the yield can be improved. Therefore, cost reduction and energy saving can be achieved.

  (3) The structure of the semiconductor regions SA11 and SA12 is a structure in which the periphery is surrounded by an insulating layer (here, the insulating layer 12 and the insulating film 13a) and is electrically insulated and separated from other regions other than those regions. It was. As a result, the noise to the semiconductor regions SA11 and SA12, that is, the respective regions where the diodes TD11 and TD12 are formed is cut, and the noise resistance of the semiconductor device is also improved. In addition, according to such a structure, a parasitic diode that is formed in the case of insulating isolation at a pn junction is not formed, so that it is possible to increase the resistance against leakage current as a semiconductor device. It becomes like this.

  (4) The semiconductor regions SA11 and SA12 are formed in such a manner that the periphery is surrounded by the insulating layer 12 constituting the SOI substrate and the trench T1. Generally, an SOI substrate and trench isolation are used in a semiconductor process. For this reason, the structure which can acquire the effect of said (2) can be implement | achieved more easily and suitably by setting it as the said structure.

  (5) The diodes TD11 and TD12 formed in each of the semiconductor regions SA11 and SA12 include the P-type semiconductor layers D11b and D12b and the N-type semiconductor layer 13 constituting the diode, and the pn formed by these semiconductor layers. A structure was formed in which the areas of the junctions were the same. Usually, by arranging the structures of the two diodes TD11 and TD12, these diodes preferably cancel each other out of the temperature characteristics of the forward voltage and the breakdown voltage. Among the parameters as the structure of the diode, parameters that particularly affect the temperature characteristics of the forward voltage and the breakdown voltage have two semiconductor layers (a P-type semiconductor layer and an N-type semiconductor layer) constituting the diode. The impurity concentration of the semiconductor layer) and the area of the pn junction formed by these semiconductor layers. In other words, the above structure is particularly effective for improving the temperature characteristics of the reference voltage output from the semiconductor device.

  (6) The reverse breakdown voltage of the diodes TD11 and TD12 formed in the semiconductor regions SA11 and SA12 is set to “5V”, respectively. As a result, the diodes TD11 and TD12 cancel each other out of the temperature characteristics of the forward voltage and the breakdown voltage, thereby making the temperature characteristics of the reference voltage output from the semiconductor device substantially constant. Will be able to.

(7) The diodes TD11 and TD12 are formed of an N-type semiconductor layer 13 having an impurity concentration (surface concentration) of “5.8 × 10 ¹⁸ cm ⁻³ ” or higher and a P-type having an impurity concentration higher than that of the semiconductor layer 13. Each of the semiconductor layers D11b and D12b is configured as a structure. As a result, as is apparent from the graph shown in FIG. 5A, the diodes TD11 and TD12 are diodes having a reverse breakdown voltage of “5V”, and the functions of the diodes TD11 and TD12 are appropriately maintained. Will come to be.

(8) Further, the impurity concentration (surface concentration) of the semiconductor layer 13 is set to a concentration of “8.1 × 10 ¹⁸ cm ⁻³ ” or less. As a result, as is apparent from the graph shown in FIG. 5B, the leakage current is suppressed to “1.0 × 10 ⁻⁶ A” or less, which is a highly demanded specification in the market.

(9) The impurity concentrations of the semiconductor layers D11a and D12a and the semiconductor layers D11b and D12b were set to “1.0 × 10 ²⁰ cm ⁻³ ” or higher. Thereby, ohmic contacts are suitably formed between these semiconductor layers and the wirings M11 to M13.

(Second Embodiment)
8 to 10 show a second embodiment of the semiconductor device according to the present invention.
Similarly to the semiconductor device of the first embodiment, the semiconductor device according to this embodiment is a reference voltage generation circuit that outputs a reference voltage, and is simplified by adopting the structure shown in FIGS. A reference voltage having a stable temperature characteristic is generated with a simple circuit configuration. In addition, in the semiconductor device of this embodiment, as shown in FIGS. 8 and 9, a plurality of diodes TD21b to TD21f electrically connected in parallel by trimming wirings can be used instead of the previous diode TD11. By adopting, it is easy to adjust the temperature characteristics of the reference voltage.

Hereinafter, the structure of the semiconductor device according to this embodiment will be described in detail with reference to FIGS.
First, the circuit configuration of this semiconductor device will be described with reference to FIG. In FIG. 8 as well, the same elements as those shown in FIG. 17 are denoted by the same reference numerals, and redundant description of these elements is omitted.

As shown in FIG. 8, in this circuit, the current is a constant current I _o, for example, "100μA~1mA" through transformer TS from the power supply terminal TE1 is, a resistor R2b~R2f connected in parallel, Similarly, the diodes TD21b to TD21f connected in parallel and the diode TD22 flow into the ground.

  Here, the anode terminals of the diodes TD21b to TD21f are connected in series to the resistors R2b to R2f, respectively. The cathode terminals at the other ends of the diodes TD21b to TD21f are connected in series to the cathode terminal of the diode TD22. An output terminal TE2 is provided on the upstream side of the resistors R2b to R2f connected in parallel. Thus, in this circuit, the reference voltage is applied to the output terminal TE2 as the sum of the voltage of the resistors R2b to R2f and the forward voltage and breakdown voltage (reverse voltage) of the diodes TD21b to TD21f and TD22. It is output. Incidentally, the diode TD22 functions as a so-called Zener diode.

  In the semiconductor device according to this embodiment, the resistors R2b to R2f are made of CrSiN, and the resistors are formed so as to be trimmed. This CrSiN is a material having excellent temperature characteristics, and its resistance value is relatively small. For this reason, the voltage rise by the resistors R2b to R2f and the influence of the reference voltage on the temperature characteristics are so small that they can be ignored.

  Next, the structure of this semiconductor device will be described with reference to FIG. In FIG. 9, FIG. 9A is a plan view of the semiconductor device, and FIG. 9B is a cross-sectional view taken along line BB in FIG. 9A. Incidentally, FIGS. 9A and 9B correspond to a plan view and a cross-sectional view of a region P20 indicated by a one-dot chain line in FIG.

As shown in FIGS. 9A and 9B, this semiconductor device is also largely made of a semiconductor substrate 21 made of, for example, silicon, an insulating layer 22 made of, for example, silicon oxide, and made of, for example, N-type silicon. A semiconductor layer 23 is sequentially stacked. Here again, the semiconductor substrate 21, the insulating layer 22, and the semiconductor layer 23 are formed as SOI substrates. The impurity concentration (surface concentration) of the semiconductor layer 23 is set to “5.8 × 10 ¹⁸ cm ^{−3 to} 8.1 × 10 ¹⁸ cm ⁻³ ”.

  The semiconductor layer 23 is partitioned in such a manner that the periphery is surrounded by the trench T2, and two adjacent semiconductor regions SA21 and SA22 separated by the trench T2 are formed. The trench T2 includes an insulating film 23a made of, for example, silicon oxide formed on the inner wall of the trench T2, and a dielectric film 23b made of, for example, polycrystalline silicon formed inside the insulating film 23a. Buried. The semiconductor regions SA21 and SA22 are completely surrounded by the trench T2 and the insulating layer 22, and are electrically isolated from other regions other than these regions.

  Also, P-type semiconductor layers D21b to D21f and D22b are formed on the surfaces of the semiconductor regions SA21 and SA22 by introducing impurities at a higher concentration than the semiconductor layer 23, respectively. 9A and 9B, N-type semiconductor layers D21a and D22a having a higher concentration than the semiconductor layer 23 are patterned. Similarly, the semiconductor layers D21a and D22a and the semiconductor layers D21b to D21f are formed by insulating films (for example, silicon oxide films) I22 and I23 having an STI structure patterned in the manner shown in FIGS. 9A and 9B. The semiconductor layers D22b are electrically separated from each other. Incidentally, the STI here is an abbreviation for “Shallow Trench Isolation”.

  The insulating film I23 having the STI structure is formed in a deeper form than the semiconductor layers D21b to D21f. More specifically, the semiconductor layers D21b to D21f are formed with a depth of, for example, “0.1 μm to 0.3 μm”. On the other hand, the insulating film I23 is formed with a depth of, for example, “0.5 μm”.

Here, pn junctions are formed between the N-type semiconductor layer 23 and the P-type semiconductor layers D21b to D21f and D22b, respectively. Thereby, diodes TD21b to TD21f (see FIG. 8) electrically connected in parallel are formed in the semiconductor region SA21. On the other hand, the diode TD22 is formed in the semiconductor region SA22. The impurity concentration of the semiconductor layers D21a and D22a, the semiconductor layers D21b to D21f, and the semiconductor layer D22b is, for example, “1.0 × 10 ²⁰ cm” in order to form an ohmic contact with the wiring connected to these semiconductor layers. ^-3 "or higher. The reverse breakdown voltage of the diodes TD21b to TD21f and TD22 is set to “5V”.

  As described above, in the semiconductor device according to this embodiment, the semiconductor layers D21b to D21f are electrically separated by the insulating film I23 formed deeper than the semiconductor layers. As a result, the pn junctions formed by the two types of semiconductor layers respectively constituting the diodes connected in parallel, that is, the N-type semiconductor layer 23 and the P-type semiconductor layers D21b to D21f, are It is formed at a position shallower than the film I23. The semiconductor layers D21b to D21f are formed in such a manner that the periphery of the semiconductor layer 23 is surrounded by the insulating film I23. For this reason, the area of each pn junction formed by the diodes TD21b to TD21f connected in parallel is the area of each region surrounded by the insulating film I23, that is, the size of each of the semiconductor layers D21b to D21f (cross section in the substrate horizontal direction). Area).

Further, an insulating film 24 is formed on the semiconductor layer 23, and the insulating film 24 is appropriately patterned to form an opening for forming a resistor. Then, for example, by performing sputtering using, for example, a Cr—Si alloy as a target in an Ar, N ₂ atmosphere, resistors R2b to R2f made of CrSiN having a thickness of “several μm” are formed in the opening. Further, contact holes are formed by appropriately patterning the insulating film 24, and a wiring material is formed in a manner to fill the contact holes. And wiring M21b-M21f and wiring M21-M23 are formed by patterning this wiring material suitably.

  Among these, the wirings M21b to M21f are connected to the wiring M21 through the resistors R2b to R2f, respectively, and are connected to the power supply terminal TE1 (FIG. 8) through the wiring M21. . The wirings M21b to M21f form contacts with the semiconductor layers D21b to D21f corresponding to the anode terminals of the diodes TD21b to TD21f, respectively. The wiring M22 is a ground wiring connected to the ground (FIG. 8), and forms a contact with the semiconductor layer D22b corresponding to the anode terminal of the diode TD22. The wiring M23 is a wiring that connects each of the diodes TD21b to TD21f and the diode TD22 in series, and forms a contact with both the semiconductor layers D21a and D22a corresponding to the cathode terminals of these diodes.

  Thus, also in the semiconductor device according to this embodiment, the cathode terminals of the diodes TD21b to TD21f and TD22 are connected in series via the wiring M23. The forward voltages and breakdown voltages of the diodes TD21b to TD21f and TD22 connected in series are applied by applying a voltage to the diodes TD21b to TD21f and TD22 through the wirings and the resistors R2b to R2f. The reference voltage is generated as the sum of In other words, the semiconductor device according to the present embodiment can generate a reference voltage having a simple structure and stable temperature characteristics.

Next, with reference to FIG. 10, the adjustment mode of the reference voltage output by the semiconductor device according to this embodiment and the adjustment mode of the temperature characteristic of the reference voltage will be described. FIG. 10A is a graph showing the relationship between the reference voltage (V _f + V _Z ) output from this semiconductor device and the sizes (μm □) of the semiconductor layers D21b to D21f. A21 to A23 in FIG. 10A represent data when the environmental temperature (Ta) in which the semiconductor device is placed is “−30 ° C.”, “25 ° C.”, and “125 ° C.”, respectively. Show. FIG. 10B is a graph showing the temperature characteristics of the breakdown voltage (V _Z ) of the diode TD22. B21 to B26 in FIG. 10B are the same size for all of the semiconductor layers D21b to D21f, and the sizes (μm □) are “2.4”, “4.0”, “6.0”. ”,“ 8.0 ”,“ 10.0 ”, and“ 14.0 ”, respectively. Further, in the measurements according to FIGS. 10A and 10B, the constant current I _o (see FIG. 8) supplied to the diode was set to “100 μA”. In addition, the size of the semiconductor layer referred to here indicates a cross-sectional size of the semiconductor layer in the horizontal direction of the substrate. For example, “2.4 (μm □)” corresponds to a cross-sectional size of “(vertical dimension) × (horizontal dimension) = 2.4 μm × 2.4 μm”.

  In the semiconductor device according to this embodiment, the area of each pn junction formed by the five diodes connected in parallel corresponds to the size of each of the semiconductor layers D21b to D21f (cross-sectional area in the substrate horizontal direction). As described above. Further, the reference voltage (particularly the breakdown voltage of the diode TD22) output from the semiconductor device according to this embodiment and the temperature characteristics thereof are shown in the graphs of FIGS. 10 (a) and 10 (b). It is correlated with the sizes of D21b to D21f. In other words, the reference voltage and its temperature characteristic correlate with the area of each pn junction formed by the diodes connected in parallel. More precisely, the reference voltage and its temperature characteristic correlate with the total area of the pn junctions formed by the diodes connected in parallel.

  Here, in the semiconductor device according to this embodiment, the diodes TD21b to TD21f are electrically connected in parallel via the trimming resistors R2b to R2f. For this reason, by selectively trimming these resistors R2b to R2f, for example, by laser trimming, the total pn junction area can be easily adjusted to a desired value. That is, the reference voltage output from the semiconductor device and its temperature characteristics can be adjusted more easily. Such adjustment can be performed even after the semiconductor device is cut out as an IC chip.

  The areas of the pn junctions formed by the diodes TD21b to TD21f connected in parallel correspond to the sizes (cross-sectional areas in the substrate horizontal direction) of the semiconductor layers D21b to D21f, respectively. Thus, the desired pn junction area can be easily obtained by setting the size of each of the semiconductor layers D21b to D21f to an appropriate value at the design stage. As a result, the reference voltage and its temperature characteristics can be obtained. Adjustment can be performed more suitably.

The semiconductor device according to this embodiment is also manufactured by a manufacturing process substantially similar to the manufacturing process shown in FIGS.
As described above, the semiconductor device according to the second embodiment also has the same effects as the above-described (1) to (4) and (6) to (9) according to the first embodiment. Alternatively, effects similar to the above can be obtained, and in addition to this, the following effects can be newly obtained.

  (10) In the semiconductor region SA21, diodes TD21b to TD21f (see FIG. 8) electrically connected in parallel via trimmable resistors R2b to R2f are formed, and these diodes TD21b to TD21f are formed in the semiconductor region. The diode TD22 formed in SA22 is electrically connected in series. As a result, the reference voltage output from the semiconductor device and its temperature characteristics can be easily adjusted. Further, the adjustment of the reference voltage and its temperature characteristic can be easily performed even after the semiconductor device is cut out as an IC chip.

  (11) Further, CrSiN is used as the material of the resistors R2b to R2f. Thereby, deterioration of the temperature characteristic of the reference voltage, which is a concern by providing the resistors R2b to R2f, is suppressed. In addition, since CrSiN is excellent in trimming properties, it is particularly effective when used as a material for the resistors R2b to R2f.

  (12) The semiconductor layers D21b to D21f are electrically isolated by an element isolation insulating layer (here, an insulating film I23 having an STI structure) formed deeper than the semiconductor layers. As a result, the reference voltage and its temperature characteristics can be adjusted more easily and suitably.

  (13) The insulating film I23 having an STI structure is used as an insulating layer for element isolation for electrically isolating the semiconductor layers D21b to D21f. In general, an insulating film having an STI structure can be easily formed deeper than a field oxide film having a LOCOS structure. For this reason, in order to obtain a structure capable of obtaining the effect (11), it is particularly effective to adopt such a structure. Incidentally, an insulating film having an STI structure can be formed relatively easily with a depth of about “0.5 μm”. On the other hand, it is difficult to form a field oxide film having a LOCOS structure deeper than a depth of about “0.3 μm”.

  (14) The insulating film having the STI structure is generally used for isolation (isolation) between elements in a semiconductor process, and its formation method is well known. For this reason, silicon oxide having such an STI structure is particularly effective as an insulating layer for element isolation.

(Third embodiment)
11 to 13 show a third embodiment of the semiconductor device according to the present invention.

  The semiconductor device according to this embodiment is also a reference voltage generation circuit that outputs a reference voltage, like the semiconductor devices of the first and second embodiments. The circuit configuration of the semiconductor device according to this embodiment is basically the same as that of the circuit shown in FIG. However, this semiconductor device employs diodes TD31 and TD32 in place of the diodes TD11 and TD12. Here, the diode TD32 functions as a so-called Zener diode. Further, in this semiconductor device, by adopting the structure shown in FIG. 11, it is possible to generate a reference voltage having a stable temperature characteristic with a simple circuit configuration and to facilitate the manufacture thereof.

  Hereinafter, the structure of the semiconductor device according to this embodiment will be described in detail with reference to FIG. 11 focusing on the diodes TD31 and TD32. In FIG. 11, FIG. 11 (a) is a plan view of the semiconductor device, and FIG. 11 (b) is a cross-sectional view taken along the line BB of FIG. 11 (a). Incidentally, these FIGS. 11A and 11B also correspond to a plan view and a cross-sectional view of a region P10 indicated by a one-dot chain line in FIG.

As shown in FIGS. 11A and 11B, this semiconductor device is also largely made of a semiconductor substrate 31 made of, for example, silicon, an insulating layer 32 made of, for example, silicon oxide, and made of, for example, N-type silicon. A semiconductor layer 33 is sequentially stacked. Here again, the semiconductor substrate 31, the insulating layer 32, and the semiconductor layer 33 are formed as SOI substrates. The impurity concentration (surface concentration) of the semiconductor layer 33 is set to “5.8 × 10 ¹⁸ cm ^{−3 to} 8.1 × 10 ¹⁸ cm ⁻³ ”. The thickness of the semiconductor layer 13 is, for example, “10 μm to 16 μm”.

  The semiconductor layer 33 is partitioned in such a manner that the periphery is surrounded by the trench T3, and two adjacent semiconductor regions SA31 and SA32 separated by the trench T3 are formed. The trench T3 includes an insulating film 33a made of, for example, silicon oxide formed on the inner wall of the trench T3 and a dielectric film 33b made of, for example, polycrystalline silicon formed inside the insulating film 33a. Buried. The semiconductor regions SA31 and SA32 are completely surrounded by the trench T3 and the insulating layer 32, and are electrically isolated from other regions other than these regions.

  Further, in these semiconductor regions SA31 and SA32, impurities are introduced into the side walls of the trench T3, respectively, and N-type semiconductor layers (diffusion layers) D31a and D32a having a higher concentration than the semiconductor layer 33 are formed. . On the surfaces of the semiconductor regions SA31 and SA32, P-type semiconductor layers D31b and D32b are formed by introducing impurities at a concentration higher than that of the semiconductor layer 33, respectively. The impurity regions are electrically isolated from each other by a field oxide film I33 having a LOCOS structure patterned in the manner shown in FIGS. 11A and 11B. More specifically, the field oxide film I33 has openings A31a and A32a for forming wiring contacts in the semiconductor layers D31a and D32a, and openings for forming wiring contacts in the semiconductor layers D31b and D32b, respectively. Part A31b and A32b are formed.

Here, pn junctions are formed between the N-type semiconductor layer 33 and the P-type semiconductor layers D31b and D32b, respectively. As a result, diodes TD31 and TD32 are formed in the semiconductor regions SA31 and SA32, respectively. Also in this case, the impurity concentration of the semiconductor layers D31a and D32a and the semiconductor layers D31b and D32b is, for example, “1.0 × 10 ²⁰ cm ⁻³ ” in order to form an ohmic contact with the wiring connected to these semiconductor layers. It is set as the above density | concentration.

  The semiconductor regions SA31 and SA32 have a line-symmetric relationship with a line perpendicular to the line BB in FIG. That is, the diodes TD31 and TD32 are diodes having a reverse breakdown voltage of “5V” by making the impurity concentrations of the semiconductor layers D31b and D32b equal to each other and the areas of the pn junctions formed by the semiconductor layers and the semiconductor layers 33, respectively. Is formed.

  Further, also in this embodiment, an insulating film 34 is formed on the semiconductor layer 33, and the insulating film 34 is appropriately patterned to form a contact hole. Then, a wiring material is formed so as to fill the contact hole, and this wiring material is appropriately patterned to form wirings M31 to M33. Among these, the wiring M31 is a power supply wiring connected to the power supply terminal TE1 (see FIG. 1), and forms a contact with the semiconductor layer D31b corresponding to the anode terminal of the diode TD31. The wiring M32 is a ground wiring connected to the ground (see FIG. 1), and forms a contact with the semiconductor layer D32b corresponding to the anode terminal of the diode TD32. The wiring M33 is a wiring for connecting the diode TD31 and the diode TD32 in series, and forms a contact with both the semiconductor layers D31a and D32a corresponding to the cathode terminals of these diodes.

  Next, with reference to FIG. 12 and FIG. 13, the manufacturing method of the semiconductor device according to this embodiment will be described in detail. Each of these figures is a cross-sectional view showing the manufacturing process of this semiconductor device.

  In this manufacturing, first, as shown in FIG. 12A, an SOI substrate in which an insulating layer 32 and a semiconductor layer 33 are sequentially formed on the semiconductor substrate 31 is prepared, and a film thickness of, for example, “1 μm” is prepared thereon. A resist RE3 made of NSG (Non Dope Silicate Glass) of ˜2 μm is applied.

  Next, as shown in FIG. 12B, required patterning is performed on the resist RE3 by, for example, photolithography, and the semiconductor layer 33 is selectively etched by, for example, RIE using the patterned resist RE3 as a mask. This is removed to form a trench T3. Then, using the patterned resist RE3 as a mask, oblique ion implantation of N-type impurities such as phosphorus is performed on the sidewalls of the trench T3, and then the introduced impurities are thermally diffused. Thereby, the semiconductor layers D31a and D32a are formed on the side wall of the trench T3.

  Then, after removing the resist RE3, for example, an appropriate heat treatment is performed to oxidize the side wall of the trench T3 to form the insulating film 33a, so that the structure shown in FIG. Subsequently, the dielectric film 33b is formed so as to completely fill the trench T3, and then subjected to an appropriate flattening process to obtain the structure shown in FIG. Here, the impurity profiles of the semiconductor layers D31a and D32a are also adjusted through heat treatment when forming the insulating film 33a.

Then, as shown in FIG. 13A, the field oxide film I33 having the LOCOS structure is selectively formed by a known selective oxidation method, for example, in the manner shown in FIG.
Thereafter, ion implantation of a P-type impurity such as boron is selectively performed to form the semiconductor layers D31b and D32b, resulting in a structure as shown in FIG. At this time, the semiconductor layers D31b and D32b are formed in a self-aligned manner using the field oxide film I33 as a mask.

  Subsequently, an appropriate heat treatment is performed to form a desired diode profile, and each impurity region is activated. Then, the insulating film 34 and the wirings M31 to M33 are patterned on the above-described manner shown in FIG. 11 to complete the semiconductor device.

  Thus, also in the semiconductor device according to this embodiment, the cathode terminals of the diodes TD31 and TD32 are connected in series via the wiring M33. By applying a voltage to the diodes TD31 and TD32 through the wirings M31 to M33, the sum of the forward voltage and the breakdown voltage (reverse voltage) of the diodes TD31 and TD32 connected in series is obtained. A reference voltage is generated. As a result, it is possible to generate a reference voltage having a stable temperature characteristic with a simple structure.

  Further, N-type semiconductor layers D31a and D32a having a higher concentration than the semiconductor layer 33 are formed on the sidewalls of the trench T3 as the semiconductor regions SA31 and SA32. The semiconductor layers D31a and D32a can be easily formed by introducing impurities into the sidewalls of the trench T3 using the mask used when forming the trench T3 as it is. For this reason, the diodes TD31 and TD32 are electrically connected in series through the semiconductor layers D31a and D32a, thereby making it easier to manufacture the semiconductor device.

  As described above, the semiconductor device according to the third embodiment can obtain the same or similar effects as the effects (1) to (9) according to the first embodiment. In addition to this, the following effects can be newly obtained.

  (15) Two adjacent semiconductor regions SA31 separated by the trench T3 in a form having semiconductor layers (diffusion layers) D31a and D32a formed on the side wall of the trench T3 so that the impurity concentration of the semiconductor layer 33 is increased. And SA32 are formed. The diodes TD31 and TD32 are electrically connected in series via a wiring M33 that forms a contact with the semiconductor layers D31a and D32a. This makes it easier to manufacture the semiconductor device.

(Fourth embodiment)
FIG. 14 shows a fourth embodiment of the semiconductor device according to the present invention.
The semiconductor device according to this embodiment is also a reference voltage generation circuit that outputs a reference voltage, like the semiconductor devices of the first to third embodiments. The circuit configuration of the semiconductor device according to this embodiment is basically the same as that of the circuit shown in FIG. However, this semiconductor device employs diodes TD41 and TD42 instead of the diodes TD11 and TD12. Here, the diode TD42 functions as a so-called Zener diode. In addition, in this semiconductor device, the structure shown in FIG. 14 is used to generate a reference voltage having a stable temperature characteristic with a simpler structure while facilitating its manufacture.

  Hereinafter, with reference to FIG. 14, the structure of the semiconductor device according to the present embodiment will be described in detail focusing on the structure of the diodes TD41 and TD42. In FIG. 14, FIG. 14A is a plan view of the semiconductor device, and FIG. 14B is a cross-sectional view taken along line BB in FIG. 14A. Incidentally, FIGS. 14A and 14B also correspond to a plan view and a cross-sectional view of a region P10 indicated by a one-dot chain line in FIG.

As shown in FIGS. 14A and 14B, this semiconductor device also has basically the same structure as the semiconductor device according to the third embodiment. That is, this semiconductor device is also configured by laminating a semiconductor substrate 41 made of, for example, silicon, an insulating layer 42 made of, for example, silicon oxide, and a semiconductor layer 43 made of, for example, N-type silicon in this order. Here again, the semiconductor substrate 41, the insulating layer 42, and the semiconductor layer 43 are formed as an SOI substrate. The impurity concentration (surface concentration) of the semiconductor layer 43 is set to “5.8 × 10 ¹⁸ cm ^{−3 to} 8.1 × 10 ¹⁸ cm ⁻³ ”.

  The semiconductor layer 43 is partitioned in such a manner that the periphery is surrounded by the trench T4, and two adjacent semiconductor regions SA41 and SA42 are formed by the trench T4. The trench T4 includes an insulating film 43a made of, for example, silicon oxide formed on the inner wall of the trench T4 and a dielectric film 43b made of, for example, polycrystalline silicon formed inside the insulating film 43a. Buried. The semiconductor regions SA41 and SA42 are completely surrounded by the trench T4 and the insulating layer 42, and are electrically isolated from other regions other than these regions.

  Further, in these semiconductor regions SA41 and SA42, impurities are introduced into the sidewalls of the trench T4, respectively, and N-type semiconductor layers (diffusion layers) D41a and D42a having a higher concentration than the semiconductor layer 43 are formed. . On the surfaces of the semiconductor regions SA41 and SA42, P-type semiconductor layers D41b and D42b are formed by introducing impurities having a concentration higher than that of the semiconductor layer 43, respectively. The impurity regions are electrically isolated from each other by a field oxide film I43 having a LOCOS structure patterned in the manner shown in FIGS. 14A and 14B. More specifically, the field oxide film I43 forms an opening as a trench T43 for forming a wiring contact in both the semiconductor layers D41a and D42a, and a wiring contact in the semiconductor layers D41b and D42b, respectively. For opening A41b and A42b.

Here, pn junctions are formed between the N-type semiconductor layer 43 and the P-type semiconductor layers D41b and D42b, respectively. As a result, diodes TD41 and TD42 are formed in the semiconductor regions SA41 and SA42, respectively. Also in this embodiment, the impurity concentrations of the semiconductor layers D41a and D42a and the semiconductor layers D41b and D42b are set to, for example, “1.0 × 10 6” in order to form ohmic contacts with wirings connected to these semiconductor layers. The concentration is ²⁰ cm ⁻³ or more.

  The semiconductor regions SA41 and SA42 have a line-symmetric relationship with a line perpendicular to the line BB in FIG. That is, the diodes TD41 and TD42 are diodes having a reverse breakdown voltage of “5 V” by making the impurity concentrations of the semiconductor layers D41b and D42b and the areas of the pn junctions formed by these semiconductor layers and the semiconductor layer 43 equal. Is formed.

  Further, an insulating film 44 is formed on the semiconductor layer 43, and the insulating film 44 is appropriately patterned to form a contact hole. Then, a wiring material is formed so as to fill the contact hole, and the wiring M41 to M43 are formed by appropriately patterning the wiring material. Further, in this embodiment, a trench T43 having both the semiconductor layers D41a and D42a formed in the semiconductor regions SA41 and SA42 as sidewalls is formed, and a conductor film made of, for example, aluminum is formed on the trench T43. By embedding, the wiring M43 is formed in such a manner that the semiconductor layers D41a and D42a are short-circuited.

  Among these, the wiring M41 is a power supply wiring connected to the power supply terminal TE1 (see FIG. 1), and forms a contact with the semiconductor layer D41b corresponding to the anode terminal of the diode TD41. The wiring M42 is a ground wiring connected to the ground (see FIG. 1), and forms a contact with the semiconductor layer D42b corresponding to the anode terminal of the diode TD42. The wiring M43 is a wiring for connecting the diode TD41 and the diode TD42 in series, and forms a contact with both the semiconductor layers D41a and D42a corresponding to the cathode terminals of these diodes.

  Thus, also in the semiconductor device according to this embodiment, the cathode terminals of the diodes TD41 and TD42 are connected in series via the wiring M43. By applying a voltage to the diodes TD41 and TD42 through the wirings M41 to M43, the sum of the forward voltage and the breakdown voltage (reverse voltage) of the diodes TD41 and TD42 connected in series is obtained. A reference voltage is generated. As a result, it is possible to generate a reference voltage having a stable temperature characteristic with a simple structure.

  Further, in this embodiment, as the wiring M43 for connecting the diodes TD41 and TD42 in series, a conductor film embedded in the trench T43 is used so as to short-circuit the semiconductor layers D41a and D42a. The diodes TD41 and TD42 are electrically connected in series via the wiring M43 having such a simple structure, whereby the structure of the semiconductor device itself can be simplified.

The semiconductor device according to this embodiment is also manufactured by a manufacturing process substantially similar to the manufacturing process shown in FIGS.
As described above, the semiconductor device according to the fourth embodiment is similar to the effects (1) to (9) and (15) according to the first or third embodiment. In addition to this, it is possible to obtain the following effects as well as the following effects.

  (16) Conductor buried in the trench by short-circuiting the semiconductor layers D41a and D42a formed in the semiconductor regions SA41 and SA42, respectively, as the wiring M43 for forming contacts in the semiconductor layers (diffusion layers) D41a and D42a A film was used. As a result, the structure of the semiconductor device can be simplified.

(Other embodiments)
Each of the above embodiments may be modified as follows.
In the second embodiment, the structure as the plurality of diodes TD21b to TD21f electrically connected in parallel is illustrated based on the device structure according to the first embodiment. However, in the device structure according to the third or fourth embodiment, similarly, a plurality of P-type semiconductor layers (for example, D31b) are electrically separated from each other by an insulating layer for element isolation. Thus, a plurality of diodes electrically connected in parallel can be formed. Even with such a structure, effects similar to or equivalent to the effects (10) to (14) of the second embodiment can be obtained.

  In the second embodiment, a method for trimming the diodes TD21b to TD21f, more precisely, an example of a method for trimming a plurality of wirings (resistors R2b to R2f) that electrically connect these diodes in parallel. Laser trimming. However, the trimming method is arbitrary. For example, an overcurrent may be passed through these resistors to cause a self-breaking. Even by such a method, for example, the resistors R2b to R2f are formed with different film thicknesses (or width dimensions), thereby enabling selective trimming.

  In the second embodiment, CrSiN is used as the material for the resistors R2b to R2f. However, the material of these resistors R2b to R2f is arbitrary as long as it functions as a wiring and can be trimmed by a laser or the like.

  In the second embodiment, the trimming resistor is used so that the wiring can be trimmed. However, it is not always necessary to use such a resistor. For example, the wiring itself may be trimmed by performing appropriate processing on the wiring itself or by selecting an appropriate material as the material of the wiring itself.

  In the second embodiment, a structure in which five diodes are connected in parallel is illustrated, but the number of diodes connected in parallel is arbitrary. A plurality of diodes connected in parallel to each of the semiconductor regions SA21 and SA22 may be formed, and the diodes formed in each of the semiconductor regions may be connected in series with each other.

  In the second embodiment, the insulating film I23 having the STI structure is used as the element isolation insulating layer for electrically isolating the semiconductor layers D21b to D21f. However, the element isolation insulating layer is not limited to this, and for example, a field oxide film having a LOCOS structure may be used. Also in this case, if the semiconductor layers D21b to D21f are electrically isolated by an element isolation insulating layer formed deeper than the semiconductor layers, at least (12) of the second embodiment. An effect similar to or equivalent to the effect of can be obtained.

  It is not always necessary that the element isolation insulating layer for electrically separating the semiconductor layers D21b to D21f is formed deeper than the semiconductor layers D21b to D21f. Even when the insulating layers for element isolation are formed shallower than the semiconductor layers D21b to D21f, at least the effects (10), (11), and (14) of the second embodiment are the same as or equivalent thereto. The effect will be obtained.

  In the first or second embodiment, the semiconductor layers D11a and D12a or the semiconductor layer D22a are formed so as to surround the semiconductor layers D11b and D12b or the semiconductor layer D22b. However, these semiconductor layers D11a and D12a, or the semiconductor layer D22a are sufficient if they are in a portion that forms a contact with the wiring M13 or M23. For example, in the first embodiment, if the semiconductor layers D11a and D12a are selectively provided in a portion where a contact is formed with the wiring M13 as shown in FIG. Further simplification will be achieved.

  In the fourth embodiment, the wiring M43 that electrically connects the diodes TD41 and TD42 in series is made of a conductive film embedded in the trench T43 formed for the wiring M43. However, the present invention is not limited to this, and as a trench for embedding the wiring M43, for example, a trench T4 that separates the semiconductor regions SA41 and SA42 can be used. In short, any trench may be used as long as it can embed a conductor film in such a manner that the semiconductor layers D41a and D41b as diffusion layers are short-circuited.

  In the third or fourth embodiment, in order to obtain a good contact with the wiring M33 or the wiring M43, the structure in which the impurity concentration of the portion where the contact is formed is increased is also used. The invention is equally applicable. For example, in the third embodiment, as shown in FIG. 16, the present invention is similarly applied to a structure in which N-type semiconductor layers D31c and D32c having higher concentrations than the semiconductor layers D31a and D32a are newly provided. Can be applied to.

  In the first, third, or fourth embodiment, the diode formed in each semiconductor region includes a P-type semiconductor layer (for example, semiconductor layers D11b and D12b) and an N-type semiconductor layer constituting the diode. (For example, the semiconductor layer 13) and the areas of the pn junctions formed by these semiconductor layers are formed to be the same. However, the present invention is not limited to such a structure, and the diodes formed in the respective semiconductor regions are also formed in a form in which the respective parameters are different from each other, as described in (1) to (9) of the first embodiment. Of these effects, effects similar to or equivalent to the effects other than the effect (5) can be obtained.

  In the first, third, or fourth embodiment, an insulating layer having an STI structure is used instead of the field oxide film I13, I33, or I43 having a LOCOS structure used as an insulating layer for element isolation. You may make it use.

In each of the above embodiments, each diode has an N-type semiconductor layer (for example, the semiconductor layer 13) having an impurity concentration of “5.8 × 10 ¹⁸ cm ⁻³ ” or higher, and the N-type semiconductor layer. The structure is constituted by a semiconductor layer (for example, semiconductor layers D11b and D12b) made of P-type having a high impurity concentration. However, the present invention is not limited to this structure, and if the reverse breakdown voltage of the diode is set to “5V”, the effect similar to or equivalent to the effect (6) of the first embodiment is at least. It will be obtained.

  In each of the above embodiments, the reverse breakdown voltage of each diode is set to “5V”. However, the reverse breakdown voltage of each of these diodes does not necessarily have to be “5V”. Even if the reverse breakdown voltage of each of these diodes is set to other than “5V”, among the effects (1) to (9) of the first embodiment, the effects other than the effect (6) The same or similar effects can be obtained.

  In each of the above embodiments, two adjacent semiconductor regions (for example, semiconductor regions) in a form surrounded by an insulating layer (for example, insulating layer 12) and a trench (for example, trench T1) constituting the SOI substrate. SA11 and SA12) were formed. However, it is not always necessary to use an SOI substrate. These semiconductor regions only need to be surrounded by an insulating layer and electrically insulated and separated from other regions other than those regions. Even if such a structure is used, at least the structure of the first embodiment is used. An effect similar to or equivalent to the effect of (3) can be obtained.

  In each of the above embodiments, as a trench (for example, T1) that separates two adjacent semiconductor regions, an insulating film (for example, the insulating film 13a) and a dielectric film (for example, the insulating film 13b) embedded are used. I made it. However, the trench used for separating the two adjacent semiconductor regions is not limited to such a trench, and is arbitrary. For example, a trench in which one kind of insulating film is embedded may be used. Further, as described above, a trench in which a conductor film (for example, the wiring M43) is embedded can be used as appropriate. In short, it may be a trench that separates two adjacent semiconductor regions.

  In each of the above embodiments, the cathode terminals of the diodes formed in two adjacent semiconductor regions are connected to each other, and the anode terminals at the other ends of the diodes are at different potentials (for example, a power supply potential and a ground potential). The reference voltage was generated by being placed. However, instead of this, the present invention is similarly applied to a structure in which the anode terminals of these diodes are connected to each other and the cathode terminals at the other ends of the diodes are placed at different potentials to generate a reference voltage. can do. Such a structure is easily realized, for example, by switching the conductivity type of each semiconductor layer in each of the above embodiments, that is, by switching the N type (first conductivity type) and the P type (second conductivity type). Is done. Moreover, it is realizable also by changing the arrangement | positioning aspect of each wiring (for example, wiring M11 and M12).

  In each of the above embodiments, the reference voltage is generated by summing the forward voltage and the breakdown voltage (reverse voltage) of the diodes formed in the two adjacent semiconductor regions. However, it suffices to generate a reference voltage that includes at least the forward voltage and breakdown voltage of the diodes.For example, a voltage obtained by appropriately correcting the voltage is used as the reference voltage. You may make it do.

1 is a circuit diagram showing a circuit configuration of a semiconductor device according to a first embodiment of the present invention; 2A is a plan view showing a planar structure of the semiconductor device according to the first embodiment, and FIG. 2B is a cross-sectional view taken along line BB in FIG. (A) and (b) show, for each semiconductor device used as a sample in the first embodiment, a voltage V _Z applied in the reverse direction to the diode and a reverse current I _Z flowing at that time. A graph showing the relationship. (A) and (b) are the diode forward voltage and breakdown voltage (reverse voltage) and the reference voltage output as the sum of these voltages for the semiconductor device used as the sample in the first embodiment. The graph which shows the temperature characteristic of. (A) is a graph showing the relationship between the reverse breakdown voltage of a diode and the surface concentration of a low-concentration (thin) side semiconductor layer constituting the diode, for two types of semiconductor devices used as samples in the first embodiment. (B) is a graph which shows the relationship between the leakage current of the said semiconductor device, and the surface concentration of the low concentration (thin) side semiconductor layer. (A)-(c) is sectional drawing which shows the manufacturing process about the semiconductor device concerning the 1st Embodiment. (A)-(c) is sectional drawing which shows the manufacturing process about the semiconductor device concerning the 1st Embodiment. The circuit diagram which shows the circuit structure about 2nd Embodiment of the semiconductor device concerning this invention. About the semiconductor device concerning the said 2nd Embodiment, (a) is a top view which shows the planar structure of the semiconductor device, (b) is sectional drawing along the BB line of (a). Regarding the semiconductor device according to the second embodiment, (a) is a graph showing the relationship between the reference voltage output from the semiconductor device and the size of the semiconductor layer, and (b) is a breakdown voltage of the diode (reverse direction). The graph which shows the temperature characteristic of voltage. (A) is a top view which shows the planar structure of the semiconductor device concerning 3rd Embodiment of this invention, (b) is sectional drawing along the BB line of (a). (A)-(c) is sectional drawing which shows the manufacturing process about the semiconductor device concerning the 3rd Embodiment. (A) And (b) is sectional drawing which shows the manufacturing process about the semiconductor device concerning the 3rd Embodiment. (A) is a top view which shows the planar structure of the semiconductor device concerning 4th Embodiment of this invention, (b) is sectional drawing along the BB line of (a). Sectional drawing which shows typically the cross-sectional structure about the modification of the semiconductor device concerning the said 1st Embodiment. Sectional drawing which shows typically the cross-section about the modification of the semiconductor device concerning the said 3rd Embodiment. The circuit diagram which shows the circuit structure about an example of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11-41 ... Semiconductor substrate, 12-42 ... Insulating layer, 13-43, D11a-D41a, D12a-D42a, D11b-D41b, D12b-D42b, D21c-D21f, D31c, D32c ... Semiconductor layer, 13a-43a, 14 ˜44, I22, I23... Insulating film, 13b to 43b... Dielectric film, I11 to I13, I33, I43... Field oxide film, M11 to M13, M21 to M23, M21b to M21f, M31 to M33, M41 to M43. , R2b to R2f ... resistors, SA11 to SA41, SA12 to SA42 ... semiconductor region, T1 to T4, T43 ... trench, TD11, TD21b to TD21f, TD31, TD41, TD12 to TD42 ... diode, TE1 ... power supply terminal, TE2 ... Ground terminal.

Claims (14)

At least one diode is formed in each of the two semiconductor regions separated by the trench, and the cathode terminals or anode terminals of the diodes formed in each of the semiconductor regions are electrically connected in series, A reference in which at least the forward voltage and breakdown voltage of the diodes connected in series are included by placing the anode terminal or cathode terminal of the other end of the diodes connected in series at different potentials. A semiconductor device for generating a voltage ,
One of the two semiconductor regions is formed with a plurality of diodes electrically connected in parallel via a plurality of wirings that can be trimmed, and the diode connected in parallel is connected to the other of the semiconductor regions. A semiconductor device characterized in that it is electrically connected in series with a formed diode . Each of the two semiconductor regions has a diffusion layer having a high impurity concentration on the sidewall of the trench, and the electrically connected diode has a wiring that forms a contact in the diffusion layer. The semiconductor device according to claim 1, wherein the cathode terminals or the anode terminals are connected via each other. The semiconductor device according to claim 2, wherein the wiring for forming a contact in the diffusion layer is formed of a conductor film embedded in a trench so as to short-circuit the diffusion layer formed in each of the two semiconductor regions. The semiconductor device according to claim 1, wherein the two semiconductor regions are surrounded by an insulating layer and electrically insulated from other regions other than those regions. The semiconductor device according to claim 4, wherein the two semiconductor regions are electrically isolated from the other regions by trench isolation on an SOI substrate. One diode is formed in each of the two semiconductor regions, and one diode is formed in each of the semiconductor regions, and at least two P-type and N-type semiconductor layers constituting the diode are included. 6. The semiconductor device according to claim 1, wherein the impurity concentration and the area of a pn junction formed by these semiconductor layers are the same. The two semiconductor regions are each formed with one diode, and the reverse breakdown voltage of each diode formed in each of the semiconductor regions is set to "5V". The semiconductor device according to any one of the above. Each of the two diodes having a reverse breakdown voltage of 5 V includes an N-type semiconductor layer having an impurity concentration of “5.8 × 10 ¹⁸ cm ⁻³ ” or higher and a P-type having an impurity concentration higher than that of the N-type semiconductor layer. The semiconductor device according to claim 7, comprising: a semiconductor layer comprising: The trimmable plurality of wires each semiconductor device according to any one of claims 1 to 8 comprising a trimmable resistor. The semiconductor device according to claim 9, wherein the trimming resistor is made of CrSiN . Each of the plurality of diodes connected in parallel is electrically separated from each other by a semiconductor layer having a first conductivity type and an insulating layer for element isolation, and the semiconductor layer having the first conductivity type. And a plurality of semiconductor layers of the second conductivity type formed on the surface of the substrate, and the element isolation insulating layer is formed deeper than the semiconductor layer of the second conductivity type. the semiconductor device according to any one of claims 1 to 10 comprising. Insulating layer for the element isolation semiconductor device according to claim 11 which is an insulating film that takes the STI structure. The semiconductor device according to any one of claims 1 to 12 , wherein the plurality of diodes connected in parallel and the reverse breakdown voltage of the diodes connected in series with each other are set to "5V". . Each of the plurality of diodes connected in parallel and the diode connected in series with each of the diodes includes an N-type semiconductor layer having an impurity concentration of “5.8 × 10 ¹⁸ cm ⁻³ ” or more, and The semiconductor device according to claim 13 , comprising a P-type semiconductor layer having an impurity concentration higher than that of the semiconductor layer .

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