JP2005079153A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an applied current of Zener zapping from leaking out to a substrate, and to provide a method of manufacturing a semiconductor device which is capable of making a metal resistance value stable after Zener zap takes place. <P>SOLUTION: The Zener zapping diode is formed on a first diffusion layer 5, a first oxide film 6 is formed on the first diffusion layer 5, a second diffusion layer 8 which is higher in concentration than the first diffusion layer 5 is formed on the surrounding region of the first diffusion layer 5, a second oxide film 9 is formed on the second diffusion layer 8, and a third diffusion layer 10 is formed in a self-aligned manner using the first oxide film 6 and the second oxide film 9 as a mask to serve as an element isolation region. A parasitic transistor which is generated in conjunction with a semiconductor substrate 1 when Zener zapping takes place is restrained from being generated, and a current path can be set stable, and a metal interconnect line 24 can be set stable in shape or directivity. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a manufacturing method for manufacturing a semiconductor device having an element region of a zener zap diode.

  In general, bipolar transistors (hereinafter abbreviated as bipolar Tr) are widely used in integrated circuits (hereinafter abbreviated as IC) that perform analog signal processing. As for IC characteristics, resistance values in the IC or transistor characteristics may deviate from design values due to variations in manufacturing processes. Trimming is achieved by connecting a Zener diode to the adjusting resistor or circuit and applying power in the reverse direction to the PN junction of the Zener diode to break it down as a method of realizing highly accurate IC characteristics that are much smaller than manufacturing process variations. There is a zener zapping method. As this zener zapping, for example, an IC as described in Patent Document 1 is used.

  FIG. 4 is a circuit diagram showing a conventional semiconductor integrated circuit for trimming the circuit characteristics described in Patent Document 1, wherein 31 is a zener zapping diode, 33 is a high potential side terminal, 34 is a low potential side terminal, 35 , 36 is a peripheral circuit, which applies a high voltage to the high potential side terminal 33 and applies a low voltage to the low potential side terminal 34, and applies a constant current from the high potential side terminal 33 to the low potential side terminal 34. The PN junction between the anode and the cathode of the zener zapping diode 31 is broken, and a part of the metal wiring of the cathode is melted to short-circuit the anode and the cathode.

  Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to FIGS.

  FIGS. 3A to 3D are cross-sectional views of intermediate steps showing a conventional method for manufacturing a Zener zap diode in which an epitaxial layer is not grown (hereinafter abbreviated as epi growth). In addition, since this manufacturing method is manufactured by a well-known technique, some process sectional drawing is abbreviate | omitted. Further, since the drawing becomes complicated, some hatching is omitted.

First, a semiconductor substrate 1 made of P-type silicon is thermally oxidized to form a nitride film 3 using a base oxide film 2 and a CVD method. Thereafter, the first resist film 4 is applied, an opening is provided by a photolithography technique (hereinafter abbreviated as “photo technique”), and the nitride film 3 is selectively removed. Thereafter, a dose of 1 × 10 ¹² to 1 × 10 ¹³ cm ⁻² is ion-implanted using an impurity such as phosphorus at an acceleration voltage of 100 to 200 keV to form the first N-type diffusion layer 5 (FIG. 3 (a)). Thereafter, the first N-type diffusion layer 5 has a diffusion depth of 4 to 6 μm and a surface concentration of 3 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ⁻³ by heat treatment. This is the element region.

  Next, after removing the nitride film 3, the second resist film 7b is applied, the resist film 7b is opened on the semiconductor substrate 1 except for the first N-type diffusion layer 5 by a photo technique, and boron is ionized. The third P type diffusion layer 10 is formed by implantation (FIG. 3B). Thereafter, the third P-type diffusion layer 10 has a diffusion depth of 2 to 3 μm by heat treatment, and finally becomes element isolation.

  Next, a third resist film 12 is applied, a predetermined region is opened by a photo technique, boron is ion-implanted, and a P-type anode 13 of a zener zap diode is formed on the surface of the first N-type diffusion layer 5. It forms (FIG.3 (c)).

Next, after removing the base oxide film 2, a predetermined region is opened by a photo technique and arsenic or the like is ion-implanted to form an N ⁺ -type cathode 15 on the surface of the P-type anode 13. Then, boron or the like is ion-implanted to form an external anode 16 of a P ⁺ -type diffusion layer on the surface of the P-type anode 13. Thereafter, a protective oxide film 17 is formed on the surface of the semiconductor substrate 1, and a field oxide film 18 is formed by a CVD method. Finally, the cathode electrode 19 and the anode electrode 20 are formed, and the Zener zap diode shown in FIG. 3 (d) is manufactured.

When a high voltage is applied between the cathode electrode 19 and the anode electrode 20 of the Zener zap diode formed as described above and the voltage becomes equal to or higher than the potential difference at which zener zapping starts, the P-type anode 13 and the N ⁺ -type cathode 15 The PN junction between them is broken, a part of the metal wiring of the cathode is melted, and the anode and the cathode are short-circuited by the metal wiring 24.

FIG. 5 shows the relationship between the cathode voltage and the current until the zener zapping is started. The breakdown voltage is about 3.5V, but a higher voltage is applied, and zener zapping is performed from about 35V at which the cathode current flows from 20 to 300 mA.
JP-A-7-22580

  However, in the conventional technique described with reference to FIGS. 3A to 3D, the cathode 15 has a breakdown voltage or higher and a leak current flows through the anode 13, so that the zener zapping is started until the zener zapping is started. A parasitic bipolar transistor operates between the semiconductor substrates 1 and a part of the Zener Zap current flows into the substrate through the surface of the element region 5 of the Zener Zap. In this case, since the current path at the time of breakdown is not constant, variations occur in the shape or direction of the metal wiring 24 that short-circuits the anode 13 and the cathode 15. That is, the shape of the short-circuited metal wiring 24 is schematic but varies as shown in FIG.

  For this reason, the resistance value after zener zap also remains uneven and cannot be adjusted with high accuracy, degrading the characteristics of the analog circuit. The conventional example has various problems as described above.

  The present invention solves the above-described problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can stabilize the shape or directivity of a metal wiring that short-circuits between an anode and a cathode.

  In order to achieve the above object, the invention according to claim 1 is a trimming circuit for applying a reverse voltage from the outside to short-circuit the zener zap diode, wherein the zener zap diode is in the region of the first diffusion layer. The second diffusion layer is formed in the peripheral region of the first diffusion layer, and the third diffusion layer formed in the region excluding the first diffusion layer and the second diffusion layer is element isolation. A method of manufacturing a semiconductor device constituting a region, comprising: forming a nitride film on a first conductivity type semiconductor substrate; and forming a first resist film having a first opening on the semiconductor substrate. A step of selectively removing the nitride film using the first resist film as a mask; and ion implantation using the first resist film as a mask to form a second conductivity type on the surface of the semiconductor substrate. Form the first diffusion layer A step of selectively oxidizing the surface of the first diffusion layer with the nitride film as a mask to form a first oxide film, the first oxide film on the semiconductor substrate, and the first oxide film Forming a second resist film having a second opening provided in a region including the outer edge region of one oxide film and a third opening provided in a region different from the second opening; A step of selectively removing the nitride film using a second resist film as a mask; and ion implantation using the first oxide film and the second resist film as a mask to the first surface of the semiconductor substrate. Forming a second conductivity type second diffusion layer having a concentration higher than that of the diffusion layer, and selectively oxidizing the surface of the second diffusion layer by using the nitride film as a mask. Forming a film; removing the nitride film; and the first oxide film and the second oxide film. It characterized by having a step of monolayer ion implantation to a mask to form the third diffusion layer of the first conductivity type on a surface of the semiconductor substrate.

  With this configuration, the first diffusion film is formed on the first diffusion layer to be the element region of the Zener zap diode, and the first diffusion film is formed in the opening including the outer edge of the first oxide film. Since the second diffusion layer having a higher concentration than the layer is formed, the parasitic bipolar transistor at the time of zener zap can be suppressed, the zener zap current can be prevented from flowing to the substrate, and stable zener zapping can be performed.

  According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the element region of the zener zap diode is formed in the first diffusion layer and the peripheral region of the first diffusion layer. And the internal collector of the first bipolar transistor with the same impurity concentration and diffusion depth as the first diffusion layer, and the interior of the collector of the second bipolar transistor is the second diffusion layer. The element isolation region is constituted by a third diffusion layer formed in a region excluding the first diffusion layer and the second diffusion layer.

  With this configuration, the internal collector of the high breakdown voltage bipolar transistor (hereinafter abbreviated as bipolar Tr) is formed at the same time as the first diffusion layer which is the element region of the Zener Zap diode, and the internal collector of the low breakdown voltage bipolar Tr is Zener Zap. Since it is formed at the same time as the second diffusion layer that forms the periphery of the first diffusion layer, which is the element region of the diode, a Zener zap diode that can be stably trimmed without adding a new manufacturing process and a high breakdown voltage The bipolar Tr and the low breakdown voltage bipolar Tr can be built in the same substrate. Furthermore, since the third diffusion layer serving as the element isolation region is formed in a self-aligned region except for the first diffusion layer and the second diffusion layer, each element area can be reduced.

  The method for manufacturing a semiconductor device according to claim 1 includes a first oxide film formed on a first diffusion layer that becomes an element region of a Zener zap diode, and an outer edge portion of the first oxide film. Since the second diffusion layer having a higher concentration than the first diffusion layer is formed in the opening of the region, it is possible to reduce the Zener zap current from flowing into the substrate. Furthermore, the zener zap current can be prevented from flowing into the diode peripheral circuit, and the peripheral circuit element can be prevented from being destroyed.

  Therefore, according to the present invention, an excellent method of manufacturing a semiconductor device incorporating a Zener zap diode that can perform stable trimming is realized.

  3. The method of manufacturing a semiconductor device according to claim 2, wherein the internal collector of the high breakdown voltage Tr is formed simultaneously with the first diffusion layer that is the element region of the Zener Zap diode, and the internal collector of the low breakdown voltage bipolar Tr is used for the Zener Zap. Since it is formed at the same time as the second diffusion layer which is formed at the periphery of the first diffusion layer which is the element region of the diode, a Zener zap diode and a high breakdown voltage bipolar capable of stable trimming without adding a new manufacturing process Tr and low breakdown voltage bipolar Tr can be built in the same substrate. Furthermore, since the third diffusion layer for element isolation is formed in a self-aligned region except for the first diffusion layer and the second diffusion layer, the area of each element can be reduced.

  Therefore, according to the present invention, an excellent semiconductor incorporating a zener zap diode capable of performing stable trimming on an analog circuit composed of a high breakdown voltage NPNTr and a low breakdown voltage NPNTr without adding a manufacturing process. An apparatus manufacturing method is realized.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
1A to 1E are cross-sectional views illustrating intermediate steps for explaining a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention. In the following description, the same reference numerals are given to the same components as those in the conventional example.

First, a base oxide film 2 having a thickness of about 50 nm is formed by thermal oxidation on a semiconductor substrate 1 made of silicon having a specific resistance containing P-type impurities of 10 to 20 Ω · cm and a plane orientation of (100). Is used to form a nitride film 3 with a thickness of about 100 nm. Thereafter, a first resist film 4 is applied, a first opening is provided by a photo technique, and the nitride film 3 is selectively removed. Thereafter, phosphorus having a dose of 1 × 10 ¹² to 1 × 10 ¹³ cm ⁻² is ion-implanted at an acceleration voltage of 100 to 200 keV to form the first N-type diffusion layer 5 (FIG. 1A). . Thereafter, the first N-type diffusion layer 5 has a diffusion depth of 4 to 6 μm by heat treatment at 1100 to 1250 ° C., and becomes a part of the element region of the Zener zap diode.

Next, the first oxide film 6 is formed to a thickness of 150 to 300 nm on the surface of the first N-type diffusion layer 5 by using the LOCOS method. After that, a second resist film 7 is applied, and a second opening is provided in a region including the first oxide film 6 and its peripheral region by photolithography, and nitridation exposed in the second opening. The film 3 is selectively removed. Thereafter, using the first oxide film 6 and the second resist film 7 as a mask, phosphorus having a dose of 5 × 10 ^{12 to} 3 × 10 ¹³ cm ⁻² is ion-implanted at an acceleration voltage of 60 to 160 keV. 2 N-type diffusion layers 8 are formed (FIG. 1B). After that, the diffusion depth of the second N-type diffusion layer 8 becomes 2 to 3 μm by the heat treatment, and the first N-type diffusion layer 5 and the second N-type diffusion layer 8 are finally formed of the Zener Zap diode. It becomes an element region.

  Next, after the second oxide film 9 is formed to a thickness of 150 to 300 nm on the surface of the second N-type diffusion layer 8 using the LOCOS method, the nitride film 3 is removed using hot phosphoric acid. Thereafter, boron is ion-implanted with a low acceleration voltage of 50 keV or less through only the base oxide film 2 exposed using the first oxide film 6 and the second oxide film 9 as a mask to form a third P-type diffusion layer 10. (FIG. 1 (c)). Thereafter, the third P-type diffusion layer 10 has a diffusion depth of 2 to 3 μm by heat treatment, and finally becomes element isolation.

Next, after removing all of the base oxide film 2, the first oxide film 6, and the second oxide film 9, a third oxide film 11 is formed on the surface of the semiconductor substrate 1 with a thickness of 10 to 20 nm. After that, the third resist film 12 is selectively opened, and boron with a dose of about 1 × 10 ¹² to 1 × 10 ¹³ cm ⁻² is ion-implanted with an acceleration voltage of 60 to 100 keV, and the first N A P-type anode 13 of a zener zap diode is formed on the surface of the mold diffusion layer 5. The concentration profile of the P-type anode 13 has a surface concentration of 1 × 10 ^{17 to} 9 × 10 ¹⁸ cm ⁻³ and a depth of 0.4 to 0.8 μm (FIG. 1 (d)).

Next, after removing the third oxide film 12, arsenic or the like is ion-implanted selectively using a photo technique to form an N ⁺ type cathode 15 of a zener zap diode on the surface of the P type anode 13. . The concentration profile of the N ⁺ -type cathode 15 has a surface concentration of 2 × 10 ²⁰ to 8 × 10 ²¹ cm ⁻³ and a depth of 0.2 to 0.4 μm. Then, boron or the like is ion-implanted to form an external anode 16 of a P ⁺ -type diffusion layer on the surface of the P-type anode 13. Thereafter, a protective oxide film 17 is formed on the surface of the semiconductor substrate 1, and a field oxide film 18 is formed by a CVD method. Finally, the cathode electrode 19 and the anode electrode 20 are formed by using a known technique, and the Zener zap diode shown in FIG. 1E is manufactured.

In the manufacturing method of the first embodiment configured as described above, the surface concentration of the first N-type diffusion layer 5 in the element region of the Zener zap diode is 3 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ^−3. Since the diffusion depth is 4 to 6 μm, the withstand voltage between the substrates is increased. In the peripheral region of the first N-type diffusion layer 5, the surface concentration is about 1 × 10 ¹⁶ to 8 × 10 ¹⁶ cm ⁻³ , the diffusion depth is 2 to 3 μm, and the second N-type diffusion layer 8 is formed, the current amplification factor of the parasitic PNP transistor operating on the surface between the anode 13 and the substrate 10 is reduced.

Therefore, a reverse voltage of 10 to 40 V is applied to the cathode electrode 19 having a contact size of about 1 μm ² to supply a power of 150 to 250 mA for several ms, and the P-type anode 13 and the N ⁺ -type cathode 15 are connected. When the PN junction is broken, a part of the metal wiring of the cathode is melted, and the anode 13 and the cathode 15 are short-circuited by the metal wiring 24 and zener zapped. At this time, the parasitic PNP transistor operation is suppressed, and the zener zap current does not flow into the substrate through the surface, so that the current path at the time of breakdown is stable and the metal wiring that short-circuits between the anode 13 and the cathode 15 There is no variation in the shape or direction of 24.

(Embodiment 2)
2A to 2F are cross-sectional views illustrating intermediate steps for explaining a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

First, a base oxide film 2 is formed with a thickness of about 50 nm on a semiconductor substrate 1 containing a P-type impurity by thermal oxidation, and a nitride film 3 is formed with a thickness of about 100 nm using a CVD method. Thereafter, a first resist film 4 is applied, a first opening is provided by a photo technique, and the nitride film 3 is selectively removed. Thereafter, phosphorus having a dose of 1 × 10 ¹² to 1 × 10 ¹³ cm ⁻² is ion-implanted at an acceleration voltage of 100 to 200 keV to form the first N-type diffusion layer 5 (FIG. 2A). . Thereafter, the heat treatment at 1100 to 1250 ° C. causes the first N-type diffusion layer 5 to have a diffusion depth of 4 to 6 μm, and finally becomes an internal collector that operates as a transistor with a high breakdown voltage NPNTr.

Next, the first oxide film 6 is formed to a thickness of 150 to 300 nm on the surface of the first N-type diffusion layer 5 by using the LOCOS method. Thereafter, a second resist film 7 is applied and a second opening is formed in a region including the first oxide film 6 and its peripheral region by a photo technique, and a second opening is formed in a region different from the second opening. 3 is provided to selectively remove the nitride film 3 exposed in the second and third openings. Thereafter, phosphorus having a dose of 5 × 10 ^{12 to} 3 × 10 ¹³ cm ⁻² is ion-implanted at an acceleration voltage of 60 to 160 keV using the first oxide film 6 and the second resist film 7 as a mask. Second N-type diffusion layers 8 and 8a are formed (FIG. 2B). Thereafter, the heat treatment makes the diffusion depth of the second N-type diffusion layers 8 and 8 a become 2 to 3 μm, and the second N-type diffusion layer 8 a finally becomes the collector of the low breakdown voltage NPNTr. The first N-type diffusion layer 5 and the second N-type diffusion layer 8 finally become the element region of the Zener zap diode.

  Next, after the second oxide film 9 is formed to a thickness of 150 to 300 nm on the surface of the second N-type diffusion layers 8 and 8a using the LOCOS method, the nitride film 3 is removed using hot phosphoric acid. . Thereafter, boron is ion-implanted with a low acceleration voltage of 50 keV or less through only the base oxide film 2 exposed using the first oxide film 6 and the second oxide film 9 as a mask, and the third P-type diffusion layer 10 is formed. It forms (FIG.2 (c)). Thereafter, the third P-type diffusion layer 10 has a diffusion depth of 2 to 3 μm by heat treatment, and finally becomes element isolation.

Next, after removing all of the base oxide film 2, the first oxide film 6, and the second oxide film 9, a third oxide film 11 is formed on the surface of the semiconductor substrate 1 with a thickness of 10 to 20 nm. . After that, the third resist film 12 is selectively opened, and boron with a dose of about 1 × 10 ¹² to 1 × 10 ¹³ cm ⁻² is ion-implanted with an acceleration voltage of 60 to 100 keV, and the first N A P-type anode 13 of a zener zap diode is formed on the surface of the mold diffusion layer 5. At the same time, the P-type base 13a of the low breakdown voltage NPNTr is formed on the surface of the second N-type diffusion layer 8a and the P-type base 13b of the high breakdown voltage NPNTr is formed on the surface of the first N-type diffusion layer 5 (FIG. 2 (d)).

Next, after removing the third oxide film 11, the fourth resist film 14 is selectively opened, and arsenic or the like is ion-implanted, so that the N ⁺ type of a zener zap diode is formed on the surface of the P-type anode 13. A cathode 15 is formed. Then, at the same time, to form a P-type base 13a, the low voltage NPNTr on the surface of 13b ^{N +} -type emitter 15a and the high-voltage NPNTr ^{N +} -type emitter 15b, further, the surface of the second N-type diffusion layer 8a An N ⁺ -type diffusion layer 15c having a collector contact with a low breakdown voltage NPNTr is formed on the surface, and an N ⁺ -type diffusion layer 15d having a collector contact with a high breakdown voltage NPNTr is formed on the surface of the first N-type diffusion layer 5 (FIG. 2). (E)).

Next, an external anode 16 of a P ⁺ type diffusion layer is formed on the surface of the P type anode 13. At the same time, external bases 16a and 16b of P ⁺ type diffusion layers are formed on the surfaces of the P type bases 13a and 13b. Thereafter, a protective oxide film 17 is formed on the surface of the semiconductor substrate 1, and a field oxide film 18 is formed by a CVD method.

  Finally, the cathode electrode 19 and the anode electrode 20 are formed using a known technique, the collector electrode 21a, the base electrode 22a, and the emitter electrode 23a are formed on the low breakdown voltage NPNTr, and the collector electrode is formed on the high breakdown voltage NPNTr. 21b, base electrode 22b, and emitter electrode 23b are formed. Here, a bipolar semiconductor device in which the zener zap, the low breakdown voltage NPNTr, and the high breakdown voltage NPNTr shown in FIG. 2 (f) are built in the same substrate is manufactured.

Also in the manufacturing method according to the second embodiment configured as described above, the zener zap diode is formed in the first N-type diffusion layer 5, and the surface concentration in the peripheral region is 1 × 10 ¹⁶ to 8 × 10 6. ^Since the second N-type diffusion layer 8 is formed at a diffusion depth of 2 to 3 μm at about ¹⁶ cm ⁻³ , a part of the zener zap current flows into the substrate through the surface. Thus, the zener zapping is stable with a constant current path when the junction between the anode 13 and the cathode 15 is broken.

Further, the first N-type diffusion layer 5b serving as the internal collector of the high breakdown voltage NPNTr is formed at the same time as the first N-type diffusion layer 5 which is a Zener Zap element region, and the surface concentration is 3 × 10 ¹⁵ to 2 ×. Since the diffusion depth is about 10 ¹⁶ cm ⁻³ and 4 to 6 μm, the breakdown voltage between the collector and the substrate and between the collector and the base is increased. This high withstand voltage NPNTr can be used for an IC used in an external device whose power supply voltage is up to about 18V. The second N-type diffusion layer 8a serving as the internal collector of the low breakdown voltage NPNTr is formed at the same time as the second N-type diffusion layer 8 formed at the periphery of the first N-type diffusion layer 5 which is a Zener Zap element region. The surface concentration is about 1 × 10 ¹⁶ to 8 × 10 ¹⁶ cm ⁻³ , the diffusion depth is 2 to 3 μm, and the power supply voltage is about 9V.

  Further, since the third P-type diffusion layer 10 for element isolation is formed in a self-aligned manner with respect to the first N-type diffusion layer 5b and the second N-type diffusion layers 8 and 8a, as in the conventional example. It is not necessary to take a mask alignment margin, and the element area can be reduced.

  Therefore, it is possible to manufacture a semiconductor device including a Zener zap diode that can stably trim the resistance value or circuit characteristics of an analog circuit including a high breakdown voltage NPNTr and a low breakdown voltage NPNTr.

  The present invention is applied to a method for manufacturing a semiconductor device in which a bipolar transistor is mounted without growing an epitaxial layer, and is particularly useful as a method for manufacturing a semiconductor device that enables stable trimming of resistance values or circuit characteristics.

(A)-(e) is sectional drawing which shows each middle process for demonstrating the manufacturing method of the semiconductor device in Embodiment 1 of this invention. (A)-(d) is sectional drawing which shows each middle process for demonstrating the manufacturing method of the semiconductor device in Embodiment 2 of this invention. (D)-(f) is sectional drawing which shows each intermediate process for demonstrating the manufacturing method of the semiconductor device in Embodiment 2 of this invention. (A)-(d) is sectional drawing which shows each intermediate process for demonstrating the manufacturing method of the conventional semiconductor device. Circuit diagram showing a conventional semiconductor integrated circuit for trimming circuit characteristics A diagram for explaining the relationship between cathode voltage and current until zener zapping is started in this type of semiconductor integrated circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Base oxide film 3 Nitride film 4 1st resist film 5 1st N type diffused layer (element area | region of Zener zap diode)
5b First N-type diffusion layer (internal collector of high breakdown voltage NPNTr)
6 1st oxide film 7, 7b 2nd resist 8 2nd N type diffused layer 8a 2nd N type diffused layer (internal collector of low breakdown voltage NPNTr)
9 Second oxide film 10 Third P-type diffusion layer (element isolation)
11 Third oxide film 12 Third resist film 13 Anode 13a, 13b Base 14 Fourth resist film 15 Cathode 15a, 15b Emitter 15c, 15d Collector contact 16 External anode 16a, 16b External base 17 Protective oxide film 18 Field oxidation Film 19 Cathode electrode 20 Anode electrode 21a, 21b Collector electrode 22a, 22b Base electrode 23a, 23b Emitter electrode 24 Metal wiring

Claims (2)

In the trimming circuit for applying a reverse voltage from the outside and short-circuiting the zener zap diode, the zener zap diode is configured in a region of the first diffusion layer, and a second region is formed in the peripheral region of the first diffusion layer. A method of manufacturing a semiconductor device in which a diffusion layer is formed, and a third diffusion layer formed in a region excluding the first diffusion layer and the second diffusion layer constitutes an element isolation region,
Forming a nitride film on a first conductivity type semiconductor substrate;
Forming a first resist film having a first opening on the semiconductor substrate;
Selectively removing the nitride film using the first resist film as a mask;
Ion-implanting the first resist film as a mask to form the first conductivity type first diffusion layer on the surface of the semiconductor substrate;
Forming a first oxide film by selectively oxidizing the surface of the first diffusion layer using the nitride film as a mask;
A second opening provided in a region including the first oxide film on the semiconductor substrate and an outer edge region of the first oxide film, and a third opening provided in a region different from the second opening Forming a second resist film having:
Selectively removing the nitride film using the second resist film as a mask;
Ions are implanted using the first oxide film and the second resist film as a mask to form the second diffusion layer of the second conductivity type having a higher concentration than the first diffusion layer on the surface of the semiconductor substrate. And a process of
Forming a second oxide film by selectively oxidizing the surface of the second diffusion layer using the nitride film as a mask;
Removing the nitride film;
Forming the third diffusion layer of the first conductivity type on the surface of the semiconductor substrate by ion implantation using the first oxide film and the second oxide film as a mask;
A method for manufacturing a semiconductor device, comprising:   The element region of the zener zap diode is composed of the first diffusion layer and a second diffusion layer formed in the peripheral region of the first diffusion layer, and the internal collector of the first bipolar transistor is the first collector. The diffusion layer is configured with the same impurity concentration and diffusion depth, the collector of the second bipolar transistor is configured with the same impurity concentration and diffusion depth as the second diffusion layer, and the element isolation region is formed with the first isolation region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the third diffusion layer is formed in a region excluding the diffusion layer and the second diffusion layer.

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