JP3942213B2 - Semiconductor manufacturing method and inspection method and apparatus therefor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture and inspection of semiconductors such as LSI and DRAM. The present invention also relates to in-line cross-sectional inspection and wiring correction of semiconductors.
[0002]
[Prior art]
In recent years, semiconductors have been miniaturized and multilayered, and their manufacture has become very difficult. Taking LSI as an example, in manufacturing consisting of a large number of processes, it is important to obtain information early by inspecting the cross section of the device in the middle of the manufacturing process and monitoring the manufacturing process. However, since the diameter of the wafer is increased and the price per wafer is increased, the loss is great if the wafer subjected to the cross-sectional inspection is discarded. In view of this, an in-line cross-section inspection technique is required that returns the wafer subjected to the cross-sectional inspection to the production line again and acquires a chip other than the chip subjected to the cross-section inspection as a non-defective product.
[0003]
Japanese Patent Application Laid-Open No. 7-320670 discloses a method and apparatus for performing in-line cross-sectional inspection, device correction, etc. by irradiating ions that do not affect the electrical characteristics of a semiconductor.
[0004]
In JP-A-6-260129, in order to return a sample irradiated with a focused ion beam using Ga as an ion source to the production line again, an ion beam of a gas element that does not significantly affect the characteristics of the sample is used. And a method of depositing an organic metal film so as to cover the Ga-implanted portion using the gas ion beam or energy beam.
[0005]
[Problems to be solved by the invention]
In order to return the semiconductor to the processing apparatus for the next process after the in-line cross-sectional inspection and continue the manufacturing process, the following problems remain in the conventional method. For example, when performing an etching process as a process after the cross-sectional inspection, the following problems occur.
[0006]
(1) In an etching apparatus that detects the end point by monitoring particles and luminescent species sputtered during etching, the exposed material of the focused ion beam processing hole or the material of the organometallic film covering the irradiated portion, When the material of the surrounding surface is different, particles and luminescent species emitted from the focused ion beam processing unit may become noise for end point determination, and accurate end point determination may not be performed.
[0007]
(2) When the focused ion beam processing unit is protected with an organic metal film, and the etching product of the organic metal film is not a material generated by normal etching, a reaction product is deposited inside the etching chamber. As a result, foreign matter is generated.
[0008]
Further, when the process after the focused ion beam process is a material application process, the following problems occur.
[0009]
(3) When there is an extreme difference between the height of the surrounding surface and the height of the focused ion beam processing section, the uneven portion becomes a hindrance to the flow of the coating material, and the material is not applied to the surrounding area, resulting in a pattern defect. It becomes.
[0010]
(4) If there is a difference in the wettability of the coating material between the surface of the metal-organic film covering the focused ion beam irradiation region or the irradiated portion and the other surface, uneven coating occurs, and this also affects the surrounding chips. .
[0011]
Further, when the process after the focused ion beam process is a planarization process using CMP (Chemical & Mechanical Polishing), the following problems occur.
[0012]
(5) When an organic metal film is deposited higher than the surrounding surface, stress concentration occurs on the convex portions, the organic metal film spills out, and the spilled material becomes foreign matter in the CMP abrasive grains, damaging the wafer surface. End up.
[0013]
(6) When the focused ion beam irradiation part is significantly recessed compared with the surrounding area, the CMP abrasive grains enter the cross-section processing hole and cannot be removed even after cleaning, and are transported to the manufacturing apparatus for the processes after CMP. At this time, the CMP abrasive grains jump out of the recesses and become foreign matters, or impurity contamination that changes device characteristics such as threshold voltage.
[0014]
[Means for Solving the Problems]
In the present invention, during the semiconductor wafer manufacturing process, the semiconductor wafer is subjected to cross-sectional inspection, and then a cross-section processing hole is filled, and the manufacturing process is continued by returning to the line again (in-line cross-sectional inspection).
[0015]
Further, according to the present invention, an in-line cross-sectional inspection of a sample is performed before a material applying process for flattening, and the process returns to the flattening material applying process to embed a cross section of the wafer with a flattening material.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart of a semiconductor manufacturing method according to the present invention. After an arbitrary step (n-th step) in the course of the manufacturing process, the wafer 2 is extracted at an arbitrary frequency, and a part of the wafer is subjected to cross-sectional inspection (for example, secondary particles generated by irradiation by scanning of electrons or ions). Is detected and the image is captured and inspected). From this cross-sectional inspection, contact holes and through-holes due to etching residue, etc., photomask pattern defects and wiring formation failures due to foreign matter adhesion, gate oxide film formation failure, alloy spikes and migration, local parts such as foreign matters Defective information such as element identification can be obtained.
[0017]
If it is determined that the cross section inspection is defective, the cross section inspection information, the manufacturing history information obtained from the manufacturing process monitor from the first step to the n-th step, the size of foreign matter in the wafer after any step As a result of foreign matter inspection (for example, dust adhesion), inspection of patterns formed on the wafer after any process (for example, chipping or misalignment), wiring pattern, film thickness, etc. Necessary information is appropriately extracted from CAD information obtained from the design database, and is analyzed in an integrated manner to analyze which process caused the failure.
[0018]
From the result of the failure analysis, the manufacturing process recipe (manufacturing process conditions, prescriptions, etc.) correction, manufacturing process equipment cleaning, photomask pattern improvement, foreign matter management, etc. Take measures (feedback). In addition to performing this manually, the optimum manufacturing conditions can be automatically extracted to correct the manufacturing process recipe.
[0019]
As an example of a specific method of automatic extraction of optimum manufacturing conditions, the relationship between the manufacturing process recipe and the processing result by this recipe is experimentally performed or simulated to create a database in advance. There is a method in which the CPU automatically selects and calculates optimum conditions based on this database. This database can improve the accuracy of automatic extraction of optimum manufacturing conditions by sequentially recording the latest information such as the cross-sectional inspection information, manufacturing history information, foreign matter inspection information, and pattern inspection information.
[0020]
As a result of the cross-sectional inspection, if it is determined to be a non-defective product, the cross-sectional hole portion of the wafer subjected to the cross-sectional inspection is filled, and then the wafer is returned to the semiconductor process line and the subsequent processing is performed. At this time, the chips subjected to the cross-sectional inspection in the wafer are classified into those that can be used thereafter and those that cannot be used depending on the processing mode of the cross-section, as will be described later. Here, even when the result of the cross-sectional inspection is defective, it is possible to debug the manufacturing process after the (n + 1) -th process early by continuing the manufacturing of the wafer after filling the hole. By performing the hole filling, there is no influence on a manufacturing process apparatus that performs processing after wafer manufacturing and cross-sectional inspection.
[0021]
There are various aspects of cross-sectional inspection of any chip in the wafer. In order to examine the uniformity of the in-plane distribution in the wafer, a plurality of chips at appropriate positions in the wafer are inspected, or cross-sectional inspection is performed by randomly selecting the inspection target chips. If the in-plane distribution in the wafer is uniform, one chip may be used for each wafer.
[0022]
The position of the cross-section processing in the chip can be considered as the following three parts. That is, a section for forming a circuit (see, for example, the processed cross-sectional structure in FIG. 7A. This chip cannot be used after the hole filling process), and the cross-section processing is performed in order to obtain a chip for cross-sectional inspection as a non-defective product. Parts that do not have any functional problems even if they are performed (for example, a cross-section of a part of the wiring that is inspected but inspected but does not hinder the conduction of the wiring. This chip can be used after filling the hole), for example Test pattern part that simulates the actual wiring formed on the scribe lane around the chip (if it is a dummy wiring part that can expect the same inspection result as the cross-sectional inspection of the chip, not just the outside of the chip like the scribe lane) (Even if it is inside a chip, the chip can naturally be used after filling in a hole).
[0023]
Next, an outline of the semiconductor manufacturing system of the present invention will be described. FIG. 2 is a diagram showing a semiconductor manufacturing system of the present invention. The various manufacturing apparatuses 1 to 4 include an ion implantation apparatus, a heat treatment apparatus, an oxidation apparatus, an etching apparatus, an exposure / development apparatus, a resist material coating apparatus, a cleaning apparatus, and a CMP apparatus. These manufacturing process apparatuses perform manufacturing based on the process recipe from the process recipe database 5.
[0024]
In addition, the manufacturing apparatuses 1 to 4 have a built-in process monitor and can acquire manufacturing history information such as process abnormality. In an arbitrary step of the manufacturing process, a foreign substance inspection process on the wafer by the foreign substance inspection apparatus 6 and an appearance process on the wafer by the pattern inspection apparatus 7 are appropriately provided. In order to perform an in-line cross-section inspection after the n-th step, the wafer is transferred to the cross-section processing apparatus 8 to perform cross-section processing.
[0025]
Next, a cross-sectional inspection is performed by the cross-sectional inspection apparatus 9. From this cross-sectional inspection information, the quality of the process is determined. If the process is defective, the cross-sectional inspection information, the inspection information from the foreign matter inspection device 6 and the pattern inspection device 7, the first step to the n-th step Defect analysis is performed based on manufacturing history information and design information from a CAD database (not shown). In the process recipe database 5, manufacturing conditions (for example, the first to nth steps of wafers to be manufactured thereafter) (for example, , Plasma power, wafer temperature, plasma pressure, etching time, film formation time, etc.) are manually updated.
[0026]
In addition to the manual fine adjustment and update, as described above, the CPU can automatically extract the optimum manufacturing conditions from the failure analysis result (various manufacturing conditions and their results by experiments or simulations in advance). This is a database in which the CPU extracts the optimum manufacturing conditions). As a result of the cross-sectional inspection, if it is determined that the product is non-defective, the cross-sectional hole filling device 10 is used to embed the cross-sectional hole of the wafer, and then the wafer is returned to the (n + 1) th step to continue the manufacturing process. Further, even if it is determined as defective as described above, it may be returned to the line again in order to debug the manufacturing process at an early stage.
[0027]
Next, an apparatus for performing inline cross-sectional inspection and cross-sectional hole filling will be described. As an example of the cross-section processing apparatus 8, FIG. 3 is a diagram showing a focused ion beam (FIB) processing apparatus which is a cross-section processing apparatus of the present invention. This FIB processing apparatus draws out an ion beam 22 from an ion source 21 in an ion beam column 20 evacuated to 10 to ⁶ to 10 to ⁷ Torr, and includes an accelerating electrode and an ion beam 22 for accelerating the ion beam 22. Irradiation onto the wafer 24 is performed via an ion optical system 23 including an electrostatic lens for focusing, a stigma electrode for performing astigmatism correction of the ion beam 22, and a deflector electrode for scanning the ion beam 22, A desired region is removed by sputtering. 10 evacuated sample chamber 25 is approximately ^1-6 to 10 ~ ⁷ Torr, so that the ion beam 22 to a desired area on the wafer 24 can be irradiated, providing a stage 26 for mounting a sample.
[0028]
Further, the secondary particles generated by the irradiation of the ion beam 22 are detected by the detector 27, an image of the surface of the wafer 24 is taken in, and the processing is positioned. By investigating the relationship between the irradiation time and the processing depth in advance, calculating an appropriate irradiation time from this relationship, and performing irradiation based on this time, it is possible to perform processing to a desired depth. As the ion beam irradiation ion source 21, when liquid metal Ga is used, or when the contamination of the manufacturing process apparatus or the wafer contamination due to the diffusion of Ga irradiated to the wafer 24 is severe, inert gas, N ₂ , A process non-contaminating ion source such as O ₂ or I ₂ is used.
[0029]
In addition to this, FIB assist etching (FIBAE) for supplying a reactive gas from a nozzle (not shown) arranged in the vicinity of the wafer 24 to accelerate the processing can be used for the cross-section processing. Further, instead of the ion beam 22, electron beam assisted etching using a scanning electron beam and processing with a reactive gas is also applicable.
[0030]
Next, the cross section of the wafer 24 is observed by the cross section inspection apparatus 9 to inspect for etching defects and wiring formation defects that have occurred in the manufacturing process. For the cross-sectional inspection, SEM (Scanning Electron Microscope) observation using an electron beam capable of obtaining an image with relatively high resolution is performed, or observation is performed using the FIB of the cross-section processing apparatus 8 described above. Further, local elemental analysis of the cross section can be performed using AES (Auger electron spectroscopy), IMA (ion microanalysis), or the like.
[0031]
Next, the wafer 24 subjected to the in-line cross-sectional inspection is transferred to the cross-sectional hole filling apparatus 10 to fill the cross-sectional hole. FIG. 4 is a diagram showing a laser CVD apparatus which is a cross-sectional hole filling apparatus according to the present invention. This apparatus uses laser CVD (Chemical Vapor Deposition) in which a film is formed by thermal decomposition or photodecomposition by irradiating a laser while supplying a compound material gas. A laser 31 generated by a laser light source 30 is condensed by an optical system 32 and introduced into a vacuum chamber 34 evacuated to 10 to ⁵ to 10 to ⁷ Torr through a laser introduction window 33. In the vacuum chamber 34, the stage 35 on which the wafer 24 is mounted is driven so that the laser can be irradiated to a desired position.
[0032]
A CVD gas 39 is introduced by a gas supply system 36 using either a method of introducing gas into the entire sample chamber or a method of supplying gas by a gas nozzle so as to increase the gas pressure in the vicinity of the sample. During or after gas introduction, the wafer 24 is irradiated with a laser 31 to form a film by decomposing gas molecules by thermal reaction or photoreaction of the surface. A laser beam 31 or a stage 35 is scanned into the cross-section processed hole 37, and the deposited film 38 is formed by irradiating the laser 31 with an appropriate scanning speed or an appropriate number of scans. By investigating the relationship between the irradiation time and the deposited film thickness in advance, calculating an appropriate irradiation time from this relationship, and performing irradiation based on this time, it is possible to form a film with a desired film thickness. Here, an Ar laser, a He—Ne laser, a YAG laser, an excimer laser, or the like is used as the laser light source.
[0033]
The cross-sectional hole filling apparatus 10 can perform CVD using a charged beam in addition to laser CVD. As an example of this, FIBCVD using FIB will be described. FIG. 5 is a diagram showing an FIBCVD apparatus which is a cross-sectional hole filling apparatus according to the present invention. The basic configuration is the same as that of the cross-section processing apparatus 8 in FIG. A difference from the cross-section processing apparatus 8 is that a gas supply system is provided in the sample chamber 25. A CVD gas 39 is supplied to the cross-section processing hole via the gas supply system 36, and the ion beam 22 is irradiated in accordance with the region of the cross-section processing hole. The CVD gas 39 is decomposed by the energy of the ion beam 22, A deposited film 38 is formed.
[0034]
By investigating the relationship between the irradiation time and the deposited film thickness in advance, an appropriate irradiation time is calculated based on this relationship, and the ion beam 22 is repeatedly scanned and irradiated based on this time to obtain a desired film thickness. Can be formed. If the ion source has severe restrictions on wafer contamination due to contamination of Ga, manufacturing process equipment, or diffusion of Ga irradiated to the wafer 24, an inert gas, non-contamination type such as N ₂ , O ₂ , I ₂ , etc. Is used. Further, electron beam CVD (EBCVD) using a scanning electron beam instead of FIB is also possible.
[0035]
In addition, a liquid coating film forming apparatus that applies a small amount of a liquid film forming material and forms a film by any one of heating, thermal decomposition, and photodecomposition by a laser or the like will be described as the cross-sectional hole filling apparatus 10. FIG. 6 is a view showing a liquid coating film forming apparatus which is a cross-sectional hole filling apparatus of the present invention. A stage 40 for mounting the wafer 24 in the atmosphere is installed so that the tip of the glass pipette 42 having the pipette lifting mechanism 41 is above the wafer 24. The liquid material 44 is filled in advance at the tip of the glass pipette 42.
[0036]
An N ₂ introduction port 43 is provided at the rear end of the glass pipette 42, the stage 40 and the pipette vertical mechanism 41 are driven to bring the tip of the glass pipette 42 into contact with a desired position of the wafer 24, and then N ₂ pressure is applied. Then, the liquid material 44 is discharged to form an appropriate amount of liquid pool using the surface tension.
[0037]
Thereafter, the material is solidified using a light source 45 such as a laser. In order to collect the light from the light source, an optical system 46 may be provided as necessary. A desired film thickness can be obtained by examining in advance the relationship between the discharge pressure of N ₂ and the discharge amount of the liquid material and the relationship between the liquid material and the deposited film thickness. In this embodiment, N ₂ is used for discharging the liquid material, but any gas that does not alter the liquid material can be used instead.
[0038]
Next, a method for filling a cross-section and selection of a CVD gas and a liquid material determined by the material of the deposited film will be described. FIG. 7 is a cross-sectional view of a semiconductor for explaining the cross-sectional hole filling method and deposited film material selection method of the present invention. In order to make it easy to observe the wiring state of the vertical cross section, the cross section inspection is performed in such a state that the wafer stage is tilted. Therefore, as shown in FIG. A stepped hole is formed in the cross-sectional portion facing the surface. In order to fill a hole, first, a processing hole such as a scanning region of a charged beam at the time of cross-section processing, a dose amount, a beam residence time, a dot pitch, an assist gas pressure and a flow rate, and a sputtering rate obtained in advance are processed. Find the dimensions.
[0039]
Further, the relationship between the film forming condition and the deposited film thickness is obtained in advance, and the film forming condition is determined so as to be approximately the same as the surrounding height based on this relationship and the processing hole size, and the hole filling is performed. At this time, the allowable accuracy of the hole filling height is appropriate for the wiring film thickness and the interlayer film thickness, and there is no problem if it is in the range of about ± 2 micrometers, but the allowable range varies depending on the manufacturing process. is not. As for the material for filling the hole, if the material of the surface film around the cross-section processed portion is SiO ₂ , the CVD gas is TEOS (tetraorthoethyl silicate) or TEMOS (tetramethylorthosilicate), and the liquid material is silicon compound and Using a liquid obtained by dissolving the additive in an organic solvent, for example, SOG (Spin on Glass), a film is formed of SiO ₂ .
[0040]
As shown in FIG. 7B, if the material of the surface film around the cross-section processed portion is Al, Al is deposited using TIBA (triisobutylaluminum), TMA (trimethylaluminum) or the like as the CVD gas. . In addition, when the material of the surface film around the cross-section processed portion is W, examples of the material gas include W halogen compounds and W (CO) ₆ (tungsten hexacarbonyl).
[0041]
Further, in order not to impair the electrical characteristics of the chip subjected to the cross-section processing, a hole is filled with an insulating film such as SiO ₂ to prevent a short circuit due to the wiring exposure, and Al, W to recover the electric resistance of the wiring. It is also effective to embed a conductive film such as Ti, TiN, or Cu. Although the film formation using the same material as the surface material around the processing hole has been described here, it is also effective to form the film using the same material of the constituent elements. It is also effective to form a film with the same constituent material as the main component.
[0042]
Next, a second embodiment of the present invention will be described. In manufacturing a multi-layer semiconductor, planarization may be performed by an interlayer insulating film. A method of observing a cross section immediately before laminating such a flattened film and embedding a cross-section processed hole with the flattened film will be described. FIG. 8 is a flowchart of the semiconductor manufacturing method according to the second embodiment of the present invention. In FIG. 8, the case where the flattening process is an SOG (Spin on Glass) coating process which is a material for depositing SiO ₂ is described. If the (n + 1) th step is an SOG coating step, a cross-sectional inspection is performed after the completion of the nth step, a failure analysis is performed as described above, and measures are taken from the first step to the nth step as necessary. If it is a non-defective product, returning to the (n + 1) th step has the advantage that the step of embedding the processed hole is not required because the cross-section processed hole is embedded by SOG application in the (n + 1) th step.
[0043]
FIG. 9 is a cross-sectional view of the semiconductor wafer before and after the cross-sectional hole filling process by SOG application. As shown in the figure, the SOG enters the cross-sectional hole, and as a result, the hole is filled.
[0044]
As described above, in the first and second embodiments, the in-line cross section inspection has been described. However, the present invention can be applied to a technique for correcting wiring in-line.
[0045]
【The invention's effect】
By embedding cross-section processed holes after in-line cross-section inspection of the sample, it is possible to stabilize the end point determination in the etching process after cross-section inspection (for example, Al or W wiring is exposed without embedding the cross-section processed holes) In the etching for SiO ₂ that covers the wiring of the other part that has not been processed in cross section, the end point determination signal is detected from the wiring that has been processed in cross section before the end point determination by exposing the wiring of the other part. In addition, it is possible to prevent an increase in foreign matter inside the etching chamber (if, for example, Al or W wiring is exposed without embedding a cross-section processing hole, Al or W is scattered by the plasma and the inside of the chamber is scattered. As foreign matter that cannot be removed by the cleaning process).
[0046]
In addition, by embedding a hole whose cross section has been processed after the inline cross section inspection of the sample, it is possible to apply the material without hindering the flow of the material in the material application step after the cross section inspection.
[0047]
Furthermore, after the in-line cross section inspection of the sample, by embedding the cross-section processed hole, in the CMP flattening process after the cross-section inspection, the stress concentration due to the cross-section processed portion becoming convex, or the CMP abrasive grains due to the concave shape Can be prevented.
[0048]
As described above, by performing in-line defect analysis by cross-sectional inspection, information can be acquired at an early stage to optimize manufacturing conditions, and the line can be stabilized at an early stage. In particular, the size of the device is reduced, the multi-layer stacking is progressing, and it is extremely effective for the present and future semiconductor manufacturing in which a small number of various products are produced.
[0049]
In addition, it is possible to eliminate the loss of wafer disposal due to cross-sectional observation as in the prior art, and to realize high-efficiency and high-yield production.
[Brief description of the drawings]
FIG. 1 is a flowchart of a semiconductor manufacturing method according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a semiconductor manufacturing system according to a first embodiment of the present invention.
FIG. 3 is a diagram showing a focused ion beam processing apparatus which is a cross-section processing apparatus according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a laser CVD apparatus which is a cross-sectional hole filling apparatus according to the first embodiment of the present invention.
FIG. 5 is a diagram showing a FIBCVD apparatus which is a cross-sectional hole filling apparatus according to the first embodiment of the present invention.
FIG. 6 is a diagram illustrating a liquid coating film forming apparatus which is a cross-sectional hole filling apparatus according to the first embodiment of the present invention.
FIG. 7 is a diagram illustrating a cross-sectional hole filling method and a deposited film material selection method according to the first embodiment of the present invention.
FIG. 8 is a flowchart of a semiconductor manufacturing method according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view of a semiconductor wafer before and after cross-sectional hole filling processing by SOG application according to a second embodiment of the present invention.
[Explanation of symbols]
5 Process Recipe Database 6 Foreign Object Inspection Device 7 Pattern Inspection Device 8 Cross Section Processing Device 9 Cross Section Inspection Known 10 Cross Section Filling Device 20 Ion Beam Column 21 Ion Source 22 Ion Beam 24 Wafer 26 Stage 27 Detector 30 Laser Light Source 36 Gas Supply System 37 Cross Section Processing hole 38 Deposited film 39 CVD gas 42 Glass pipette 43 N ₂ inlet 44 Liquid material 45 Light source 46 Optical system

Claims (8)

After any process in the process of manufacturing a semiconductor wafer,
Processing locally to expose a cross section of the semiconductor wafer;
Inspect the cross section,
When it is determined as defective in the inspection, the cross-sectional inspection information, the manufacturing history information up to the arbitrary process, the inspection information of the foreign matter in the wafer up to the arbitrary process, the wafer formed up to the arbitrary process Perform defect analysis of the semiconductor wafer based on pattern inspection information, information appropriately extracted from design information,
Correct manufacturing conditions up to the arbitrary process based on the failure analysis results,
A small amount of a liquid material is applied to a portion removed to expose a cross section of the semiconductor wafer using a glass pipette, and the applied liquid material is irradiated with an energy beam to remove the removed portion with an insulating film having a desired film quality. embedded,
The method for producing a semiconductor wafer, wherein the semiconductor wafer is returned to the next step after the arbitrary step and the production is continued. After any process in the process of manufacturing a semiconductor wafer,
Processing locally to expose a cross section of the semiconductor wafer;
Inspect the cross section,
When it is determined that the inspection is defective, the semiconductor wafer is analyzed for defects based on the cross-sectional inspection information,
Based on the failure analysis results, the optimum manufacturing conditions up to the arbitrary process are extracted by a computer that has a database of various manufacturing conditions, and the manufacturing conditions up to the arbitrary process are corrected,
A small amount of a liquid material is applied to a portion removed to expose a cross section of the semiconductor wafer using a glass pipette, and the applied liquid material is irradiated with an energy beam to remove the removed portion with an insulating film having a desired film quality. embedded,
The method for producing a semiconductor wafer, wherein the semiconductor wafer is returned to the next step after the arbitrary step and the production is continued. After any process in the process of manufacturing a semiconductor wafer,
Processing locally to expose a cross section of the semiconductor wafer;
Inspect the cross section,
When it is determined as defective in the inspection, the cross-sectional inspection information, the manufacturing history information up to the arbitrary process, the inspection information of the foreign matter in the wafer up to the arbitrary process, the wafer formed up to the arbitrary process Perform defect analysis of the semiconductor wafer based on pattern inspection information, information appropriately extracted from design information,
Based on the failure analysis results, the optimum manufacturing conditions up to the arbitrary process are extracted by a computer that has a database of various manufacturing conditions, and the manufacturing conditions up to the arbitrary process are corrected,
A small amount of a liquid material is applied to a portion removed to expose a cross section of the semiconductor wafer using a glass pipette, and the applied liquid material is irradiated with an energy beam to remove the removed portion with an insulating film having a desired film quality. embedded,
The method for producing a semiconductor wafer, wherein the semiconductor wafer is returned to the next step after the arbitrary step and the production is continued. In the manufacturing method of the semiconductor wafer according to any one of claims 1 to 3,
A method of manufacturing a semiconductor wafer, wherein a processing position of the semiconductor wafer is a place that does not affect electrical characteristics of devices in the semiconductor wafer. In the manufacturing method of the semiconductor wafer described in any one of Claims 1 thru | or 4,
A method of manufacturing a semiconductor wafer, comprising embedding a processed portion of the semiconductor wafer to a height substantially equal to a surface of a surrounding unprocessed portion. In the manufacturing method of the semiconductor wafer described in any one of Claims 1 thru | or 4,
A method of manufacturing a semiconductor wafer, comprising embedding a processed portion of the semiconductor wafer so that a difference in height from a surface of a peripheral unprocessed portion is within ± 2 micrometers. In the manufacturing method of the semiconductor wafer described in any one of Claims 1 thru | or 6,
A method of manufacturing a semiconductor wafer, comprising embedding a processed portion of the semiconductor wafer with a material of the same constituent element as a material of a surface of an unprocessed portion or a material containing the same constituent element. In the manufacturing method of the semiconductor wafer described in any one of Claims 1 thru | or 6 ,
A method of manufacturing a semiconductor wafer, wherein the insulating film is SiO ₂ .

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