JP3929381B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3929381B2
JP3929381B2 JP2002291803A JP2002291803A JP3929381B2 JP 3929381 B2 JP3929381 B2 JP 3929381B2 JP 2002291803 A JP2002291803 A JP 2002291803A JP 2002291803 A JP2002291803 A JP 2002291803A JP 3929381 B2 JP3929381 B2 JP 3929381B2
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substrate
semiconductor element
land
wiring
semiconductor device
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JP2004128290A (en
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康弘 中
直敬 田中
孝洋 内藤
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に関し、特に、半導体素子とそれを搭載する基板を備えた半導体装置に関する。
【０００２】
【従来の技術】
高性能、高機能、小型化が加速されている電子情報機器に搭載される半導体パッケージには、従来以上に動作周波数の高速化、実装面積の小型化が求められており、半導体装置が搭載されるマザーボードとの間のはんだ接続部は、多ピン、狭ピッチ化が進んで、微細化している。さらに、マザーボードに搭載される、半導体パッケージ他、様々な電子部品の搭載密度も高くなる一方で、はんだ接続部への負荷が増加し、信頼性確保が重要な課題となっている。
【０００３】
これを解決して、さらに高信頼化を図るために、例えば、以下の公知例がある。
特開平11-97575号公報では、最外周に沿って位置する最外周電極について、隣接する最外周電を結んでできる多角形の内側から引き出すようにする形態が開示され、半導体装置が搭載された機器が落下した際の衝撃など、外力による外周部はんだ接続部の破壊を防止しようとしている。
【０００４】
前記特開2000-261110号公報では、基板60上の変形中心０を基点として、各電極パッド６０１から放射方向に沿って内側に引き出されるように形成された、基板60を備えた半導体素子を搭載する搭載基板の構造が開示されており、電極パッドの強い接合強度を得ようとするものである。
【特許文献１】
特開平11-97575号公報（図２、及びその説明）
【特許文献２】
特開2000-261110号公報（図１、及びその説明）
【０００５】
【発明が解決しようとする課題】
しかし、特開平11-97575号公報に記載の形態では、環境温度の変化などによって生じる熱応力による疲労破壊は、破壊メカニズムが外力による破壊とは異なるため防止することができない。例えば、実際に、信頼性評価のために、125℃〜-55℃の温度サイクル試験を実施した場合、内周部のバンプでも断線不良が生じる場合がある。内周部のバンプの断線は、ほとんどの場合、はんだに生じるき裂によるものではなく、ランド配線に生じたき裂による断線である。
【０００６】
また、特開2000-261110号公報に記載の形態では、基板60が搭載される搭載基板上の構造を開示しているが、基板60の搭載面でのランド構造の開示はない。このため半導体が搭載された基板とそれを搭載する搭載基板との間の接続部が熱応力による損傷を効果的に抑制することは困難である。
【０００７】
本発明は、前記従来技術で十分解決できなかった上記課題を解決することを目的とする。
【０００８】
【課題を解決するための手段】
本発明によって前記課題を解決し、この熱応力によるはんだ接続部断線を抑制する。
以下にその具体的形態例を記載する。
（１）半導体素子の外縁コーナ部の外部端子の配線を内側に引き出す形態に関する。具体的には、半導体素子と、前記半導体素子が搭載された第一の基板と、前記第一の基板の前記半導体素子搭載面と反対側面に形成された複数の外部端子と、前記反対側面に形成され、前記外部端子に連絡する配線と、を有し、前記第一の基板での前記半導体素子の外縁に対応する位置より内側であって、前記外縁の主辺に沿って仮想した線が交わる位置に最も近い領域に位置する第一の外部端子から伸びる前記配線は、前記第一の外部端子の中心から前記基板の前記半導体素子の中心を結ぶ線分となす角が９０度以下になるように前記第一の外部端子からの引出し部が位置することを特徴とする半導体装置である。
（２）第一の基板の最内周の外部端子の配線の引き出す形態に関する。具体的には、半導体素子と、前記半導体素子が搭載された第一の基板と、前記第一の基板の前記半導体素子搭載面と反対側面に形成された複数の外部端子と、前記反対側面に形成され、前記外部端子に連絡する配線と、を有し、前記第一の基板の最も中心側に配列される第一外部端子から伸びる前記配線は、前記第一の外部端子の中心から前記基板の前記半導体素子の中心を結ぶ線分となす角が９０度以下になるように前記第一の外部端子からの引出し部が位置することを特徴とする半導体装置である。
（３）ビアホールの配置に関するものである。具体的には、半導体素子と、前記半導体素子が搭載された第一の基板と、前記第一の基板の前記半導体素子搭載面と反対側面に形成された複数の外部端子を備え、第一の外部端子は、前記第一の外部端子に電気的に連絡され、前記反対側面に沿って形成される第一の配線と、前記配線に電気的に連絡される前記基板の厚さ方向に形成される第一のビアホールを有し、第二の外部端子は、前記外部端子の前記第一の基板側主面に電気的に連絡される前記基板の厚さ方向に形成される第一のビアホールを有し、前記第一の基板での前記半導体素子の外縁に対応する位置より内側であって、前記外縁の辺に沿って引いた線が交わる位置に最も近い領域に位置する外部端子或いは前記第一の基板の最も中心側に配列される前記外部端子には前記第一の外部端子が配置されることを特徴とする半導体装置である。
（４）前記（１）から（２）の何れかにおいて、前記半導体素子の前記外縁に位置する領域より外側に位置する第二の外部端子の配線は、前記第一の外部端子で形成されるのと異なる角度を形成する方向になるように前記第一の外部端子からの引出し部が位置することを特徴とする。
（５）多角形状の半導体素子と、前記半導体素子が接着剤を介して搭載される多角形状の第一の基板と、前記第一の基板の前記半導体素子が配置される面の反対側の面に外部との電気的接続のための複数の外部端子、前記外部端子に連絡する配線及び前記配線を被う絶縁膜を有し、前記外部端子から間隔を介して前記絶縁膜の端が形成され、前記第一の基板での前記半導体素子の外縁に対応する位置より内側であって前記半導体素子の外縁における隣接する主辺の交点に最も近い第一の外部端子の配線は、前記第一の外部端子の中心と前記半導体素子の中心に対応する位置とを結ぶ線分となす第一の角度の方向から前記第一の外部端子に連絡されており、前記第一の基板の外縁における隣接する主辺の交点に最も近い第二の外部端子の配線は、前記第一の外部端子より大きい第二の角度を形成する方向から前記第二の外部端子に連絡されていることを特徴とする半導体装置である。
【０００９】
なお、例えば、前記第一の角度は９０度以内の方向である。前記第二角度は９０度以上の方向である。
【００１０】
また、前記構成は、前記外部端子とソルダレジスト等の前記絶縁膜との重なりがないように、外部端子の上部面の端部と間隔を介して前記絶縁膜の表面端部（表面の開口端部）が形成される。
（６）多角形状の半導体素子と、前記半導体素子が接着剤を介して搭載される多角形状の第一の基板と、前記第一の基板の前記半導体素子が配置される面の反対側の面に外部との電気的接続のための複数の外部端子、前記外部端子に連絡する配線及び前記配線を被う絶縁膜を有し、前記外部端子から間隔を介して前記絶縁膜の端が形成され、前記第一の基板の最も中心側に配列される第一の外部端子の配線は、前記第一の外部端子の中心と前記半導体素子の中心に対応する位置とを結ぶ線分となす第一の角度の方向から前記第一の外部端子に連絡されており、前記第一の基板の外縁における隣接する主辺の交点に最も近い第二の外部端子の配線は、前記第一の外部端子より大きい第二の角度を形成する方向から前記第二の外部端子に連絡されていることを特徴とする半導体装置である。
（７）多角形状の半導体素子と、前記半導体素子が接着剤を介して搭載される多角形状の第一の基板と、前記第一の基板の前記半導体素子が配置される面の反対側の面に外部との電気的接続のための複数の外部端子、前記外部端子に連絡する配線及び前記配線を被う絶縁膜を有し、前記外部端子から間隔を介して前記絶縁膜の端が形成され、第一の外部端子は、前記第一の外部端子に電気的に連絡され、前記反対側面に沿って形成される第一の配線と、前記配線に電気的に連絡される前記基板の厚さ方向に形成される第一のビアホールを有し、第二の外部端子は、前記外部端子の前記第一の基板側主面に電気的に連絡される前記基板の厚さ方向に形成される第一のビアホールを有し、前記第一の基板での前記半導体素子の外縁に対応する位置より内側であって前記代位置の基板の外縁における隣接する主辺の交点に最も近い領域に位置する外部端子及び、前記第一の基板での前記半導体素子の外縁に対応する位置より内側であって、前記外縁の延長線が交わる位置に最も近い領域に位置する外部端子或いは前記第一の基板の最も中心側に配列される前記外部端子には前記第一の外部端子が配置されることを特徴とする半導体装置である。
【００１１】
前記（１）他で記載した、中心、とは、例えば、半導体素子の中心とは素子の角を結ぶ最も長い２つの対角線の交点であり、外部端子の中心とは円形の場合は直径を形成する線の中央であり、多角形の場合は最も長い２つの対角線の交点である。
【００１２】
また、前記（５）他で記載した、多角形状、とは、例えば、四角形状の場合であれば、四角形を形成する４つの主辺が必ずしも直線でなくとも曲率を有しても良く、隣接する主辺の交点の角部は直交していなくとも、曲率を有しても良く、角部を切り落として隣接する主辺を結ぶ前記主辺より短い辺を形成していても良く、全体形状としては四角形と判別できる形状をなしていればよい。
【００１３】
また、前記で記載した、（）前記第一の基板での前記半導体素子の外縁に対応する位置より内側であって前記代位置の基板の外縁における隣接する主辺の交点に最も近い領域に位置する外部端子と、前記第一の基板の外縁における隣接する主辺の交点に最も近い外部端子とが同じ外部端子を指すことになる場合は、前記した前者（外縁コーナーの外部端子）についての規定に従うようにする。
【００１４】
【発明の実施の形態】
以下、本発明を採用した半導体装置の実施例を詳しく説明する。なお、本発明は、本明細書に記載した形態に限定するものではなく、開示した形態から周知技術、或は新たに生じた技術に基づく変形を許容するものである。
図1に、本発明の第１の実施例の半導体装置の形態の概要を示す。各々、断面模式図（a）、およびはんだボール取付前の基板１の底面（搭載基板との接続面）の平面模式図（ｂ）を示す。基板（インターポーザ）1上にエポキシ樹脂系接着材2などを介して半導体チップ3を搭載し、Auなどのワイヤ4を使用して、基板とチップとをボンディング接続して電気的接続を図った後、エポキシ樹脂系封止材5などにより半導体チップ3を被うように封止される。例えば、半導体チップ3の基板１に面する主面以外の面にかかるように形成される。
【００１５】
半導体チップ3は、インターポーザである基板１と対向する主面と反対側主面にトランジスタ回路が形成されている。
【００１６】
基板１は、ガラスエポキシなどの樹脂材料をコア材料として形成される。基板１には、Cuなどの導電材料により配線が施されており、表面には接続用のCuなどの導電材料から成るランド6が外部端子として設けられる。
【００１７】
熱応力による接続部の断線防止のため、少なくとも、チップ輪郭コーナー部のランドの配線は、ランド中心とチップ搭載領域の中心とを結ぶ線分となす角90度以内の方向へ引出される（図1では、チップコーナー部のランド配線のみ、部分的に図示した）。これによって、半導体装置の熱応力に伴う断線を抑制して、高性能の半導体装置を形成することができる。ランドに、Sn-Pbまたは環境問題を考慮したPbフリー（Sn-Ag-Cuなど）のはんだボール9が取付けられ、搭載基板10に取付けられる。なお、本発明の本質とは関係ない、詳細な配線構造などの説明は省略する。
【００１８】
なお、本実施例のランド６の構造の具体例、図21に示す。絶縁層22の上に形成されたランド６から基板表面に沿って配線であるランドからの引き出し線8が形成されている。ランド6から離れた位置に、引き出し線8に連絡するように導電性部材を備えたビアホール14が設けられ、基板１内部と電気的に連絡している。一例としては、前記ビアホール14は基板内部に形成される内部配線21に連絡していてもよい。絶縁膜としてのソルダレジスト７が絶縁層２２の上に形成される。ソルダレジスト７の端部はランド６の端部に対して間隔を介して配置されている。好ましくは、ランド６付近のランド全体が露出するように開口部を設けて、基板表面は絶縁のため樹脂であるソルダレジスト7で覆われる。ランドから引出される配線8は、少なくとも一部がソルダレジスト７開口部から露出しており、ソルダレジスト７開口端が位置している。
【００１９】
また、基板１の最も外周に位置するランド６のうち、チップ搭載中心から最も離れた領域のランド６の配線８について、そのランド６中心と半導体チップ３中心に相当する位置を結ぶ線分となす角が９０度以下になるようにランド６からの引き出し配線８を形成する。前記のランド６は、言い換えれば基板６での半導体チップ３の外縁に対応する位置（破線で記載）より内側であって、前記外縁に沿った線が交わる位置に最も近い領域に位置するランド６から伸びる前記配線に適用する。このようにすることにより、熱応力に伴う外周のランド付近の配線の断線を抑制することができる。
【００２０】
また、半導体チップ３の外縁部コーナに形成されるランドから引き出される配線８において、チップ中心に相当する位置とランド中心とのなす角より、基板１の最外周に位置のコーナに形成されるランドから引き出される配線８における前記なす角の方が大きくなる。これにより、熱応力によって影響の大きい領域においてその応力に適切に対応した対策を施すことができるので、装置全体としての熱応力にともなう破損を効果的に抑制することができる。具体的には以下のようになる。
【００２１】
半導体チップ３の外縁部のコーナに位置するランド６から引き出される配線を、チップ中心に相当する位置とランド中心とのなす角（θ1〜θ4）が90度以内になるようにすることが好ましい。また、基板１の最外周に位置するランドのうちコーナーに位置するランド６から引き出される配線を、チップ中心に相当する位置とランド中心とのなす角（θ5〜θ8）が90度以上になるようにすることが好ましい。なお、図２４に図１の（ｂ）の詳述した一例を示す。基本的な構成は図１(b)と同様である。前記した半導体チップの外縁のコーナ部に最も近いランドの近傍には前記最も近いランドの配線引き出し方向と同様の方向に配線を引き出すランドを備える。その場合、最外周のコーナーのランドの近傍のランドも同様である。
【００２２】
一方、半導体チップ３の外縁の外側に配置されるランドであって、前記規定したランド以外のランド（例えばランドのうち最外周あるいは最内周のランドとの間に位置するランド）は、前記規定したランドから引き出される配線方向とは異なる方向に引き出される配線を有する。前記熱応力による配線の断線を抑制しつつ、基板の小型化を図るためである。
【００２３】
熱応力による、はんだ接続部の破壊メカニズムを解明するため、3次元モデルを用いた有限要素解析を行った。図5に、解析モデルの概略構造を示す。搭載基板上に基板に半導体素子を搭載した半導体装置が配置されている。破線はチップの外縁の位置を示し、ランドをアレイ状に配置する形態とする。本解析では、全体の1／４の領域について解析を行った。なお、本解析では、はんだ接続部界面における最大応力発生位置が明確となり、応力発生メカニズムの把握に都合が良いため、ランド構造はSMDとした。図6に、125℃〜-55℃の温度サイクルを弾塑性解析したときの、1サイクル当たりはんだに生じるひずみ振幅Depeq（相当塑性ひずみ範囲）(6a)と、ランドに生じる応力振幅Ds（冷却過程で引張応力が増加する場合を正、減少する場合を負とした）の分布図(6b)をそれぞれ示す。なお、はんだのひずみは、最外周コーナー部で大きくなった。また、チップ（半導体素子）輪郭コーナー部に近いランドで、同様に大きくなった。一方、ランドに生じる応力は、チップコーナー部のランドで最大となり、外周コーナー部の応力は、その半分程度であった。特に、チップコーナ部のランドでは半導体チップ中心側がに比べて外側が非常に大きな応力が生じ、一方、最外周コーナー部のランドでは、反対に、中心側の方が外側より大きな応力を生じた。
【００２４】
図7に、はんだ接続部の熱応力発生メカニズムを模式的に示す。半導体装置は昇温して搭載用基板と溶融接合（リフロー）されるので（一例としては約250℃）、125℃の高温時には熱応力はゼロに近く、冷却過程で、線膨張係数差に起因して、図7のような熱変形を伴い、熱応力が発生すると考えられる（一例としては、基板の線膨張係数が通常、12〜18 ppm/K程度であるのに対して、封止樹脂は9〜12 ppm/K程度、チップは3 ppm/K程度である。）。外周コーナー部のバンプには、主に、せん断変形によるせん断力が負荷され、熱応力が発生するのに対し、チップコーナー部のバンプには、せん断力に加えて、半導体装置の反り変形による回転力（モーメント力）が負荷され、熱応力が生じていると考えられる。この回転力により、チップコーナー部バンプのランドに、特に大きな応力が生じると考える。図8のように、バンプ1個とその近傍のみを取出したモデルを用いて、せん断力および回転力を負荷し、その影響を調べた。せん断力のみを負荷した場合と、せん断力、回転力両方を負荷した場合とで比較した結果、はんだのひずみの差に比べて、ランドに生じる応力は、回転力が加わった方が、大幅に大きくなった。このように、熱応力による接続不良防止するためには、まず、再内周側のランドまたは、半導体チップの外縁の内側であって、外縁の線の交点に最も近いランドについて対策することにより効果的な対策を図ることができる。
【００２５】
SMD構造でははんだにクラックが発生して接続不良になる傾向が高いのに対して、NSMD構造では、配線の断線により接続不良になる傾向が高く、配線の断線にはひずみよりも応力の影響が大きい。NSMD構造とした場合、ランド配線は、チップコーナー部のバンプで最も断線が生じやすく、それを本発明で効果的に対策することにより、他のランド配線の引回しの自由度を高めることができ、小型化などに寄与することができる。
【００２６】
熱応力によるはんだ接続部断線を防止するために、この領域のランドから引き出される配線の向きを、大きな応力が発生する方向を避けて配向させることが有効であることを見出した。例えば、ランド部の応力が最も大きくなるチップコーナー部では、図6(b)のように、ランドの半導体装置コーナー側に近い位置で最大応力が生じるため、これを避けた位置に配線を引出すようにする。ランド配線の引き出し部は、ランド中心とチップ搭載エリアの中心とを結ぶ線分となす角90度以内の方向へ引出されることが望ましい。
【００２７】
図9に、ランドからの配線引出し方向と応力の関係を示す。横軸は、応力が最大となる引き出し方向からの傾きとし、縦軸は、最大応力（配線傾き0度のときの応力）を1とした場合の、配線部の応力である。ランドからの引き出し方向を応力が大きくなる方向を避けて、特に、９０度以上避けることによって応力を効果的に低減することができる。好ましくは、１８０度に近い方が良い。製造制度などの観点から135度以上避けることが好ましい。よって、言い換えれば、ランド中心とチップ搭載エリアの中心などの基板中心側とを結ぶ線分とのなす角は、半導体チップ外縁内の外縁コーナー部、或は最内周ランドのコーナ部では45度以内の方向であることが好ましい。一方、最外周ランドのコーナー部では、135度以上の方向であることが好ましいということになる。
【００２８】
また、はんだを起点とした破壊の防止に関しては、最大ひずみが生じる方向に配線が引き出され、同位置で配線とはんだが接触すると、はんだへのひずみ集中が助長され、寿命が低下するため、最大ひずみ発生位置を避けた方向にランド配線を引き出すことが有効である。図6より、ランド部内の最大応力が生じる位置と、はんだ内の最大ひずみが生じる位置は比較的一致しているため、前述のような方向へランド配線を引出すことによって、配線の断線を防止し、はんだの断線を抑制できる。チップの輪郭線の近傍数列分のバンプでは、応力発生メカニズムを考慮すれば、ランド部の応力は、チップコーナー部と同レベルに大きくなることが予測されるため、チップ輪郭線近傍数列のバンプのランド配線は、同様に、ランド中心とチップ搭載エリアの中心とを結ぶ線分となす角90度以内の方向へ引出されることが望ましい。
【００２９】
さらに、外周コーナー部のバンプに関して、はんだ内の最大ひずみが生じている位置から判断して、ランド中心とチップ搭載エリアの中心とを結ぶ線分となす角90度以上の方向へ引出されることが望ましい。より好ましくは、最外周部バンプのランド配線を、ランド中心とチップ搭載エリアの中心とを結ぶ線分となす角90度以上の方向へ引出されるよう形成することが望ましい。過半数以上、より好ましくは８割以上形成されることが好ましい。最外周部に位置するバンプのはんだ内のひずみは、大きな応力レベル下にあると予測されるためである。
【００３０】
本発明の前記形態を適応するに好適なランド構成としては、ランドの側壁に接着剤であるはんだが及ぶように接続されているものである。また、言い換えれば、ランドの上部主面端部まではんだが及ぶタイプである。前記配線の引き出し方向による作用と相まって、熱応力による接触不良を効果的に抑制できるからである。図2に、比較例の半導体装置のはんだ接続部構造を模式的に示す。図2のように、はんだと接続するランドの端部が絶縁樹脂（ソルダーレジスト）で覆われたSMD（Solder Mask Defined）と呼ばれる構造では、例えば、環境温度の変化によって生じる熱ひずみは、はんだとソルダーレジストとが接触する点（図2中A点）に集中する。これに対し、図3に示す、ランドがソルダーレジストから露出したNSMD（Non- Solder Mask Defined）と呼ばれる構造では、ひずみの集中部が基板部（図3中B点）となるため、はんだ部のひずみは軽減され、高信頼化が実現できる。一方、通常、ランドには、図4のように配線が接続されているため、配線とはんだの接触部（図4中C点）にひずみが集中し、配線側にき裂が発生する場合があるため、前述の引き出し線の方向を適正化することにより効果的に不良を抑制することができる。
【００３１】
図10に、ランド部応力のはんだ接続高さ依存性を示す。ここでの、はんだ接続部径は、0.35 mmである。ランド部に生じる応力は、はんだ接続高さが低くなるほど低下している。ランド部応力は、半導体装置の反り変形による回転力の影響が大きいと前述したが、はんだ接続高さが低くなることにより、回転力の作用点と回転中心との距離が小さくなるため、回転力が低下すると考えられる。従って、ランド配線断線を防止するためには、はんだ接続高さは低い方が有利であり、はんだボールを使用せずはんだペースト剤のみで半導体装置を接続する、LGA（Land Grid Array）方式が有利といえる（LGAの場合、通常、はんだ接続高さは0.1 mm以下となる）。また、ランド配線断線を防止する観点から、よりき裂進展寿命を長くするため、配線幅は広い方が良い。
【００３２】
図12に、本発明の第2の実施例の半導体装置の断面模式図および底面（搭載基板との接続面）の平面模式図を示す。基本的には第1の実施例と同様であるが、第2の実施例においては、チップがパッケージサイズに比して小さく、チップ搭載領域内にバンプが存在しない形態である点が特徴の1つである。なお、それ以外の構造、材料構成、製造方法は、第1の実施例と同一である。しかし、さらに熱応力による接続部の断線を防止し、寿命向上を図るため、少なくとも、最内周コーナー部のランドの配線において、第１の実施例同様にランド中心と半導体装置の中心とを結ぶ線分となす角90度以内の方向へ引出される。なお、チップ搭載領域内にバンプが存在しない構造の半導体装置の場合は、最内周のランドに生じる熱応力が最も大きくなるため、はんだ接続部断線防止のため、最内周のランド配線を前記のように引出すことが有効である。
【００３３】
第2の実施例により、第1の実施例の作用効果に加えて、応力の大きいチップ外縁の内側にランドを配置しないようにすることにより、更に第1の実施例の形態より寿命を向上させることができる。
図13に、本発明の第3の実施例の半導体装置の断面模式図および底面（搭載基板との接続面）の平面模式図を示す。基本的には第1の実施例と同様であるが、第3の実施例では、基板１上に、接続用バンプ11を介して半導体チップ３が搭載される点が特徴の一つである。半導体チップ3基板１との間に、半導体チップ３と基板１との電気的接続を図る接続部である接続用バンプ11と、その接続部の周囲に半導体チップ3と基板１とを連結する樹脂を有している。
【００３４】
接続用バンプ11として、チップ3の端子から再配線してはんだが取付けられる場合は、溶融接合後、アンダーフィルと呼ばれるエポキシ樹脂系の材料12がチップと基板の間に挿入される。接続用バンプとして、低コスト化のためチップの端子に直接Auまたは、デバイス配線材が現在のAlからより電気特性の良いCuへ変わったときに、Auよりも接続性の良いCuが取付けられる場合は、フリップチップ接続用接着材（ACF: Anisotropic Conductive FilmまたはNCF: Non- Conductive Film）13を介して熱圧着されるか、または、より接続信頼性の高い方法として、はんだを解して溶融接続され、チップと基板の間にアンダーフィル12が挿入される方法がある。封止樹脂は、通常使用されない。熱応力による接続部の断線防止のため、少なくとも、チップ輪郭コーナー部のランドの配線は、ランド中心とチップ搭載領域の中心とを結ぶ線分となす角90度以内の方向へ引出される。それ以外の構造、材料構成、製造方法は、第1の実施例と同一である。
【００３５】
第3の実施例によって、前記第1の実施例の作用効果に加えて、半導体素子と基板１との間に接続部を形成するので、ワイヤボンディングによる接続と比して、配線長が短くなるため、電気特性が向上する。また、第1の実施例の封止樹脂に代えて、半導体チップの前記基板１側と反対側面に封止樹脂を設けず露出させえる形態にすることにより、パッケージの薄型化に有利である。
【００３６】
図14に、本発明の第4の実施例の半導体装置の断面模式図および底面（搭載基板との接続面）の平面模式図を示す。基本的には第3の実施例と同様であるが、第４の実施例では、チップ3がパッケージサイズに比して小さく、基板１のチップの外縁の外側に最内周のランドが形成される点が特徴の1つである。熱応力による接続部の断線防止のため、少なくとも、最内周コーナー部のランドの配線は、ランド中心と半導体装置の中心とを結ぶ線分となす角90度以内の方向へ引出される。それ以外の構造、材料構成、製造方法は、第3の実施例と同一である。
【００３７】
第4の実施例によって、前記第3の実施例の作用効果に加えて、チップ搭載領域内にバンプが存在しないため、第3の実施例よりも寿命を向上させることができる。
図15に、本発明の第5の実施例の半導体装置の断面模式図および底面（搭載基板との接続面）の平面模式図を示す。基本的には第1の実施例と同様であるが、第5の実施例では、基板1上に、複数個の半導体チップ3が搭載される点が特徴の1つである。本実施例では、一例として、複数の半導体チップ３を共通する封止樹脂で封止した形態を示している。チップの搭載方法は、第1または第3の実施例と同様である。熱応力による接続部の断線防止のため、少なくとも、チップ輪郭コーナー部のランドの配線は、ランド中心と各チップ搭載領域の中心とを結ぶ線分となす角90度以内の方向へ引出される。それ以外の構造、材料構成、製造方法は、第1または第3の実施例と同一である。
【００３８】
なお、第1の実施例において、解析例として図5のようなチップ1個が搭載され樹脂封止された半導体装置を挙げたが、熱応力発生メカニズムを考慮すれば、ベアチップがフリップチップ実装された半導体装置や、複数チップが実装されたMCM（Multi- Chip Module）についても、半導体チップの下までランドが形成される場合は、各半導体チップの外縁コーナ部について第1の実施例同様のはんだ接続部断線防止のための構造が有効である。一方、最外周のランドのコーナ部については、複数の半導体素子の中心の変わりに、基板１の中心に対しての角度を同様に求めることで対応の容易化を図ることができる。
【００３９】
第5の実施例により、前記第1の実施例の作用効果に加えて、高いパッケージ性能を得ることができる。
【００４０】
図16に、本発明の第6の実施例の半導体装置の断面模式図および底面（搭載基板との接続面）の平面模式図を示す。基本的には第5の実施例と同様であるが、第6の実施例では、チップがパッケージサイズに比して小さく、各チップの外縁の外側に最内周のランドが形成されている点が特徴の1つである。熱応力による接続部の断線防止のため、少なくとも、最内周コーナー部のランドの配線は、ランド中心と基板１の中心とを結ぶ線分となす角90度以内の方向へ引出される。それ以外の構造、材料構成、製造方法は、第5の実施例と同一である。
【００４１】
第6の実施例により、前記第5の実施例の作用効果に加えて、チップ搭載領域内にバンプが存在しないので第5の実施例よりも寿命を向上することができる。
【００４２】
図17に、本発明の第7の実施例の半導体装置の断面模式図および底面（搭載基板との接続面）の平面模式図を示す。基本的には第1の実施例と同様であるが、第7の実施例では、基板１上に、複数の半導体チップが積層して搭載される点が特徴の1つである。半導体チップ３の基板１側と反対側主面側に、基板1に電気的に接続する他の半導体素子を配置している。
【００４３】
第1の実施例と同様な方法で搭載されたチップ上に、もう1個のチップが搭載されている。これは、接着剤を介して固定する形態であってもよい。なお、最下段のチップの基板との接続は、第3の実施例のように、フリップチップ接続される場合であってもよい。また、上段のチップは、下段チップに設けられた接続用端子にフリップチップ接続される場合もある。その場合、一例としては、上段チップと基板との電気的接続は、下段チップの接続用端子と接続するように下段チップ内に設けられた貫通孔を通して行われるようにすることができる。図17は、代表例として、2個のチップが積層され、それぞれワイヤボンディング接続された例を示すが、さらに複数個のチップが積層される場合も有り得る。熱応力による接続部の断線防止のため、少なくとも、最下段チップ輪郭コーナー部のランドの配線は、ランド中心とチップ搭載領域の中心とを結ぶ線分となす角90度以内の方向へ引出される。それ以外の構造、材料構成、製造方法は、第1の実施例と同一である。
【００４４】
第7の実施例により、前記第1の実施例の作用効果に加えて、平面上にチップを配した第5の実施例と比して、パッケージサイズの小型化を図ることができる。
【００４５】
なお、解析例として図5のようなチップ1個が搭載され樹脂封止された半導体装置を挙げたが、熱応力発生メカニズムを考慮すれば、ベアチップがフリップチップ実装された半導体装置や、複数チップが実装されたMCM（Multi- Chip Module）についても、同様のはんだ接続部断線防止のための構造が有効であるといえ、実際、解析により効果は確認済みである。なお、チップが積層されたタイプのMCMでは、最も基板（インターポーザ）に近い位置にあるチップが、ランド部応力へ最も影響するため、基板に近いチップ輪郭線に沿った位置のバンプのランド配線について、ランド中心とチップ搭載エリアの中心とを結ぶ線分となす角90度以内の方向へ引出すなど、これまで述べた対策を施すことが有効である。
【００４６】
図18に、本発明の第8の実施例の半導体装置の断面模式図および底面（搭載基板との接続面）の平面模式図を示す。基本的には第7の実施例と同様であるが、第8の実施例では、チップがパッケージサイズに比して小さく、基板１のチップの搭載領域の外側に最内周のランドが配置されている点が特徴の一つである。
熱応力による接続部の断線防止のため、少なくとも、最内周コーナー部のランドの配線は、ランド中心と半導体装置の中心とを結ぶ線分となす角90度以内の方向へ引出される。それ以外の構造、材料構成、製造方法は、第7の実施例と同一である。
【００４７】
第8の実施例によって、第7の実施例よりも寿命を向上することができる。
【００４８】
図19に、本発明の第9の実施例の半導体装置の底面（搭載基板との接続面）の平面模式図、及び搭載基板10の接続面の平面模式図を示す。基本的には第1の実施例と同様であるが、第9の実施例で搭載基板10の形態を具体化した点が特徴の一つである。ランドに形成されたはんだバンプなどの接続部には、半導体素子を搭載する基板１側とそれを搭載する搭載基板側の両方に大きなひずみが生じる場合、両者の発生位置がランド中心に対して反対側となる。バンプ中心に対称な領域に生じる。このため前述した基板１におけるチップ外縁コーナー部のランドに対応する搭載基板側のランドの引き出し配線の方向は、ランド中心とチップの中心に対応する位置とを結ぶ線分となす角度９０度以上の方向へ引き出す。また、基板１の最外周部のコーナーに最も近いランドに対応する搭載基板側のランドの引き出し配線の方向は、同角度９０度以内の方向に引き出す。
【００４９】
または、基板１における前記半導体チップの外縁内側であって外縁部コーナーに最も近い第一のランドの配線は、その第一のランドの中心と前記半導体チップの中心に対応する位置とを結ぶ線分となす第一の角度の方向からその第一のランドに連絡されており、前記基板１の外縁における隣接する主辺の交点に最も近い第二のランドの配線は、前記第一のランドより大きい第二の角度を形成する方向から前記第二のランドに連絡されていることを特徴とし、基板１が搭載される搭載基板に形成されるランドであって、前記第一のランドに対応する第三のランドの配線は、その第一のランドの中心と前記半導体チップの中心に対応する位置とを結ぶ線分となす第三の角度の方向からその第三のランドに連絡されており、第二のランドに対応する第四のランドの配線は、前記第三のランドより小さい第四の角度を形成する方向から前記第四のランドに連絡されている。または、さらに、前記第一の角度より第三の角度の方が大きい。また、さらに、第二の角度より第四の角度の方が小さい。それ以外の構造、材料構成、製造方法は、第1から第8の実施例のうちいずれかと同一である。
【００５０】
第９の実施例によって、前記第１の実施例の作用効果に加えて、搭載基板側の構成と相まってより効果的に熱応力による接続不良を抑制することができる。なお、第２の実施例などのように、ランドの最内周が半導体チップの外縁より外側の場合は、最内周のランドのコーナーについて前述の規定を適応することができる。
図20に、本発明の第10の実施例の半導体装置のランド部構造を模式的に示す。基本的には第1から第9の実施例のうちいずれかの半導体装置と同様であるが、第10実施例において、ランド配線方向を規定したランドを、図20のように、Cuなどの導電性材を備えるビアホール14に直接接続して基板内部の配線と接続させ、基板表面にランド配線が露出しない構造としている。なお、ビアホール中心部は、樹脂材料で埋められる場合も有り得る。このように、ランドの外部との電気的接触する主面と反対側の主面に導電性部材を備えたビアホール14を配置する。少なくとも、前述の、チップコーナー部に位置するランド（チップ搭載領域内にバンプが存在しない場合は、最内周のランド）や、外周コーナー部のランドのいずれかは、図20のように、ランドに導電性のビアホールを設けて、直接下層部の配線との接続を図ることが有効である。また、それ以外の領域には基板１表面に沿って形成される配線が連絡されている図21のようなランドを配置することができる。
【００５１】
このように、はんだ接続部信頼性を低下させる原因である、ランドからの引出し配線を露出させない構造とすることも有効である。
【００５２】
第10の実施例によって、第1の実施例の作用効果に加えて、配線の引き回しの自由度を高めることができる。
図22に、本発明の第11の実施例の半導体装置のランド部の形状を模式的に示す。ランド配線断線を防止する観点から、よりき裂進展寿命を長くするため、配線幅は広い方が良い。図22のような、ランドと配線が交わる部分の形状が、滑らかに幅広にされたティアドロップ形状が有利と考える。このため、配線幅は、連絡する外部端子であるランドの中心に近い領域より離れた領域の方が幅が狭くなるよう形成されていることが好ましい。それ以外の構造、材料構成、製造方法は、第1から第9の実施例のうちいずれかと同一である。
【００５３】
図23に、本発明の第12の実施例の半導体装置の断面模式図を示す。基本構成は第1〜第9の実施例のいずれかを基本とし、基板１と搭載基板１０とが基板１のランド幅に対して、搭載基板１０と基板１との外部端子であるランド間の接着剤の高さが薄いタイプを示す。熱応力による接続部の断線防止のため、ランド部に、はんだボールは取付けず、はんだペースト15で接続されるLGA方式で、搭載基板との接続が行われることができる。それ以外の構造、材料構成、製造方法は、第1から第11の実施例のうちいずれかと同一である。
【００５４】
【発明の効果】
本発明によれば、 熱応力による半導体装置のはんだ接続部断線を防止することができ、高信頼構造の半導体装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の第1の実施例の形態に係る半導体装置の断面模式図およびはんだボール取付前の底面（搭載基板との接続面）の平面模式図。
【図２】はんだ接続部構造がSMD構造である半導体装置の模式図。
【図３】はんだ接続部構造がNSMD構造である半導体装置の模式図。
【図４】NSMD構造のランドおよび配線構造の模式図。
【図５】本発明を行う過程において、解析に用いたモデルの一例を示す模式図。
【図６】熱応力、熱ひずみ分布の解析結果の一例。
【図７】熱応力発生メカニズムを説明するための模式図。
【図８】熱応力発生メカニズムの解明のために行った解析結果の一例。
【図９】応力方向に対してランドの引き出し線方向を変化させた場合の応力変化概要図。
【図１０】ランド部熱応力のはんだ接続高さ依存性の傾向を示す図。
【図１１】本発明の第1の実施例の形態に係る半導体装置の底面の説明図。
【図１２】本発明の第2の実施例の形態に係る半導体装置の断面模式図およびはんだボール取付前の底面（搭載基板との接続面）の平面模式図。
【図１３】本発明の第3の実施例の形態に係る半導体装置の断面模式図およびはんだボール取付前の底面（搭載基板との接続面）の平面模式図。
【図１４】本発明の第4の実施例の形態に係る半導体装置の断面模式図およびはんだボール取付前の底面（搭載基板との接続面）の平面模式図。
【図１５】本発明の第5の実施例の形態に係る半導体装置の断面模式図およびはんだボール取付前の底面（搭載基板との接続面）の平面模式図。
【図１６】本発明の第6の実施例の形態に係る半導体装置の断面模式図およびはんだボール取付前の底面（搭載基板との接続面）の平面模式図。
【図１７】本発明の第7の実施例の形態に係る半導体装置の断面模式図およびはんだボール取付前の底面（搭載基板との接続面）の平面模式図。
【図１８】本発明の第8の実施例の形態に係る半導体装置の断面模式図およびはんだボール取付前の底面（搭載基板との接続面）の平面模式図。
【図１９】本発明の第9の実施例の形態に係る半導体装置の断面模式図およびはんだボール取付前の底面（搭載基板との接続面）の平面模式図。
【図２０】本発明の第10の実施例の形態に係る半導体装置のランド部構造の模式図。
【図２１】ランドと基板内部配線との結線構造の模式図。
【図２２】本発明の第11の実施例の形態に係る半導体装置のランド部構造の模式図。
【図２３】本発明の第12の実施例の形態に係る半導体装置の断面模式図。
【符号の説明】
1…基板（インターポーザ）、2…接着材、3…半導体素子（チップ）、4…ワイヤ、5…封止樹脂、6…接続用ランド、7…ソルダレジスト、8…ランドからの引出し配線、9…はんだボール、10…搭載基板、11…接続用バンプ、12…アンダーフィル、13…フリップチップ接続用接着剤（ACF: Anisotropic Conductive FilmまたはNCF: Non- Conductive Film）、14…導電性ビア、15…はんだペースト、21…配線、22…絶縁層。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a semiconductor element and a substrate on which the semiconductor element is mounted.
[0002]
[Prior art]
Higher performance, higher functionality, and smaller semiconductor packages installed in electronic information devices are required to have higher operating frequencies and smaller mounting areas than ever before. The solder connection between the mother board and the motherboard is becoming finer as the number of pins and the pitch are reduced. Furthermore, while the mounting density of various electronic components other than the semiconductor package mounted on the mother board increases, the load on the solder connection portion increases, and ensuring reliability is an important issue.
[0003]
In order to solve this and achieve higher reliability, for example, there are the following known examples.
Japanese Patent Laid-Open No. 11-97575 discloses a configuration in which the outermost peripheral electrode located along the outermost periphery is drawn out from the inside of a polygon formed by connecting adjacent outermost peripheral electrodes, and a semiconductor device is mounted. We are trying to prevent the outer peripheral solder joints from being damaged by external forces, such as impact when the equipment falls.
[0004]
In Japanese Patent Laid-Open No. 2000-261110, a semiconductor element including a substrate 60 formed so as to be drawn inward along the radial direction from each electrode pad 601 with a deformation center 0 on the substrate 60 as a base point is mounted. The structure of the mounting substrate is disclosed, and it is intended to obtain a strong bonding strength of the electrode pad.
[Patent Document 1]
Japanese Patent Laid-Open No. 11-97575 (FIG. 2 and its explanation)
[Patent Document 2]
Japanese Unexamined Patent Publication No. 2000-261110 (FIG. 1 and its description)
[0005]
[Problems to be solved by the invention]
However, in the form described in Japanese Patent Application Laid-Open No. 11-97575, fatigue failure due to thermal stress caused by changes in environmental temperature or the like cannot be prevented because the failure mechanism is different from failure due to external force. For example, when a temperature cycle test of 125 ° C. to −55 ° C. is actually performed for reliability evaluation, a disconnection failure may occur even in the inner peripheral bump. In most cases, the disconnection of the bumps in the inner peripheral portion is not caused by a crack generated in the solder, but by a crack generated in the land wiring.
[0006]
Moreover, in the form described in Japanese Patent Laid-Open No. 2000-261110, the structure on the mounting substrate on which the substrate 60 is mounted is disclosed, but the land structure on the mounting surface of the substrate 60 is not disclosed. For this reason, it is difficult for the connection part between the board | substrate with which a semiconductor is mounted, and the mounting board | substrate which mounts it to suppress the damage by a thermal stress effectively.
[0007]
An object of the present invention is to solve the above-described problems that have not been sufficiently solved by the conventional technology.
[0008]
[Means for Solving the Problems]
The present invention solves the above-mentioned problems and suppresses the solder joint disconnection due to the thermal stress.
The specific example of the form is described below.
(1) The present invention relates to a configuration in which the wiring of the external terminal of the outer edge corner portion of the semiconductor element is drawn inward. Specifically, a semiconductor element, a first substrate on which the semiconductor element is mounted, a plurality of external terminals formed on the side surface opposite to the semiconductor element mounting surface of the first substrate, and on the opposite side surface A wiring that is formed and communicates with the external terminal, and is located inside a position corresponding to the outer edge of the semiconductor element on the first substrate, and a virtual line along the main side of the outer edge The wiring extending from the first external terminal located in the region closest to the intersecting position has an angle of 90 degrees or less with the line segment connecting the center of the first external terminal and the center of the semiconductor element of the substrate. As described above, the lead-out portion from the first external terminal is located.
(2) The present invention relates to a form of drawing out the wiring of the outermost outer terminal of the first substrate. Specifically, a semiconductor element, a first substrate on which the semiconductor element is mounted, a plurality of external terminals formed on the side surface opposite to the semiconductor element mounting surface of the first substrate, and on the opposite side surface And the wiring extending from the first external terminal arranged on the most central side of the first substrate, the wiring extending from the center of the first external terminal to the substrate The semiconductor device is characterized in that a lead-out portion from the first external terminal is positioned so that an angle formed with a line connecting the centers of the semiconductor elements is 90 degrees or less.
(3) This relates to the arrangement of via holes. Specifically, a semiconductor element, a first substrate on which the semiconductor element is mounted, and a plurality of external terminals formed on a side surface opposite to the semiconductor element mounting surface of the first substrate, The external terminal is electrically connected to the first external terminal, and is formed in a thickness direction of the substrate that is electrically connected to the first wiring formed along the opposite side surface. A first via hole formed in the thickness direction of the substrate that is electrically connected to the first substrate side main surface of the external terminal. An external terminal located in a region closest to a position where a line drawn along a side of the outer edge intersects with a position corresponding to an outer edge of the semiconductor element on the first substrate; The external terminal arranged on the most central side of one substrate has the first A semiconductor device characterized by part terminal is placed.
(4) In any one of (1) to (2), the wiring of the second external terminal located outside the region located on the outer edge of the semiconductor element is formed by the first external terminal. The lead-out portion from the first external terminal is positioned so as to be in a direction that forms an angle different from.
(5) A polygonal semiconductor element, a polygonal first substrate on which the semiconductor element is mounted via an adhesive, and a surface of the first substrate opposite to the surface on which the semiconductor element is disposed A plurality of external terminals for electrical connection to the outside, a wiring connecting to the external terminal, and an insulating film covering the wiring, and an end of the insulating film is formed at a distance from the external terminal. The wiring of the first external terminal closest to the intersection of the adjacent principal sides at the outer edge of the semiconductor element, which is inside the position corresponding to the outer edge of the semiconductor element on the first substrate, It is connected to the first external terminal from the direction of the first angle that forms a line segment connecting the center of the external terminal and the position corresponding to the center of the semiconductor element, and is adjacent to the outer edge of the first substrate. The wiring of the second external terminal closest to the intersection of the main sides is Is a semiconductor device according to claim being contacted to the second external terminal from the direction of forming the first external terminal is larger than the second angle.
[0009]
For example, the first angle is a direction within 90 degrees. The second angle is a direction of 90 degrees or more.
[0010]
In addition, the configuration is such that the surface end of the insulating film (open end of the surface) is interposed between the end of the upper surface of the external terminal and the interval so that the external terminal does not overlap with the insulating film such as solder resist. Part) is formed.
(6) A polygonal semiconductor element, a polygonal first substrate on which the semiconductor element is mounted via an adhesive, and a surface of the first substrate opposite to the surface on which the semiconductor element is disposed A plurality of external terminals for electrical connection to the outside, a wiring connecting to the external terminal, and an insulating film covering the wiring, and an end of the insulating film is formed at a distance from the external terminal. The wiring of the first external terminal arranged on the most central side of the first substrate is a first line segment connecting the center of the first external terminal and the position corresponding to the center of the semiconductor element. The wiring of the second external terminal closest to the intersection of the adjacent main sides at the outer edge of the first board is connected to the first external terminal from the direction of the angle of Is connected to the second external terminal from the direction forming a large second angle. A semiconductor device characterized by there.
(7) A polygonal semiconductor element, a polygonal first substrate on which the semiconductor element is mounted via an adhesive, and a surface of the first substrate opposite to the surface on which the semiconductor element is disposed A plurality of external terminals for electrical connection to the outside, a wiring connecting to the external terminal, and an insulating film covering the wiring, and an end of the insulating film is formed at a distance from the external terminal. The first external terminal is electrically connected to the first external terminal, and the first wiring formed along the opposite side surface and the thickness of the substrate electrically connected to the wiring A first via hole formed in a direction and a second external terminal formed in a thickness direction of the substrate electrically connected to the first substrate side main surface of the external terminal. A position having one via hole and corresponding to an outer edge of the semiconductor element on the first substrate External terminals located in the region closest to the intersection of adjacent main sides at the outer edge of the substrate at the substitution position and inside the position corresponding to the outer edge of the semiconductor element on the first substrate. The first external terminal is disposed on the external terminal located in the region closest to the position where the extension lines of the outer edges intersect or the external terminal arranged on the most central side of the first substrate. This is a featured semiconductor device.
[0011]
The center described in (1) et al. Is, for example, the center of the semiconductor element is the intersection of the two longest diagonal lines connecting the corners of the element, and forms a diameter when the center of the external terminal is circular. In the case of a polygon, it is the intersection of the two longest diagonal lines.
[0012]
In addition, the polygonal shape described in (5) et al. Is, for example, in the case of a quadrangular shape, the four principal sides forming the quadrilateral may not necessarily be a straight line but may have a curvature, and are adjacent to each other. The corners of the intersections of the main sides may have a curvature even if they are not orthogonal to each other, the corners may be cut off to form a side shorter than the main side connecting adjacent main sides, and the overall shape As long as it has a shape that can be determined as a quadrangle.
[0013]
In addition, as described above, () located in the region closest to the intersection of the adjacent principal sides at the outer edge of the substrate at the substitute position inside the position corresponding to the outer edge of the semiconductor element on the first substrate When the external terminal to be connected and the external terminal closest to the intersection of the adjacent main sides at the outer edge of the first substrate refer to the same external terminal, the above-mentioned provision (external terminal at the outer edge corner) is specified. To follow.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the semiconductor device employing the present invention will be described in detail. Note that the present invention is not limited to the modes described in the present specification, and allows modifications based on known technologies or newly generated technologies from the disclosed modes.
FIG. 1 shows an outline of the form of the semiconductor device according to the first embodiment of the present invention. A cross-sectional schematic diagram (a) and a schematic plan view (b) of the bottom surface of the substrate 1 (connection surface with the mounting substrate) before solder ball attachment are shown. After mounting a semiconductor chip 3 on a substrate (interposer) 1 via an epoxy resin adhesive 2 or the like and using a wire 4 such as Au to bond and connect the substrate and the chip for electrical connection Then, the semiconductor chip 3 is sealed with an epoxy resin sealing material 5 or the like. For example, the semiconductor chip 3 is formed so as to cover a surface other than the main surface facing the substrate 1.
[0015]
The semiconductor chip 3 has a transistor circuit formed on the main surface opposite to the main surface facing the substrate 1 serving as an interposer.
[0016]
The substrate 1 is formed using a resin material such as glass epoxy as a core material. The substrate 1 is wired with a conductive material such as Cu, and a land 6 made of a conductive material such as Cu for connection is provided on the surface as an external terminal.
[0017]
In order to prevent disconnection of the connection part due to thermal stress, at least the land wiring at the corner of the chip outline is drawn in a direction within 90 degrees formed by a line segment connecting the center of the land and the center of the chip mounting area (see FIG. In Fig. 1, only the land wiring at the chip corner is partially shown). As a result, disconnection associated with thermal stress of the semiconductor device can be suppressed, and a high-performance semiconductor device can be formed. A solder ball 9 of Sn-Pb or Pb-free (Sn-Ag-Cu or the like) in consideration of environmental problems is attached to the land, and attached to the mounting board 10. A detailed description of the wiring structure and the like that is not related to the essence of the present invention will be omitted.
[0018]
A specific example of the structure of the land 6 in this embodiment is shown in FIG. From the land 6 formed on the insulating layer 22, a lead-out line 8 from the land, which is a wiring, is formed along the substrate surface. A via hole 14 having a conductive member is provided at a position away from the land 6 so as to communicate with the lead wire 8 and is in electrical communication with the inside of the substrate 1. As an example, the via hole 14 may communicate with an internal wiring 21 formed inside the substrate. A solder resist 7 as an insulating film is formed on the insulating layer 22. The end portion of the solder resist 7 is arranged with a distance from the end portion of the land 6. Preferably, an opening is provided so that the entire land near the land 6 is exposed, and the substrate surface is covered with a solder resist 7 which is a resin for insulation. At least a part of the wiring 8 drawn from the land is exposed from the opening of the solder resist 7 and the opening end of the solder resist 7 is located.
[0019]
Of the lands 6 located on the outermost periphery of the substrate 1, the wiring 8 of the land 6 in the region farthest from the chip mounting center is a line segment connecting the center of the land 6 and the position corresponding to the center of the semiconductor chip 3. The lead wiring 8 from the land 6 is formed so that the angle is 90 degrees or less. In other words, the land 6 is inside the position corresponding to the outer edge of the semiconductor chip 3 on the substrate 6 (described by a broken line), and is located in a region closest to the position where the lines along the outer edge intersect. Applies to the wiring extending from By doing in this way, the disconnection of the wiring near the land of the outer periphery accompanying thermal stress can be suppressed.
[0020]
Further, in the wiring 8 drawn from the land formed at the outer edge corner of the semiconductor chip 3, the land formed at the corner located at the outermost periphery of the substrate 1 from the angle formed by the position corresponding to the chip center and the land center. The angle formed by the wiring 8 drawn out of the wiring 8 becomes larger. Thereby, since the countermeasure corresponding to the stress can be appropriately taken in the region that is greatly affected by the thermal stress, the damage due to the thermal stress of the entire apparatus can be effectively suppressed. Specifically:
[0021]
It is preferable that the angle (θ1 to θ4) between the position corresponding to the center of the chip and the center of the land (θ1 to θ4) be within 90 degrees for the wiring drawn from the land 6 positioned at the corner of the outer edge portion of the semiconductor chip 3. Further, the angle (θ5 to θ8) between the position corresponding to the chip center and the land center of the wiring drawn from the land 6 positioned at the corner among the lands positioned on the outermost periphery of the substrate 1 is 90 degrees or more. It is preferable to make it. FIG. 24 shows an example detailed in FIG. The basic configuration is the same as in FIG. In the vicinity of the land closest to the corner portion on the outer edge of the semiconductor chip, a land for drawing out the wiring in the same direction as the wiring drawing direction of the nearest land is provided. In this case, the same applies to the lands in the vicinity of the outermost corner lands.
[0022]
On the other hand, lands disposed outside the outer edge of the semiconductor chip 3 and other than the defined lands (for example, lands located between the outermost or innermost lands of the lands) are defined as described above. The wiring is drawn in a direction different from the wiring direction drawn from the land. This is for reducing the size of the substrate while suppressing disconnection of the wiring due to the thermal stress.
[0023]
In order to elucidate the failure mechanism of solder joints due to thermal stress, a finite element analysis using a three-dimensional model was performed. FIG. 5 shows a schematic structure of the analysis model. A semiconductor device having a semiconductor element mounted on the substrate is disposed on the mounting substrate. The broken line indicates the position of the outer edge of the chip, and lands are arranged in an array. In this analysis, the analysis was performed for a quarter of the entire region. In this analysis, the location of the maximum stress at the solder joint interface became clear and convenient for understanding the stress generation mechanism, so the land structure was SMD. Figure 6 shows the strain amplitude De generated in the solder per cycle when an elastic-plastic analysis is performed at a temperature cycle of 125 ° C to -55 ° C. peq (Equivalent plastic strain range) (6a) and a distribution map (6b) of the stress amplitude Ds generated in the land (positive when the tensile stress increases during the cooling process and negative when the tensile stress decreases) are shown. In addition, the distortion | strain of solder became large in the outermost periphery corner part. Moreover, it became large similarly in the land near a chip | tip (semiconductor element) outline corner part. On the other hand, the stress generated in the land is maximum at the land at the chip corner portion, and the stress at the outer peripheral corner portion is about half of that. In particular, in the land of the chip corner portion, the outer side of the semiconductor chip has a very large stress compared to the outer side of the semiconductor chip. On the other hand, in the land of the outermost peripheral corner portion, the stress on the center side is larger than that of the outer side.
[0024]
FIG. 7 schematically shows the thermal stress generation mechanism of the solder joint. Since the semiconductor device is heated and melt-bonded (reflowed) to the mounting substrate (for example, about 250 ° C), the thermal stress is close to zero at a high temperature of 125 ° C, which is caused by the difference in coefficient of linear expansion during the cooling process. Then, it is considered that thermal stress occurs with thermal deformation as shown in FIG. 7 (for example, the linear expansion coefficient of the substrate is usually about 12 to 18 ppm / K, whereas the sealing resin Is about 9-12 ppm / K, and the tip is about 3 ppm / K.) The bumps at the outer corner are mainly subjected to shearing force due to shear deformation, and thermal stress is generated. On the other hand, the bumps at the chip corner rotate due to warpage deformation of the semiconductor device in addition to the shearing force. A force (moment force) is applied and it is considered that thermal stress is generated. It is considered that a particularly large stress is generated on the land of the bump at the chip corner by this rotational force. As shown in FIG. 8, using a model in which only one bump and the vicinity thereof were taken out, a shearing force and a rotational force were applied, and the effects were examined. As a result of comparison between the case where only the shearing force is applied and the case where both the shearing force and the rotational force are applied, the stress generated in the land is significantly greater when the rotational force is applied, compared to the difference in solder strain. It became bigger. In this way, in order to prevent poor connection due to thermal stress, first, it is effective to take measures against the land on the inner periphery side or the land closest to the intersection of the outer edge lines inside the outer edge of the semiconductor chip. Measures can be taken.
[0025]
In the SMD structure, solder tends to crack and cause poor connection, whereas in the NSMD structure, there is a high tendency to cause poor connection due to wire breakage, and the wire breakage is affected by stress rather than strain. large. In the case of NSMD structure, the land wiring is most likely to be broken at the bumps at the chip corners, and by effectively taking countermeasures for this with the present invention, the degree of freedom in routing other land wiring can be increased. This can contribute to downsizing and the like.
[0026]
In order to prevent disconnection of the solder joint due to thermal stress, it has been found effective to orient the wiring drawn from the land in this region while avoiding the direction in which a large stress is generated. For example, in the chip corner portion where the stress of the land portion is the largest, as shown in FIG. 6 (b), the maximum stress is generated at a position close to the semiconductor device corner side of the land. To. The lead portion of the land wiring is preferably drawn in a direction within 90 degrees formed by a line segment connecting the center of the land and the center of the chip mounting area.
[0027]
FIG. 9 shows the relationship between the wiring drawing direction from the land and the stress. The horizontal axis represents the inclination from the pulling direction where the stress is maximum, and the vertical axis represents the stress in the wiring portion when the maximum stress (stress when the wiring inclination is 0 degree) is 1. The stress can be effectively reduced by avoiding the direction in which the stress increases from the land and avoiding the direction in which the stress increases, in particular, 90 degrees or more. Preferably, it is better near 180 degrees. It is preferable to avoid 135 degrees or more from the viewpoint of manufacturing system. Therefore, in other words, the angle formed by the line connecting the center of the land and the center of the substrate such as the center of the chip mounting area is 45 degrees at the corner of the outer edge of the semiconductor chip or the corner of the innermost land. It is preferable that the direction is within. On the other hand, in the corner portion of the outermost peripheral land, the direction is preferably 135 degrees or more.
[0028]
In addition, regarding the prevention of breakage starting from solder, if the wiring is pulled out in the direction in which the maximum strain occurs, and the wiring and solder come into contact with each other at the same position, the strain concentration on the solder is promoted and the life is reduced. It is effective to pull out the land wiring in a direction that avoids the strain generation position. As shown in Fig. 6, the position where the maximum stress in the land portion and the position where the maximum strain in the solder are generated are relatively coincident. , Solder disconnection can be suppressed. For bumps in the vicinity of the chip outline, the stress in the land is expected to increase to the same level as the chip corner if the stress generation mechanism is considered. Similarly, the land wiring is desirably drawn in a direction within an angle of 90 degrees formed by a line segment connecting the center of the land and the center of the chip mounting area.
[0029]
Furthermore, regarding the bumps at the outer corners, it is drawn from the position where the maximum strain in the solder is generated and pulled out in the direction of 90 degrees or more, which forms the line connecting the center of the land and the center of the chip mounting area. Is desirable. More preferably, it is desirable that the land wiring of the outermost peripheral bump is formed so as to be drawn out in a direction of an angle of 90 degrees or more which forms a line segment connecting the center of the land and the center of the chip mounting area. It is preferable to form a majority or more, more preferably 80% or more. This is because the distortion in the solder of the bump located at the outermost peripheral portion is predicted to be under a large stress level.
[0030]
A land configuration suitable for applying the above-described embodiment of the present invention is such that the solder which is an adhesive reaches the side wall of the land. In other words, it is a type in which the solder reaches the end of the upper main surface of the land. This is because contact failure due to thermal stress can be effectively suppressed in combination with the action of the wiring drawing direction. FIG. 2 schematically shows a solder connection portion structure of a semiconductor device of a comparative example. As shown in Fig. 2, in the structure called SMD (Solder Mask Defined) where the end of the land connected to the solder is covered with insulating resin (solder resist), for example, thermal strain caused by changes in environmental temperature is Concentrate on the point of contact with the solder resist (point A in Fig. 2). On the other hand, in the structure called NSMD (Non-Solder Mask Defined) where the land is exposed from the solder resist as shown in Fig. 3, the strain concentration part is the substrate part (point B in Fig. 3), so the solder part Distortion is reduced and high reliability can be realized. On the other hand, since the wiring is usually connected to the land as shown in Fig. 4, strain concentrates on the contact area between the wiring and the solder (point C in Fig. 4), and a crack may occur on the wiring side. Therefore, defects can be effectively suppressed by optimizing the direction of the above-described lead lines.
[0031]
FIG. 10 shows the dependency of the land portion stress on the solder connection height. Here, the diameter of the solder connection portion is 0.35 mm. The stress generated in the land portion decreases as the solder connection height decreases. As described above, the stress of the land portion is greatly influenced by the rotational force due to the warp deformation of the semiconductor device. However, since the distance between the operating point of the rotational force and the rotation center is reduced by reducing the solder connection height, the rotational force is reduced. Is expected to decrease. Therefore, in order to prevent disconnection of the land wiring, it is advantageous that the solder connection height is low, and the LGA (Land Grid Array) method in which the semiconductor device is connected only by the solder paste without using solder balls is advantageous. (In the case of LGA, the solder connection height is usually 0.1 mm or less). Further, from the viewpoint of preventing land wiring disconnection, it is preferable that the wiring width is wider in order to extend the crack propagation life.
[0032]
FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting substrate). Basically the same as in the first embodiment, but the second embodiment is characterized in that the chip is smaller than the package size and no bumps are present in the chip mounting area. One. Other structures, material configurations, and manufacturing methods are the same as those in the first embodiment. However, in order to further prevent disconnection of the connection portion due to thermal stress and improve the life, at least in the land wiring at the innermost peripheral corner portion, the land center and the semiconductor device center are connected as in the first embodiment. It is drawn in the direction within 90 degrees with the line segment. In the case of a semiconductor device having a structure in which no bump is present in the chip mounting area, the thermal stress generated in the innermost land is the largest, so that the innermost land wiring is connected to prevent the solder connection portion from being disconnected. It is effective to pull out like this.
[0033]
According to the second embodiment, in addition to the effects of the first embodiment, the life is further improved as compared with the first embodiment by not arranging the land inside the chip outer edge where the stress is large. be able to.
FIG. 13 shows a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting substrate). Although basically the same as the first embodiment, the third embodiment is characterized in that the semiconductor chip 3 is mounted on the substrate 1 via the bumps 11 for connection. Between the semiconductor chip 3 and the substrate 1, there are connecting bumps 11 which are connection portions for electrical connection between the semiconductor chip 3 and the substrate 1, and a resin for connecting the semiconductor chip 3 and the substrate 1 around the connection portion. have.
[0034]
When solder is attached by rewiring from the terminals of the chip 3 as the connection bumps 11, an epoxy resin material 12 called underfill is inserted between the chip and the substrate after fusion bonding. As a bump for connection, when the device wiring material is changed from current Al to Cu with better electrical characteristics, Cu with better connectivity than Au is attached to the chip terminals for cost reduction. Can be thermocompression-bonded via flip-chip adhesive (ACF: Anisotropic Conductive Film or NCF: Non-Conductive Film) 13, or, as a more reliable connection method, unsoldering and fusion bonding There is a method in which an underfill 12 is inserted between the chip and the substrate. Sealing resin is not usually used. In order to prevent disconnection of the connection portion due to thermal stress, at least the land wiring at the chip outline corner portion is drawn in a direction within 90 degrees formed by a line segment connecting the land center and the center of the chip mounting area. Other structures, material configurations, and manufacturing methods are the same as those in the first embodiment.
[0035]
According to the third embodiment, in addition to the function and effect of the first embodiment, a connection portion is formed between the semiconductor element and the substrate 1, so that the wiring length is shortened compared to the connection by wire bonding. Therefore, the electrical characteristics are improved. Further, instead of the sealing resin of the first embodiment, it is advantageous for making the package thinner by adopting a form in which the semiconductor chip can be exposed without providing the sealing resin on the side surface opposite to the substrate 1 side.
[0036]
FIG. 14 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting substrate). Basically the same as in the third embodiment, but in the fourth embodiment, the chip 3 is smaller than the package size, and the innermost peripheral land is formed outside the outer edge of the chip of the substrate 1. This is one of the features. In order to prevent disconnection of the connection portion due to thermal stress, at least the wiring of the land at the innermost peripheral corner is drawn in a direction within 90 degrees formed by a line segment connecting the land center and the center of the semiconductor device. Other structures, material configurations, and manufacturing methods are the same as those in the third embodiment.
[0037]
According to the fourth embodiment, in addition to the function and effect of the third embodiment, there is no bump in the chip mounting area, so that the lifetime can be improved as compared to the third embodiment.
FIG. 15 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting substrate). Basically the same as the first embodiment, but the fifth embodiment is characterized in that a plurality of semiconductor chips 3 are mounted on the substrate 1. In the present embodiment, as an example, a form in which a plurality of semiconductor chips 3 are sealed with a common sealing resin is shown. The chip mounting method is the same as in the first or third embodiment. In order to prevent disconnection of the connection portion due to thermal stress, at least the land wiring at the chip contour corner portion is drawn in a direction within 90 degrees formed by a line segment connecting the land center and the center of each chip mounting area. Other structures, material configurations, and manufacturing methods are the same as those in the first or third embodiment.
[0038]
In the first embodiment, as an analysis example, a semiconductor device in which one chip as shown in FIG. 5 is mounted and resin-sealed is mentioned, but in consideration of the thermal stress generation mechanism, the bare chip is flip-chip mounted. In the case of a semiconductor device or an MCM (Multi-Chip Module) on which a plurality of chips are mounted, if the land is formed below the semiconductor chip, the solder at the outer corner portion of each semiconductor chip is the same as in the first embodiment. A structure for preventing disconnection of the connecting portion is effective. On the other hand, regarding the corner portion of the outermost land, it is possible to facilitate correspondence by obtaining the angle with respect to the center of the substrate 1 in the same manner instead of the centers of the plurality of semiconductor elements.
[0039]
According to the fifth embodiment, high package performance can be obtained in addition to the operational effects of the first embodiment.
[0040]
FIG. 16 shows a schematic cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting substrate). Basically the same as the fifth embodiment, but in the sixth embodiment, the chip is smaller than the package size, and the innermost land is formed outside the outer edge of each chip. Is one of the features. In order to prevent disconnection of the connection portion due to thermal stress, at least the wiring of the land at the innermost peripheral corner portion is drawn in a direction within 90 degrees formed by a line segment connecting the land center and the center of the substrate 1. Other structures, material configurations, and manufacturing methods are the same as those in the fifth embodiment.
[0041]
According to the sixth embodiment, in addition to the function and effect of the fifth embodiment, since the bump does not exist in the chip mounting area, the lifetime can be improved as compared with the fifth embodiment.
[0042]
FIG. 17 shows a schematic cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting substrate). Although basically the same as the first embodiment, the seventh embodiment is characterized in that a plurality of semiconductor chips are stacked and mounted on the substrate 1. On the main surface side opposite to the substrate 1 side of the semiconductor chip 3, another semiconductor element that is electrically connected to the substrate 1 is disposed.
[0043]
Another chip is mounted on the chip mounted in the same manner as in the first embodiment. This may be in the form of fixing via an adhesive. Note that the bottom chip may be connected to the substrate by flip chip connection as in the third embodiment. Further, the upper chip may be flip-chip connected to a connection terminal provided on the lower chip. In that case, as an example, the electrical connection between the upper chip and the substrate can be made through a through-hole provided in the lower chip so as to be connected to the connection terminal of the lower chip. FIG. 17 shows an example in which two chips are stacked and connected by wire bonding as a representative example, but a plurality of chips may be stacked. In order to prevent disconnection of the connection part due to thermal stress, at least the wiring of the land at the lowermost chip contour corner is drawn in a direction within 90 degrees formed by the line segment connecting the land center and the center of the chip mounting area. . Other structures, material configurations, and manufacturing methods are the same as those in the first embodiment.
[0044]
According to the seventh embodiment, in addition to the function and effect of the first embodiment, the package size can be reduced as compared with the fifth embodiment in which chips are arranged on a plane.
[0045]
As an analysis example, a semiconductor device in which one chip as shown in FIG. 5 is mounted and resin-sealed is mentioned. However, considering the thermal stress generation mechanism, a semiconductor device in which a bare chip is flip-chip mounted or a plurality of chips As for the MCM (Multi-Chip Module) on which is mounted, it can be said that the same structure for preventing disconnection of the solder joint is effective, and the effect has been confirmed by the analysis. In addition, in the MCM of the type in which the chips are stacked, the chip closest to the substrate (interposer) has the most influence on the land stress, so the land wiring of the bump along the chip outline close to the substrate It is effective to take the measures described so far, such as drawing out in a direction within 90 degrees formed by the line connecting the center of the land and the center of the chip mounting area.
[0046]
FIG. 18 shows a schematic cross-sectional view and a schematic plan view of the bottom surface (connection surface with the mounting substrate) of the semiconductor device according to the eighth embodiment of the present invention. Basically the same as in the seventh embodiment, but in the eighth embodiment, the chip is smaller than the package size, and the innermost land is disposed outside the chip mounting area of the substrate 1. This is one of the features.
In order to prevent disconnection of the connection portion due to thermal stress, at least the wiring of the land at the innermost peripheral corner is drawn in a direction within 90 degrees formed by a line segment connecting the land center and the center of the semiconductor device. Other structures, material configurations, and manufacturing methods are the same as those in the seventh embodiment.
[0047]
According to the eighth embodiment, the lifetime can be improved as compared with the seventh embodiment.
[0048]
FIG. 19 is a schematic plan view of the bottom surface (connection surface with the mounting substrate) of the semiconductor device according to the ninth embodiment of the present invention, and a schematic plan view of the connection surface of the mounting substrate 10. This is basically the same as the first embodiment, but one of the features is that the form of the mounting substrate 10 is embodied in the ninth embodiment. When large distortion occurs on both the board 1 side on which the semiconductor element is mounted and the mounting board side on which the semiconductor element is mounted in the connection portion such as a solder bump formed on the land, the generation position of both is opposite to the center of the land On the side. It occurs in an area that is symmetric with respect to the bump center. For this reason, the direction of the lead-out wiring of the land on the mounting substrate side corresponding to the land on the chip outer edge corner portion of the substrate 1 described above is an angle of 90 degrees or more that forms the line segment connecting the land center and the position corresponding to the chip center Pull in the direction. Further, the direction of the lead-out wiring of the land on the mounting substrate side corresponding to the land closest to the corner of the outermost peripheral portion of the substrate 1 is drawn out within the same angle of 90 degrees.
[0049]
Alternatively, the wiring of the first land closest to the corner of the outer edge of the semiconductor chip on the substrate 1 is a line segment connecting the center of the first land and the position corresponding to the center of the semiconductor chip. The first land is connected to the first land from the direction of the first angle, and the wiring of the second land closest to the intersection of the adjacent main sides on the outer edge of the substrate 1 is larger than the first land. The land is connected to the second land from the direction of forming the second angle, and is a land formed on the mounting substrate on which the substrate 1 is mounted, and corresponds to the first land. The wiring of the third land is connected to the third land from the direction of the third angle formed by the line segment connecting the center of the first land and the position corresponding to the center of the semiconductor chip. Corresponds to the second land Fourth lands of the wiring is contacted to the fourth land from the direction of forming the third lands is smaller than the fourth angle. Alternatively, the third angle is larger than the first angle. Furthermore, the fourth angle is smaller than the second angle. Other structures, material configurations, and manufacturing methods are the same as those in any of the first to eighth embodiments.
[0050]
According to the ninth embodiment, in addition to the operational effects of the first embodiment, it is possible to more effectively suppress the connection failure due to thermal stress in combination with the configuration on the mounting substrate side. When the innermost periphery of the land is outside the outer edge of the semiconductor chip as in the second embodiment, the above-mentioned definition can be applied to the corner of the innermost land.
FIG. 20 schematically shows the land portion structure of the semiconductor device according to the tenth embodiment of the present invention. Basically, it is the same as any one of the semiconductor devices in the first to ninth embodiments, but in the tenth embodiment, the land defining the land wiring direction is made of conductive material such as Cu as shown in FIG. The structure is such that the land wiring is not exposed on the surface of the substrate by directly connecting to the via hole 14 provided with a conductive material and connecting to the wiring inside the substrate. The via hole center may be filled with a resin material. In this way, the via hole 14 provided with the conductive member is disposed on the main surface opposite to the main surface in electrical contact with the outside of the land. At least one of the above-mentioned lands located at the chip corner (the innermost land when there is no bump in the chip mounting area) and the land at the outer corner are as shown in FIG. It is effective to provide a conductive via hole in the substrate and to directly connect to the lower layer wiring. Further, lands as shown in FIG. 21 to which wirings formed along the surface of the substrate 1 are communicated can be arranged in other regions.
[0051]
As described above, it is also effective to adopt a structure that does not expose the lead-out wiring from the land, which is a cause of reducing the reliability of the solder connection portion.
[0052]
According to the tenth embodiment, in addition to the function and effect of the first embodiment, the degree of freedom in routing the wiring can be increased.
FIG. 22 schematically shows the shape of the land portion of the semiconductor device according to the eleventh embodiment of the present invention. From the viewpoint of preventing land wiring disconnection, a wider wiring width is better in order to extend the crack growth life. A tear drop shape in which the shape of the portion where the land and the wiring intersect as shown in FIG. 22 is smoothly widened is considered advantageous. For this reason, it is preferable that the wiring width is formed so that the width is narrower in a region away from the region near the center of the land which is an external terminal to be connected. Other structures, material configurations, and manufacturing methods are the same as those in any one of the first to ninth embodiments.
[0053]
FIG. 23 is a schematic cross-sectional view of a semiconductor device according to a twelfth embodiment of the present invention. The basic configuration is based on any one of the first to ninth embodiments, and the substrate 1 and the mounting substrate 10 are between the lands which are external terminals of the mounting substrate 10 and the substrate 1 with respect to the land width of the substrate 1. A type with a thin adhesive. In order to prevent disconnection of the connection portion due to thermal stress, the solder ball is not attached to the land portion, and the connection with the mounting substrate can be performed by the LGA method in which the solder paste 15 is connected. Other structures, material configurations, and manufacturing methods are the same as those in any of the first to eleventh embodiments.
[0054]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the solder connection part disconnection of the semiconductor device by a thermal stress can be prevented, and the semiconductor device of a highly reliable structure can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting board) before mounting solder balls.
FIG. 2 is a schematic diagram of a semiconductor device in which a solder connection portion structure is an SMD structure.
FIG. 3 is a schematic view of a semiconductor device in which a solder connection portion structure is an NSMD structure.
FIG. 4 is a schematic diagram of a land and a wiring structure of an NSMD structure.
FIG. 5 is a schematic diagram showing an example of a model used for analysis in the process of carrying out the present invention.
FIG. 6 shows an example of an analysis result of thermal stress and thermal strain distribution.
FIG. 7 is a schematic diagram for explaining a thermal stress generation mechanism.
FIG. 8 shows an example of analysis results performed for elucidating the mechanism of thermal stress generation.
FIG. 9 is a schematic diagram showing changes in stress when the direction of the lead line of the land is changed with respect to the stress direction.
FIG. 10 is a diagram showing a tendency of land portion thermal stress dependency on solder connection height.
FIG. 11 is an explanatory view of the bottom surface of the semiconductor device according to the first embodiment of the present invention.
FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention, and a schematic plan view of a bottom surface (a connection surface with a mounting board) before mounting solder balls.
FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting board) before mounting solder balls.
FIG. 14 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention, and a schematic plan view of a bottom surface (a connection surface with a mounting board) before mounting solder balls.
FIG. 15 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention, and a schematic plan view of a bottom surface (a connection surface with a mounting board) before mounting solder balls.
FIG. 16 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting board) before mounting solder balls.
FIG. 17 is a schematic cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting board) before mounting solder balls.
FIG. 18 is a schematic cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting board) before mounting solder balls.
FIG. 19 is a schematic cross-sectional view of a semiconductor device according to a ninth embodiment of the present invention and a schematic plan view of a bottom surface (a connection surface with a mounting board) before mounting solder balls.
FIG. 20 is a schematic diagram of a land portion structure of a semiconductor device according to a tenth embodiment of the present invention.
FIG. 21 is a schematic diagram of a connection structure between a land and a substrate internal wiring.
FIG. 22 is a schematic view of a land portion structure of a semiconductor device according to an eleventh embodiment of the present invention.
FIG. 23 is a schematic sectional view of a semiconductor device according to a twelfth embodiment of the present invention.
[Explanation of symbols]
1 ... Substrate (interposer), 2 ... Adhesive, 3 ... Semiconductor element (chip), 4 ... Wire, 5 ... Sealing resin, 6 ... Land for connection, 7 ... Solder resist, 8 ... Lead wiring from land, 9 ... Solder ball, 10 ... Mounting board, 11 ... Bump for connection, 12 ... Underfill, 13 ... Adhesive for flip chip connection (ACF: Anisotropic Conductive Film or NCF: Non-Conductive Film), 14 ... Conductive via, 15 ... solder paste, 21 ... wiring, 22 ... insulating layer.

Claims (8)

半導体素子と、
前記半導体素子が搭載された第一の基板と、
前記第一の基板の前記半導体素子搭載面の反対側面に形成された複数の外部端子と、
前記反対側面に形成され、前記外部端子に連絡する配線と、を有し、
前記第一の基板での前記半導体素子の外縁に対応する位置より内側であって、前記外縁の主辺に沿って引いた線が交わる位置に最も近い領域に位置する外部端子から伸びる前記配線は、前記外部端子の中心から前記基板の前記半導体素子の中心を結ぶ線分となす角が９０度以下になるように前記外部端子からの引出し部が位置し、
最外周コーナーに位置する前記外部端子から伸びる前記配線は、前記外部端子の中心から前記基板の前記半導体素子の中心を結ぶ線分となす角が９０度以上になるように前記外部端子からの引出し部が位置することを特徴とする半導体装置。A semiconductor element;
A first substrate on which the semiconductor element is mounted;
A plurality of external terminals formed on a side surface opposite to the semiconductor element mounting surface of the first substrate;
A wiring formed on the opposite side surface and connected to the external terminal;
An inner than a position corresponding to the outer edge of the semiconductor device in the first substrate, said extending from the external terminal you located closest area to the position where the main edge line drawn along the intersection of the outer edge wiring located drawer unit from the front Kigai part center from the semiconductor front Kigai unit terminal as a line segment and the angle is less than 90 degrees connecting the centers of elements of the substrate terminals,
The wiring extending from the external terminal located at the outermost peripheral corner is drawn out from the external terminal so that an angle formed by a line segment connecting the center of the external terminal and the center of the semiconductor element of the substrate is 90 degrees or more. A semiconductor device, wherein the portion is located . 半導体素子と、
前記半導体素子が搭載された第一の基板と、
前記第一の基板の前記半導体素子搭載面の反対側面に形成された複数の外部端子と、
前記反対側面に形成され、前記外部端子に連絡する配線と、を有し、
前記第一の基板での前記半導体素子の外縁に対応する位置より内側には前記外部端子は存在せず、
前記第一の基板での前記半導体素子の外縁に対応する位置より外側であり、前記第一の基板の最も中心側に配列される外部端子から伸びる前記配線は、前記外部端子の中心から前記基板の前記半導体素子の中心を結ぶ線分となす角が９０度以下になるように前記外部端子からの引出し部が位置し、
最外周コーナーに位置する前記外部端子から伸びる前記配線は、前記外部端子の中心から前記基板の前記半導体素子の中心を結ぶ線分となす角が９０度以上になるように前記外部端子からの引出し部が位置することを特徴とする半導体装置。A semiconductor element;
A first substrate on which the semiconductor element is mounted;
A plurality of external terminals formed on a side surface opposite to the semiconductor element mounting surface of the first substrate;
A wiring formed on the opposite side surface and connected to the external terminal;
The external terminal does not exist inside the position corresponding to the outer edge of the semiconductor element on the first substrate,
The first is outside the position corresponding to the outer edge of the semiconductor element in the substrate, the first most central extending from the outer portion the terminal that will be arranged on the side the wiring substrate, the center of the front Kigai unit terminal lines and the angle connecting the centers of the semiconductor element of the substrate is positioned is lead portions from the front Kigai unit terminals to be less than 90 degrees from,
The wiring extending from the external terminal located at the outermost peripheral corner is drawn out from the external terminal so that an angle formed by a line segment connecting the center of the external terminal and the center of the semiconductor element of the substrate is 90 degrees or more. A semiconductor device, wherein the portion is located . 請求項１に記載の半導体装置において、前記半導体素子は、前記第一の基板と対向する主面と反対側の主面にトランジスタ回路が形成されていることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein a transistor circuit is formed on the main surface of the semiconductor element opposite to the main surface facing the first substrate. 請求項１に記載の半導体装置において、前記半導体素子と前記第一の基板との間に、前記半導体素子と前記第一の基板との電気的接続を図る接続部と、前記接続部の周囲に前記半導体素子と前記第一の基板とを連結する樹脂を有することを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein a connection portion is provided between the semiconductor element and the first substrate for electrical connection between the semiconductor element and the first substrate, and the periphery of the connection portion. A semiconductor device comprising a resin for connecting the semiconductor element and the first substrate. 請求項１に記載の半導体装置において、複数の前記半導体素子が前記第一の基板に搭載されていることを特徴とする半導体装置。 The semiconductor device according to claim 1 , wherein a plurality of the semiconductor elements are mounted on the first substrate. 請求項１に記載の半導体装置において、前記半導体素子の前記第一の基板側と反対側の主面側に位置し、前記第一の基板に電気的に接続する第二の半導体素子を有することを特徴とする半導体装置。 The semiconductor device according to claim 1, further comprising a second semiconductor element that is located on a main surface side opposite to the first substrate side of the semiconductor element and is electrically connected to the first substrate. A semiconductor device characterized by the above. 請求項１に記載の半導体装置において、前記配線は、連絡する外部端子の中心に近い領域より離れた領域の方が幅が狭くなるよう形成されていることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the wiring is formed so that a width is narrower in a region away from a region near the center of the external terminal to be connected. 請求項１に記載の半導体装置において、前記半導体素子を被う封止樹脂を備えていることを特徴とする半導体装置。2. The semiconductor device according to claim 1, further comprising a sealing resin that covers the semiconductor element.
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