JP3923307B2 - Image coding / decoding device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image encoding / decoding device capable of high-speed encoding / decoding processing.
[0002]
[Prior art]
For example, in image processing apparatuses such as facsimile machines and digital copying machines, image data is encoded and compressed so that the image data can be handled with a smaller amount of data, so that communication efficiency and storage efficiency can be improved. .
[0003]
In recent years, in response to a request for high-speed reading or writing of an original in an image processing apparatus, it is necessary to increase the speed of a compression encoding method when storing a read image in a memory.
[0004]
In addition, with advances in LSI manufacturing process technology, circuits have been operating with faster clocks, but with higher resolution or colorization of images, high-speed processing and mass data processing are required. There is a situation where the processing speed is not sufficient even if the progress of circuit technology is taken into consideration.
[0005]
[Problems to be solved by the invention]
In consideration of this, there is a method for performing high-speed processing by operating a plurality of encoders in parallel, as disclosed in Japanese Patent Application Laid-Open No. 2000-21703, for example. However, in this prior art, in order to make the output code into one data string (stream), when there is no code to be output at a timing at which a certain encoder has to output, dummy output is performed. Therefore, there is a problem that the amount of code increases meaninglessly depending on the operation state of each parallel operation encoder.
[0006]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide an image encoding / decoding device capable of high-speed processing and capable of processing efficient code data.
[0007]
[Means for Solving the Problems]
The present invention comprises a number of image encoding / decoding means, and for image data that requires high-speed processing, the image data to be encoded is interleaved in the bit order in the same number as the above-mentioned image encoding / decoding means. A data sequence is formed, and each of the image encoding / decoding means is independently applied to each data sequence to create each code data, and a plurality of code data obtained thereby are collected into one code data file. And encoding the image data, while decoding the code data file, the image encoding / decoding means are independently applied to the plurality of code data included in the data file. Each decoded data is created, and a plurality of decoded data obtained thereby are deinterleaved corresponding to the above interleaving in bit units. Forming the original image data, for high-speed processing is not required image data is obtained by so as to operate in parallel by assigning the plurality of image coding and decoding means to each one of the image data processing.
[0008]
For image data that includes a plurality of image encoding / decoding means and requires high-speed processing, the image data to be encoded is interleaved in the line order in the same number as the image encoding / decoding means, and a plurality of data series Forming the code data by applying the above-mentioned image coding / decoding means independently for each data series, and combining the plurality of code data obtained thereby to form one code data file The image data is encoded, and when the code data file is decoded, each of the plurality of image encoding / decoding means is independently applied to the plurality of code data included in the data file. Create decoded data, and de-interleave multiple decoded data obtained by that corresponding to the above interleaving in line units. The image data is formed of, for high-speed processing unnecessary image data, it is obtained so as to operate in parallel by assigning the plurality of image coding and decoding means to each one of the image data processing.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0016]
FIG. 1 shows an example of an encoding apparatus according to an embodiment of the present invention.
[0017]
In the figure, image data CD to be encoded is sequentially stored in the FIFO buffer 2 via the input circuit 1. Then, the image data CD read from the FIFO buffer 2 is added to the image separation unit 3.
[0018]
The image separation unit 3 interleaves input image data CD into two systems in a bit order. For example, as shown in FIGS. 2A to 2C, the odd-numbered bits A1, A2, A3,... And the even-numbered bits B1, B2, B3,. The
[0019]
The interleaved image data CDa and CDb of the respective systems are input to the data buffers 4a and 4b, respectively. The image data CDa and CDb output from the data buffers 4a and 4b are respectively encoded by the encoders 5a and 5b. Independent encoding processing is applied by the encoders 5a and 5b.
[0020]
The two systems of code data IDa and IDb output from the encoders 5a and 5b are output to the next stage device (not shown) via the output circuits 6a and 6b, respectively.
[0021]
At this time, in the next stage apparatus, as shown in FIG. 2 (d), the code data IDa and IDb are handled as independent A signal sequence code data file FDa and B signal sequence code data file FDb, respectively. The A signal sequence code data file FDa and the B signal sequence code data file FDb are collectively handled as one code data file FD corresponding to the original image data CD.
[0022]
FIG. 3 shows an example of a decoding apparatus that decodes the code data file FD to form the original image data CD.
[0023]
In the figure, the code data IDa of the A signal series code data file FDa included in the code data file FD is input via the input circuit 11a and temporarily stored in the data buffer 12a.
[0024]
The code data IDa output from the data buffer 12a is added to the decoder 13a, and is converted into partial image data CPa by applying a corresponding decoding process. The partial image data CPa is added to the pixel synthesis unit 15 via the FIFO buffer 14a.
[0025]
The code data IDb of the B signal series code data file FDb included in the code data file FD is input via the input circuit 11b and temporarily stored in the data buffer 12b.
[0026]
The code data IDb output from the data buffer 12b is added to the decoder 13b, applied with a corresponding decoding process, and converted into partial image data CPb. The partial image data CPb is added to the pixel synthesis unit 15 via the FIFO buffer 14b.
[0027]
The pixel synthesis unit 15 synthesizes (deinterleaves) the partial image data CPa and the partial image data CPb in bit order. That is, the A signal sequence partial image data CPa as shown in FIG. 4A and the B signal sequence partial image data CPb as shown in FIG. 4B are deinterleaved and shown in FIG. Such integrated image data CC is formed. The image data CC is output to the next stage device (not shown) via the output circuit 16.
[0028]
In this way, in this embodiment, the image data CD is interleaved into two systems in the bit order, and each system is encoded in parallel by the independent encoders 5a and 5b, and the code obtained thereby Since each data is processed as a single data stream (in this case, filed), the encoding speed can be doubled, which is very convenient.
[0029]
Also, when decoding such code data, two decoders can process in parallel, reducing the time required for the decoding process by half and realizing a high-speed decoding process. can do.
[0030]
In the above-described embodiment, code data is interleaved in two systems, but may be interleaved in an arbitrary number of systems of three or more. In that case, a code processing system and a decoding processing system corresponding to the number of systems to be divided are required.
[0031]
FIG. 5 shows an example of an encoding apparatus according to another embodiment of the present invention.
[0032]
In the figure, for example, image data CA output from a low-speed image source having a low throughput speed such as a facsimile processing system is added to the FIFO buffer 22a via the input circuit 21a, and is then selected via the FIFO buffer 22a via the selector 23a. Is applied to one of the input terminals.
[0033]
Further, image data CB output from a low-speed image source or a high-speed image source having a high throughput speed such as a digital copy processing system is added to the FIFO buffer 22b via the input circuit 21b, and then via the FIFO buffer 22b. , Added to one input terminal of the pixel separator 24 and the selector 23b.
[0034]
The pixel separation unit 24 interleaves the image data CB into two data series in the bit order. One data series is added to the other input terminal of the selector 23a, and the other data series is It is added to the other input terminal of the selector 23b.
[0035]
The selector 23a selects the output of the FIFO buffer 22a in the case of the low-speed image processing mode, and selects the output of the pixel separation unit 24 in the case of the high-speed image processing mode. The signal is added to the encoder 26a through the buffer 25a.
[0036]
The encoder 26a applies a predetermined encoding process to the input image data, and the output is output as encoded data to the next stage device (not shown) via the output circuit 27a.
[0037]
The selector 23b selects the output of the FIFO buffer 22b in the low-speed image processing mode, and selects the output of the pixel separation unit 24 in the high-speed image processing mode. Are added to the encoder 26b through the data buffer 25b.
[0038]
The encoder 26b applies a predetermined encoding process to the input image data, and the output is output as code data to the next stage device (not shown) via the output circuit 27b.
[0039]
With the above configuration, when the low-speed image processing mode is set, the selector 23a selects the FIFO buffer 22a, whereby the image data CA output from the FIFO buffer 22a is sent to the data buffer 25a via the selector 23a. Is output.
[0040]
The image data CA output from the data buffer 25a is encoded and compressed by the encoder 26a, and is output as code data to the next stage device via the output circuit 27a.
[0041]
When the low-speed image processing mode is set, the selector 23b selects the FIFO buffer 22b, whereby the image data CB output from the FIFO buffer 22b is output to the data buffer 25b via the selector 23b. .
[0042]
The image data CB output from the data buffer 25b is encoded and compressed by the encoder 26b, and is output as code data to the next stage device via the output circuit 27b.
[0043]
In this way, this encoding device can realize a function of processing two sets of image data in parallel in the low-speed image processing mode.
[0044]
On the other hand, when the high-speed image processing mode is set, the selector 22a and the selector 22b select partial image data output from the pixel separation unit 24, respectively.
[0045]
Thereby, the image data CB input via the input circuit 21b is separated into two signal series by the pixel separation unit 24, and the partial image data of one signal series is sent to the data buffer 25a via the selector 23a. The input partial image data of the other signal series is input to the data buffer 25b via the selector 23b.
[0046]
Therefore, in this case, the partial image data of one signal series is encoded by the encoder 26a, and is output to the next stage apparatus as the A signal series code data as described above, for example, via the output circuit 27a.
[0047]
Further, the partial image data of the other signal series is encoded by the encoder 26b, and is output to the next stage apparatus as B signal series code data as described above, for example, via the output circuit 27b.
[0048]
In the next stage apparatus, the A signal sequence code data file composed of A signal sequence code data and the B signal sequence code data file composed of B signal sequence code data are handled as independent code data files. The signal sequence code data file and the B signal sequence code data file are collected and handled as one code data file corresponding to the original image data.
[0049]
As described above, in the encoding apparatus according to the present embodiment, two systems of encoding processing can be executed in the low-speed image processing mode, and in the high-speed image processing mode, low-speed images are processed for image data that requires high-speed processing. Since the encoding process can be performed at a processing speed twice as high as that in the processing mode, the present invention can be applied to both a low-speed image source and a high-speed image source, and the availability of this encoding apparatus is very large.
[0050]
FIG. 6 shows an example of a decoding apparatus according to another embodiment of the present invention.
[0051]
In the figure, code data PA is added to a data buffer 32a via an input circuit 31a, and is added to a decoder 33a via a data buffer 32a. The decoder 33a converts the input code data PA into image data by applying a corresponding decoding process. This image data is added to the output circuit 35a and one input terminal of the pixel synthesis unit 36 via the FIFO buffer 34a.
[0052]
The code data PB is added to the data buffer 32b via the input circuit 31b, and is added to the decoder 33b via the data buffer 32b. The decoder 33b converts the input code data PB into image data by applying a corresponding decoding process. This image data is added to the other input terminal of the pixel composition unit 36 and one input terminal of the selector 37 via the FIFO buffer 34 b.
[0053]
The pixel synthesizing unit 36 synthesizes the image data output from the FIFO buffer 34 a and the image data output from the FIFO buffer 34 b in bit order, and the output is added to the other input terminal of the selector 37. It is done.
[0054]
The selector 37 selects the output of the FIFO buffer 34b in the low-speed processing mode, and selects the output of the pixel synthesizer 36 in the high-speed processing mode. The output is output via the output circuit 35b. Output to the next stage device. In the high-speed processing mode, the output circuit 35a is in an output prohibited state.
[0055]
With the above configuration, in the low-speed processing mode, the selector 37 selects the output of the FIFO buffer 34b, and independent code data is added to the input circuit as code data PA and PB.
[0056]
Therefore, in this case, the decoding device functions as a decoding device having two independent processing systems (two channels).
[0057]
On the other hand, in the high-speed processing mode, the code data file as shown in FIG. 2D is to be processed, the code data of the A signal sequence code data file FDa is added as the code data PA, and the B signal sequence The code data of the code data file FDb is added as code data PB. Further, in this case, the selector 37 selects the output of the pixel synthesis unit 36, and the output circuit 35a is in an output prohibited state.
[0058]
As a result, the A signal sequence code data is added to the decoder 33a via the input circuit 31a and the data buffer 32a, and is converted into one partial image data by applying a corresponding decoding process. The partial image data is added to the pixel composition unit 36 via the FIFO buffer 34a.
[0059]
Further, the B signal series code data is added to the decoder 33b via the input circuit 31b and the data buffer 32b, and is converted into the other partial image data by applying a corresponding decoding process. This partial image data is added to the pixel composition unit 36 via the FIFO buffer 34b.
[0060]
The pixel synthesis unit 36 synthesizes (deinterleaves) one partial image data output from the FIFO buffer 34a and the other partial image data output from the FIFO buffer 34b in a bit order. That is, the A signal sequence (one) partial image data as shown in FIG. 4A and the B signal sequence (other) partial image data as shown in FIG. Integrated image data as shown in FIG. The image data is output to the next stage device (not shown) via the selector 37 and the output circuit 35b.
[0061]
In the above embodiment, a plurality of signal sequence code data are generated by interleaving the image data to be encoded in the bit order. However, this interleaving mode can be set in units of lines.
[0062]
Here, there is a concept that an image is treated as one of two-dimensional directions as a main scanning direction and the other perpendicular direction as a sub-scanning direction. The above-described line unit indicates a line in the main scanning direction or a line in the sub-scanning direction. For example, when image data is created by reading an original image with a scanner or the like, the line in the main scanning direction is often indicated.
[0063]
At the time of encoding in this case, the original image data as shown in FIG. 7A is converted into odd-numbered lines A1, A2, A3,... And even-numbered lines B1, B2, B3,. Are interleaved to form an A signal sequence as shown in FIG. 4B and a B signal sequence as shown in FIG. Apply.
[0064]
At the time of decoding, an A signal sequence as shown in FIG. 8A and a B signal sequence as shown in FIG. Are alternately combined (deinterleaved) to form the original image data.
[0065]
【The invention's effect】
As described above, according to the present invention, image data is interleaved into a plurality of systems in the bit order or line order, and each system is encoded in parallel by an independent encoder and obtained by this. Since the encoded data is processed as a single data stream (in this case, filed), the encoding speed can be greatly increased, which is very convenient.
[0066]
In addition, when decoding such code data, it can be processed in parallel by a plurality of decoders, so the time required for the decoding process is reduced by half and high-speed decoding processing is realized. The effect that it can do is also acquired.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of an encoding apparatus according to an embodiment of the present invention.
FIG. 2 is a schematic diagram for explaining a mode of bit order interleaving during encoding.
FIG. 3 is a block diagram showing an example of a decoding device according to an embodiment of the present invention.
FIG. 4 is a schematic diagram for explaining a mode of deinterleaving of bit order at the time of decoding.
FIG. 5 is a block diagram showing an example of an encoding apparatus according to another embodiment of the present invention.
FIG. 6 is a block diagram showing an example of a decoding device according to another embodiment of the present invention.
FIG. 7 is a schematic diagram for explaining an interleaving mode of line order at the time of encoding.
FIG. 8 is a schematic diagram for explaining a mode of deinterleaving of line order at the time of decoding.
[Explanation of symbols]
1, 11a, 11b, 21a, 21b, 31a, 31b Input circuit 2, 14a, 14b, 22a, 22b, 34a, 34b FIFO buffer 3, 24 Pixel separation unit 4a, 4b, 12a, 12b, 25a, 25b, 32a, 32b Data buffers 5a, 5b, 26a, 26b Encoders 6a, 6b, 16, 27a, 27b, 35a, 35b Output circuits 13a, 13b, 33a, 33b Decoders 15, 36 Pixel synthesis units 23a, 23b, 37 selectors

Claims (2)

A plurality of image encoding and decoding means,
For image data that requires high-speed processing, the image data to be encoded is interleaved in the same order as the image encoding / decoding means in the bit order to form a plurality of data sequences, and the image encoding is performed for each data sequence. While creating each code data to which each decoding means is applied independently, a plurality of code data obtained thereby is combined into one code data file to encode the image data,
When decoding the code data file, each of the plurality of code data included in the data file is independently applied to each of the plurality of image encoding / decoding means, and the decoded data is obtained. A plurality of decoded data is deinterleaved in bit units corresponding to the above interleave to form the original image data,
An image coding / decoding apparatus, wherein image data that does not require high-speed processing is assigned to each of the plurality of image coding / decoding means for one image data processing to be operated in parallel. A plurality of image encoding and decoding means,
For image data that requires high-speed processing, the image data to be encoded is interleaved in the line order in the same number as the image encoding / decoding means to form a plurality of data sequences, and the image encoding is performed for each data sequence. While creating each code data to which each decoding means is applied independently, a plurality of code data obtained thereby is combined into one code data file to encode the image data,
When decoding the code data file, each of the plurality of code data included in the data file is independently applied to each of the plurality of image encoding / decoding means, and the decoded data is obtained. A plurality of decoded data is deinterleaved corresponding to the above interleave in line units to form original image data,
An image coding / decoding apparatus, wherein image data that does not require high-speed processing is assigned to each of the plurality of image coding / decoding means for one image data processing to be operated in parallel.

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