JP3920002B2 - Memory bank control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory bank control device and a memory bank control method, and more particularly to a memory bank control device and a memory bank control method in a FIFO (First In First Out) buffer system used for image / audio signal processing.
[0002]
[Prior art]
A memory bank control device and a memory bank control method in a conventional FIFO buffer system will be described with reference to FIGS. 9, 10, and 11. FIG.
FIG. 9 is a block electric circuit diagram of a memory bank control device in a conventional FIFO buffer system. M0 (13) to M3 (16) are storage areas in which data is input / output in the FIFO format.
FIG. 10 is a diagram showing the operation of the bank address counter used in the memory bank control device in the conventional FIFO buffer system.
[0003]
In the memory bank control device in the conventional FIFO buffer system, a counter constituted by all values represented by binary numbers is used as a counter constituting the flag of the storage area. FIG. 10 shows a counter when the flag is composed of 2 bits. In this case, the counter is composed of four flags 00 (b), 01 (b), 10 (b), and 11 (b). (Hereinafter, (b) indicates that the value is a binary number).
FIG. 11 is a flowchart showing the operation of the write permission signal generator. When the read field address is 01 (b) and the write field address is 10 (b), the operation of the write permission signal generator will be described according to the flow of FIG. When the field writing is completed in this state (S21), 1 is added to the writing field address (S22) to become 11 (b), and the value is compared with the reading field address. When the read field address is referred to, when it is in a transient state (FIG. 10) and 11 (b) is referred to as the read field address, it is determined that the read field address and the write field address are the same, and the write field address is 2 Are added to obtain 01 (b).
[0004]
[Problems to be solved by the invention]
However, in the memory bank control method in the conventional FIFO buffer system described above, a counter composed of all values represented by binary numbers is used. For this reason, the counter value in the transient state also indicates another memory bank in the same manner as the counter value in the normal state. As a result, there is a problem that malfunction may occur when the counter value in the transient state is referred to. Specifically, since the field memory is not written for two fields, the data is not updated, and when reading is performed, a phenomenon occurs in which the image is discontinuous or disturbed.
Furthermore, depending on the timing of reading and writing, there is a problem that the read address overtakes the write address or vice versa, resulting in the phenomenon that the image is discontinuous or disturbed.
[0005]
The present invention has been made in view of such a problem in the conventional technology, and reading and writing of a memory are asynchronous, and address overtaking does not occur even when reading and writing of a memory are performed simultaneously. An object is to provide a memory bank control method.
[0006]
[Means for Solving the Problems]
The memory bank control method of the present invention for solving the above-mentioned problem shifts the write bank flag and the read bank flag in which only one of a plurality of 1 bits constituting the bank flag is "1", and the write bank flag And a memory bank control method for selecting a different memory bank of memories composed of at least three or more memory banks by a read bank flag and performing a write operation and a read operation asynchronously,
When performing a read operation,
When two or more 1 bits constituting the write bank flag indicate “1”, or when all 1 bits constituting the write bank flag indicate “0”, the read bank flag is shift-controlled. On the other hand, when only one of a plurality of 1 bits constituting the write bank flag indicates “1”, the read bank flag after the shift control is compared with the current write bank flag. If they match, the read bank flag value before the shift control is used for reading, and if they do not match, the read bank flag value after the shift control is used for reading.
Also, the memory bank control method of the present invention shifts and controls the write bank flag and the read bank flag in which only one of a plurality of 1 bits constituting the bank flag is “1”, and the write bank flag and read bank A memory bank control method for selecting a different memory bank of memories composed of at least three or more memory banks according to a flag and performing a write operation and a read operation asynchronously,
When performing a write operation,
When two or more 1 bits constituting the read bank flag indicate “1”, or when all 1 bits constituting the read bank flag indicate “0”, the write bank flag is shift-controlled. On the other hand, if only one of a plurality of 1 bits constituting the read bank flag indicates “1”, the write bank flag after the shift control is compared with the current read bank flag. If they match, writing is performed using the value of the write bank flag before the shift control, and if not, writing is performed using the value of the write bank flag after the shift control.
[0007]
According to such a memory bank control method of the first and second inventions of the present application, two or more 1 bits are represented by a binary number and a plurality of flags (hereinafter referred to as a plurality of bits) constituting the bank flag. "1" state and all the 1-bit indicates "0" state and a plurality of bits of the write bank flag indicating a plurality of bits of the read bank flag as possible out to prevent a state of the same value .
Therefore, in the memory control device in which the read operation and the write operation are performed asynchronously, overtaking of the address can be prevented even if the read and write are performed simultaneously.
In addition, the ring counter can circulate data internally to perform a counting operation, and a shift register using N flip-flops can form an N-ary counter.
Further, for example, when one bit of two or more flags constituting either one of the write bank flag and the read bank flag indicates “1”, the bank flag is detected as an abnormal value. . The bank flag detected as an abnormal value is processed as a non-existing value, and ring counter shift control is performed.
Therefore, duplication of both bank flags can be prevented. Further, reading and writing are asynchronous, and address overtaking can be easily prevented even when reading and writing are performed simultaneously.
[0014]
According to the memory bank control device of the fifth and sixth inventions of the present application, two or more 1 bits are represented by a binary number and a plurality of flags (hereinafter referred to as a plurality of bits) constituting the bank flag. "1" state and all the 1-bit indicates "0" state and a plurality of bits of the write bank flag indicating a plurality of bits of the read bank flag as possible out to prevent a state of the same value .
Therefore, in the memory control device in which the read operation and the write operation are performed asynchronously, overtaking of the address can be prevented even if the read and write are performed simultaneously.
In addition, the ring counter can circulate data internally to perform a counting operation, and a shift register using N flip-flops can form an N-ary counter.
Further, since the bank flag indicating each operation at the time of data writing and data reading is provided, duplication of both bank flags can be prevented.
Further, for example, when one bit of two or more flags constituting either one of the write bank flag and the read bank flag indicates “1”, the bank flag is detected as an abnormal value. . The bank flag detected as an abnormal value is processed as a non-existing value, and ring counter shift control is performed.
Therefore, duplication of both bank flags can be prevented. Further, reading and writing are asynchronous, and address overtaking can be easily prevented even when reading and writing are performed simultaneously.
Further, when all of a plurality of bits constituting either one of the write bank flag and the read bank flag indicate “0”, the bank flag is detected as an abnormal value.
Therefore, duplication of both bank flags can be prevented. Further, reading and writing are asynchronous, and address overtaking can be easily prevented even when reading and writing are performed simultaneously.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of a memory bank control method and a memory bank control apparatus according to the present invention will be described with reference to the drawings.
Referring to FIG. 1, there is shown a memory bank control block using flags in the embodiment of the present invention. In FIG. 1, a memory 1 includes three memory banks 101, 102, and 103 , and inputs and outputs data in a FIFO format.
The read bank flag 4 is a flag representing a memory bank that is currently reading.
The write bank flag 5 is a flag representing a memory bank that is currently being written.
Referring to FIG. 2, there is shown a counter that shift-controls the read bank flag 4 and the write bank flag 5. As shown in FIG. 2, the counter that controls the shift of the read bank flag 4 and the write bank flag 5 is a ring counter. This ring counter is set so that only one bit of a plurality of flags (hereinafter referred to as a plurality of bits) constituting the memory bank is set to “1”. That is, there is no state where a plurality of bits in the memory bank indicate “1”, a state where all the bits indicate “0”, and a state where the read bank flag 4 and the write bank flag 5 indicate the same value. Therefore, it is possible to determine that the bank flag in such a state, that is, a transient state, is abnormal.
[0024]
The read control unit 2 advances the read memory bank of the memory 1 according to the truth table of FIG. A read reset and a write bank flag 5 are input to the read control unit 2, and an input / output connection is made with the read bank flag 4.
The write control unit 3 advances the write memory bank of the memory 1 according to the truth table of FIG. A write reset and a read bank flag 4 are input to the write control unit 3, and an input / output connection with the write bank flag 5 is made.
The read control unit 2 and the write control unit 3 correspond to an abnormal value detection unit.
A read signal, a read reset, and a read bank flag 4 are input to the read address counter 6, and a read address is output to the memory bank 101, the memory bank 102, and the memory bank 103 of the memory 1.
A write signal, write reset, and write bank flag 5 are input to the write address counter 7, and a write address is output to the memory bank 101, the memory bank 102, and the memory bank 103 of the memory 1.
The write bank selector 111 receives the write bank flag 5 and a write signal.
A read bank flag 4 and a read signal are input to the read bank selector 112 .
[0025]
Next, the configuration of the read control unit 2 and the write control unit 3 will be described in detail with reference to FIGS.
The write control unit 3 is configured as shown in FIG.
As shown in FIG. 3, the write bank flag 5 (N) (N is a natural number) is input to the flag left shifter 201 and connected to the flag decoder 205 .
The coincidence detector 202 receives the write bank flag 5 and the read bank flag 4 after the left shift , and the output is connected to the AND gate.
The read bank flag discriminator 203 receives the read bank flag 4 and outputs the discrimination result to the AND gate.
The flag decoder 205 is connected to the selector and outputs the write bank flag 5 (N + 1).
The timing adjuster 204 is connected to a write reset, and a write update timing signal is output.
[0026]
Similarly, the read control unit 2 is configured as shown in FIG.
As shown in FIG. 4, the read bank flag 4 (N) is input to the flag left shifter 301 and connected to the flag decoder 305 .
The coincidence detector 302 receives the read bank flag 4 and the write bank flag 5 after the left shift , and the output is connected to the AND gate.
The write bank flag discriminator 303 receives the write bank flag 5 and outputs the discrimination result to the AND gate.
The flag decoder 305 is connected to the selector and outputs the read bank flag 4 (N + 1).
The timing adjuster 304 is connected to a read reset, and a read update timing signal is output.
[0027]
Next, operations of the read address counter 6 and the write address counter 7 in the embodiment of the present invention will be described with reference to FIG.
The read address counter 6 indicates the address at the time of read access to the memory bank designated by the read bank flag 4. When a read reset is input to the read address counter 6, the read address counter 6 sets the top address of the memory bank specified by the read bank flag 4. When the read signal is input, the address value is counted up. However, a read reset is input so that the final address of each memory bank is not exceeded.
Similarly, the write address counter 7 indicates the address at the time of write access to the memory bank designated by the write bank flag 5. When a write reset is input to the write address counter 7, the write address counter 7 sets the top address of the memory bank specified by the write bank flag 5. When a write signal is input, the address value is counted up. However, a write reset is input so that the final address of each memory bank is not exceeded.
The read bank selector 112 distributes the read signal by the read bank flag 4 so that the input data and the read address input in common to each memory bank are valid only in one of the memory banks.
Similarly, the write bank selector 111 distributes the write signal by the write bank flag 5 in order to validate the input data and the write address input in common to each memory bank only in one of the memory banks.
[0028]
Next, operations of the read control unit 2 and the write control unit 3 in the embodiment of the present invention will be described with reference to FIGS.
First, as shown in FIG. 3, the write bank flag 5 (N) input to the flag left shifter 201 represents the current write memory bank, and the write bank flag 5 (N + 1) output from the flag decoder 205. Represents a memory bank to be written next.
The coincidence detector 202 outputs the value 1′b1 if the write bank flag 5 and the read bank flag 4 after the left shift match, and 1′b0 otherwise.
The read bank flag discriminator 203 outputs 1′b1 when the read bank flag 4 is any one of 001 (b), 010 (b), and 100 (b), and outputs 1′b0 otherwise.
The timing adjuster 204 receives the write reset signal as an input, and generates a signal indicating the timing for writing the write bank flag 5 (N + 1).
[0029]
The operation of the read control unit 2 shown in FIG. 4 is performed similarly to the operation of the write control unit 3 shown in FIG. That is, in FIG. 4, the read bank flag 4 (N) input to the flag left shifter 301 represents the current read memory bank, and the read bank flag 4 (N + 1) output from the flag decoder 305 is Represents the memory bank to be read.
The coincidence detector 302 outputs the value 1′b1 if the read bank flag 4 and the write bank flag 5 after the left shift match, and 1′b0 otherwise.
The write bank flag discriminator 303 outputs 1′b1 when the write bank flag 5 is any of 001 (b), 010 (b), and 100 (b), and outputs 1′b0 otherwise.
The timing adjuster 304 receives the read reset signal as an input, and generates a signal indicating the timing for reading the read bank flag 4 (N + 1).
[0030]
Next, the operation of the memory bank control block using the flag in the embodiment of the present invention will be described using the flowcharts shown in FIGS.
When performing a write operation, as shown in FIG. 5, when a system reset is applied, the write bank flag 5 is initialized to 001 (b) (S1), and input data is stored in the memory 1 until a write reset is input. Is written into the memory bank 101 (S2).
When a write reset is given (S3), the write bank flag 5 is shifted to the left as shown in FIG. 2 (S4).
Here, the value of the read bank flag 4 is read (S5). If the read bank flag 4 = the write bank flag 5 after the left shift (S6), the write bank flag 5 is shifted to the right (S7). However, if the read bank flag 4 is other than the specified value, or if the read bank flag 4 is not equal to the write bank flag 5 after the left shift , the write bank flag 5 is decoded (S8), and writing is permitted and executed (S9). . Here, the specified value refers to values 001 (b), 010 (b), and 100 (b) indicating the memory bank.
[0031]
The above flow will be described with reference to FIGS. 1 and 7 in the case where a write reset is given.
As an example, consider the case where the read bank flag 4 is 010 (b).
First, when the write reset signal becomes 1 when the write bank flag 5 is 001 (b), it is desired to advance the write memory bank from the memory bank 101 to the memory bank 102 . However, since the read memory bank is the memory bank 102 , when the write memory bank advances to the memory bank 102 , the read memory bank and the write memory bank become the same. As a result, the write address may overtake the read address. In order to solve this problem, the write memory bank is not advanced, and the same memory bank is written again. That is, the write bank flag 5 holds the state of 001 (b).
When the write reset signal becomes 1 when the write bank flag 5 is 100 (b), the write memory bank advances from the memory bank 103 to the memory bank 101 . In this case, the write memory bank can be advanced because the write memory bank does not overlap the read memory bank .
Further, consider a case where the write reset signal becomes 1 when the write bank flag 5 is 010 (b). This is a combination that cannot occur originally, but considers a malfunction or the like. In this case, since the read memory bank and the write memory bank are the same, the access to the same memory bank can be prevented by moving the write memory bank from the memory bank 102 to the memory bank 103 .
The case where the read bank flag 4 is 001 (b) and 100 (b) can be considered in the same manner as the above three patterns.
[0032]
However, if the read bank flag 4 is other than 001 (b), 010 (b), and 100 (b), it is determined that the read bank flag 4 is in a transient state, and the write memory bank is advanced. This prevents the read memory bank from overlapping the write memory bank.
If the read bank flag 4 is other than the specified value, it is assumed that the read bank flag 4 is in a transient state. That is, it means that the write reset and the read reset are performed simultaneously. This means that both the read memory bank and the write memory bank are going to advance to the next memory bank. Therefore, if the read bank flag 4 is other than the specified value, the write bank flag 5 is decoded, and writing is permitted and executed.
The flow when the write reset is given has been described above, but the flow when the read reset shown in FIG. 8 is also performed in the same manner as the flow when the write reset is given.
In the embodiment described above, the memory 1 is composed of three memory banks, but the present invention is not limited to this. The memory bank constituting the memory 1 may be in any format as long as there are three or more storage areas. For example, the memory 1 may be composed of three, and one memory 1 may be divided into three areas.
[0033]
【The invention's effect】
As described above, the memory bank control method and the memory bank control device of the present invention have the following effects.
Since the read bank flag and the write bank flag use a truth table that includes any combination including the transient state, even if each bank flag is in the transient state, the operation considering it can do. Further, in the case where the read access and the write access to the memory are asynchronous, it is possible to operate accurately even when the memory bank switching for read and write is performed at the same time. Accordingly, it is possible to prevent the read address from overtaking the write address, and it is possible to prevent the write address from overtaking the read address. As a result, the interruption of the image and the disturbance of the image can be prevented, and the quality can be maintained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a memory bank control block using a flag in an embodiment of the present invention.
FIG. 2 is a diagram showing an operation of a bank flag in the embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of a write control unit in the embodiment of the present invention.
FIG. 4 is a diagram showing a configuration of a read control unit in the embodiment of the present invention.
FIG. 5 is a flowchart showing an operation of a memory bank write control unit in the embodiment of the present invention.
FIG. 6 is a flowchart showing an operation of a memory bank read control unit in the embodiment of the present invention.
FIG. 7 is a truth table showing an operation when writing a bank flag in the embodiment of the present invention.
FIG. 8 is a truth table showing an operation at the time of reading a bank flag in the embodiment of the present invention.
FIG. 9 is a block electric circuit diagram of a memory bank control device in the prior art.
FIG. 10 is a diagram showing an operation of a bank address counter in the prior art.
FIG. 11 is a flowchart showing the operation of the write permission signal generator in the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Memory 2 Read control part 3 Write control part 4 Read bank flag 5 Write bank flag 6 Read address counter 7 Write address counter
101, 102, 103 memory banks
111 write bank selector
112 read bank selector
201, 301 flag left shifter
202, 302 coincidence detector
203 read bank flag discriminator
204, 304 timing adjuster
303 write bank flag discriminator
205, 305 flag decoder

Claims (2)

A write bank flag and a read bank flag in which only one of a plurality of 1 bits constituting the bank flag is set to “1”, and at least three or more memory banks are configured by the write bank flag and the read bank flag. A memory bank control method for selecting a different memory bank of the memory to be executed and performing a write operation and a read operation asynchronously,
When performing a read operation,
When two or more 1 bits constituting the write bank flag indicate “1”, or when all 1 bits constituting the write bank flag indicate “0”, the read bank flag is shift-controlled. On the other hand, when only one of a plurality of 1 bits constituting the write bank flag indicates “1”, the read bank flag after the shift control is compared with the current write bank flag. If they match, the read bank flag value before the shift control is used for reading, and if not matched, the read bank flag value after the shift control is used for reading. Control method. A write bank flag and a read bank flag in which only one of a plurality of 1 bits constituting the bank flag is set to “1”, and at least three or more memory banks are configured by the write bank flag and the read bank flag. A memory bank control method for selecting a different memory bank of the memory to be executed and performing a write operation and a read operation asynchronously,
When performing a write operation,
When two or more 1 bits constituting the read bank flag indicate “1”, or when all 1 bits constituting the read bank flag indicate “0”, the write bank flag is shift-controlled. On the other hand, if only one of a plurality of 1 bits constituting the read bank flag indicates “1”, the write bank flag after the shift control is compared with the current read bank flag. If they match, writing is performed using the value of the write bank flag before the shift control, and if not, writing is performed using the value of the write bank flag after the shift control. Control method.

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