JP3917472B2 - PLL circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a PLL circuit in which a plurality of voltage controlled oscillators are integrated on a semiconductor integrated circuit substrate.
[0002]
[Prior art]
In recent years, it has become possible to integrate inductors and variable capacitance elements on a semiconductor integrated circuit substrate, so that a voltage-controlled oscillator (hereinafter abbreviated as VCO), which has been conventionally externally mounted, is integrated with other circuits. A PLL circuit integrated on a substrate is realized.
[0003]
However, since the inductance value of the inductor that can be integrated on the semiconductor integrated circuit board is limited, and the variable capacity of the variable capacitor that can be integrated is inferior to that of the conventional discrete capacitor, the semiconductor integrated circuit The frequency variable range of the VCO integrated on the circuit board is inferior to that of a conventional external VCO.
[0004]
Therefore, in the case of a PLL circuit that requires a wide frequency variable range over a wide band, such as a TV (television) tuner, as shown in FIG. 6, by using a combination of a plurality of VCOs having different oscillation frequency ranges, a semiconductor can be obtained. The frequency range of a PLL circuit in which a VCO is integrated on an integrated circuit substrate is expanded.
[0005]
FIG. 6 shows a block diagram of a conventional PLL circuit of this type. In this PLL circuit, for example, one VCO output is selected from three VCO outputs according to the PLL output frequency.
[0006]
In FIG. 6, 101 is a PLL reference oscillation circuit, 102 is a PLL reference frequency divider (1 / Nref), 103 is a PLL phase comparator (PD), 104 is a charge pump circuit (CP), and 105 is a PLL loop filter (LPF). ), 106 is a PLL programmable frequency divider (1 / N). 201 is a first VCO, 202 is a second VCO, 203 is a third VCO, and 204 is a VCO output switching circuit. 401 is a VCO control voltage, 403 is PLL frequency setting data, 405 is a PLL output signal, and 407 is a VCO switching signal. The above configuration is a PLL circuit.
[0007]
Reference numeral 501 denotes a PLL control computer (hereinafter referred to as CPU) that controls the PLL circuit.
[0008]
The operation of the PLL circuit configured as described above will be described below. The oscillation output of the PLL reference oscillation circuit 101 is frequency-divided by 1 / Nref by the PLL reference frequency divider 102 and supplied to the PLL phase comparator 103 as one input. 1 / Nref is a preset frequency division ratio. As the other input of the PLL phase comparator 103, an output of the PLL programmable frequency divider 106 is given. The PLL phase comparator 103 compares these two inputs with each other.
[0009]
The charge / discharge operation of the charge pump circuit 104 is controlled by the output signal of the PLL phase comparator 103. Further, when the output of the charge pump circuit 104 is input to the PLL loop filter 105, a VCO control voltage 401 is obtained. By applying this VCO control voltage 401 to the first VCO 201, the second VCO 202 and the third VCO 203, the first VCO 201, the second VCO 202 and the third VCO 203 each oscillate at a frequency corresponding to the VCO control voltage 401.
[0010]
The CPU 501 outputs PLL frequency setting data 403 according to the PLL output frequency to be output as the PLL output signal 405 and supplies the PLL frequency setting data 403 to the PLL programmable frequency divider 106. Here, the frequency division ratio (1 / N) set in the PLL programmable frequency divider 106 is determined by the PLL frequency setting data 403.
[0011]
At this time, the CPU 501 outputs a VCO switching signal 407 for selecting one of the outputs of the first VCO 201, the second VCO 202, and the third VCO 203 according to the PLL output frequency to be output as the PLL output signal 405. To the VCO output switching circuit 204. As a result, any one of the oscillation outputs of the first VCO 201, the second VCO 202, and the third VCO 203 is selected and supplied to the PLL programmable frequency divider 106. The PLL programmable frequency divider 106 divides the oscillation signal supplied from the VCO output switching circuit 204 by a frequency division ratio determined by the PLL frequency setting data 403 and inputs the result to the PLL phase comparator 103.
[0012]
As described above, the PLL phase comparator 103 performs phase comparison between the output of the PLL reference divider 102 and the output of the PLL programmable divider 106, and controls the charge / discharge operation of the charge pump circuit 104 by the phase comparison output. To do. Then, as described above, the output signal of the charge pump circuit 104 is converted to the VCO control voltage 401 through the PLL loop filter 105 and is supplied to the first VCO 201, the second VCO 202 and the third VCO 203.
[0013]
By the loop operation as described above, the frequency of the output signal of the VCO output switching circuit 204 is controlled to be constant at a frequency corresponding to the PLL frequency setting data 403 output from the CPU 501. The output signal of the VCO output switching circuit 204 controlled to be constant is output to the outside as a PLL output signal 405.
[0014]
[Problems to be solved by the invention]
Since the characteristic of the control voltage versus the capacitance value of the variable capacitance element integrated on the semiconductor generally has a non-linear region with respect to the control voltage of the VCO as shown in FIG. 4, the oscillation frequency sensitivity Kv of the VCO is as shown in FIG. Has a non-linear region with respect to the control voltage. Since the loop gain of the PLL is proportional to the VCO control sensitivity Kv, the non-linear region causes frequency dependence in the oscillation frequency of the VCO versus the loop gain characteristic of the PLL.
[0015]
As for the phase noise characteristic of the PLL, the phase noise characteristic of the VCO itself appears as it is at a frequency away from the vicinity of the carrier, that is, a frequency outside the loop band of the PLL. In order to reduce the phase noise characteristic of the PLL, it is necessary to improve both the inside and outside phase noise characteristics of the PLL loop band. Therefore, it is necessary to reduce the phase noise characteristic of the VCO itself. Here, it is known that the phase noise characteristic of the VCO generally deteriorates in proportion to the VCO control sensitivity Kv. The fact that the VCO control sensitivity Kv has frequency dependence indicates that the phase noise characteristic of the VCO itself is It has frequency-dependent characteristics, and there is a problem of causing frequency-dependent characteristics in the phase noise characteristics of the PLL.
[0016]
The step response characteristic of the PLL is generally a damped vibration characteristic characterized by a natural angular frequency ωn and a damping factor ζ.
[0017]
Here, taking the case where the loop filter is a primary LPF composed of C and R as an example,
N: Frequency division number
Kv; VCO control sensitivity
Kp: Phase comparator gain
τ: Loop filter time constant
τ = CR
, The loop gain K, the natural angular frequency ωn, and the damping factor ζ are respectively expressed by the following equations.
[0018]
K = Kv · Kp · 1 / N (1)
ωn = √ (K / τ) (2)
ζ = 1/2 · √ {N / (τ · K)} (3)
It is generally known that the time until the damped vibration obtained as a result of the step response converges depends on the value of the damping factor ζ. Further, since the PLL lockup time is defined by the time until the PLL step response characteristic converges to a certain range of frequency difference, it is closely related to the PLL step response characteristic. Therefore, the fact that the VCO control sensitivity Kv has frequency-dependent characteristics means that the loop gain has frequency-dependent characteristics from the above equation (1). Since the damping factor ζ and the natural angular frequency ωn are also functions of the loop gain K from the above equations (2) and (3), the phase step response characteristic of the PLL changes depending on the PLL frequency. The same applies to a lag reed filter generally known as a PLL loop filter. From the above, there is a drawback that the PLL lock-up time varies depending on the PLL frequency.
[0019]
In addition, since the nonlinear characteristics of the integrated variable capacitance elements depend on semiconductor manufacturing variations, the oscillation frequency sensitivity characteristics of the VCO vary among individual semiconductor integrated circuits, and the PLL characteristics vary from one semiconductor integrated circuit to another. End up. Therefore, when the user uses the conventional PLL using a plurality of VCOs shown in FIG. 6, it is necessary to set the switching frequency of the VCO according to the characteristics of the plurality of VCOs integrated on each semiconductor integrated circuit. For this reason, the VCO switching signal 407 is required separately, and there is a problem that handling of the PLL becomes complicated.
[0020]
Accordingly, an object of the present invention is to provide a PLL circuit capable of reducing the phase noise characteristics and the frequency dependence characteristics of the lock-up time.
[0021]
Another object of the present invention is to provide a PLL circuit that is easy to handle and simple.
[0022]
[Means for Solving the Problems]
  In order to solve the above-described problem, a PLL circuit according to claim 1 of the present invention is a PLL circuit in which first and second voltage controlled oscillators having different oscillation frequency ranges are integrated on a semiconductor integrated circuit substrate. The frequency at the boundary between the frequency domain for selecting the voltage controlled oscillator and the frequency domain for selecting the second voltage controlled oscillator isSetData storage means for storing first switching frequency setting data, and a frequency divider according to a PLL output frequency to be output as a PLL output signalData for setting the frequency division ratio of the first switching frequency setting data according to the PLL output frequency.A CPU for outputting PLL frequency setting data, a data comparison means for comparing the first switching frequency setting data and the PLL frequency setting data, and the first and second voltage controlled oscillators based on the comparison result by the data comparison means. Output selection means for selecting the output of one voltage controlled oscillator from the output, and the first and second voltage controlled oscillators are used in a frequency range in which the control sensitivity of the first and second voltage controlled oscillators is linear. As described above, the first switching frequency setting data is set.
[0023]
  According to this configuration,First and secondAccording to the characteristics of the voltage controlled oscillator, the switching frequency setting data is stored in the data storage means,FirstThe switching frequency setting data and the PLL frequency setting data are compared by the data comparison means, and the output selection means is based on the comparison result by the data comparison means.First and secondSince the output of one voltage controlled oscillator is selected from the outputs of the voltage controlled oscillator, the VCO switching frequency can be set so that each VCO can be used as much as possible within the linear frequency range of the control sensitivity Kv of the VCO. . Therefore, it is possible to reduce the phase noise characteristics and the frequency dependence characteristics of the lock-up time in the PLL circuit that can change the frequency over a wide band by using a plurality of VCOs.
[0024]
  For VCO switching frequency data, since each PLL circuit has a data storage means, by storing the VCO switching frequency setting data at the time of shipment of the PLL circuit, the user can change the VCO characteristics of each PLL circuit. The PLL circuit can be used easily and simply without considering the above.
  A PLL circuit according to a second aspect of the present invention is the PLL circuit according to the first aspect, further comprising a third voltage controlled oscillator, wherein the data storage means includes a frequency region for selecting the second voltage controlled oscillator and a third voltage controlled oscillator. Second switching frequency setting data for setting a frequency at a boundary with a frequency region for selecting the voltage controlled oscillator is further stored, and the data comparison means includes:Data for setting the frequency division ratio of the frequency divider according to the PLL output frequency to be output as the PLL output signal, and the first switching frequency setting data and the second switching frequency setting data according to the PLL output frequency; With data to comparePLL frequency setting data andFirst and second switching frequency setting data;And the output selection means selects the output of one voltage controlled oscillator from the outputs of the first, second and third voltage controlled oscillators based on the comparison result by the data comparison means, and the second and third The second switching frequency setting data is set so that the second and third voltage controlled oscillators are used in a frequency range in which the control sensitivity of the voltage controlled oscillator is linear.
[0025]
  Further, the claims of the present invention3The PLL circuit according to claim 1, wherein the PLL circuit according to claim 1First and secondVoltage control oscillator selection means for operating one voltage control oscillator whose output is selected by the output selection means from among the voltage control oscillators and stopping the operation of the remaining voltage control oscillators whose output is not selected is further provided. .
  According to a fourth aspect of the present invention, there is provided a PLL circuit according to the second aspect, wherein one output whose output is selected by the output selecting means from the first, second and third voltage controlled oscillators is selected. Voltage control oscillator selection means for operating the voltage control oscillator and stopping the operation of the remaining voltage control oscillator whose output is not selected is further provided.
[0026]
According to this configuration, the voltage-controlled oscillator selection unit stops the operation of the remaining voltage-controlled oscillator whose output is not selected, so that unnecessary spurious components are suppressed from being emitted from the PLL circuit and selected. Since no VCO other than the VCO is operating, the current consumption of the PLL circuit can be reduced.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 is a block diagram of a PLL circuit according to the first embodiment of the present invention. In the present embodiment, a case where three VCOs having different oscillation frequency ranges are integrated on a semiconductor integrated circuit substrate will be described as an example. This PLL circuit selects any one VCO output from, for example, three VCO outputs according to the PLL output frequency. This will be specifically described below.
[0028]
In FIG. 1, 101 is a PLL reference oscillation circuit, 102 is a PLL reference divider (1 / Nref), 103 is a PLL phase comparator (PD), 104 is a charge pump circuit (CP), and 105 is a PLL loop filter (LPF). ), 106 is a PLL programmable frequency divider (1 / N). Reference numeral 201 denotes a first VCO, 202 denotes a second VCO, 203 denotes a third VCO, and 204 denotes a VCO output switching circuit as output selection means. Reference numeral 301 denotes a VCO switching frequency setting data storage circuit as data storage means, and 302 denotes a set value comparison circuit as data comparison means. 401 is a VCO control voltage, 402 is a VCO output switching circuit control signal, 403 is PLL frequency setting data, 404a is first VCO-second VCO switching frequency setting data, 404b is second VCO-third VCO switching frequency setting data, and 405 is PLL output. Signal. The above configuration is a PLL circuit. The VCO switching frequency setting data storage circuit 301 is composed of an EEPROM or the like.
[0029]
Reference numeral 501 denotes a CPU that controls the PLL circuit.
[0030]
In the present embodiment, as shown in FIG. 3, the VCO oscillation frequency variable range is set to increase in the order of the first VCO 201, the second VCO 202, and the third VCO 203. First, the first VCO-second VCO switching frequency setting data 404a and the second VCO-third VCO switching frequency setting data 404b are values such that the VCO is switched at a frequency at which the VCO control sensitivity Kv is constant, as shown in FIG. And stored in the VCO switching setting data storage circuit 301.
[0031]
The first VCO-second VCO switching frequency setting data 404a and the second VCO-third VCO switching frequency setting data 404b correspond to the first VCO-second VCO switching frequency and the second VCO-third VCO switching frequency in FIG. 3, respectively. The frequency region below the first VCO-second VCO switching frequency is the first VCO selection range, the frequency region above the first VCO-second VCO switching frequency and below the second VCO-third VCO switching frequency is the second VCO selection range, and the second VCO selection range. -The frequency region above the third VCO switching frequency is the third VCO selection range.
[0032]
Note that the lower limit of the first VCO selection range is limited by the lower limit of the oscillation frequency range of the first VCO 201. The upper limit of the third VCO selection range is limited by the upper limit of the oscillation frequency range of the third VCO 203.
[0033]
The operation of the PLL circuit configured as described above will be described below. The oscillation output of the PLL reference oscillation circuit 101 is frequency-divided by 1 / Nref by the PLL reference frequency divider 102 and supplied to the PLL phase comparator 103 as one input. 1 / Nref is a preset frequency division ratio. As the other input of the PLL phase comparator 103, an output of the PLL programmable frequency divider 106 is given. The PLL phase comparator 103 compares these two inputs with each other.
[0034]
The charge / discharge operation of the charge pump circuit 104 is controlled by the output signal of the PLL phase comparator 103. Further, when the output of the charge pump circuit 104 is input to the PLL loop filter 105, a VCO control voltage 401 is obtained. By applying this VCO control voltage 401 to the first VCO 201, the second VCO 202 and the third VCO 203, the first VCO 201, the second VCO 202 and the third VCO 203 each oscillate at a frequency corresponding to the VCO control voltage 401.
[0035]
The CPU 501 outputs PLL frequency setting data 403 according to the PLL output frequency to be output as the PLL output signal 405 and supplies the PLL frequency setting data 403 to the PLL programmable frequency divider 106. Here, the frequency division ratio (1 / N) set in the PLL programmable frequency divider 106 is determined by the PLL frequency setting data 403.
[0036]
As described above, when the frequency of the PLL output signal 405 is changed, the frequency division ratio of the PLL programmable frequency divider 106 is set by inputting the PLL frequency setting data 403 from the CPU 501, but at this time, the PLL frequency is set. The setting data 403 is also input to the setting value comparison circuit 302. Then, in the set value comparison circuit 302, the first VCO-second VCO switching frequency setting data 404a and the second VCO-third VCO switching frequency setting data 404b stored in the VCO switching setting data storage circuit 301 are compared with the PLL frequency setting data 403. As a result, a VCO switching circuit control signal 402 is output, and this VCO switching circuit control signal 402 is applied to the VCO output switching circuit 204.
[0037]
The first VCO-second VCO switching frequency setting data 404a and the second VCO-third VCO switching frequency setting data 404b are, for example, data input means (not shown) at the time of shipment according to the manufacturing variation of the VCO integrated on each semiconductor integrated circuit board. To the VCO switching frequency setting data storage circuit 301, the values can be set or changed.
[0038]
As a result, any one of the oscillation outputs of the first VCO 201, the second VCO 202, and the third VCO 203 is selected and supplied to the PLL programmable frequency divider 106. The PLL programmable frequency divider 106 divides the oscillation signal given from the VCO output switching circuit 204 by a frequency division ratio determined by the PLL frequency setting data 403 and inputs the frequency to the PLL phase comparator 103.
[0039]
As described above, the PLL phase comparator 103 performs phase comparison between the output of the PLL reference divider 102 and the output of the PLL programmable divider 106, and controls the charge / discharge operation of the charge pump circuit 104 by the phase comparison output. To do. Then, as described above, the output signal of the charge pump circuit 104 is converted to the VCO control voltage 401 through the PLL loop filter 105 and is supplied to the first VCO 201, the second VCO 202 and the third VCO 203.
[0040]
By the loop operation as described above, the frequency of the output signal of the VCO output switching circuit 204 is controlled to be constant at a frequency corresponding to the PLL frequency setting data 403 output from the CPU 501. The output signal of the VCO output switching circuit 204 controlled to be constant is output to the outside as a PLL output signal 405.
[0041]
In the present embodiment, as described above, the VCO output switching circuit 204 is changed from the three output signals of the first VCO 201, the second VCO 202, and the third VCO 203 by the VCO switching circuit control signal 402 output from the set value comparison circuit 302. Any one VCO output signal is selected.
[0042]
Specifically, as shown in FIG. 3, when the PLL frequency setting data 403 is a value not less than the PLL lower limit frequency and less than the first VCO-second VCO switching frequency setting data 404a, the output of the first VCO 201 is selected and the PLL frequency setting is performed. When the data 403 is a value not less than the first VCO-second VCO switching frequency setting data 404a and less than the second VCO-third VCO switching frequency setting data 404b, the output of the second VCO 202 is selected, and the PLL frequency setting data 403 is the second VCO-third VCO. When the value is not less than the switching frequency setting data 404b and not more than the PLL upper limit frequency, the output of the third VCO 203 is selected.
[0043]
According to the PLL circuit of this embodiment, the first VCO-second VCO switching frequency setting data 404a and the second VCO-third VCO switching frequency setting data 404b are input by data input means (not shown) according to the characteristics of the VCOs 202 to 203. The first VCO-second VCO switching frequency setting data 404a and the second VCO-third VCO switching frequency setting data 404b are stored by the VCO switching frequency setting data storage circuit 301, and the switching frequency setting stored by the VCO switching frequency setting data storage circuit 301 is stored. The data and the PLL frequency setting data 403 are compared by the set value comparator 302, and based on the comparison result by the set value comparator 302, the VCO output switching circuit 204 outputs one VCO from the outputs of the first VCO 201, the second VCO 202 and the third VCO 203. Since so as to select the O output, so that the control sensitivity Kv of the VCO can be used each VCO201~203 as possible linear frequency range can be set VCO switching frequency. Therefore, it is possible to reduce the phase noise characteristics and the frequency dependence characteristics of the lock-up time in the PLL circuit that can change the frequency over a wide band by using a plurality of VCOs 201 to 203.
[0044]
The first VCO-second VCO switching frequency setting data 404a and the second VCO-third VCO switching frequency setting data 404b are the switching frequency setting data and the PLL frequency setting that the PLL circuit individually stores in the VCO switching frequency setting data storage circuit 301. Since the data 403 is stored, the VCO switching frequency setting data storage circuit 301 stores the first VCO-second VCO switching frequency setting data 404a and the second VCO-third VCO switching frequency setting data 404b when the PLL circuit is shipped. However, the PLL circuit can be used easily and simply without considering the VCO characteristics of the individual PLL circuits.
[0045]
(Second Embodiment)
FIG. 2 shows a block diagram of a PLL circuit according to the second embodiment of the present invention. In the present embodiment, as in the first embodiment, a case where three VCOs having different oscillation frequency ranges are integrated on a semiconductor integrated circuit substrate will be described as an example. As in the first embodiment, this PLL circuit selects any one VCO output from, for example, three VCO outputs according to the PLL output frequency. This will be specifically described below.
[0046]
In this PLL circuit, a VCO selection circuit 205 is added as a VCO selection means to the configuration of FIG. The VCO selection circuit 205 receives the VCO switching circuit control signal 402 as an input, and operates only one of the VCOs whose output is selected among the first VCO 201, the second VCO 202, and the third VCO 203 based on the VCO switching circuit control signal 402. And the function of stopping the operation of the remaining VCOs whose outputs are not selected. Other configurations are the same as those of the PLL circuit of FIG.
[0047]
Specifically, the VCO selection circuit 205 generates the first VCO control signal 406a, the second VCO control signal 406b, and the third VCO control signal 406c in response to the input of the VCO switching circuit control signal 402. The first VCO control signal 406a, the second VCO control signal 406b, and the third VCO control signal 406c are the first VCO 201, the second VCO 202, and the third VCO 203 so as to stop the operation of VCOs other than the VCO whose output is selected by the VCO output switching circuit 204. To control the operation.
[0048]
For example, when the output of the first VCO 201 is selected by the VCO output switching circuit 204, the first VCO control signal 406a of the VCO selection circuit 205 turns on the operation of the first VCO 201, and the second VCO control signal 406b turns off the operation of the second VCO 202. The third VCO control signal 406c turns off the operation of the third VCO 203.
[0049]
According to the PLL circuit of this embodiment, the operation of the remaining VCO whose output is not selected by the VCO selection circuit 205 is stopped, so that unnecessary spurious components are suppressed from being emitted from the PLL circuit and selected. Since no VCO other than the operated VCO is operating, the current consumption of the PLL circuit can be reduced.
[0050]
【The invention's effect】
  According to the PLL circuit of claim 1 of the present invention,First and secondIn a PLL circuit that switches and uses a VCO, the VCO control sensitivity Kv can be set in a linear frequency range so that the VCO switching frequency can be set.First and secondBy using the VCO, it is possible to reduce the phase noise characteristics and the frequency dependence characteristics of the lock-up time in the PLL circuit capable of changing the frequency over a wide band.
[0051]
For VCO switching frequency data, since each PLL circuit has a data storage means, by storing the VCO switching frequency setting data at the time of shipment of the PLL circuit, the user can change the VCO characteristics of each PLL circuit. The PLL circuit can be used easily and simply without considering the above.
[0052]
  Claims of the invention3, 4According to the described PLL circuit, since the operation of the remaining voltage-controlled oscillator whose output is not selected is stopped by the voltage-controlled oscillator selecting means, unnecessary spurious components are suppressed from being radiated from the PLL circuit and selected. Since no VCO other than the operated VCO is operating, the current consumption of the PLL circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a PLL circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a PLL circuit according to a second embodiment of the present invention.
FIG. 3 is a characteristic diagram showing VCO control voltage versus VCO oscillation frequency characteristics of a PLL circuit in which three VCOs are integrated.
FIG. 4 is a characteristic diagram showing a general control voltage versus variable capacitance characteristic of an integrated variable capacitance element.
FIG. 5 is a characteristic diagram showing a general control voltage versus oscillation frequency characteristic of a VCO using an integrated variable capacitance element.
FIG. 6 is a block diagram showing a configuration of a conventional PLL circuit using a plurality of VCOs.
[Explanation of symbols]
101 PLL reference oscillation circuit
102 PLL reference divider
103 PLL phase comparator
104 Charge pump circuit
105 PLL loop filter
106 PLL programmable frequency divider
201 First VCO
202 2nd VCO
203 3rd VCO
204 VCO output switching circuit
205 VCO selection circuit
301 VCO switching frequency setting data storage circuit
302 Set value comparison circuit
401 VCO control voltage
402 VCO switching circuit control signal
403 PLL frequency setting data
404a First VCO-second VCO switching frequency setting data
404b 2nd VCO-3rd VCO switching frequency setting data
405 PLL output signal
406a First VCO control signal
406b Second VCO control signal
406c Third VCO control signal
407 VCO switching signal
501 PLL control computer (CPU)

Claims (4)

A PLL circuit in which first and second voltage controlled oscillators having different oscillation frequency ranges are integrated on a semiconductor integrated circuit substrate,
Data storage means for storing first switching frequency setting data for setting a frequency at a boundary between a frequency region for selecting the first voltage controlled oscillator and a frequency region for selecting the second voltage controlled oscillator;
Data for setting the frequency division ratio of the frequency divider according to the PLL output frequency to be output as the PLL output signal and data for comparison with the first switching frequency setting data according to the PLL output frequency A CPU for outputting PLL frequency setting data;
Data comparison means for comparing the first switching frequency setting data and the PLL frequency setting data;
Output selecting means for selecting an output of one voltage controlled oscillator from outputs of the first and second voltage controlled oscillators based on a comparison result by the data comparing means;
A PLL in which the first switching frequency setting data is set so that the first and second voltage controlled oscillators are used in a frequency range in which the control sensitivity of the first and second voltage controlled oscillators is linear. circuit. A third voltage controlled oscillator;
The data storage means further stores second switching frequency setting data for setting a frequency at a boundary between a frequency region for selecting the second voltage controlled oscillator and a frequency region for selecting the third voltage controlled oscillator. ,
The data comparison means includes data for setting a frequency division ratio of a frequency divider in accordance with a PLL output frequency to be output as a PLL output signal, and includes first switching frequency setting data and first data in accordance with the PLL output frequency. Comparing PLL frequency setting data having data to be compared with two switching frequency setting data and the first and second switching frequency setting data ;
The output selection means selects an output of one voltage controlled oscillator from outputs of the first, second and third voltage controlled oscillators based on a comparison result by the data comparison means,
The second switching frequency setting data is set such that the second and third voltage controlled oscillators are used in a frequency range in which the control sensitivity of the second and third voltage controlled oscillators is linear. Item 2. The PLL circuit according to Item 1.   Voltage-controlled oscillator selection for operating one voltage-controlled oscillator whose output is selected by the output selection means from among the first and second voltage-controlled oscillators and stopping the operation of the remaining voltage-controlled oscillator whose output is not selected The PLL circuit according to claim 1, further comprising means.   A voltage for operating one voltage controlled oscillator whose output is selected by the output selecting means from among the first, second and third voltage controlled oscillators, and stopping the operation of the remaining voltage controlled oscillator whose output is not selected. 3. The PLL circuit according to claim 2, further comprising controlled oscillator selection means.

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