JP3914613B2 - バス機構 - Google Patents

バス機構 Download PDF

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Publication number
JP3914613B2
JP3914613B2 JP20797697A JP20797697A JP3914613B2 JP 3914613 B2 JP3914613 B2 JP 3914613B2 JP 20797697 A JP20797697 A JP 20797697A JP 20797697 A JP20797697 A JP 20797697A JP 3914613 B2 JP3914613 B2 JP 3914613B2
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JP
Japan
Prior art keywords
circuit
differential amplifier
signal
transmitter
bus mechanism
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Expired - Fee Related
Application number
JP20797697A
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English (en)
Japanese (ja)
Other versions
JPH10126250A5 (https=
JPH10126250A (ja
Inventor
フレデリック・エー・パーナー
Original Assignee
アバゴ・テクノロジーズ・ジェネラル・アイピー（シンガポール）プライベート・リミテッド
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Application filed by アバゴ・テクノロジーズ・ジェネラル・アイピー（シンガポール）プライベート・リミテッド filed Critical アバゴ・テクノロジーズ・ジェネラル・アイピー（シンガポール）プライベート・リミテッド
Publication of JPH10126250A publication Critical patent/JPH10126250A/ja
Publication of JPH10126250A5 publication Critical patent/JPH10126250A5/ja
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Publication of JP3914613B2 publication Critical patent/JP3914613B2/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
JP20797697A 1996-08-08 1997-08-01 バス機構 Expired - Fee Related JP3914613B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US694,891 1996-08-08
US08/694,891 US5818261A (en) 1996-08-08 1996-08-08 Pseudo differential bus driver/receiver for field programmable devices

Publications (3)

Publication Number Publication Date
JPH10126250A JPH10126250A (ja) 1998-05-15
JPH10126250A5 JPH10126250A5 (https=) 2005-05-19
JP3914613B2 true JP3914613B2 (ja) 2007-05-16

Family

ID=24790682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20797697A Expired - Fee Related JP3914613B2 (ja) 1996-08-08 1997-08-01 バス機構

Country Status (3)

Country Link
US (1) US5818261A (https=)
EP (1) EP0823786A3 (https=)
JP (1) JP3914613B2 (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3173386B2 (ja) * 1996-09-18 2001-06-04 日本電気株式会社 ノイズ除去バスレシーバ
US5977796A (en) * 1997-06-26 1999-11-02 Lucent Technologies, Inc. Low voltage differential swing interconnect buffer circuit
US6184717B1 (en) * 1998-12-09 2001-02-06 Nortel Networks Limited Digital signal transmitter and receiver using source based reference logic levels
US6587323B1 (en) * 1999-12-22 2003-07-01 Intel Corporation Dual pseudo reference voltage generation for receivers
US6697896B1 (en) * 1999-12-31 2004-02-24 Intel Corporation Method and apparatus for implementing high speed signals using differential reference signals
US7099395B1 (en) * 2000-11-07 2006-08-29 Rambus Inc. Reducing coupled noise in pseudo-differential signaling systems
US6545521B2 (en) 2001-06-29 2003-04-08 International Business Machines Corporation Low skew, power sequence independent CMOS receiver device
US6686774B1 (en) * 2001-07-19 2004-02-03 Raza Microelectronics, Inc. System and method for a high speed, bi-directional, zero turnaround time, pseudo differential bus capable of supporting arbitrary number of drivers and receivers
US7127003B2 (en) * 2002-09-23 2006-10-24 Rambus Inc. Method and apparatus for communicating information using different signaling types
US7079427B2 (en) * 2004-07-02 2006-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for a high-speed access architecture for semiconductor memory
US7262634B2 (en) * 2005-01-19 2007-08-28 Altera Corporation Methods of reducing power in programmable logic devices using low voltage swing for routing signals
US20070008004A1 (en) 2005-07-11 2007-01-11 Vikram Santurkar Apparatus and methods for low-power routing circuitry in programmable logic devices
FR2918826B1 (fr) * 2007-07-09 2009-10-02 Excem Soc Par Actions Simplifi Dispositif d'interface pseudo-differentiel avec circuit de commutation.
FR2934728B1 (fr) * 2008-08-04 2010-08-27 Excem Procede de transmission pseudo-differentiel utilisant des variables electriques naturelles
FR2934727B1 (fr) 2008-08-04 2010-08-13 Excem Procede de transmission pseudo-differentiel utilisant des variables electriques modales
FR2941108B1 (fr) 2009-01-15 2013-11-01 Excem Dispositif de transmission utilisant une pluralite de conducteurs de retour elementaires
FR2950761B1 (fr) 2009-09-28 2012-02-10 Excem Procede de transmission pseudo-differentiel utilisant une interconnexion non uniforme
CN116414053A (zh) * 2021-12-30 2023-07-11 北京石竹科技股份有限公司 一种实现1553b总线4m通讯速率的方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2772051B2 (ja) * 1988-09-08 1998-07-02 川崎製鉄株式会社 プログラマブル入出力回路及びプログラマブル論理素子
FR2650452B1 (fr) * 1989-07-27 1991-11-15 Sgs Thomson Microelectronics Point de croisement pour matrice de commutation
US5241224A (en) * 1991-04-25 1993-08-31 Altera Corporation High-density erasable programmable logic device architecture using multiplexer interconnections
FR2682505B1 (fr) * 1991-10-11 1996-09-27 Sgs Thomson Microelectronics Dispositif pour detecter le contenu de cellules au sein d'une memoire, notamment une memoire eprom, procede mis en óoeuvre dans ce dispositif, et memoire munie de ce dispositif.
US5283482A (en) * 1992-07-06 1994-02-01 Ncr Corporation CMOS circuit for receiving ECL signals
US5355035A (en) * 1993-01-08 1994-10-11 Vora Madhukar B High speed BICMOS switches and multiplexers
US5311083A (en) * 1993-01-25 1994-05-10 Standard Microsystems Corporation Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads
US5315178A (en) * 1993-08-27 1994-05-24 Hewlett-Packard Company IC which can be used as a programmable logic cell array or as a register file
US5614844A (en) * 1994-01-27 1997-03-25 Dyna Logic Corporation High speed programmable logic architecture
JP3494469B2 (ja) * 1994-05-26 2004-02-09 株式会社ルネサステクノロジ フィールドプログラマブルゲートアレイ
US5585744A (en) * 1995-10-13 1996-12-17 Cirrus Logic, Inc. Circuits systems and methods for reducing power loss during transfer of data across a conductive line

Also Published As

Publication number Publication date
EP0823786A3 (en) 1998-11-25
EP0823786A2 (en) 1998-02-11
JPH10126250A (ja) 1998-05-15
US5818261A (en) 1998-10-06

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