JP3904587B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that can prevent an upper surface of an electrode provided around a chip mounting area from being covered with a filler, and can reduce the distance between the chip mounting area and the electrode.
For example, in the wiring chip 10 on which the memory device chip 20 and the ASIC 30 are mounted, the thickness of the gold bumps 16 for external connection disposed so as to surround the chip mounting regions 18A and 18B is set as the chip mounting area. The thickness is made larger than the thickness of the gold bumps 13A and 13B. In addition, the gold bumps 16 for external connection are arranged at a predetermined interval. Thereby, even if the distance between the mounting regions 18A and 18B where the memory device chip 20 and the ASIC 30 are mounted and the gold bumps 16 for external connection is shortened, the underfill resin 42 on the upper surface of the gold bumps 16 for external connection can be reduced. Riding is suppressed, and the upper surface of the gold bump 16 for external connection is more reliably prevented from being covered with the underfill resin 42.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device in which two or more chips (for example, a semiconductor chip and a wiring chip (mounting substrate), or between semiconductor chips) are stacked (mounted) and a method for manufacturing the same.

  In recent years, with the increasing scale of LSI and the complexity of processes, a method called SIP (system in package) is spreading by storing different types of semiconductor chips in one package. By this method, it becomes possible to promote multi-functionality such as mixed mounting with semiconductor chips of other companies and mixed mounting with different types of semiconductor chips such as optical and mechanical devices.

  Such conventional SIP technology is disclosed in, for example, Patent Document 1 or Patent Document 2. In this conventional SIP, for example, two different semiconductor chips are stacked and arranged on a lead frame. That is, in the SIP, the semiconductor chip is mounted on the lead frame, and the semiconductor chip is mounted on the chip. The SIP is bonded from the bonding pad of the chip to the lead frame with a wire. The SIP is bonded to the lead frame from the bonding pad of the chip with a wire. As a result, high-density semiconductor integrated circuit chips can be mounted.

  Furthermore, as another example of the prior art, after providing additional wiring on a semiconductor chip, such as CSP (chip size package) or flip chip, solder, gold or copper bumps are generated and mounted. There is a technique that enables high-density semiconductor chip mounting by pressure bonding to a substrate.

  In the case of Philip chip mounting in which a normal semiconductor chip (semiconductor integrated circuit chip) and a mounting substrate are connected via bumps, it is well known that stress is applied to the bumps due to thermal deformation and impact after connection. Yes. For this reason, in order to alleviate the stress concentration in the bump and to improve the adhesion between the semiconductor chip and the substrate, for example, an epoxy-based underfill resin is generally filled between the semiconductor chip and the substrate. It is.

  In these packaging methods, bumps (electrodes) for external connection are disposed around the semiconductor chip mounting region of the mounting substrate. However, if an underfill resin (or a precursor thereof) is poured between the semiconductor chip and the mounting substrate after the semiconductor chip is mounted, the underfill resin is disposed around the semiconductor chip mounting region of the mounting substrate. There is a problem that the upper surface of the external connection bump (electrode) is mounted on the provided upper surface and the upper surface of the external connection bump (electrode) is covered with the underfill resin, resulting in a connection failure.

  Therefore, in Patent Document 3, a dam is provided between the semiconductor chip mounting region on the mounting substrate and the bump (electrode) for external connection to block the underfill resin flowing into the bump (electrode) for external connection. It is disclosed.

JP 2004-134715 A JP 2003-007960 A JP 2005-276879 A

  The dam disclosed in Patent Document 3 is continuously formed so as to surround the periphery of the semiconductor chip mounting region, and the underfill resin overcomes the dam in order to receive and dam the entire pressure that the underfill resin flows. As a result, there is a problem that the upper surface of the bump (electrode) for external connection is covered with the underfill resin.

  On the other hand, the dam disclosed in Patent Document 3 must be provided at a predetermined distance from the semiconductor chip mounting region in order to reliably dam the underfill resin. The distance between the connection electrodes (bumps) and the semiconductor chip mounting region is also increased, which is very disadvantageous from the recent trend of miniaturization of semiconductor devices.

  Further, the present invention is not limited to the case where semiconductor chips are mounted on a mounting substrate, and the same problem arises when semiconductor chips are stacked together.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can prevent the upper surface of the electrode provided around the chip mounting area from being covered with the filler and reduce the distance between the chip mounting area and the electrode. It is to be.

The above problem is solved by the following means. That is,
The semiconductor device of the present invention is
A first chip;
A first connection electrode disposed on a main surface of the first chip;
A second chip for mounting the first chip;
A second connection electrode disposed on a main surface of the second chip, the second connection being electrically connected to the first connection electrode when the first chip is mounted on the second chip. Electrodes for
External connection electrodes arranged at predetermined intervals so as to surround the mounting area of the first chip along the main surface edge of the second chip, and having a thickness larger than the thickness of the second connection electrode An external connection electrode having
A filling material filled between the first chip and the second chip, which is blocked by a side wall of the external connection electrode and in which the filler flows into a gap between the external connection electrodes Agent,
A semiconductor device comprising:

  In the semiconductor device of the present invention, the thickness of the external connection electrode disposed so as to surround the mounting area of the first chip in the second chip on which the first chip is mounted is set to the first connection electrode of the first chip. Since the thickness of the second connection electrode electrically connected to the external connection electrode is larger than that of the second connection electrode, the flow of the filler is blocked by the side wall of the external connection electrode. Covering is prevented. In addition, since the external connection electrodes are arranged at predetermined intervals, the filler flows into the gaps between the external connection electrodes, so that the flow pressure of the filler applied to the side walls of the external connection electrodes is dispersed and reduced. Is done. For this reason, even if the distance between the chip mounting region and the electrode is shortened, the loading of the filler onto the upper surface of the external connection electrode is suppressed, and the coating of the upper surface of the external connection electrode with the filler is more reliably prevented.

On the other hand, the method of manufacturing a semiconductor device of the present invention
Forming a second connection electrode on the main surface of the second chip;
Forming an external connection electrode at a predetermined interval so as to surround a mounting area of the first chip along a main surface edge of the second chip and having a thickness larger than the thickness of the second connection electrode; ,
Electrically connecting the first connection electrode provided on the first chip and the second connection electrode, and mounting the first chip on the second chip;
Filling the space between the first chip and the second chip , and damming with a sidewall of the external connection electrode and flowing into the gap between the external connection electrodes;
It is characterized by having.

  In the manufacturing method of the semiconductor device of the present invention, as described in the semiconductor device of the present invention, even when the chip mounting region and the electrode distance are shortened, the loading of the filler onto the upper surface of the external connection electrode is suppressed, Covering the upper surface of the external connection electrode with the filler is prevented.

  According to the present invention, it is possible to provide a semiconductor device and a manufacturing method thereof that can prevent the upper surface of an electrode provided around a chip mounting area from being covered with a filler and reduce the distance between the chip mounting area and the electrode. Can do.

  Next, embodiments to which the present invention can be applied will be described. The following description is to describe the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Moreover, those skilled in the art can easily change, add, and convert each element of the following embodiments within the scope of the present invention. In addition, what attached | subjected the same code | symbol in each figure has shown the same component, and abbreviate | omits description suitably.

  FIG. 1 is a plan view illustrating the semiconductor device according to the embodiment. 2 is a cross-sectional view taken along line AA and BB in FIG. 1. FIG. 3 is a plan view showing a wiring chip in the semiconductor device according to the embodiment. FIG. 4 is a process diagram illustrating the method for manufacturing a semiconductor chip according to the embodiment. FIG. 5 is a partially enlarged plan view showing a state in which an underfill resin (filler) flows in the semiconductor device according to the embodiment.

  As shown in FIGS. 1 to 2, the semiconductor device 100 according to the present embodiment includes a memory device chip 20 (first chip) on the same main surface of a wiring chip 10 (second chip) as an interposer (mounting substrate). ) And an application specific chip (Application Specific Chip: theoretical circuit chip for specific application, hereinafter referred to as ASIC: first chip) 30 is mounted on a Philip chip. An underfill resin 42 is filled between the wiring chip 10 and the storage device chip 20 and the ASIC 30.

  The wiring chip 10 is formed by arranging a plurality of metal wirings (not shown) such as aluminum wires and copper wires on a silicon substrate. As shown in FIGS. 1 to 3, bump pads 11A for mounting the storage device chip 20 and bump pads 11B for mounting the ASIC 30 are respectively provided at one end side and the other end side of each metal wiring. Connected to form a group. These bump pads 11A and 11B are made of a conductive material such as aluminum.

  The bump pads 11 </ b> A and 11 </ b> B of the wiring chip 10 are arranged in a lattice shape corresponding to the storage device chip 20 and the connection pads of the ASIC 30 to be mounted. Of course, the bump pads 11 </ b> A and 11 </ b> B of the wiring chip 10 may be a staggered arrangement or other arrangement depending on the storage device chip 20 and the connection pads of the ASIC 30 to be mounted.

  The wiring pitch of the bump pads 11A and 11B of the wiring chip 10 is appropriately set according to the chip to be mounted. For example, in the present embodiment, 256 Mbit multi-media memory (two) as the memory device chip 20 and a minimum bandwidth of 256 bits × 2 = 512 bits are required for the ASIC 30. The arrangement pitch of the pads 11A and 11B in the X direction is required to be 20 μm. However, the present invention is not limited thereto, and can be set as appropriate within a range of 20 μm to 60 μm, for example.

  The number of bump pads 11A and 11B of the wiring chip 10 is also appropriately set according to the chip to be mounted. For example, in the present embodiment, since the storage device chip 20 includes two 256 Mbit multi-media memories and the ASIC 30, about 2000 are provided. However, the present invention is not limited to this, and can be set as appropriate within a range of, for example, 2000 to 5000 according to the semiconductor chip to be mounted.

  On the bump pads 11A and 11B of the wiring chip 10, chip mounting gold bumps 13A and 13B are disposed via barrier metal layers 12A and 12B, respectively.

  On the wiring chip 10, connection pads 14 for external connection are provided at predetermined intervals along the main surface edge of the wiring chip 10 so as to surround the periphery of the mounting area 18 </ b> A of the storage device chip 20 and the mounting area 18 </ b> B of the ASIC 30. It is arranged. On the connection pad 14 for external connection, a gold bump 16 (external connection electrode) for external connection is disposed via a barrier metal layer 15. The connection pad 14 is made of a conductive material such as aluminum.

  The external connection gold bumps 16 are disposed to be thicker than the chip mounting gold bumps 13A and 13B. In other words, the height (distance) from the main surface of the wiring chip 10 to the upper surface of the gold bump 16 for external connection is the height (distance) from the main surface of the wiring chip 10 to the upper surfaces of the chip mounting gold bumps 13A and 13B. Gold bumps 16 for external connection are arranged so as to increase.

  Specifically, for example, the thickness of the gold bumps 16 for external connection is 1 to 2 μm, the thickness of the gold bumps 13A and 13B for chip mounting is 15 to 20 μm, and the difference between these thicknesses is 14 to 18 μm. .

  The gold bumps 16 for external connection are disposed at predetermined intervals along the main surface edge of the wiring chip 10 so as to surround the mounting area 18A of the storage device chip 20 and the mounting area 18B of the ASIC 30. However, the pitch of this predetermined space | interval is 35-50 micrometers, for example. By setting this range, the underfill resin 42 can easily flow between the gold bumps 16 for external connection.

  The main surface of the wiring chip 10 is covered and protected by a protective layer 17 except for the region where the external connection gold bumps 16 and the chip mounting gold bumps 13A and 13B are disposed.

  Further, since the wiring chip 10 uses the same silicon substrate as the memory device chip 20 and the ASIC 30 to be mounted, the physical strength against heat, expansion and contraction, etc. is high, and high reliability can be ensured.

  The storage device chip 20 is formed on a silicon substrate by a semiconductor process, and in this embodiment, although not shown, for example, two multimedia memories having a storage capacity of 256 Mbit are mounted.

  The storage device chip 20 is not limited to this, and a general-purpose dynamic random access memory (DRAM) can also be used. Similarly, a general-purpose static random access memory (SRAM), a non-volatile storage device, or the like can be used as the storage device chip 20.

  As shown in FIG. 2, the memory device chip 20 is arranged so that the connection pads 21 face the bump pads 11 </ b> A (pad openings) of the wiring chip 10.

  Although not shown, the connection pads 21 of the storage device chip 20 are arranged in a lattice pattern similarly to the bump pads 11A of the wiring chip 10 to form a group. A barrier metal layer 22 is disposed on the connection pad 21.

  The main surface of the wiring chip 10 is covered and protected by a protective layer 27 except for the region where the connection pads 21 (barrier metal layer 22) are provided.

  The storage device chip 20 is arranged so that the wiring chip 10 and the gold bumps (pad openings) face each other, and the gold bumps are physically connected by the solder 40 and electrically connected. Philip chip mounted on top.

  The ASIC 30 is formed on a silicon substrate by a semiconductor process. For example, a logic circuit including a general-purpose CPU is employed. In the present embodiment, since the storage device chip 20 includes two multi-media memories having a storage capacity of 256 Mbits, the bandwidth of the ASIC 30 is 512 bits. Of course, it may be more depending on the storage capacity of the storage device chip 20.

  Further, the ASIC 30 is not limited to this, and for example, a general-purpose analog circuit including an A / D converter that converts an analog signal into a digital signal can be used.

  The ASIC 30 is arranged so that the connection pad 31 faces the bump pad 11B (pad opening) of the wiring chip 10.

  Although not shown, the connection pads 31 of the ASIC 30 are arranged in a lattice pattern similarly to the bump pads 11B of the wiring chip 10 to form a group. A barrier metal layer 32 is disposed on the connection pad 31.

  Further, the main surface of the ASIC 30 is covered and protected by a protective layer 37 except for the region where the connection pad 31 (barrier metal layer 32) is provided.

  The ASIC 30 is arranged so that the wiring chip 10 and the gold bumps (pad openings) face each other, and the gold bumps are physically connected by the solder 40 and electrically connected, and the Philip 30 is formed on the wiring chip 10. Chip mounted.

  The storage device chip 20 and the ASIC 30 are electrically and physically connected via gold bumps (connection pads) for mounting each chip and metal wiring (not shown) of the wiring chip 10. The ASIC 30 is electrically connected to two 256 Mbit multi-media memories as the storage device chip 20, so that signals are input and output in parallel by 512 bits.

  Thus, the bus line connection is achieved by electrically connecting the connection pads 21 (barrier metal layer 22) of the memory device chip 20 and the connection pads 31 (barrier metal layer 32) of the ASIC 30.

  A connection wire 43 is electrically connected to the upper surface of the external connection gold bump 16 of the wiring chip 10, and the connection wire 43 is connected to the outside of the semiconductor device 100.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. FIG. 4 is a process diagram showing a manufacturing process in the cross-sectional view of FIG.

  First, as shown in FIG. 4A, the wiring chip 10 provided with the connection pads 14 for external connection and the bump pads 11A and 11B for chip mounting is shown in FIG. Further, the protective layer 17 is formed so that the connection pads 14 for external connection and the bump pads 11A and 11B for chip mounting are exposed.

  Next, as shown in FIG. 4C, barrier metal layers 12A, 12B, and 15 are formed on the exposed external connection pads 14 and chip mounting bump pads 11A and 11B, respectively. Gold bumps 16 for external connection and gold bumps 13A, 13B for chip mounting are provided on connection pads 14 for external connection and bump pads 11A, 11B for chip mounting via barrier metal layers 12A, 12B, 15. Each is formed by plating treatment with the same thickness.

  Next, as shown in FIG. 4D, the gold bump 16 for external connection is further subjected to a second plating process, and the gold for external connection is thicker than the gold bumps 13A and 13B for chip mounting. Bumps 16 are formed. In addition, the frequency | count of a plating process is not restricted to 2 times, You may be 3 times or more.

  Next, as shown in FIG. 4E, the storage device chip 20 and the ASIC 30 are mounted on the wiring chip 10 so that the gold bumps for chip connection (connection pads for chip mounting) face each other through the solder 40. Mount them facing each other.

  Here, although not shown, in order to improve the electrical connection and physical connection by the solder 40, oil called flux is applied on the upper surface of the gold bump. Since this flux is deteriorated when applied to a connection pad made of aluminum, the gold bumps also play a role in preventing the connection pad from being deteriorated by the flux. Similarly, the external connection gold bumps 16 to which the connection wires 43 are connected also protect the connection pads for external connection.

  Next, as shown in FIG. 4F, the solder 40 is heated and crushed to electrically connect the chip mounting gold bumps between the chips, and then the wiring chip 10 and the memory are connected. An underfill resin 42 is poured into the gap between the device chip 20 and the ASIC 30 and filled.

  At this time, as shown in FIG. 5, the underfill resin is blocked by the side wall of the external connection gold bump 16 disposed on the wiring chip 10 and flows into the gap between the gold bumps 16. The flow pressure of the underfill resin 42 on the side walls of the bumps 16 is dispersed and reduced.

  After filling the underfill resin 42, the connection wires 43 are electrically and physically connected to the upper surface of the external connection gold bumps 16 disposed on the wiring chip 10, so that the external connection of the semiconductor device 100 is performed. Figured.

  In this way, the semiconductor device according to this embodiment can be manufactured.

  In the semiconductor device according to the present embodiment described above, the wiring chip 10 on which the memory device chip 20 and the ASIC 30 are mounted is disposed so as to surround the mounting regions 18A and 18B on which the memory device chip 20 and the ASIC 30 are mounted. The thickness of the gold bumps 16 for external connection is determined by the thickness of the gold bumps 13A and 13B for chip mounting that are electrically connected to the connection pads 21 and 31 (barrier metal layers 22 and 32) of the storage device chip 20 and the ASIC 30. Therefore, the flow of the underfill resin 42 is blocked by the side wall of the gold bump 16 for external connection, and the upper surface of the gold bump 16 for external connection is prevented from being covered with the filler.

  In addition, since the gold bumps 16 for external connection are arranged at a predetermined interval, the underfill resin 42 flows into the gap between the gold bumps 16 for external connection. The flow pressure of the added underfill resin 42 is dispersed and reduced. Therefore, even if the distance between the mounting regions 18A and 18B on which the memory device chip 20 and the ASIC 30 are mounted and the external connection gold bumps 16 is shortened, the underfill resin 42 on the upper surface of the external connection gold bumps 16 can be reduced. Riding is suppressed, and the upper surface of the gold bump 16 for external connection is more reliably prevented from being covered with the underfill resin 42.

  In the present embodiment, the embodiment in which the semiconductor chip is mounted on the wiring chip as the interposer has been described. However, the present invention is also applicable to the mounting of other semiconductor chips on the semiconductor chip in which the electrodes for external connection are provided around the chip. Can do.

It is a top view showing a semiconductor device concerning an embodiment. It is AA sectional drawing and BB sectional drawing of FIG. It is a top view showing a wiring chip in a semiconductor device concerning an embodiment. It is process drawing which shows the manufacturing method of the semiconductor chip which concerns on embodiment. In the semiconductor device concerning an embodiment, it is a partial expansion top view showing signs that underfill resin (filler) flows.

Explanation of symbols

10 Wiring chip (second chip)
11A, 11B Bump pads 12A, 12B, 15 Barrier metal layers 13A, 13B Gold bumps for mounting chips (second connection electrodes)
14 Connection pad 15 for external connection Barrier metal layer 16 Gold bump 17 Protective layer 18A, 18B Semiconductor chip mounting area 20 Storage device chip (first chip)
21 Connection pad (first connection electrode)
22 Barrier metal layer 27 Protective layer 30 ASIC (first chip)
31 connection pad (first connection electrode)
32 Barrier metal layer 37 Protective layer 40 Solder 42 Underfill resin 43 Connection wire 100 Semiconductor device

Claims (3)

A first chip;
A first connection electrode disposed on a main surface of the first chip;
A second chip for mounting the first chip;
A second connection electrode disposed on a main surface of the second chip, the second connection being electrically connected to the first connection electrode when the first chip is mounted on the second chip. Electrodes for
An external connection electrode disposed at a predetermined interval of 35 to 50 μm so as to surround a mounting area of the first chip along a main surface edge portion of the second chip, based on a thickness of the second connection electrode An external connection electrode having a large thickness, and
A filling material filled between the first chip and the second chip, which is blocked by a side wall of the external connection electrode and in which the filler flows into a gap between the external connection electrodes Agent ,
A semiconductor device comprising: Forming a second connection electrode on the main surface of the second chip;
An external connection electrode is formed with a predetermined interval of 35 to 50 μm and a thickness larger than the thickness of the second connection electrode so as to surround the mounting area of the first chip along the main surface edge of the second chip. And a process of
Electrically connecting the first connection electrode provided on the first chip and the second connection electrode, and mounting the first chip on the second chip;
Filling the space between the first chip and the second chip , and damming with a sidewall of the external connection electrode and flowing into the gap between the external connection electrodes;
A method for manufacturing a semiconductor device, comprising: In the step of forming the second connection electrode and the step of forming the external connection electrode, after forming the second connection electrode and the external connection electrode with the same thickness by plating, the external connection electrode 3. The method of manufacturing a semiconductor device according to claim 2, wherein a second plating process is performed to form an external connection electrode having a thickness larger than that of the second connection electrode.

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