JP3895756B1 - Semiconductor device - Google Patents

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JP3895756B1
JP3895756B1 JP2005346148A JP2005346148A JP3895756B1 JP 3895756 B1 JP3895756 B1 JP 3895756B1 JP 2005346148 A JP2005346148 A JP 2005346148A JP 2005346148 A JP2005346148 A JP 2005346148A JP 3895756 B1 JP3895756 B1 JP 3895756B1
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義宏 間淵
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株式会社システム・ファブリケーション・テクノロジーズ
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Abstract

【課題】ノイズやクロストークが生じることなく、チップ間の転送レートを向上させることが可能な半導体装置を提供すること。
【解決手段】記憶装置チップ20及びASIC30における外部(互いのチップ)との接続を図るための接続パッド21,31毎に入出力回路(入力回路27,37、出力回路26,36)を配設し、これらをアレイ状(本実施形態では格子状)に配列している。即ち、入出力回路を含む単位セル領域25,35をアレイ状に配列して、I/Oアレイ(入出力領域24、34)を構成している。そして、記憶装置チップ20及びASIC30を配線チップ10両面にI/Oアレイ(入出力領域24、34)同士を対向させて実装する。
【選択図】図1
A semiconductor device capable of improving a transfer rate between chips without causing noise or crosstalk.
An input / output circuit (input circuits 27 and 37, output circuits 26 and 36) is provided for each connection pad 21 and 31 for connection to the outside (mutual chip) in the memory device chip 20 and the ASIC 30. These are arranged in an array (in this embodiment, a lattice). That is, unit cell regions 25 and 35 including input / output circuits are arranged in an array to form an I / O array (input / output regions 24 and 34). Then, the memory device chip 20 and the ASIC 30 are mounted on both surfaces of the wiring chip 10 with the I / O arrays (input / output areas 24 and 34) facing each other.
[Selection] Figure 1

Description

本発明は、少なくとも2つ半導体チップを互いに電気的に接続した半導体装置に関する。   The present invention relates to a semiconductor device in which at least two semiconductor chips are electrically connected to each other.

近年、LSIの大規模化、プロセスの複雑化に伴い、異種の半導体チップを1つのパッケージに収納することで、SIP(システム・イン・パッケージ)という手法が広まりつつある。この手法により、他社の半導体チップとの混載や、光・機械等の異種の半導体チップとの混載等の多機能化を進める事も可能となる。   In recent years, with the increasing scale of LSI and the complexity of processes, a method called SIP (system in package) is spreading by storing different types of semiconductor chips in one package. By this method, it becomes possible to promote multi-functionality such as mixed mounting with semiconductor chips of other companies and mixed mounting with different types of semiconductor chips such as optical and mechanical devices.

このような従来のSIPの技術が、例えば、特許文献1又は特許文献2に開示されている。この従来のSIPは、例えば、2つの異なる半導体チップを重ねてリードフレーム上にスタック配置している。すなわち、SIPは、半導体チップがリードフレームにマウントされ、半導体チップがチップにマウントされる。そして、このSIPは、チップのボンディング・パッドから、リードフレームへワイヤーでボンディングされている。また、SIPは、チップのボンディング・パッドから、リードフレームへワイヤーでボンディングされている。これにより高密度な半導体集積回路チップの実装を可能としている。   Such conventional SIP technology is disclosed in, for example, Patent Document 1 or Patent Document 2. In this conventional SIP, for example, two different semiconductor chips are stacked and arranged on a lead frame. That is, in the SIP, the semiconductor chip is mounted on the lead frame, and the semiconductor chip is mounted on the chip. The SIP is bonded from the bonding pad of the chip to the lead frame with a wire. The SIP is bonded to the lead frame from the bonding pad of the chip with a wire. As a result, high-density semiconductor integrated circuit chips can be mounted.

さらに、別の従来技術の例として、CSP(チップ・サイズ・パッケージ)やフリップ・チップの様に、半導体チップ上に、追加配線を施した後に、はんだ、金又は銅のバンプを生成して基板と圧着して、高密度な半導体チップの実装を可能とする手法がある。   Furthermore, as another example of the prior art, after providing additional wiring on a semiconductor chip, such as CSP (chip size package) and flip chip, solder, gold or copper bumps are generated to form a substrate. There is a technique that enables high-density semiconductor chip mounting.

とろこで、これらのパッケージング手法における半導体チップ間の電気的な接続については、例えば、非特許文献に示すように、半導体チップの周囲に配列された接続パッド同士を、マイクロバンプを介して行うことが開示されている。   With regard to the electrical connection between the semiconductor chips in these packaging methods, for example, as shown in non-patent literature, connection pads arranged around the semiconductor chip are performed via micro bumps. It is disclosed.

特開2004−134715号公報JP 2004-134715 A 特開2003−007960号公報JP 2003-007960 A 2004 IEEE International Solid−State Circuits Conference(ISCC 2004/SESSION 7/TD:SCALINF TRENDS/7.5)「A 160Gb/s Interface Design for Multichip LSI」 p.140〜1412004 IEEE International Solid-State Circuits Conference (ISCC 2004 / SESSION 7 / TD: SCALINF TRENDS / 7.5) “A 160 Gb / s Interface Design for Multichip LSI”. 140-141

上記非特許文献3も含め、上記パッケージングにおける半導体チップ間では、バス間の転送レートのさらなる向上が求められている。しかしながら、半導体チップ間の転送レート(バス間の転送レート)を上げようと、周波数を上昇させるとノイズが発生したり、接続配線のクロストークなどが生じてしまう。   Further improvement of the transfer rate between the buses is required between the semiconductor chips in the packaging including the non-patent document 3. However, if the frequency is increased in order to increase the transfer rate between semiconductor chips (transfer rate between buses), noise is generated or crosstalk of connection wiring occurs.

従って、本発明の目的は、ノイズやクロストークが生じることなく、チップ間の転送レートを向上させることが可能な半導体装置を提供することである。   Accordingly, an object of the present invention is to provide a semiconductor device capable of improving the transfer rate between chips without causing noise or crosstalk.

上記課題は、以下の手段により解決される。
即ち、本発明の半導体装置は、
チップ厚み方向に貫く複数の貫通電極を有する配線チップと、
主面にアレイ状に配列された第1接続パッド群を有し、さらに当該第1接続パッド群のパッド毎に当該パッドと電気的に接続した第1入出力回路を当該パッドの直下に配設し、且つ当該パッドと共に前記第1入出力回路をアレイ状に配列した第1入出力領域を有する第1半導体チップと、
主面にアレイ状に配列された第2接続パッド群を有し、さらに当該第2接続パッド群のパッド毎に当該パッドと電気的に接続した第2入出力回路を当該パッドの直下に配設し、且つ当該パッドと共に前記第2入出力回路をアレイ状に配列した第2入出力領域を有する第2半導体チップと、
を有し、
前記配線チップを介して前記第1入出力領域と前記第2入出力領域とが対向し、且つ前記複数の各貫通電極を介して前記第1接続パッド群の各パッドと前記第2接続パッド群の各パッドとが各々電気的に接続するように、第1半導体チップ及び第2半導体チップを前記配線チップの第1主面及び第2主面にそれぞれ実装したことを特徴としている。
The above problem is solved by the following means.
That is, the semiconductor device of the present invention is
A wiring chip having a plurality of through electrodes penetrating in the chip thickness direction;
A first input / output circuit having a first connection pad group arranged in an array on the main surface and further electrically connected to the pad for each pad of the first connection pad group is disposed immediately below the pad. And a first semiconductor chip having a first input / output region in which the first input / output circuits are arranged in an array together with the pads;
A second input / output circuit having a second connection pad group arranged in an array on the main surface and further electrically connected to the pad for each pad of the second connection pad group is disposed immediately below the pad. And a second semiconductor chip having a second input / output region in which the second input / output circuits are arranged in an array together with the pads;
Have
The first input / output region and the second input / output region face each other via the wiring chip, and each pad of the first connection pad group and the second connection pad group via the plurality of through electrodes. The first semiconductor chip and the second semiconductor chip are respectively mounted on the first main surface and the second main surface of the wiring chip so that the pads are electrically connected to each other.

本発明の半導体装置では、外部との接続を図るための接続パッド毎に入出力回路を配設し、これらをアレイ状に配列した半導体チップを適用している。この半導体チップは、多ビットのI/Oアレイ(アレイ状に配列された単位セル領域(単位セル領域は入出力回路を含む)で構成される入出力領域)を実現でき、例えば、256〜4096ビットのビット幅を持つことができる。このため、周波数を上昇させる必要がなく、ノイズや接続配線のクロストークなどが発生することなく、バス間の転送レートを飛躍的に改善することができる。   In the semiconductor device of the present invention, an input / output circuit is provided for each connection pad for connection to the outside, and a semiconductor chip in which these are arranged in an array is applied. This semiconductor chip can realize a multi-bit I / O array (an input / output region composed of unit cell regions arranged in an array (the unit cell region includes an input / output circuit)), for example, 256 to 4096. Can have a bit width of bits. For this reason, it is not necessary to increase the frequency, and the transfer rate between the buses can be drastically improved without causing noise or crosstalk of connection wiring.

そして、このようなI/Oアレイ(入出力領域)を有する2つの半導体チップを、互いのI/Oアレイ(入出力領域)を対向させつつ、貫通電極を介して電気的に接続して、配線チップの第1主面及び第2主面にそれぞれ実装している。このため、2つの半導体チップのI/Oアレイ(入出力領域)同士の距離が最短となると共に、配線としての貫通電極の長さ(配線チップの厚み方向長さ)も実質的にその距離と同一となり、最短接続が図れるためバス間の転送レートをさらに改善することができる。   Then, two semiconductor chips having such an I / O array (input / output region) are electrically connected through a through electrode while facing each other's I / O array (input / output region), It is mounted on each of the first main surface and the second main surface of the wiring chip. Therefore, the distance between the I / O arrays (input / output regions) of the two semiconductor chips is the shortest, and the length of the through electrode as the wiring (the thickness direction length of the wiring chip) is substantially equal to the distance. Since they are the same and the shortest connection can be achieved, the transfer rate between the buses can be further improved.

ここで、「入出力回路」とは、信号の入力及び出力の双方の機能を有する回路のみならず、入力単独の機能を有する回路、出力単独の機能を有する回路をも含む。つまり、入所回路を配設する接続パッドは入力専用の接続パッドであり、出力回路を配設する接続パッドは出力専用の接続パッドであり、入力・出力を機能別に設け、接続パッド群全体で出入力を行わせる構成であってもよいことを意味する。   Here, the “input / output circuit” includes not only a circuit having functions of both input and output of signals, but also a circuit having a function of only an input and a circuit having a function of an output alone. In other words, the connection pad for the entrance circuit is an input-only connection pad, and the connection pad for the output circuit is an output-only connection pad. Input and output are provided for each function, and the entire connection pad group is output. This means that it may be configured to allow input.

また、本発明の半導体装置において、第1半導体チップとしては、例えば所定ビットずつパラレルに信号を入出力する記憶手段を有する記憶装置チップを適用することがよい。また、第2半導体チップとしては例えば記憶装置チップと所定ビットずつパラレルに信号を入出力する特定用途用理論回路チップを適用することがよい。無論、特定用途用理論回路チップに限られず、通常の論理回路チップを適用してもよい。   In the semiconductor device of the present invention, as the first semiconductor chip, for example, a storage device chip having storage means for inputting and outputting signals in parallel by predetermined bits may be applied. Further, as the second semiconductor chip, for example, a special purpose theoretical circuit chip that inputs / outputs signals in parallel with the storage device chip by a predetermined bit may be applied. Of course, the logic circuit chip is not limited to a specific purpose logic circuit chip, and a normal logic circuit chip may be applied.

また、本発明の半導体装置において、前記第1半導体チップの主面に、前記第1半導体チップの最外周に対して最も近くに位置するように第1電源用パッド群を設け、前記第2半導体チップの主面に、前記第2半導体チップの最外周に対して最も近くに位置するように第2電源用パッド群を設けることがよい。隣合うパッド(或いはバンプ)間がショートし易い、半導体チップの最外周に一番近くに位置するパッドとして、電源用パッドを配設することで、チップ間の接続不良を防止した半導体装置を得ることができる。   In the semiconductor device of the present invention, a first power supply pad group is provided on the main surface of the first semiconductor chip so as to be located closest to the outermost periphery of the first semiconductor chip, and the second semiconductor A second power supply pad group may be provided on the main surface of the chip so as to be located closest to the outermost periphery of the second semiconductor chip. Providing a power supply pad as a pad that is closest to the outermost periphery of a semiconductor chip that is likely to short-circuit between adjacent pads (or bumps), thereby obtaining a semiconductor device that prevents connection failure between chips. be able to.

本発明によれば、ノイズやクロストークが生じることなく、チップ間の転送レートを向上させることが可能な半導体装置を提供することができる。   According to the present invention, it is possible to provide a semiconductor device capable of improving the transfer rate between chips without causing noise or crosstalk.

次に、本発明の適用可能な実施形態を説明する。以下の説明は、本発明の実施形態を説明するものであり、本発明が以下の実施形態に限定されるものではない。説明の明確化のため、以下の記載及び図面は、適宜、省略及び簡略化がなされている。また、当業者であれば、以下の実施形態の各要素を、本発明の範囲において容易に変更、追加、変換することが可能である。なお、各図において同一の符号を付されたものは同一の構成要素を示しており、適宜、説明を省略する。   Next, embodiments to which the present invention can be applied will be described. The following description is to describe the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Moreover, those skilled in the art can easily change, add, and convert each element of the following embodiments within the scope of the present invention. In addition, what attached | subjected the same code | symbol in each figure has shown the same component, and abbreviate | omits description suitably.

(第1実施形態)
図1は、第1実施形態に係る半導体装置を示す概略断面図である。図2は、第1実施形態に係る配線チップを示す平面図である。図3は、第1実施形態に係る記憶装置チップを示す平面図である。図4は、第1実施形態に係るASICを示す平面図である。図5は、第1実施形態に係る半導体装置のチップ間の接続を説明するための概念図である。
(First embodiment)
FIG. 1 is a schematic cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 2 is a plan view showing the wiring chip according to the first embodiment. FIG. 3 is a plan view showing the memory device chip according to the first embodiment. FIG. 4 is a plan view showing the ASIC according to the first embodiment. FIG. 5 is a conceptual diagram for explaining connection between chips of the semiconductor device according to the first embodiment.

本実施形態に係る半導体装置100は、図1に示すように、積層チップ50を半導体パッケージ基板60に配置して構成している。   As shown in FIG. 1, the semiconductor device 100 according to the present embodiment is configured by arranging a laminated chip 50 on a semiconductor package substrate 60.

積層チップ50は、配線チップ10の第1主面10A及び第2主面10Bにそれぞれ記憶装置チップ20及びアプリケ−ション・スペシフィック・チップ(Application Specific Chip:特定用途用理論回路チップ、以下、ASICと称する)30がフィリップチップ実装して構成している。そして、記憶装置チップ20及びASIC30は、互いの入出力領域24,34(I/Oアレイ)を対向するように実装されている。また、記憶装置チップ20と配線チップ10との間はアンダーフィル樹脂41により封止されている。同様に、ASIC30と配線チップ10との間にはアンダーフィル樹脂41により封止されている。   The multilayer chip 50 includes a memory device chip 20 and an application specific chip (Application Specific Chip: ASIC for specific application, hereinafter referred to as ASIC) on the first main surface 10A and the second main surface 10B of the wiring chip 10, respectively. 30) is configured by mounting a Philip chip. The storage device chip 20 and the ASIC 30 are mounted so that the input / output areas 24 and 34 (I / O array) face each other. The space between the memory device chip 20 and the wiring chip 10 is sealed with an underfill resin 41. Similarly, an underfill resin 41 is sealed between the ASIC 30 and the wiring chip 10.

そして、この積層チップ50は、そのASIC30が半導体パッケージ基板60と当接するように、半導体パッケージ基板60上に配置すると共に、半導体パッケージ基板60上に設けられた外部から電源接続・接地するためのパッド61とASIC30の電源用パッド32とをワイヤ42を介して電気的に接続している。   The laminated chip 50 is arranged on the semiconductor package substrate 60 so that the ASIC 30 is in contact with the semiconductor package substrate 60, and is a pad for power supply connection / grounding provided from the outside provided on the semiconductor package substrate 60. 61 and the power supply pad 32 of the ASIC 30 are electrically connected via a wire 42.

配線チップ10は、図1及び図2に示すように、シリコン基板で構成され、シリコン基板の厚み方向を貫いて設けられた貫通電極14(例えばアルミや銅などからなる埋め込み電極)が設けられている。そして、シリコン基板の表裏面には、不図示の配線層が形成されており、当該配線層に形成される金属配線(例えばアルミ線や銅線など)を介して、貫通電極14の一端と記憶装置チップ20実装用の接続パッド11Aとが電気的に接続され、また、貫通電極14の他端とASIC30実装用の接続パッド11Bとが電気的に接続され、接続パッド11A,11Bがそれぞれ配線チップ10の第1主面10A及び第2主面10B上で群を成している。   As shown in FIGS. 1 and 2, the wiring chip 10 is formed of a silicon substrate, and is provided with a through electrode 14 (for example, an embedded electrode made of aluminum, copper, or the like) provided through the thickness direction of the silicon substrate. Yes. A wiring layer (not shown) is formed on the front and back surfaces of the silicon substrate, and one end of the through electrode 14 is stored via a metal wiring (for example, an aluminum wire or a copper wire) formed on the wiring layer. The connection pad 11A for mounting the device chip 20 is electrically connected, the other end of the through electrode 14 and the connection pad 11B for mounting the ASIC 30 are electrically connected, and the connection pads 11A and 11B are respectively wiring chips. A group is formed on the first main surface 10A and the second main surface 10B.

配線チップ10の接続パッド11A,11Bは、図2に示すように、実装する記憶装置チップ20及びASIC30の接続パッドに対応して、それぞれ格子状に配列されている。無論、配線チップ10の接続パッド11A、11Bは、実装する記憶装置チップ20及びASIC30の接続パッドに応じて、千鳥配列でもよいし、それ以外の配列であってもよい。   As shown in FIG. 2, the connection pads 11 </ b> A and 11 </ b> B of the wiring chip 10 are arranged in a grid pattern corresponding to the connection pads of the storage device chip 20 and the ASIC 30 to be mounted. Of course, the connection pads 11A and 11B of the wiring chip 10 may be in a staggered arrangement or other arrangement depending on the connection pads of the storage device chip 20 and the ASIC 30 to be mounted.

これら配線チップ10の接続パッド11A、11Bの配線ピッチは、実装するチップに応じて、適宜設定される。例えば、本実施形態では、記憶装置チップ20として256Mビットのマルチ・メディア・メモリ(2個)とASIC30のバンド幅が最低256ビット×2=512ビット必要とし、これを実装するためには接続パッド11A,11Bの配列ピッチは20μm必要となる。これに限られず、例えば、20μm〜60μmの範囲で適宜設定することができる。   The wiring pitch of the connection pads 11A and 11B of these wiring chips 10 is appropriately set according to the chip to be mounted. For example, in the present embodiment, 256 Mbit multi-media memory (two) as the memory device chip 20 and a bandwidth of the ASIC 30 are required to be at least 256 bits × 2 = 512 bits. The arrangement pitch of 11A and 11B is required to be 20 μm. However, the present invention is not limited thereto, and can be set as appropriate within a range of 20 μm to 60 μm, for example.

また、配線チップ10の接続パッド11A,11Bの数も、実装するチップに応じて、適宜設定される。例えば、本実施形態では、記憶装置チップ20として256Mビットのマルチ・メディア・メモリを2個とASIC30とを搭載するため、約2000個設ける。これに限られず、実装する半導体チップに応じて例えば2000個〜5000個の範囲で適宜設定することができる。   The number of connection pads 11A and 11B of the wiring chip 10 is also set as appropriate according to the chip to be mounted. For example, in the present embodiment, since the storage device chip 20 includes two 256 Mbit multi-media memories and the ASIC 30, about 2000 are provided. However, the present invention is not limited to this, and can be set as appropriate within a range of, for example, 2000 to 5000 according to the semiconductor chip to be mounted.

また、配線チップ10は、実装する記憶装置チップ20及びASIC30と同じシリコン基板を使用するので、熱や伸び縮み等に対する物理的な強度も高く、高信頼性を確保できる。   Further, since the wiring chip 10 uses the same silicon substrate as the memory device chip 20 and the ASIC 30 to be mounted, the physical strength against heat, expansion and contraction, etc. is high, and high reliability can be ensured.

記憶装置チップ20は、シリコン基板上に半導体プロセスにより形成されたものであり、本実施形態では、図示しないが、例えばその記憶容量が256Mビットのマルチ・メディア・メモリを2つ搭載している。   The storage device chip 20 is formed on a silicon substrate by a semiconductor process, and in this embodiment, although not shown, for example, two multimedia memories having a storage capacity of 256 Mbit are mounted.

また、記憶装置チップ20としては、これに限られず、汎用のダイナミック・ランダム・アクセス・メモリ(DRAM)を使うこともできる。同様に、記憶装置チップ20としては、汎用のスタテック・ランダム・アクセス・メモリ(SRAM)、不揮発性記憶装置等も使うこともできる。   The storage device chip 20 is not limited to this, and a general-purpose dynamic random access memory (DRAM) can also be used. Similarly, a general-purpose static random access memory (SRAM), a non-volatile storage device, or the like can be used as the storage device chip 20.

記憶装置チップ20は、図1及び図3に示すように、接続パッド21が主面の中央部に格子状に配列されている。接続パッド21は配線チップ10の接続パッド11A(パッド開口部)と向き合うように配置されている。   As shown in FIGS. 1 and 3, in the memory device chip 20, connection pads 21 are arranged in a lattice shape at the center of the main surface. The connection pads 21 are arranged to face the connection pads 11A (pad openings) of the wiring chip 10.

記憶装置チップ20の接続パッド21は、図3に示すように、配線チップ10の接続パッド11Aと同様に格子状に配列されて群を成している。そして、その直下(チップ厚み方向直下)に接続パッド21と電気的に接続された入出力回路を含む単位セル領域25が配設されている。このため、単位セル領域25も接続パッド21と共に格子状に配列されている。単位セル領域25及び接続パッド21の配列は格子状限られず、アレイ状に配列されていれば特に制限はなく、例えば、千鳥状に配列していてもよい。この単位セル領域25をアレイ状に配列することで、入出力領域24(I/Oアレイ)を構成している。   As shown in FIG. 3, the connection pads 21 of the storage device chip 20 are arranged in a lattice pattern similarly to the connection pads 11 </ b> A of the wiring chip 10 to form a group. A unit cell region 25 including an input / output circuit electrically connected to the connection pad 21 is disposed immediately below (directly below the chip thickness direction). For this reason, the unit cell regions 25 are also arranged in a grid with the connection pads 21. The arrangement of the unit cell regions 25 and the connection pads 21 is not limited to a lattice shape, and is not particularly limited as long as the unit cell regions 25 and the connection pads 21 are arranged in an array shape. By arranging the unit cell regions 25 in an array, an input / output region 24 (I / O array) is configured.

記憶装置チップ20は、配線チップ10とパッド(パッド開口部)同士が向き合うように配置され、パッド間がバンプ40で物理的に接続され、かつ、電気的に接続されて、配線チップ10の第1主面10A上にフィリップチップ実装されている。   The memory device chip 20 is arranged so that the wiring chip 10 and the pads (pad openings) face each other, and the pads are physically connected by the bumps 40 and electrically connected. A lip chip is mounted on one main surface 10A.

ASIC30は、シリコン基板上に半導体プロセスにより形成されたものであり、例えば、汎用のCPUを含む論理回路が採用されている。本実施形態では、記憶装置チップ20として、その記憶容量が256Mビットのマルチ・メディア・メモリを2つ搭載しているため、ASIC30のバンド幅が512ビットである。無論、記憶装置チップ20の記憶容量に応じてそれ以上であってもよい。   The ASIC 30 is formed on a silicon substrate by a semiconductor process. For example, a logic circuit including a general-purpose CPU is employed. In the present embodiment, since the storage device chip 20 includes two multi-media memories having a storage capacity of 256 Mbits, the bandwidth of the ASIC 30 is 512 bits. Of course, it may be more depending on the storage capacity of the storage device chip 20.

また、ASIC30としては、これに限られず、例えば、アナログ信号をディジタル信号に変換するA/D変換器を含むような汎用のアナログ回路を使うこともできる。   Further, the ASIC 30 is not limited to this, and for example, a general-purpose analog circuit including an A / D converter that converts an analog signal into a digital signal can be used.

ASIC30は、図1及び図4に示すように、接続パッド31が主面の中央部に格子状に配列されている。また、ASIC30には、接続パッド31を囲むように、主面の縁部に沿って電源用パッド32が2列で配設されている。接続パッド31は配線チップ10の接続パッド11Bと向き合うように配置されている。なお、電源用パッド32は、ASIC30及び記憶装置チップ20への電源接続・接地用の接続パッドである。   As shown in FIGS. 1 and 4, the ASIC 30 has connection pads 31 arranged in a lattice shape at the center of the main surface. The ASIC 30 has power supply pads 32 arranged in two rows along the edge of the main surface so as to surround the connection pads 31. The connection pads 31 are arranged so as to face the connection pads 11B of the wiring chip 10. The power supply pad 32 is a connection pad for power supply connection / grounding to the ASIC 30 and the storage device chip 20.

ASIC30の接続パッド31は、図4に示すように、配線チップ10の接続パッド11Bと同様に格子状に配列されて群を成している。そして、その直下(チップ厚み方向直下)に接続パッド31と電気的に接続された入出力回路を含む単位セル領域35が配設されている。このため、単位セル領域35も接続パッド31と共に格子状に配列されている。単位セル領域35及び接続パッド31の配列は格子状限られず、アレイ状に配列されていれば特に制限はなく、例えば、千鳥状に配列していてもよい。この単位セル領域をアレイ状に配列することで、入出力領域34(I/Oアレイ)を構成している。   As shown in FIG. 4, the connection pads 31 of the ASIC 30 are arranged in a lattice pattern similarly to the connection pads 11 </ b> B of the wiring chip 10 to form a group. A unit cell region 35 including an input / output circuit electrically connected to the connection pad 31 is disposed immediately below (directly below the chip thickness direction). For this reason, the unit cell regions 35 are also arranged in a grid with the connection pads 31. The arrangement of the unit cell regions 35 and the connection pads 31 is not limited to a lattice shape, and is not particularly limited as long as the unit cell regions 35 and the connection pads 31 are arranged in an array shape. By arranging the unit cell areas in an array, an input / output area 34 (I / O array) is configured.

ASIC30は、配線チップ10とそのパッド(パッド開口部)同士が向き合うように配置され、パッド間がバンプ40で物理的に接続され、かつ、電気的に接続されて、配線チップ10の第2主面10B上にフィリップチップ実装されている。   The ASIC 30 is arranged so that the wiring chip 10 and its pads (pad openings) face each other, and the pads are physically connected by the bumps 40 and electrically connected to each other. A Philip chip is mounted on the surface 10B.

記憶装置チップ20とASIC30とは、各接続パッド及び配線チップ10の貫通電極14を介して電気的に接続されている。なお、ASIC30は、記憶装置チップ20として、2個の256Mビットのマルチ・メディア・メモリと電気的に接続されるので、512ビットずつパラレルで信号の入出力が行われる。   The storage device chip 20 and the ASIC 30 are electrically connected via the connection pads and the through electrodes 14 of the wiring chip 10. The ASIC 30 is electrically connected to two 256 Mbit multi-media memories as the storage device chip 20, so that signals are input and output in parallel by 512 bits.

ここで、記憶装置チップ20とASIC30とは、図5に示すように電気的に接続が図られている。即ち、記憶装置チップ20の単位セル領域25に設けられた出力回路26としてのインターフェイスバッファ回路(例えばインバータ回路)と、ASIC30の単位セル領域35に設けられた入力回路37としてのインターフェイスバッファ回路(例えばクロックドインバータ回路)と、電気的に接続するように記憶装置チップ20の接続パッド21及びASIC30の接続パッド31、そして配線チップ10の貫通電極14(接続パッド含む)を介して接続している。   Here, the storage device chip 20 and the ASIC 30 are electrically connected as shown in FIG. That is, an interface buffer circuit (for example, an inverter circuit) as an output circuit 26 provided in the unit cell region 25 of the storage device chip 20 and an interface buffer circuit (for example, an input circuit 37 provided in the unit cell region 35 of the ASIC 30). The clocked inverter circuit) is connected via the connection pads 21 of the memory device chip 20 and the connection pads 31 of the ASIC 30 and the through electrodes 14 (including the connection pads) of the wiring chip 10 so as to be electrically connected.

一方、記憶装置チップ20の単位セル領域25に設けられた入力回路27としてのインターフェイスバッファ回路(例えばクロックドインバータ回路)と、ASIC30の単位セル領域35に設けられた出力回路36としてのインターフェイスバッファ回路(例えばインバータ回路)と、電気的に接続するように記憶装置チップ20の接続パッド21及びASIC30の接続パッド31、そして配線チップ10の貫通電極14(接続パッド含む)を介して接続している。   On the other hand, an interface buffer circuit (for example, a clocked inverter circuit) as an input circuit 27 provided in the unit cell region 25 of the memory device chip 20 and an interface buffer circuit as an output circuit 36 provided in the unit cell region 35 of the ASIC 30. (For example, an inverter circuit) is connected via the connection pads 21 of the memory device chip 20 and the connection pads 31 of the ASIC 30 and the through electrodes 14 (including the connection pads) of the wiring chip 10 so as to be electrically connected.

記憶装置チップ20の入出力回路(入力回路27、出力回路26)は、メモリセル領域28へ電気的に接続されている。そして、ASIC30の入出力回路(入力回路37、出力回路36)は、ロジック回路38へ電気的に接続されている。   The input / output circuits (input circuit 27 and output circuit 26) of the memory device chip 20 are electrically connected to the memory cell region 28. The input / output circuits (input circuit 37 and output circuit 36) of the ASIC 30 are electrically connected to the logic circuit 38.

このようにして、記憶装置チップ20には接続パッド21とASIC30の接続パッド31とを接続することで、上記バス・ライン接続が図られる。   Thus, the bus line connection is achieved by connecting the connection pad 21 and the connection pad 31 of the ASIC 30 to the storage device chip 20.

一方、各接続パッドを物理的、且つ電気的に接続するバンプ40は、マイクロバンプが採用され、例えば、金バンプ、半田バンプなどで構成することができる。Auを含んで構成される金バンプを適用すると、良好な接合が図れる。   On the other hand, the bump 40 that physically and electrically connects each connection pad employs a micro bump, and can be composed of, for example, a gold bump or a solder bump. When a gold bump including Au is applied, good bonding can be achieved.

バンプ40は、半導体チップの接続パッド、配線チップの接続パッドのいずれか或いは両方に予め形成しておくが、配線チップの接続パッドに予め形成しておくと一括して実装する半導体チップ分を形成できる点で低コスト化が図れると共に、半導体チップとして追加配線やバンプを形成することなく既存のものが適用できる。各チップはバンプ40を介して接続しているため、ボンディングワイヤーによる接続に比べ、例えば、インダクタンスが10分の1程度になり内部の信号どうしでの高速なインターフェスが可能になる。   The bump 40 is formed in advance on one or both of the connection pad of the semiconductor chip and / or the connection pad of the wiring chip. The cost can be reduced in that it can be done, and an existing semiconductor chip can be applied without forming additional wiring or bumps. Since the chips are connected via the bumps 40, the inductance is, for example, about 1/10 compared to the connection using the bonding wire, and high-speed interface between internal signals becomes possible.

なお、図示しないが、各チップは接続パッド以外を保護するパッシベ−ション膜、チップ上に形成された絶縁皮膜などを備えている。また、上記半導体チップや配線チップの接続パッド(或いは単位セル領域)は、例えば、2000個〜5000個で、配列ピッチを、20μ〜60μmとすることができる。   Although not shown, each chip includes a passivation film that protects other than the connection pads, an insulating film formed on the chip, and the like. The connection pads (or unit cell regions) of the semiconductor chip or wiring chip are, for example, 2000 to 5000, and the arrangement pitch can be set to 20 μm to 60 μm.

以上説明した本実施形態では、記憶装置チップ20及びASIC30における外部(互いのチップ)との接続を図るための接続パッド21,31毎に入出力回路(入力回路27,37、出力回路26,36)を配設し、これらをアレイ状(本実施形態では格子状)に配列している。即ち、この入出力回路を含む単位セル領域25,35をアレイ状に配列して、I/Oアレイ(入出力領域24、34を構成している。このため、チップに多ビットのI/Oアレイ(アレイ状に配列された単位セル領域で構成される入出力領域24,34)を実現でき、例えば、256〜4096ビットのビット幅を持つ記憶装置チップ20及びASIC30となっている。従って、周波数を上昇させる必要がなく、ノイズや接続配線のクロストークなどが発生することなく、バス間の転送レートを飛躍的に改善することができる。   In the present embodiment described above, input / output circuits (input circuits 27 and 37, output circuits 26 and 36) are provided for each of the connection pads 21 and 31 for connection to the outside (mutual chip) in the storage device chip 20 and the ASIC 30. Are arranged in an array (in this embodiment, a lattice). That is, the unit cell regions 25 and 35 including the input / output circuits are arranged in an array to form an I / O array (input / output regions 24 and 34. Therefore, a multi-bit I / O is provided on the chip. An array (input / output areas 24 and 34 composed of unit cell areas arranged in an array) can be realized, for example, the storage device chip 20 and the ASIC 30 having a bit width of 256 to 4096 bits. There is no need to increase the frequency, and the transfer rate between the buses can be drastically improved without causing noise or crosstalk of connection wiring.

そして、I/Oアレイ(入出力領域24,34)をそれぞれ有する記憶装置チップ20及びASIC30を、互いのI/Oアレイ(入出力領域24,34)を対向させつつ、貫通電極14を介して電気的に接続して、配線チップ10の第1主面10A及び第2主面10Bにそれぞれ実装している。このため、記憶装置チップ20及びASIC30のI/Oアレイ(入出力領域24,34)同士の距離が最短となると共に、配線としての貫通電極14の長さ(配線チップ10の厚み方向長さ)も実質的にその距離と同一であり、最短接続が図れ、バス間の転送レートをさらに改善することができる。   Then, the storage device chip 20 and the ASIC 30 each having the I / O array (input / output areas 24 and 34) are placed through the through electrode 14 while the I / O arrays (input / output areas 24 and 34) face each other. They are electrically connected and mounted on the first main surface 10A and the second main surface 10B of the wiring chip 10, respectively. Therefore, the distance between the I / O arrays (input / output areas 24 and 34) of the memory device chip 20 and the ASIC 30 is the shortest, and the length of the through electrode 14 as the wiring (the thickness direction length of the wiring chip 10). Is substantially the same as the distance, the shortest connection can be achieved, and the transfer rate between the buses can be further improved.

即ち、本実施形態では、互いのチップ間の転送レートが高い半導体装置となる。また、半導体装置の周波数を、例えば、同一性能のDDR(Double Data Rate)シンクロナス・ダイナミック・ランダム・メモリ(DDR−SDRRAM)の周波数の1/10程度に削減し、且つマイクロバンプ及びシリコンインターポーザを使用することでI/Oアレイ端子に付随する付加を軽減しているため、消費電力が大幅に削減できる。   That is, in this embodiment, the semiconductor device has a high transfer rate between the chips. Further, the frequency of the semiconductor device is reduced to, for example, about 1/10 of the frequency of a DDR (Double Data Rate) synchronous dynamic random memory (DDR-SDRRAM) having the same performance, and the micro bump and the silicon interposer are reduced. Since the use accompanying the I / O array terminal is reduced, the power consumption can be greatly reduced.

一方、通常の半導体チップ(半導体集積回路チップ)と基板(配線チップ)とをバンプを介して接続するフィリップチップ実装の場合には、接続後の熱変形や衝撃によりバンプに応力がかかることがよく知られている。このため、このバンプにおける応力集中を緩和させることと、半導体チップと基板との密着性を向上させるために、半導体チップと基板との間に例えばエポキシ系のアンダーフィル樹脂を充填させる方法が一般的である。   On the other hand, in the case of a Philip chip mounting in which a normal semiconductor chip (semiconductor integrated circuit chip) and a substrate (wiring chip) are connected via bumps, the bumps are often stressed by thermal deformation or impact after connection. Are known. For this reason, in order to alleviate the stress concentration in the bump and to improve the adhesion between the semiconductor chip and the substrate, for example, an epoxy-based underfill resin is generally filled between the semiconductor chip and the substrate. It is.

このため、記憶装置チップ20及びASIC30などの半導体チップのパッド形成面(各チップ間の間隙)には、アンダーフィル樹脂が充填されている。このアンダーフィル樹脂を充填する際、半導体チップの形状、配置位置関係に依っては半導体チップの最外集に対して最も近くに位置するパッド間(バンプを形成した場合バンプ間)にはアンダーフィル樹脂が流れ込み難く、アンダーフィル樹脂が充填されない空隙(ボイド)が形成されることがある。このようなアンダーフィル樹脂の空隙がある場合、実装時のリフロー等の熱処理で隣合うパッド(或いはバンプ)間がショートしてしまうということがある。   For this reason, underfill resin is filled in the pad formation surfaces (gap between the chips) of the semiconductor chip such as the memory device chip 20 and the ASIC 30. When filling this underfill resin, depending on the shape and arrangement position of the semiconductor chip, there is an underfill between the pads located closest to the outermost collection of semiconductor chips (bumps between bumps). There are cases where voids are formed in which the resin does not flow easily and is not filled with the underfill resin. When there is such an underfill resin gap, there may be a short circuit between adjacent pads (or bumps) due to heat treatment such as reflow during mounting.

加えて、半導体チップの最外周のバンプは、ウエハから個片へのダイシング工程やマウント工程で機械的な衝撃の影響を受けやすいため、一部バンプが欠けるなどバンプ形成の歩留りが低く、SIPチップ全体としての歩留りに影響が大きいという問題もある。   In addition, the bumps on the outermost periphery of the semiconductor chip are easily affected by mechanical impacts in the dicing process and mounting process from the wafer to the individual pieces. There is also a problem that the overall yield is greatly affected.

そこで、本実施形態では、ASIC30の主面縁部に沿って電源用パッド32を配設、即ち、チップ主面最外周(縁部)に対し最も近くに位置するパッドを全て電源用パッド32としている。電源用パッド32は、信号の伝達に使用する接続パッドとは異なり、電源供給や接地を目的としているため、隣合うパッド(或いはバンプ)間がショートしていてもチップの機能に影響することがない。このため、当該パッド間にアンダーフィル樹脂が充填されなくとも、チップ間の接続不良を確実に防止することができる。また、バンプ形成歩留りも下がらず、SIPチップ全体として高い歩留りも実現できる。   Therefore, in the present embodiment, the power supply pads 32 are arranged along the main surface edge of the ASIC 30, that is, all the pads positioned closest to the outermost periphery (edge) of the chip main surface are all power supply pads 32. Yes. Unlike the connection pads used for signal transmission, the power supply pads 32 are intended for power supply and grounding. Therefore, even if adjacent pads (or bumps) are short-circuited, the function of the chip may be affected. Absent. For this reason, even if the underfill resin is not filled between the pads, a connection failure between chips can be surely prevented. In addition, the bump formation yield does not decrease, and a high yield can be realized for the entire SIP chip.

(第2実施形態)
図6は、第2実施形態に係る半導体装置を示す概略断面図である。図7は、第2実施形態に係る配線チップを示す平面図であり、(A)が第1主面を示す平面図であり、(B)が第2主面を示す平面図である。図8は、第2実施形態に係る記憶装置チップを示す平面図である。図9は、第2実施形態に係るASICを示す平面図である。
(Second Embodiment)
FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to the second embodiment. 7A and 7B are plan views showing the wiring chip according to the second embodiment, wherein FIG. 7A is a plan view showing the first main surface, and FIG. 7B is a plan view showing the second main surface. FIG. 8 is a plan view showing a memory device chip according to the second embodiment. FIG. 9 is a plan view showing an ASIC according to the second embodiment.

本実施形態に係る半導体装置101は、積層チップ50をその記憶装置チップ20が半導体パッケージ基板60と当接するように、半導体パッケージ基板60上に配置すると共に、半導体パッケージ基板60上に設けられた外部から電源接続・接地するためのパッド61と配線チップ10の外部接続用パッド12Bとをワイヤ42を介して電気的に接続している。   In the semiconductor device 101 according to the present embodiment, the stacked chip 50 is arranged on the semiconductor package substrate 60 so that the storage device chip 20 contacts the semiconductor package substrate 60, and an external device provided on the semiconductor package substrate 60. The pads 61 for connecting and grounding the power supply are electrically connected to the external connection pads 12B of the wiring chip 10 via wires 42.

配線チップ10は、図7(A)及び図7(B)に示すように、不図示の配線層に形成される金属配線(例えばアルミ線や銅線など)を介して、貫通電極14の一端と記憶装置チップ20実装用の接続パッド11Aとが電気的に接続され、また、貫通電極14の他端とASIC30実装用の接続パッド11Bとが電気的に接続され、それぞれ配線チップ10の第1主面10A及び第2主面10B上で格子状に群を成している。   As shown in FIGS. 7A and 7B, the wiring chip 10 has one end of the through electrode 14 via a metal wiring (for example, an aluminum wire or a copper wire) formed in a wiring layer (not shown). And the connection pad 11A for mounting the memory device chip 20 are electrically connected, and the other end of the through electrode 14 and the connection pad 11B for mounting the ASIC 30 are electrically connected. Groups are formed in a lattice pattern on the main surface 10A and the second main surface 10B.

配線チップ10の第2主面10Bには、図7(B)に示すように、ASIC30実装用の接続パッド11Bの周囲を囲むように、ASIC30の電源用パッド32と電気的に接続される電源用パッド12Aが1列で配設されている。そして、さらに、電源用パッド12Aの周囲を囲むように配線チップ10の第2主面10Bの縁部に沿って、外部接続用パッド12Bも2列で配設されている。電源用パッド12Aと外部接続用パッド12Bとは、配線チップ10の第2主面10Bに設けられた不図示の配線層の金属配線(例えばアルミ線や銅線など)を介して、電気的に接続されている。   On the second main surface 10B of the wiring chip 10, as shown in FIG. 7B, a power supply electrically connected to the power supply pad 32 of the ASIC 30 so as to surround the connection pad 11B for mounting the ASIC 30 The pads 12A are arranged in one row. Further, the external connection pads 12B are also arranged in two rows along the edge portion of the second main surface 10B of the wiring chip 10 so as to surround the power supply pad 12A. The power supply pad 12A and the external connection pad 12B are electrically connected via a metal wiring (for example, an aluminum wire or a copper wire) of a wiring layer (not shown) provided on the second main surface 10B of the wiring chip 10. It is connected.

記憶装置チップ20は、図6及び図8に示すように、接続パッド21が主面の中央部に格子状に配列されている。接続パッド21は配線チップ10の接続パッド11A(パッド開口部)と向き合うように配置されている。   As shown in FIGS. 6 and 8, in the memory device chip 20, the connection pads 21 are arranged in a lattice shape at the center of the main surface. The connection pads 21 are arranged to face the connection pads 11A (pad openings) of the wiring chip 10.

記憶装置チップ20の接続パッド21は、図8に示すように、配線チップ10の接続パッド11Aと同様に格子状に配列されて群を成している。そして、その直下(チップ厚み方向直下)に接続パッド21と電気的に接続された入出力回路を含む単位セル領域25が配設されている。   As shown in FIG. 8, the connection pads 21 of the storage device chip 20 are arranged in a lattice pattern similarly to the connection pads 11 </ b> A of the wiring chip 10 to form a group. A unit cell region 25 including an input / output circuit electrically connected to the connection pad 21 is disposed immediately below (directly below the chip thickness direction).

記憶装置チップ20は、配線チップ10とそのパッド(パッド開口部)同士が向き合うように配置され、パッド間がバンプ40で物理的に接続され、かつ、電気的に接続されて、配線チップ10の第1主面10A上にフィリップチップ実装されている。   The storage device chip 20 is arranged so that the wiring chip 10 and its pads (pad openings) face each other, and the pads are physically connected by the bumps 40 and electrically connected. The lip chip is mounted on the first main surface 10A.

ASIC30は、図6及び図9に示すように、接続パッド31が主面の中央部に格子状に配列されている。また、ASIC30には、接続パッド31を囲むように、主面の縁部に沿って電源用パッド32が1列で配設されている。接続パッド31は配線チップ10の接続パッド11Bと向き合うように配置されている。そして、電源用パッド32は配線チップ10の電源用パッド12Aと向き合うように配置されている。なお、電源用パッド32は、ASIC30及び記憶装置チップ20への電源接続・接地用の接続パッドである。   As shown in FIGS. 6 and 9, the ASIC 30 has connection pads 31 arranged in a lattice shape at the center of the main surface. In the ASIC 30, power supply pads 32 are arranged in a row along the edge of the main surface so as to surround the connection pads 31. The connection pads 31 are arranged so as to face the connection pads 11B of the wiring chip 10. The power supply pads 32 are arranged so as to face the power supply pads 12A of the wiring chip 10. The power supply pad 32 is a connection pad for power supply connection / grounding to the ASIC 30 and the storage device chip 20.

ASIC30の接続パッド31は、図9に示すように、配線チップ10の接続パッド11Bと同様に格子状に配列されて群を成している。そして、その直下(チップ厚み方向直下)に接続パッド31と電気的に接続された入出力回路を含む単位セル領域35が配設されている。   As shown in FIG. 9, the connection pads 31 of the ASIC 30 are arranged in a lattice pattern similarly to the connection pads 11 </ b> B of the wiring chip 10 to form a group. A unit cell region 35 including an input / output circuit electrically connected to the connection pad 31 is disposed immediately below (directly below the chip thickness direction).

ASIC30は、配線チップ10とパッド(パッド開口部)同士が向き合うように配置され、パッド間がバンプ40で物理的に接続され、かつ、電気的に接続されて、配線チップ10の第2主面10B上にフィリップチップ実装されている。   The ASIC 30 is arranged so that the wiring chip 10 and the pads (pad openings) face each other, the pads are physically connected by the bumps 40, and are electrically connected, and the second main surface of the wiring chip 10. Philip chip is mounted on 10B.

これら以外の構成は、第1実施形態と同様であるので説明を省略する。   Since the configuration other than these is the same as that of the first embodiment, the description thereof is omitted.

以上説明した本実施形態でも、記憶装置チップ20及びASIC30における外部(互いのチップ)との接続を図るための接続パッド21,31毎に入出力回路(入力回路27,37、出力回路26,36)を配設し、これらをアレイ状(本実施形態では格子状)に配列している。即ち、この入出力回路を含む単位セル領域25,35をアレイ状に配列して、I/Oアレイ(入出力領域24、34を構成している。このため、チップに多ビットのI/Oアレイ(アレイ状に配列された単位セル領域で構成される入出力領域24,34)を実現でき、例えば、256〜4096ビットのビット幅を持つ記憶装置チップ20及びASIC30となっている。従って、周波数を上昇させる必要がなく、ノイズや接続配線のクロストークなどが発生することなく、バス間の転送レートを飛躍的に改善することができる。   Also in the present embodiment described above, input / output circuits (input circuits 27 and 37, output circuits 26 and 36) are provided for each connection pad 21 and 31 for connection to the outside (mutual chip) in the memory device chip 20 and the ASIC 30. Are arranged in an array (in this embodiment, a lattice). That is, the unit cell regions 25 and 35 including the input / output circuits are arranged in an array to form an I / O array (input / output regions 24 and 34. Therefore, a multi-bit I / O is provided on the chip. An array (input / output areas 24 and 34 composed of unit cell areas arranged in an array) can be realized, for example, the storage device chip 20 and the ASIC 30 having a bit width of 256 to 4096 bits. There is no need to increase the frequency, and the transfer rate between the buses can be drastically improved without causing noise or crosstalk of connection wiring.

そして、I/Oアレイ(入出力領域24,34)をそれぞれ有する記憶装置チップ20及びASIC30を、互いのI/Oアレイ(入出力領域24,34)を対向させつつ、貫通電極14を介して電気的に接続して、配線チップ10の第1主面10A及び第2主面10Bにそれぞれ実装している。このため、記憶装置チップ20及びASIC30のI/Oアレイ(入出力領域24,34)同士の距離が最短となると共に、配線としての貫通電極14の長さ(配線チップ10の厚み方向長さ)も実質的にその距離と同一であり、最短接続が図れ、バス間の転送レートをさらに改善することができる。   Then, the storage device chip 20 and the ASIC 30 each having the I / O array (input / output areas 24 and 34) are placed through the through electrode 14 while the I / O arrays (input / output areas 24 and 34) face each other. They are electrically connected and mounted on the first main surface 10A and the second main surface 10B of the wiring chip 10, respectively. Therefore, the distance between the I / O arrays (input / output areas 24 and 34) of the memory device chip 20 and the ASIC 30 is the shortest, and the length of the through electrode 14 as the wiring (the thickness direction length of the wiring chip 10). Is substantially the same as the distance, the shortest connection can be achieved, and the transfer rate between the buses can be further improved.

即ち、本実施形態では、互いのチップ間の転送レートが高い半導体装置となる。また、半導体装置の周波数を、例えば、同一性能のDDR(Double Data Rate)シンクロナス・ダイナミック・ランダム・メモリ(DDR−SDRRAM)の周波数の1/10程度に削減し、且つマイクロバンプ及びシリコンインターポーザを使用することでI/Oアレイ端子に付随する付加を軽減しているため、消費電力が大幅に削減できる。   That is, in this embodiment, the semiconductor device has a high transfer rate between the chips. Further, the frequency of the semiconductor device is reduced to, for example, about 1/10 of the frequency of a DDR (Double Data Rate) synchronous dynamic random memory (DDR-SDRRAM) having the same performance, and the micro bump and the silicon interposer are reduced. Since the use accompanying the I / O array terminal is reduced, the power consumption can be greatly reduced.

なお、いずれの実施形態でも、複数の半導体チップを集積することが可能になるため、携帯電話・PDA・スチールカメラ・ディジタルビデオカメラ・腕時計型携帯機器等、小容積化並びに少消費電力を志向するシステムの実装に有効である。さらに、高速な内部バスを構成できる事よりグラフィックチップ関連、パーソナルコンピュータ等のシステムの小型化・高性能化に有効である。   In any of the embodiments, since a plurality of semiconductor chips can be integrated, it is intended to reduce the volume and consume less power in mobile phones, PDAs, still cameras, digital video cameras, wristwatch-type portable devices, etc. Effective for system implementation. Furthermore, since a high-speed internal bus can be configured, it is effective for downsizing and high performance of graphics chip related systems, personal computers and the like.

第1実施形態に係る半導体装置を示す概略断面図である。1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. 第1実施形態に係る配線チップを示す平面図である。It is a top view which shows the wiring chip which concerns on 1st Embodiment. 第1実施形態に係る記憶装置チップを示す平面図である。1 is a plan view showing a memory device chip according to a first embodiment. 第1実施形態に係るASICを示す平面図である。It is a top view which shows ASIC which concerns on 1st Embodiment. 第1実施形態に係る半導体装置のチップ間の接続を説明するための概念図である。It is a conceptual diagram for demonstrating the connection between the chips | tips of the semiconductor device which concerns on 1st Embodiment. 第2実施形態に係る半導体装置を示す概略断面図である。It is a schematic sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. 第2実施形態に係る配線チップを示す平面図であり、(A)が第1主面を示す平面図であり、(B)が第2主面を示す平面図である。It is a top view which shows the wiring chip which concerns on 2nd Embodiment, (A) is a top view which shows a 1st main surface, (B) is a top view which shows a 2nd main surface. 第2実施形態に係る記憶装置チップを示す平面図である。It is a top view which shows the memory | storage device chip | tip concerning 2nd Embodiment. 第2実施形態に係るASICを示す平面図である。It is a top view which shows ASIC which concerns on 2nd Embodiment.

符号の説明Explanation of symbols

10 配線チップ
10A 第1主面
10B 第2主面
11A 接続パッド
11B 接続パッド
11A,11B 接続パッド
12A 電源用パッド
12B 外部接続用パッド
14 貫通電極
20 記憶装置チップ
21 接続パッド
24 入出力領域
25 単位セル領域
26 出力回路
27 入力回路
28 メモリセル領域
30 ASIC
31 接続パッド
32 電源用パッド
34 入出力領域
35 単位セル領域
36 出力回路
37 入力回路
38 ロジック回路
40 バンプ
41 アンダーフィル樹脂
42 ワイヤ
50 積層チップ
60 半導体パッケージ基板
61 パッド
100、101 半導体装置
DESCRIPTION OF SYMBOLS 10 Wiring chip 10A 1st main surface 10B 2nd main surface 11A Connection pad 11B Connection pad 11A, 11B Connection pad 12A Power supply pad 12B External connection pad 14 Through electrode 20 Memory device chip 21 Connection pad 24 Input / output area 25 Unit cell Area 26 Output circuit 27 Input circuit 28 Memory cell area 30 ASIC
31 Connection Pad 32 Power Supply Pad 34 Input / Output Area 35 Unit Cell Area 36 Output Circuit 37 Input Circuit 38 Logic Circuit 40 Bump 41 Underfill Resin 42 Wire 50 Multilayer Chip 60 Semiconductor Package Substrate 61 Pads 100 and 101 Semiconductor Device

Claims (2)

チップ厚み方向に貫く複数の貫通電極を有する配線チップと、
主面にアレイ状に配列された第1接続パッド群を有し、さらに当該第1接続パッド群のパッド毎に当該パッドと電気的に接続した第1入出力回路を当該パッドの直下に配設し、且つ当該パッドと共に前記第1入出力回路をアレイ状に配列した第1入出力領域を有する第1半導体チップと、
主面にアレイ状に配列された第2接続パッド群を有し、さらに当該第2接続パッド群のパッド毎に当該パッドと電気的に接続した第2入出力回路を当該パッドの直下に配設し、且つ当該パッドと共に前記第2入出力回路をアレイ状に配列した第2入出力領域を有する第2半導体チップと、
を有し、
前記配線チップを介して前記第1入出力領域と前記第2入出力領域とが対向し、且つ前記複数の各貫通電極を介して前記第1接続パッド群の各パッドと前記第2接続パッド群の各パッドとが各々電気的に接続するように、第1半導体チップ及び第2半導体チップを前記配線チップの第1主面及び第2主面にそれぞれ実装したことを特徴とする半導体装置。
A wiring chip having a plurality of through electrodes penetrating in the chip thickness direction;
A first input / output circuit having a first connection pad group arranged in an array on the main surface and further electrically connected to the pad for each pad of the first connection pad group is disposed immediately below the pad. And a first semiconductor chip having a first input / output region in which the first input / output circuits are arranged in an array together with the pads;
A second input / output circuit having a second connection pad group arranged in an array on the main surface and further electrically connected to the pad for each pad of the second connection pad group is disposed immediately below the pad. And a second semiconductor chip having a second input / output region in which the second input / output circuits are arranged in an array together with the pads;
Have
The first input / output region and the second input / output region face each other via the wiring chip, and each pad of the first connection pad group and the second connection pad group via the plurality of through electrodes. A semiconductor device, wherein the first semiconductor chip and the second semiconductor chip are respectively mounted on the first main surface and the second main surface of the wiring chip so that the pads are electrically connected to each other.
第1半導体チップは所定ビットずつパラレルに信号を入出力する記憶手段を有する記憶装置チップであり、第2半導体チップは記憶装置チップと所定ビットずつパラレルに信号を入出力する特定用途用理論回路チップであることを特徴とする請求項1に記載の半導体装置。   The first semiconductor chip is a storage device chip having storage means for inputting / outputting a signal in parallel in predetermined bits, and the second semiconductor chip is a theoretical circuit chip for specific application that inputs / outputs a signal in parallel with the storage device chip in predetermined bits. The semiconductor device according to claim 1, wherein:
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KR20100046760A (en) 2008-10-28 2010-05-07 삼성전자주식회사 Semiconductor package
JP2010161102A (en) * 2009-01-06 2010-07-22 Elpida Memory Inc Semiconductor device
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