JP3893637B2 - Microcomputer and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a logic function such as a microcomputer and a gate array configured on a semiconductor substrate.
[0002]
[Prior art]
Conventionally, in a microcomputer and a semiconductor device incorporating an EPROM / FLASH memory block, as shown in FIG. 7A, a wiring region is provided and arranged at a distance from other internal structural blocks. By waiting for extinction due to recombination, or by disposing a P + diffusion region connected to the ground line Vss as disclosed in JP-A-57-48257, etc., the substrate current generated during writing is absorbed. there were.
[0003]
[Problems to be solved by the invention]
Conventionally, since the above configuration has been adopted, there has been a great drawback that latch-up is likely to occur or the latch-up tolerance is low, which is triggered by a carrier caused by channel hot electrons generated when writing to the EPROM and FLASH memory. .
[0004]
[Means for Solving the Problems]
In order to achieve the above object, a microcomputer according to claim 1 is a microcomputer in which a memory unit for performing writing by channel hot electrons is integrated on a first conductivity type semiconductor substrate together with a micro control unit and peripheral functions. A second impurity diffusion layer of the first conductivity type is disposed adjacent to the periphery of the storage means and is connected to a ground line in the first impurity diffusion layer. A third impurity diffusion layer of the second conductivity type connected to the layer and the ground line is disposed.
[0005]
A microcomputer according to a second aspect of the present invention is the microcomputer according to the first aspect, wherein the first impurity diffusion layer of the second conductivity type is arranged without any break so as to surround the storage means.
[0006]
The microcomputer according to claim 3 is the microcomputer according to claim 1, wherein the first impurity diffusion layer of the second conductivity type is arranged seamlessly, and the microcomputer is arranged in the first impurity diffusion layer. The second and third impurity diffusion layers are also arranged without any break so as to surround the storage means.
[0007]
According to a fourth aspect of the present invention, there is provided a microcomputer in which a memory means for performing writing by channel hot electrons is integrated on a first conductive type semiconductor substrate together with a micro control unit and peripheral functions. A first impurity diffusion layer of the second conductivity type is disposed, and the second impurity diffusion layer of the first conductivity type connected to the ground line in the first impurity diffusion layer and connected to the ground line A third impurity diffusion layer of the second conductivity type is disposed, and the first impurity diffusion layer of the second conductivity type is disposed on the side facing the micro control unit and the peripheral function.
[0008]
According to a fifth aspect of the present invention, there is provided a microcomputer in which a memory means for performing writing by means of channel hot electrons is integrated on a first conductive type semiconductor substrate together with a micro control unit and peripheral functions, and is adjacent to the periphery of the memory means. A first impurity diffusion layer of the second conductivity type is disposed in a form, and a second conductivity type of the second conductivity type connected to the ground line on the near side facing the storage means in the first impurity diffusion layer An impurity diffusion layer is disposed, and a second conductivity type third connected to a ground line on the side far from the storage means so as to be parallel to the second impurity diffusion layer in the first impurity diffusion layer. An impurity diffusion layer is arranged.
[0009]
According to a sixth aspect of the present invention, there is provided a microcomputer in which a memory means for writing data by channel hot electrons is integrated on a first conductivity type semiconductor substrate together with a micro control unit and peripheral functions. A first impurity diffusion layer of the first conductivity type is disposed, and the second impurity diffusion of the first conductivity type is connected to the ground line on the near side facing the storage means in the first impurity diffusion layer. A third impurity diffusion layer of a second conductivity type arranged in parallel with the second impurity diffusion layer in the first impurity diffusion layer and connected to a ground line on the side far from the storage means A layer is disposed, and the first impurity diffusion layer of the second conductivity type is disposed on the side facing the micro control unit and the peripheral function.
[0010]
According to a seventh aspect of the present invention, there is provided a semiconductor device in which storage means for writing by channel hot electrons is integrated on a semiconductor substrate of the first conductivity type, and the second conductivity type of the semiconductor device adjacent to the periphery of the storage means. One impurity diffusion layer is disposed, a second impurity diffusion layer of the first conductivity type connected to the ground line in the first impurity diffusion layer, and a second conductivity type of the second conductivity type connected to the ground line. Three impurity diffusion layers are arranged.
[0011]
A semiconductor device according to an eighth aspect is the semiconductor device according to the sixth aspect, characterized in that the first impurity diffusion layer of the second conductivity type is arranged without any break so as to surround the storage means.
[0012]
The semiconductor device according to claim 9 is the semiconductor device according to claim 6, wherein the first impurity diffusion layer of the second conductivity type is arranged seamlessly and the first impurity diffusion layer is arranged in the first impurity diffusion layer. The second and third impurity diffusion layers are also arranged without any break so as to surround the storage means.
[0013]
According to a tenth aspect of the present invention, there is provided a semiconductor device in which a storage means for writing data by channel hot electrons is integrated with a logic function on a semiconductor substrate of a first conductivity type, and is adjacent to the periphery of the storage means. A first impurity diffusion layer of a conductivity type is disposed, and a second impurity diffusion layer of a first conductivity type connected to a ground line on the near side facing the storage means is disposed in the first impurity diffusion layer. A third impurity diffusion layer of a second conductivity type disposed and connected to a ground line on a side far from the storage means so as to be parallel to the second impurity diffusion layer in the first impurity diffusion layer. It is characterized by arranging.
[0014]
A semiconductor device according to claim 11 is a semiconductor device in which a memory means for writing data by channel hot electrons is integrated with a logic function on a semiconductor substrate of a first conductivity type, and the second conductivity type is adjacent to the memory means. A first impurity diffusion layer of the first conductivity type connected to a ground line on the near side facing the storage means is disposed in the first impurity diffusion layer. The third impurity diffusion layer of the second conductivity type connected to the ground line is disposed on the side far from the storage means so as to be parallel to the second impurity diffusion layer in the first impurity diffusion layer. The first impurity diffusion layer of the second conductivity type is disposed on the side facing the logic function.
[0015]
[Action]
In the microcomputer according to claim 1, carriers generated from the memory means for writing by channel hot electrons are collected in a parasitic bipolar transistor constituted by an impurity diffusion layer connected to the ground line and absorbed by the ground line. , Latch-up measures can be taken.
[0016]
According to another aspect of the microcomputer of the present invention, carriers generated from the storage means for writing by channel hot electrons are connected to the ground line through the impurity diffused layer arranged seamlessly around and the parasitic bipolar transistor formed inside the impurity diffused layer. Latch-up measures can be taken by absorbing them.
[0017]
According to another aspect of the microcomputer of the present invention, carriers generated from the storage means for writing by channel hot electrons are grounded without any leakage by the unbroken parasitic bipolar transistor composed of the impurity diffusion layer arranged without breaks. Latch-up measures can be taken by absorbing them.
[0018]
In the microcomputer according to claim 4, the impurity diffusion layer is intensively arranged at a place where the latch-up is likely to occur by using the carrier generated from the memory means for writing by channel hot electrons as a trigger, and absorbed to the ground line through the parasitic bipolar transistor. By doing so, it is possible to effectively take measures against latch-up with a small area.
[0019]
In the microcomputer according to claim 5, the impurity diffusion layer is arranged so that the current amplification factor of the parasitic bipolar transistor can be increased, and the carrier generated from the storage means for writing by channel hot electrons is absorbed by the ground line. Up resistance can be dramatically increased.
[0020]
In the microcomputer according to the sixth aspect, the impurity diffusion layer is arranged so that the current amplification factor of the parasitic bipolar transistor can be increased, and the impurity diffusion layer is intensively arranged at a position where latch-up is likely to occur, and writing is performed by channel hot electrons. By absorbing the carrier generated from the storage means for performing the above into the ground line, it is possible to effectively take a latch-up measure with a small area.
[0021]
According to another aspect of the semiconductor device of the present invention, carriers generated from the storage means for writing by channel hot electrons are collected in a parasitic bipolar transistor composed of an impurity diffusion layer connected to the ground line and absorbed by the ground line. , Latch-up measures can be taken.
[0022]
According to another aspect of the semiconductor device of the present invention, carriers generated from the storage means for writing by channel hot electrons are connected to the ground line through the impurity diffused layer arranged in a continuous manner and the parasitic bipolar transistor formed inside the impurity diffused layer. Latch-up measures can be taken by absorbing them.
[0023]
In the microcomputer according to claim 9, carriers generated from the storage means for writing by channel hot electrons are grounded without leakage by the unbroken parasitic bipolar transistor composed of the impurity diffusion layer arranged without breaks around. Latch-up measures can be taken by absorbing them.
[0024]
According to another aspect of the semiconductor device of the present invention, the impurity diffusion layer is arranged so that the current amplification factor of the parasitic bipolar transistor can be increased, and the carriers generated from the storage means for writing by channel hot electrons are absorbed by the ground line. Up resistance can be dramatically increased.
[0025]
In the semiconductor device according to the eleventh aspect, the impurity diffusion layer is arranged so that the current amplification factor of the parasitic bipolar transistor can be increased, and the impurity diffusion layer is intensively arranged at a position where latch-up is likely to occur, and writing is performed by channel hot electrons. By absorbing the carrier generated from the storage means for performing the above into the ground line, it is possible to effectively take a latch-up measure with a small area.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to FIGS. 1, 2, 3, and 4. FIG.
[0027]
FIG. 1 is a block diagram showing the overall configuration and arrangement of a microcomputer according to the present invention. FIG. 1A is a block diagram in which the NWELL area 101 is arranged so as to surround the EPROM / FLASH memory block 102. An NWELL region 101 connected to the ground line Vss on the semiconductor substrate 100 is disposed around the EPROM / FLASH memory block 102, and hot carriers generated during a write operation are generated by another micro control unit (hereinafter referred to as MCU) 103 or the like. Is prevented from entering the circuit block.
[0028]
FIG. 1B is a block diagram in which the NWELL areas 111 and 112 are arranged around the EPROM / FLASH memory block 113 at positions facing the MCU 114, the peripheral circuit 115, and the storage function RAM 116.
[0029]
FIG. 2 is a block diagram showing the overall configuration and arrangement of the semiconductor device according to the present invention. FIG. 2A is a block diagram in which the NWELL area 201 is arranged so as to surround the EPROM / FLASH memory block 202. An NWELL region 201 connected to the ground line Vss is disposed on the semiconductor substrate 200 around the EPROM / FLASH memory block 202, and hot carriers generated during a write operation enter a circuit block such as another gate array 203. To prevent.
[0030]
FIG. 2B is a block diagram in which the NWELL areas 211 and 212 are arranged around the EPROM / FLASH memory block 213 at positions facing the gate array 214 and the storage function RAM 215.
[0031]
3 and 4 show enlarged views of the guard ring by the NWELL region, respectively. FIG. 3A shows an NWELL area 302 disposed at a position adjacent to the EPROM / FLASH memory block 301, and an N + area 304 and a P + area 303 are formed in the NWELL area 302. An N + region 304 is formed on the side closer to the EPROM / FLASH memory block 301, and a P + region 303 is formed on the far side. The N + and P + regions are connected to ALs 305 and 306 by CONTACT 307, respectively. Although not explicitly shown in the figure, the ALs are each connected to a ground line Vss.
[0032]
FIG. 3B shows another embodiment of the NWELL region arranged at a position adjacent to the EPROM / FLASH memory block. The N + region 314 and the P + region 313 are formed in the NWELL region 312. An N + region 314 is formed on the side closer to the EPROM / FLASH memory block 311 and a P + region 313 is formed on the far side. The N + and P + regions are connected to ALs 315 and 316 by CONTACT 317, respectively. The respective ALs are connected to each other at appropriate intervals as shown in the figure. In this case, it is also possible to arrange the AL on the entire surface so as to cross the N + region 314 and the P + region 313. Although not explicitly shown in the figure, the AL is connected to the ground line Vss.
[0033]
FIG. 4A shows another embodiment of the NWELL area arranged at a position adjacent to the EPROM / FLASH memory block. The N + area 403 and the P + area 404 are formed in the NWELL area 402. A P + region 404 is formed on the side closer to the EPROM / FLASH memory block 401, and an N + region 403 is formed on the far side. The N + and P + regions are connected to ALs 405 and 406 by CONTACT 407, respectively. Although not explicitly shown in the figure, the ALs are each connected to a ground line Vss.
[0034]
FIG. 4B shows another embodiment of the NWELL area arranged at a position adjacent to the EPROM / FLASH memory block. The N + 413 area and the P + area 414 are formed in the NWELL area 412. A P + region 414 is formed on the side closer to the EPROM / FLASH memory block 411, and an N + region 415 is formed on the far side. The N + and P + regions are connected to ALs 415 and 416 by CONTACT 417, respectively. Each AL is connected to each other at an appropriate interval as shown in the figure. In this case, it is also possible to arrange the AL on the entire surface so as to straddle the N + region 413 and the P + region 414. Although not explicitly shown in the figure, the AL is connected to the ground line Vss.
[0035]
5 and 6 show equivalent circuit diagrams of a cross section of the guard ring by the NWELL region. FIG. 5A shows an equivalent circuit diagram of a cross section of the guard ring shown in FIG. 3, in which carriers of hot electrons generated during writing to the stack gate type memory cell 502 which is a constituent element of the EPROM / FLASH memory block are shown. Parasitic elements are illustrated for explaining the absorption path. In the write state, the stacked gate memory cell 502 includes a floating gate 511, a control gate 510, an N + drain region 503 to which a program voltage Vpp is applied, and an N + source region 504 connected to the ground line Vss. . The ground line Vss is also connected to a P + region 505 for taking a potential to the P− substrate 500. A guard ring by the NWELL area 501 is arranged adjacent to the periphery of the EPROM / FLASH memory block. An N + region 507 and a P + region 508 connected to the ground line Vss are disposed in the NWELL. A parasitic diode 506 is formed between the P− substrate 500-N + and the source region 504. A PNP parasitic bipolar transistor Tr509 is formed between the P− substrate 500 and the NWELL 501−P + region 508. The emitter region E of the parasitic bipolar transistor is connected to the ground line Vss through the P− substrate and the P + region 505. The base region B of the parasitic bipolar transistor is connected to Vss through NWELL and N + region 507. The collector region C of the parasitic bipolar transistor 509 is connected to Vss through the P + region 508.
[0036]
In the written state, Vpp is applied to the drain 503 of the stacked gate type memory cell 502. The voltage of Vpp is about 12V to 20V, and a voltage sufficient to generate channel hot electrons necessary for injecting electrons into the floating gate 511 is supplied. The control gate 510 is applied with a positive potential sufficient to attract the generated hot electrons. However, writing by hot carrier injection in an EPROM / FLASH memory has very poor injection efficiency and contributes only a small part of the channel current. In general, the injection efficiency is said to be about 0.1 to 1%. The remaining electrons become a substrate current and become a latch-up trigger current, so it is necessary to quickly flow to the ground power supply line. When the substrate current due to channel hot electrons raises the potential of the P− substrate and the amount of carriers is small, it flows as a current to the P + region 505 through the parasitic resistance of the P− substrate and is absorbed by the ground line Vss. However, when the substrate potential rises by 0.6 to 0.7 V or more with respect to Vss, the forward current I3 of the parasitic diode 506 flows. At the same time, a forward current I2 of the diode flows between the emitter E and base B of the parasitic transistor 509. When the substrate potential further rises, a current I1 determined by the parasitic bipolar amplification factor flows between the emitter E and the collector C of the parasitic transistor 509 and is absorbed to Vss through the P + region 508. Since the base region of the parasitic transistor 509 is constituted by the NWELL 501, a parasitic transistor is constituted in the depth direction of the NWELL. Therefore, a guard ring determined by the diffusion depth of NWELL can be configured.
[0037]
FIG. 6 shows an equivalent circuit diagram of a cross section of the guard ring shown in FIG. 4, and shows the absorption path of carriers by hot electrons generated at the time of writing in the stacked gate type memory cell 602 which is a component of the EPROM / FLASH memory block. For the purpose of illustration, parasitic elements are illustrated. In the write state, the stack gate type memory cell 602 of the EPROM / FLASH memory block includes a floating gate 611, a control gate 610, an N + drain region 603 to which a program voltage Vpp is applied, and an N + source region connected to the ground line Vss. 604. The ground line Vss is also connected to a P + region 605 for taking a potential to the P− substrate 600. A guard ring by the NWELL area 601 is arranged adjacent to the periphery of the EPROM / FLASH memory block. A P + region 607 and an N + region 608 connected to the ground line Vss are disposed in the NWELL. A parasitic diode 606 is formed between the P− substrate 600-N + and the source region 604. A PNP parasitic bipolar transistor 609 is formed between the P− substrate 600 and the NWELL 601−P + region 607. The emitter region E of the parasitic bipolar transistor Tr1 is connected to the ground line Vss through the P− substrate 500 and the P + region 605. The base region B of the parasitic transistor is connected to Vss through NWELL 601 and N + region 608. The collector region C of the parasitic transistor 609 is connected to Vss through the P + region 607. In the written state, Vpp is applied to the drain 603 of the stacked gate type memory cell 602 as described above. When the potential of the P-substrate 600 rises due to the substrate current caused by channel hot electrons and the amount of carriers is small, it flows as a current to the P + region 605 through the parasitic resistance of the P-substrate and is absorbed by the ground line Vss. However, when the substrate potential rises by 0.6 to 0.7 V or more with respect to Vss, the forward current I3 of the parasitic diode 606 flows. At the same time, a forward current I2 of the diode flows between the emitter E and base B of the parasitic transistor 609. When the substrate potential further rises, a current I1 determined by the parasitic bipolar amplification factor flows between the emitter E and the collector C of the parasitic transistor and is absorbed to Vss through the P + region 608. Electrons injected from the emitter E of the parasitic transistor diffuse through the base B and recombine by an amount determined by the correlation between the base width and the minority carrier diffusion length, and the remaining electrons reach the end of the base.
[0038]
By placing the P + region 607 facing the EPROM / FLASH memory block, the base width of the parasitic bipolar transistor 609 is shortened, and carriers that disappear due to recombination can be reduced, thereby increasing the amplification factor. It is possible to flow the substrate current to the ground line Vss more effectively.
[0039]
As described above, in this embodiment, the EPROM / FLASH memory block formed on the P-substrate has been described. However, a similar NWELL guard ring can be configured for the EPROM / FLASH memory block formed on the PWELL. .
[0040]
【The invention's effect】
As described above, according to the microcomputer of the first to third aspects, the carrier generated from the storage means for writing by channel hot electrons is grounded through the parasitic bipolar transistor formed by the impurity diffusion layer connected to the ground line. By absorbing it into the wire, an effective latch-up measure can be taken.
[0041]
According to the microcomputer of the fourth aspect, the impurity diffusion layer is intensively arranged at a location where latch-up is likely to occur by using the carrier generated from the storage means for writing by channel hot electrons as a trigger, and the ground line is connected through the parasitic bipolar transistor. By absorbing it, effective latch-up measures can be taken with a small area.
[0042]
According to the microcomputer of the fifth aspect of the present invention, the impurity diffusion layer is arranged so that the current amplification factor of the parasitic bipolar transistor can be increased, and carriers generated from the storage means for writing by channel hot electrons are absorbed by the ground line. As a result, the latch-up resistance can be dramatically increased.
[0043]
According to the microcomputer of the sixth aspect, the impurity diffusion layer is arranged so that the current amplification factor of the parasitic bipolar transistor is large, the impurity diffusion layer is intensively arranged at a position where latch-up is likely to occur, and channel hot electrons are arranged. By absorbing the carriers generated from the storage means for writing to the ground line, it is possible to effectively take a latch-up measure with a small area.
[0044]
According to the semiconductor device of the seventh to ninth aspects, carriers generated from the storage means for writing by channel hot electrons are absorbed into the ground line through the parasitic bipolar transistor constituted by the impurity diffusion layer connected to the ground line. By doing this, it is possible to take measures against latch-up.
[0045]
According to the semiconductor device of the tenth aspect, the impurity diffused layer is arranged so that the current amplification factor of the parasitic bipolar transistor is large, and carriers generated from the storage means for writing by channel hot electrons are absorbed by the ground line. As a result, the latch-up resistance can be dramatically increased.
[0046]
According to the semiconductor device of the eleventh aspect, the impurity diffusion layer is arranged such that the current amplification factor of the parasitic bipolar transistor can be increased, and the impurity diffusion layer is intensively arranged at a position where latch-up is likely to occur, so that the channel hot electrons are arranged. By absorbing the carriers generated from the storage means for writing to the ground line, it is possible to effectively take a latch-up measure with a small area.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration and its arrangement according to the present invention.
FIG. 2 is an enlarged view showing an example of a guard ring with an NWELL region according to the present invention.
FIG. 3 is an enlarged view showing an example of a guard ring with an NWELL region according to the present invention.
FIG. 4 is an enlarged view showing an example of a guard ring by an NWELL region according to the present invention.
FIG. 5 is an equivalent circuit diagram of a cross section of a guard ring by an NWELL region shown in FIG. 3;
6 is an equivalent circuit diagram of a cross section of the guard ring by the NWELL region shown in FIG. 4;
FIG. 7 is a block diagram showing a conventional example and an equivalent circuit diagram of a cross section.
[Explanation of symbols]
100 Semiconductor substrate
101 NWELL area
102 EPROM / FLASH memory block
103 Micro Control Unit (MCU)
104 Memory function (RAM)
105 peripheral circuit
110 Semiconductor substrate
111 NWELL area
112 NWELL area
113 EPROM / FLASH memory block
114 Micro Control Unit (MCU)
115 Peripheral circuit
116 Memory function (RAM)
200 Semiconductor substrate
201 NWELL area
202 EPROM / FLASH memory block
203 Gate array
204 Memory function (RAM)
210 Semiconductor substrate
211 NWELL area
212 NWELL area
213 EPROM / FLASH memory block
214 Gate array
215 Memory function (RAM)
301 EPROM / FLASH memory block
302 NWELL area
303 P + region
304 N + region
305 AL
306 AL
307 CONACT
311 EPROM / FLASH memory block
312 NWELL area
313 P + region
314 N + region
315 AL
316 AL
317 CONTACT
401 EPROM / FLASH memory block
402 NWELL area
403 N + region
404 P + region
405 AL
406 AL
407 CONTACT
411 EPROM / FLASH memory block
412 NWELL area
413 N + region
414 P + region
415 AL
416 AL
417 CONTACT
500 P-substrate
501 NWELL area
502 Stacked gate memory cell
503 N + drain region
504 N + source region
505 P + region
506 Parasitic diode
507 N + region
508 P + region
509 PNP type parasitic bipolar transistor
510 control gate
511 Floating gate
600 P-substrate
601 NWELL area
602 Stack gate type memory cell
603 N + drain region
604 N + source region
605 P + region
606 Parasitic diode
607 P + region
608 N + region
609 Parasitic bipolar transistor
610 Control gate
611 Floating gate

Claims (11)

In a microcomputer that integrates a memory means for writing by channel hot electrons together with a micro control unit and peripheral functions on a semiconductor substrate of the first conductivity type,
A first impurity diffusion layer of a second conductivity type disposed adjacent to the periphery of the storage means ;
A second impurity diffusion layer of the first conductivity type formed in the first impurity diffusion layer and connected to a ground line ;
The first formed in the impurity diffusion layer, a microcomputer, characterized in that arranged and a second conductivity type third impurity diffusion layer connected to the ground line. The microcomputer according to claim 1.
A microcomputer characterized in that the first impurity diffusion layer of the second conductivity type is arranged without a break so as to surround the storage means. The microcomputer according to claim 1.
Said second conductivity type first impurity diffusion layer, before Symbol microcomputer second and third impurity diffusion layers, characterized in that arranged seamlessly so as to surround the periphery of the said storage means. In a microcomputer that integrates a memory means for writing by channel hot electrons together with a micro control unit and peripheral functions on a semiconductor substrate of the first conductivity type,
A first impurity diffusion layer of a second conductivity type disposed adjacent to the storage means ;
A second impurity diffusion layer of the first conductivity type formed in the first impurity diffusion layer and connected to a ground line ;
A third impurity diffusion layer of a second conductivity type formed in the first impurity diffusion layer and connected to the ground line ;
A microcomputer characterized in that the first impurity diffusion layer of the second conductivity type is disposed on the side facing the micro control unit and the peripheral function. In a microcomputer that integrates a memory means for writing by channel hot electrons together with a micro control unit and peripheral functions on a semiconductor substrate of the first conductivity type,
A first impurity diffusion layer of a second conductivity type disposed adjacent to the periphery of the storage means ;
A second impurity diffusion layer of a first conductivity type formed in the first impurity diffusion layer, disposed on the near side facing the storage means, and connected to a ground line ;
A third impurity of a second conductivity type formed in the first impurity diffusion layer, disposed on a side far from the storage means so as to be parallel to the second impurity diffusion layer, and connected to a ground line; A diffusion layer ;
A microcomputer characterized by arranging In a microcomputer that integrates a memory means for writing by channel hot electrons together with a micro control unit and peripheral functions on a semiconductor substrate of the first conductivity type,
A first impurity diffusion layer of a second conductivity type disposed adjacent to the storage means ;
A second impurity diffusion layer of a first conductivity type formed in the first impurity diffusion layer, disposed on the near side facing the storage means, and connected to a ground line ;
A third impurity of a second conductivity type formed in the first impurity diffusion layer, disposed on a side far from the storage means so as to be parallel to the second impurity diffusion layer, and connected to a ground line; microcomputer, wherein the diffusion layer, a first impurity diffusion layer of the second conductivity type can be placed on the side facing the micro control unit and the peripheral function. In a semiconductor device in which storage means for writing by channel hot electrons is integrated on a semiconductor substrate of the first conductivity type,
A first impurity diffusion layer of a second conductivity type disposed adjacent to the periphery of the storage means ;
A second impurity diffusion layer of the first conductivity type formed in the first impurity diffusion layer and connected to a ground line ;
The first formed in the impurity diffusion layer, a semiconductor device, characterized in that arranged and a second conductivity type third impurity diffusion layer connected to the ground line. The semiconductor device according to claim 7.
A semiconductor device characterized in that the first impurity diffusion layer of the second conductivity type is arranged without a break so as to surround the memory means. The semiconductor device according to claim 7.
It said second conductivity type first impurity diffusion layer, before Symbol second and third impurity diffusion layer of a semiconductor device, characterized in that arranged seamlessly so as to surround the periphery of the said storage means. In a semiconductor device that integrates a storage means for writing by channel hot electrons together with a logic function on a semiconductor substrate of a first conductivity type,
A first impurity diffusion layer of a second conductivity type disposed adjacent to the periphery of the storage means ;
A second impurity diffusion layer of a first conductivity type formed in the first impurity diffusion layer, disposed on the near side facing the storage means, and connected to a ground line ;
A third impurity diffusion of the second conductivity type formed in the first impurity diffusion layer and disposed on the side far from the storage means so as to be parallel to the second impurity diffusion layer and connected to a ground line the semiconductor device, characterized in that placing the layer, the. In a semiconductor device that integrates a storage means for writing by channel hot electrons together with a logic function on a semiconductor substrate of a first conductivity type,
A first impurity diffusion layer of a second conductivity type disposed adjacent to the storage means ;
A second impurity diffusion layer of a first conductivity type formed in the first impurity diffusion layer, disposed on the near side facing the storage means, and connected to a ground line ;
A third impurity of a second conductivity type formed in the first impurity diffusion layer, disposed on a side far from the storage means so as to be parallel to the second impurity diffusion layer, and connected to a ground line; A semiconductor device , wherein a diffusion layer and a first impurity diffusion layer of the second conductivity type are arranged on the side facing the logic function.

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