JP3893210B2 - Parallel data processing device and visual inspection device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a system for processing input digital signals in parallel using a plurality of processor elements and an inspection device for inspecting an object to be inspected using the system, and particularly requires high-speed and large-scale processing such as image data. The present invention relates to a parallel data processing apparatus suitable for processing digital signals and an appearance inspection apparatus using the parallel data processing apparatus.
[0002]
[Prior art]
In a conventional parallel data processing apparatus having a plurality of processor elements (PE), all these processor elements are connected to a data input unit via a common communication bus, and digital data is transferred from the data input unit. The digital data is distributed to any one of these processor elements and processed. In this case, in order to determine a processor element that distributes digital data from the data input unit, a state management unit that manages the state of each processor element (a state such as data processing, standby, or failure), and this state And a processing distribution unit for determining a processor element to which data is transferred based on management information indicating the state of the processor element in the management unit. Only the processor element determined by the processing distribution unit uses the communication bus. Data is taken in and processed, and an example of such a prior art is disclosed in JP-A-5-173990.
[0003]
FIG. 10 is a block diagram showing such a conventional parallel data processing apparatus, wherein 1 is a data input unit, 6 is a data output unit, 21 is a state management unit, 22 is management information, 23 is a processing distribution unit, and 24 is a communication unit. The buses PE (1) to (n) are processor elements.
[0004]
In the figure, a common communication bus 24 has a data input unit 1, data output unit 6, n (where n is an integer of 2 or more) processor elements PE (1) to (n), state management unit 21, and processing. A distribution unit 23 is connected. Digital data input from the data input unit 1 is distributed to the processor elements PE (1) to (n) through the communication bus 24 and processed in parallel. The processed data is transmitted from the data output unit 6 through the communication bus 24. Is output.
[0005]
The state management unit 21 and the processing distribution unit 23 can communicate with the processor elements PE (1) to (n) via the communication bus 24. In the state management unit 21, the processor elements PE (1) to (n) Information indicating the current state as described above is sent from (n), held as management information 22, and the state of each of the processor elements PE (1) to (n) is managed. Further, the processing distribution unit 23 grasps the states of the respective processor elements PE (1) to (n) based on the management information 22 in the state management unit 21, and the data to be input next in the data input unit 1 Processor elements PE to be distributed and processed are determined.
[0006]
Here, when the state changes, the processor elements PE (1) to (n) do not transfer data indicating the new state (hereinafter referred to as state information) over the communication bus 24 (non-transfer period). ) To the state management unit 21 to inform the state of itself, and the processing distribution unit 23 determines a distribution destination of data to be transferred next from the data input unit 1 within the non-transfer period.
[0007]
Therefore, the processor elements PE (1) to (n) recognize the state of the communication bus 24 and transfer the current data, for example, when the state changes from the processing state to the standby state after the processing is completed. If the data transfer is not completed, the status information is immediately sent to the status management unit 21. The processing distribution unit 23 determines the processor element PE to be subjected to data processing next based on the management information 22 of the state management unit 21, and then the processor element determined by data input from the data input unit 1. Transferred to PE.
[0008]
[Problems to be solved by the invention]
In this way, since the data input unit 1 inputs the next data after the processing distribution unit 23 determines the processor element PE to process the next data, the processor element PE sends the next data to the state management unit 21. Transmission of the status information and determination of the processor element PE to be processed next by the processing distribution unit 23 can be performed with a margin, and input data is not missed.
[0009]
However, if the data input unit 1 is an image detector such as an image sensor or a video camera, and the data to be processed is image data that is two-dimensional data, the image data depends on the state of the processor element PE and the operation of the processing distribution unit 23. Regardless of this, the data is sequentially input from the data input unit 1, and the amount of information is large, so that there are many cases where the data cannot be overlooked. For this reason, as in the above-described prior art, a period for transmission of status information from the processor element PE to the status management unit 21 and determination of the processor element PE to be processed next by the processing distribution unit 23 is set with a margin. In order to provide such a marginal period, a large-capacity buffer memory for temporarily storing input data is required.
[0010]
Thus, a method is known in which the order of distributing input data to a plurality of processor elements PE is set for parallel processing of image data. It is assumed that four processor elements PE (1), (2), (3), and (4) are used, and image data D is sequentially input as shown in FIG. The image data D is distributed to the processor elements PE (1), (2), (3), and (4) in order for each unit image data (image data in one horizontal scanning period or field period). It is to make. Therefore, every three unit data D1, D5, D9, D13,... Are distributed and processed by the processor element PE (1) (note that the hatched portion in FIG. 11 represents the processing period of the unit image data, This processing period includes output processing of the processed unit data), and the processor element PE (2) distributes and processes every other unit data D2, D6, D10,. PE (3) further distributes and processes every other unit data D3, D7, D11,..., And processor element PE (4) processes the remaining unit data D4, D8, D12,. …… is distributed and processed. In this case, how many unit image data each processor element PE processes is determined by the maximum time required for processing the unit image data, and this processing time varies depending on the information amount of the unit image data. The longer the maximum processing time, the longer the interval for taking in unit data, and the number of processor elements PE to be used increases accordingly, which increases the size and cost of the parallel data processing device.
[0011]
Further, according to such a parallel processing method of image data, for example, the captured unit image data is processed in a short time like the processing of the unit image data D5 of the processor element PE (1) in FIG. Even in this case, the processor element PE (1) must wait until the next unit image data D9 is transferred. For this reason, the operation rate of the processor element PE as the whole parallel data processing apparatus is lowered.
[0012]
An object of the present invention is to solve such a problem, and can efficiently process data that has a large amount of information such as image data and is input at high speed, and can improve the operating rate of the processor element. The object is to provide a compact, low-cost parallel data processing device that can be improved.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the present invention comprises a data input unit that is driven by a drive signal transmitted through a drive signal bus and inputs a digital signal in a first predetermined state of the drive signal. A plurality of processor elements to which a digital signal input through the data bus through the data input unit is supplied through the data bus; and a second state of the drive signal in which the data input unit does not input the digital signal. A processing distribution unit that communicates with the plurality of processor elements via a communication bus, and the processing distribution unit monitors the states of the plurality of processor elements when the drive signal is in the second state, According to the monitoring result, there is provided means for determining the processor element to distribute and process the digital signal from the data input unit.
[0014]
With such a configuration, it is possible to grasp the state of each processor element during a period in which no digital signal is input, and to determine that the next input digital signal is to be distributed and processed in any standby processor element. The input digital signal can be processed without being missed without increasing the number of processor elements, and can be uniformly distributed to the respective processor elements. The operating rate of
[0015]
The present invention also divides a plurality of the processor elements into a plurality of groups, and provides the processing distribution unit for each group, and distributes the digital signal from the data input unit to the processor elements in each group. To process.
[0016]
According to such a configuration, even if there is a large amount of communication between each processor element PE and the processing distribution unit, such communication is shared by each group, so the amount of communication in each group is reduced and input is reduced. The division of the digital signal to the respective processor elements is ensured.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
FIG. 1 is a block diagram showing an embodiment of a parallel data processing apparatus according to the present invention, wherein 1 is a data input unit, 2 is a drive signal bus, 3 is a data bus, 4 is a communication bus, 5 is a processing distribution unit, Reference numeral 6 denotes a data output unit, and PEs (1), (2), (3),..., (N) are processor elements.
[0019]
In the figure, a data input unit 1 is an image detector for inputting two-dimensional image data, such as an image sensor or a video camera, and is driven by a drive signal supplied via a drive signal bus 2. . Here, the data input unit 1 is a video camera. Therefore, the drive signal is a horizontal or vertical sync pulse (hereinafter collectively referred to as a sync pulse).
[0020]
The image data input from the data input unit 1 is n (where n is an integer of 2 or more) processor elements PE (1), (2), (3),. n). These processor elements PE (1), (2), (3),..., (N) and the processing distribution unit 5 can communicate with each other via the communication bus 4. The processor elements PE (1), (2), (3),..., (N) and the processing distribution unit 5 are connected to the drive signal bus 2, and the state of the drive signal bus 2 is always changed. Monitoring. Now, assuming that the state of the drive signal bus 2 is “H” in the pulse period of the synchronization pulse transmitted through the drive signal bus 2 and the state of the other period is “L”, the state of the drive signal bus 2 is “L”. Each time “”, image data is transferred from the data input unit 1 via the data bus 3, and when the state of the drive signal bus 2 is “H” (that is, the pulse period of the synchronization pulse), the data bus 3 Image data is not transferred.
[0021]
In the following, image data transferred from the data input unit 1 in a period between synchronization pulses (a period in which the state of the drive signal bus 2 is “L”) is unit image data, and this unit image data is When the sync pulse is a horizontal sync pulse, image data in one horizontal scanning period, and when the sync pulse is a vertical sync pulse or a frame pulse, it is image data of one field or one frame.
[0022]
The processor elements PE (1), (2), (3),..., (N) and the processing distribution unit 5 constantly monitor the state of the drive signal bus 2 as described above. When it is “H” (that is, within the pulse period of the synchronization pulse), it is possible to communicate with each other via the communication bus 4. From the processor elements PE (1), (2), (3),..., (N), information indicating a new state when the state (processing, standby, failure, etc.) is changed. (Hereinafter, referred to as state information) is transmitted to the processing distribution unit 5 via the communication bus 4, and the processing distribution unit 5 receives the state information and holds it as management information, whereby these processor elements PE (1) , (2), (3),..., (N), and a processor element PE for distributing image data from the data input unit 1 for each unit image data based on this management information. The information representing the decision (hereinafter referred to as distribution decision information) is transmitted to the corresponding processor element PE. As a result, the processor element PE whose distribution has been determined takes in the unit image data to be transferred next from the data input unit 1 via the data bus 3. When this capture is completed, the state of the drive signal bus 2 becomes “H” (that is, the pulse period of the synchronization pulse), so that the processor element PE distributes the status information “processing” via the communication bus 4. The data is transmitted to the unit 5, and then processing of the captured unit image data is started. The processed unit image data is transferred through the data bus 3 and output from the data output unit 6. When the output processing of the processed unit image data is completed, the next time the drive signal bus 2 is in the “H” state, the processor element PE transmits the “standby” state information to the processing distribution unit 5. .
[0023]
The unit image data processed by the processor element PE is output from the data output unit 6 through the same data bus 3 or a processing result transfer bus provided separately. When the data is transferred, for example, a process such as modulation is performed so that the data output unit 6 can be distinguished from the input image data from the data input unit 1. Perform processing.
[0024]
In this way, this embodiment detects a synchronization pulse period that is inevitably added to image data, and performs communication between the processor element PE and the processing distribution unit 5 during that period. Even if image data is successively input from the data input unit 1, each processor element PE can send status information to the processing distribution unit 5, and the processing distribution unit 5 also monitors the status of all the processor elements PE. Therefore, the distribution of the unit image data to the processor elements PE can be reliably performed without being lost.
[0025]
2 is a block diagram showing a specific example of the processor element PE in FIG. 1, wherein 7 is a microprocessor (hereinafter referred to as a microcomputer), 8 is a local memory, 9 is a switch unit, 10 is a drive signal monitoring unit, 11 Is a processing state storage unit, and 12 is a distribution content storage unit.
[0026]
In the figure, the drive signal monitoring unit 10 constantly monitors the state of the drive signal bus 2. The processing state storage unit 11 stores state information indicating the state of the microcomputer 7 (processing, standby, failure, etc.), and may be part of the local memory 8. The microcomputer 7 processes the unit image data fetched from the data bus 3 to the local memory 8 via the switch unit 9. When the status is changed from standby to processing, from processing to standby, etc. State information representing the new state after the change is stored in the processing state storage unit 11.
[0027]
Further, the distribution content storage unit 12 stores the content (distribution content) of the distribution determination information sent from the processing distribution unit 5 (FIG. 1) via the communication bus 4, and the switch unit 9 responds accordingly. ON / OFF controlled. When this distribution content indicates that it is decided to distribute the unit image data to the processor element PE, the distribution content storage unit 12 turns on the switch unit 9 and the unit image data is transferred from the data bus 3 to the switch unit 9. Is taken into the local memory 8 via.
[0028]
Next, the operation of this specific example will be described.
[0029]
Assuming that the microcomputer 7 is in a standby state, the distribution content stored in the distribution content storage unit 12 is “not distributed”, and the switch unit 9 is in an OFF state. The status information in the processing status storage unit 11 also indicates “standby”.
[0030]
Now, a synchronization pulse is supplied to the data input unit 1 (FIG. 1) via the drive signal bus 2, and when the drive signal monitoring unit 10 detects that the state of the drive signal bus 2 has become "H". Under the control of the drive signal monitoring unit 10, the processing state storage unit 11 can transmit the state information stored therein to the processing distribution unit 5 (FIG. 1) via the communication bus 4 (in this case, of course, this Although the status information may be transmitted, the content of the status information may not be transmitted because the content of the status information has not changed.Here, the status information is not transmitted unless the content is changed. In addition, the distribution content storage unit 12 can receive distribution determination information from the processing distribution unit 5 via the communication bus 4.
[0031]
Therefore, when the distribution determination information of the content determined to be distributed to the processor element PE is sent from the processing distribution unit 5 via the communication bus 4, the distribution content storage unit 12 stores this and stores the content. Judgment is made and the switch unit 9 is turned on. Thereafter, when the state of the drive signal bus 2 becomes “L” and the data input unit 1 (FIG. 1) starts transferring the unit image data from the data bus 3, the unit image data is transferred to the microcomputer via the switch unit 9. 7 is taken into the local memory 8 under the control of 7. When this capture is completed, the switch unit 9 is turned off, and the microcomputer 7 changes the content of the state information in the processing state storage unit 11 from “standby” to “processing”. When the state of the drive signal bus 2 changes to “H” by the next synchronization pulse, the drive signal monitoring unit 10 transmits the status information “processing” in the processing state storage unit 11 via the communication bus 4 to the processing distribution unit. 5 is transmitted. Along with the above operation, the microcomputer 7 starts the processing operation of the unit image data fetched into the local memory 8.
[0032]
When the processing operation ends, the microcomputer 7 changes the content of the state information in the processing state storage unit 11 from “processing” to “standby”. When the state of the drive signal bus 2 is changed to “H” by the next synchronization pulse, the drive signal monitoring unit 10 transmits the status information “waiting” in the processing state storage unit 11 via the communication bus 4 to the processing distribution unit. 5 is transmitted.
[0033]
In this way, each processor element PE can transmit its state information to the processing distribution unit 5 (FIG. 1) during the “H” state of the drive signal bus 2 where no image data is transferred. Distribution determination information from the processing distribution unit 5 can be received.
[0034]
In this specific example, only specific data of the image data (for example, image data at a specific portion such as the upper left corner on the screen) can be processed. In this case, for each configuration data (for example, pixel data) of the unit image data of the image data, for example, information (identification information) for identifying the type of data is added to the header portion, and In FIG. 2, information (designation information) for designating this specific data is also stored in the distribution content storage unit 12, and the distribution determination information supplied via the communication bus 2 stores unit image data in the processor element PE. Even if it represents that the data is to be distributed, the distribution content storage unit only when it is the configuration data having the type information specified by the specified information of the unit image data sent via the data bus 3 12 turns on the switch unit 9.
[0035]
FIG. 3 is a block diagram showing a specific example of the processing distribution unit 5 in FIG. 1, in which 13 is a state management unit, 14 is a processing distribution determination unit, and 15 is a drive signal monitoring unit.
[0036]
In the figure, when the state information is supplied from the processor element PE through the communication bus 4 during the period in which the drive signal bus 2 is in the “H” state, the state management unit 13 captures this. That is, management information representing the state of each processor element PE is stored in the state management unit 13, and when the state information is sent from a certain processor element PE, the management information in the state management unit 13 is obtained from this state information. The content for the corresponding processor element PE is changed. In this way, the current state of each processor element PE can be known from this management information.
[0037]
On the other hand, the drive signal monitoring unit 15 constantly monitors the state of the drive signal bus 2, and when the drive signal bus 2 is in an “H” state that enables communication with the processor element PE, the drive signal monitoring unit 15. Operates the processing distribution determination unit 14. As a result, the processing distribution determination unit 14 determines the processor element PE to which the next unit image data is to be distributed using the management information of the state management unit 13, and waits for the processor element PE that has been in the processing state so far. In this case, it is determined that the processor element PE is changed to the standby state, and each determination is transmitted to the corresponding processor element PE via the communication bus 4 as distribution determination information.
[0038]
In this manner, the processing distribution unit 5 can communicate with the processor element PE when the drive signal bus 2 is in the “H” state.
[0039]
FIG. 4 is a diagram showing the timing relationship between the state of the drive signal bus 2 and the image data. As shown in FIG. 4, the image is displayed in the “L” period between the synchronization pulses in which the drive signal bus 2 is in the “H” state. Data exists. Communication between the processing distribution unit 5 and the processor element PE is performed within a period of “H” state in which no image data exists, and the processor element PE to which unit image data is to be distributed is determined. The unit image data in the “L” state is always distributed to the determined processor element PE, and the image data is processed without missing.
[0040]
FIG. 5 is a timing diagram showing the operation of the embodiment shown in FIG. 1, and FIG. 6 is a diagram showing management information of the information management unit 13 in FIG. 3 in each state of FIG.
[0041]
In FIG. 5, S1, S2, S3, S4, S5, S6,... In the state of the drive signal bus 2 indicate the “H” state of the pulse period of the synchronization pulse as the drive signal. The unit image data D1, D2, D3, D4, D5, D6,... Are transferred on the data bus 3 every “L” period.
[0042]
Here, assuming that three (N = 3) processor elements PE (1), (2), (3) are used, these processor elements PE (1), (2), If all (3) are in the standby state, the management information in the state management unit 13 (FIG. 3) is as shown in FIG. 6 (a). The processing distribution determination unit 14 (FIG. 3) searches for the “waiting” processor element from the top of this management information in the state S1 in which the drive signal bus 2 is “H”, and first finds the “waiting” processor. Although the element is determined to process the next unit image data, in the state S1 in which the drive signal bus 2 in the initial state is “H”, the processing distribution unit 5 determines the unit from the management information shown in FIG. The processor element PE (1) is determined as the image data to be distributed. As a result, the unit image data D1 transferred after this "H" state S1 is taken into the processor element PE (1). When this capture is completed, the processor element PE (1) starts processing the unit image data D1, and the state management unit starts from the processor element PE (1) in the "S" state S2 of the next drive signal bus 2. As shown in FIG. 6B, the management information in the state management unit 13 indicates that the processor element PE (1) is “processing” by communication of the state information to 13 (FIG. 3). become.
[0043]
In this case, in the arrangement in the management information, the state information of the processor element whose state has changed is arranged last, and the order of the state information of the other processor elements is advanced accordingly. Accordingly, when the state management unit 13 receives the state information “processing” from the processor element PE (1), the management information there is as shown in FIG. 6B.
[0044]
The hatched portion in the operation of the processor element PE (1) indicates the processing period of the captured unit image data and the period for outputting the processing result. The other processor elements PE (2), (3) The same applies to.
[0045]
The processing distribution determination unit 14 of the processing distribution unit 5 performs this state management after a set period for capturing the state information from the processor element PE in the state management unit 13 in the “H” state S2 of the drive signal bus 2. The management information in the section 13 is searched to determine the processor element PE that should process the next unit image data. In this case, the processor element PE (2) is determined as the processor element PE based on the management information shown in FIG. Thus, when the “H” state S2 of the drive signal bus 2 elapses, the next unit image data D2 is taken into the processor element PE (2).
[0046]
When the capture of the unit image data D2 in the processor element PE (2) is completed and the next "H" state S3 of the drive signal bus 2 is reached, the processor element PE (2) sends "in process" to the information management unit 13. As a result, as shown in FIG. 6C, the processor element PE (2) is managed as “processing” and the management information in the state management unit 13 is Finally arranged. At the same time, the processor element PE (2) starts processing the unit image data D2.
[0047]
Similarly, in the “H” state S3 of the drive signal bus 2, it is determined that the management information shown in FIG. 6C is to be processed by the processor element PE (3) for the next unit image data D3. When the “H” state S3 of the bus 2 elapses, the processor element PE (3) starts taking in the unit image data D3.
[0048]
When the processing of the unit image data D2 in the processor element PE (2) is completed while the unit image data D3 is being taken in by the processor element PE (3), the processor element PE (3 in the “H” state S4 of the drive signal bus 2 ) From the processor element PE (2) and “standby” status information to the state management unit 13. Therefore, the management information in the state management unit 13 is As shown in FIG. 6D, only the processor element PE (2) becomes “standby”. Accordingly, the processing distribution determination unit 14 selects the processor element PE (2) from this management information, and determines the processor element that processes the next unit image data D4. Accordingly, after the “H” state S4 of the drive signal bus 2 elapses, the processor element PE (2) takes in the unit image data D4.
[0049]
While the unit image data D4 is being captured by the processor element PE (2), the processor element PE (3) finishes the processing of the unit image data D3, and the above-described “H” state S5 of the drive signal bus 2 is described above. When the processing of the unit image data D1 of the processor element PE (1) is completed within the set period for fetching the state information from the processor element of FIG. 6 (e), the processor elements PE (3) and (1) are managed as “standby”, and the processing distribution determination unit 14 gives priority to the processor element PE (3), and The unit image data D5 is determined to be processed. As a result, when the “H” state S5 of the drive signal bus 2 elapses, the processor element PE (3) starts taking in the next unit image data D5.
[0050]
When the processor element PE (2) completes the processing of the unit image data D4 while the unit image data D5 of the processor element PE (3) is being fetched, in the next “H” state S6 of the drive signal bus 2, the state management unit As shown in FIG. 6 (f), the management information at 13 is managed with processor elements PE (1) and (2) as “waiting” and processor element PE (3) as “processing”. . Therefore, the processing distribution determination unit 14 preferentially determines the processor element PE (1) as processing the next unit image data D6.
[0051]
Similarly, for each period of the drive signal path 2 in the “H” state S, the processing distribution determination unit 14 selects a processor element PE that is “waiting” at that time, and a plurality of processor elements PE are “standby”. When it is “medium”, the processor element PE in which the state information is arranged in advance in the management information is preferentially determined to process the next unit image data.
[0052]
In this manner, in this embodiment, since it is determined that any processor element in the “standby” state in the “H” state S of the drive signal bus 2 should be processed for the next unit image data, sequentially. Image data transferred from the data input unit 1 (FIG. 1) at regular intervals can be processed without being missed and the number of processor elements used is reduced.
[0053]
In the conventional technique described with reference to FIG. 11 in which a plurality of processor elements are used for processing in the same manner as in FIG. 5, assuming that three processor elements PE (1) to (3) are used, the processor element PE Even if the processor elements PE (2) and (3) finish the processing of the unit image data D2 and D3 while (1) is processing the unit image data D1, the unit image data D4 is processed in order according to the processor element PE. Since it is supposed to be processed in (1), it is impossible to know that these processor elements PE (2) and (3) are “waiting”. For this reason, the unit image data D4 cannot be processed, and the unit image data D4 is lost. In order to prevent this, it is necessary to add another processor element.
[0054]
In image data, the larger the amount of information, the longer the time required to process it. Accordingly, the processing time of the unit image data varies depending on the amount of information that it has, and it is difficult to predict the degree of variation in advance. However, the larger the variation is, the more processor elements are required. For this reason, in the conventional technique shown in FIG. 11, the longest processing time of the unit image data is estimated in consideration of the variation and the processor is used. In order to determine the number of elements used, a very large number of processor elements are required. On the other hand, in this embodiment, the processor element PE in which the pulse period of the synchronization pulse in which the image data is not transmitted (the period of the “H” state of the drive signal bus 2) is effectively used and is “waiting” in this period is used. Therefore, any processor element PE that is "waiting" can be used for processing the next unit image data, and the processor element PE can be used. The increase in the number can be prevented.
[0055]
Further, in this embodiment, among the processor elements PE managed as “waiting” by the state management unit 13, the processor unit PE that is previously “waiting” is prioritized and the next unit image is given priority. Since it is determined that the data is to be processed, the “waiting” state of each processor element PE can be shortened, and the operating rate of the processor element PE can be increased.
[0056]
In the specific example shown in FIG. 5, the operating state of each processor element PE is checked every time the synchronization pulse is valid, and the processor element PE that processes the unit image data to be processed next is determined. However, depending on the transfer speed of the image data and the content of the arithmetic processing, it is not always necessary to perform every synchronization pulse pulse period. Each synchronization pulse period may be used for each synchronization pulse period, such as once every several synchronization pulse periods. You may make it investigate the operation state of processor element PE, and determine the transmission partner of the next unit image data. The same applies to other embodiments described below.
[0057]
FIG. 7 is a block diagram showing another embodiment of the parallel data processing apparatus according to the present invention. 4a and 4b are communication buses, 5a and 5b are processing distribution units, and parts corresponding to those in FIG. A duplicate description is omitted.
[0058]
This embodiment is a case where n processor elements PE as shown in FIG. 1 cannot be managed by one processing distribution unit 5 (for example, a processor element with a short pulse period of a synchronization pulse). Communication of status information from the PE to the processing distribution unit 5 and communication of distribution determination information from the processing distribution unit 5 to a predetermined processor element PE are performed, but there is communication of status information from a plurality of processor elements PE. In this case, the processing distribution unit 5 may not be able to capture all the state information during this short pulse period), and divide the plurality of processor elements PE into a plurality of groups (hereinafter referred to as PE groups), and A processing distribution unit is provided for each PE group and is controlled independently. Here, the PE group A is divided into two PE groups A and B. The PE group A is composed of a processing distribution unit 5a and m processor elements PE (1) to (m), and the PE group B is a processing distribution unit 5b. It is assumed that (n−m) processor elements PE (m + 1) to (n) are included.
[0059]
In the PE group A, the processing distribution unit 5a and the processor elements PE (1) to (m) can communicate with each other via the communication bus 4a. In the PE group B, the processing distribution unit 5b and the processor elements PE (m + 1) to PE (m + 1) to (n) can communicate with each other via the communication bus 4b. Further, these processing distribution units 5a and 5b manage each other. That is, these processing distribution units 5a and 5b have, for example, the configuration shown in FIG. 3, but when all the processor elements PE managed by one of the processing distribution units 5a and 5b are in “processing”, the other The managed “standby” processor element PE is allowed to process the next unit image data.
[0060]
Therefore, similarly to the embodiment shown in FIG. 1, in the processing distribution unit 5a, management information indicating the states of the processor elements PE (1) to (m) is stored in the information management unit 13 (FIG. 3). In the processing distribution unit 5b, management information indicating the state of each processor element PE (m + 1) to (n) is stored in the information management unit 13, but now the information management of the processing distribution unit 5a If all the processor elements PE (1) to (m) are in “processing” from the management information in the unit 13, the processing distribution unit 5a notifies the processing distribution unit 5b of this fact. As a result, the processing distribution unit 5b searches for the processor element PE in “standby” using the management information in the information management unit 13 in the same manner as in the embodiment shown in FIG. It is determined as a processor element PE that processes unit image data.
[0061]
Here, the processor element PE for processing the next unit image data is determined with priority in the PE groove A, and when there is no such processor element PE (all the processor elements PE (1) to (m) are present). In the case of “in process”, the processor element PE may be searched from the processor elements PE (m + 1) to (n) in the PE group B. In order not to shift to the PE group, the processor elements PE for processing the next unit image data are determined alternately in the PE groups A and B, and when there is no processor element PE to be determined, the other You may make it move to the PE group.
[0062]
The above processing distributes the unit image data from the data input unit 1 to any one of the processor elements PE (1) to (n), and this is the same as the embodiment shown in FIG. However, as a modification of this embodiment shown in FIG. 7, different unit image data in images may be processed in PE group A and PE group B.
[0063]
For example, as shown in FIG. 8A, PE group A processes every other unit image data D1, D3,... From data input unit 1, while PE group B receives other data from data input unit 1. Alternatively, every other unit image data D2, D4,... May be processed. In this case, every other unit image data transferred from the data input unit 1 and every other unit image data are added with identification information for identifying them, and In the processor element PE (1) to PE (m) of the PE group A, designation information for the identification information of the unit image data to be captured is stored in the distribution content storage unit 12 (FIG. 2). Similarly, the PE group B Also in the processor elements PE (m + 1) to (n), the distribution information storage unit 12 stores designation information for identification information of unit image data to be captured.
[0064]
As another modification, for example, as shown in FIG. 8B, a part (for example, the first half) of each unit image data is distributed to the PE group A for processing. Another part (for example, the second half) may be distributed to the PE group B for processing. Different identification information is added to each of these parts, and the distribution content storage unit 12 (FIG. 2) of the processor elements PE (1) to (m) of the PE group A and the processor element PE (m + 1) of the PE group B In the distribution content storage unit 12 of () to (n), instruction information for identification information of data to be fetched is stored. In this case, if the unit image data is image data of one horizontal scanning period, PE group A processes image data of the left half of the screen, and PE group B processes image data of the right half of the screen. become. When the unit image data is one-field image data, PE group A processes the upper half of the screen image data, and PE group B processes the lower half of the image data. become. The processing contents may be different between PE group A and PE group B.
[0065]
In the above embodiment, the number of PE groups and the number of processor elements PE constituting one PE group are determined according to conditions such as data transfer amount, data transfer rate, and frequency and length of synchronization pulse period. Thus, an optimum configuration can be taken under various conditions.
[0066]
In the embodiment described above, the state of the drive signal bus 2 in the pulse period of the synchronization pulse is “H”, but may be “L”. In short, in these embodiments, when the drive signal bus 2 is in a specific state where image data is not transferred, communication is performed between the processing distribution units 5, 5a, 5b and the processor element PE as described above. It is only necessary to manage the state of the processor element PE and determine the processor element for processing the unit image data.
[0067]
From this point, communication between the processing distribution units 5, 5a, 5b and the processor element PE does not necessarily have to be performed in the pulse period of the synchronization pulse, and the data to be processed is image data. If there is a period in which arbitrary data to be processed is interrupted as in the case of observing an object at a predetermined time interval, the period is detected and the processing distribution units 5 and 5a are detected in that period. , 5b and the processor element PE may perform the same communication.
[0068]
FIG. 9 is a block diagram showing an embodiment of a semiconductor wafer visual inspection apparatus using a parallel data processing apparatus according to the present invention, wherein 16 is a parallel data processing apparatus according to the present invention, 17 is a stage, 18 is a semiconductor wafer, Reference numeral 19 denotes a lens, and 20 denotes a linear sensor.
[0069]
In this embodiment, the appearance of a semiconductor wafer is inspected. In FIG. 9, a semiconductor wafer 18 to be inspected is mounted on a stage 17. This stage 17 can be driven in the x and y directions. A predetermined part of the semiconductor wafer 18 is imaged on the linear sensor 20 via the lens 19, and an image of this part is output from the linear sensor 20 as image data. This image data is transferred to the parallel data processing device 16. The parallel data processing device 16 has the configuration shown in FIGS. 1 and 7 and performs the efficient parallel processing on the transferred image data as described with reference to FIGS.
[0070]
In general, in the appearance inspection of a semiconductor wafer, the amount of image data detected by the linear sensor 20 is enormous. Further, the detection speed of the linear sensor 20 is also improved, and the parallel data processing device 16 needs to process enormous image data at high speed.
[0071]
Therefore, by using the parallel data processing apparatus according to the above-described embodiment as the parallel data processing apparatus 16, even in the appearance inspection of a semiconductor wafer that needs to process such a huge amount of image data, Since image data can be distributed to the processor elements PE, processing can be performed with the minimum number of processor elements PE.
[0072]
Further, when the detection speed of the linear sensor 20, the data transfer speed, and the sensor to be used differ depending on the inspection conditions and the change in the inspection target, a plurality of processor elements PE are grouped as described with reference to FIG. In addition, by changing the number of groups and the number of processor elements PE constituting one group to an optimum one, it is possible to efficiently distribute image data to each processor element PE and to operate the processor element PE. The rate is improved and the price of the appearance inspection apparatus can be reduced.
[0073]
The inspection target is not limited to the semiconductor wafer, but may be a printed wiring board or other ones. The same effect as described above can be obtained, and the price of the appearance inspection apparatus can be reduced.
[0074]
【The invention's effect】
As described above, according to the present invention, a plurality of processor elements can be effectively used. As a result, a large amount of data can be processed at high speed, and the price / performance ratio is improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a parallel data processing apparatus according to the present invention.
FIG. 2 is a block diagram showing a specific example of a processor element in FIG.
3 is a block diagram illustrating a specific example of a processing distribution unit in FIG. 1. FIG.
4 is a diagram showing a timing relationship between the state of the drive signal bus in FIG. 1 and image data on the data bus. FIG.
FIG. 5 is a timing chart showing an operation of the embodiment shown in FIG. 1;
6 is a diagram showing a change in management information of the state management unit in FIG. 3 according to the operation shown in FIG.
FIG. 7 is a block diagram showing another embodiment of a parallel data processing apparatus according to the present invention.
FIG. 8 is a diagram showing an operation of a modification of the embodiment shown in FIG.
FIG. 9 is a configuration diagram showing an embodiment of an appearance inspection apparatus using a parallel data processing apparatus according to the present invention.
FIG. 10 is a block diagram showing an example of a conventional parallel data processing apparatus.
FIG. 11 is a diagram illustrating a processing operation of a conventional parallel data processing apparatus for image data.
[Explanation of symbols]
PE (1)-(n) Processor element
1 Data input section
2 Drive signal bus
3 Data bus
4, 4a, 4b Communication bus
5, 5a, 5b Processing distribution unit
6 Data output part
7 Microprocessor
8 Local memory
9 Switch part
10 Drive signal monitoring unit
11 Processing state storage unit
12 Distribution contents storage
13 State Management Department
14 Processing distribution decision section
15 Drive signal monitoring unit
16 Parallel data processor
17 stages
18 Semiconductor wafer
19 Lens
20 Linear sensor

Claims (5)

A data input unit that is driven by a drive signal transmitted via a drive signal bus and inputs a digital signal in a first state of the drive signal;
A plurality of processor elements to which a digital signal input at the data input unit via the data bus is supplied via the data bus;
A processing distribution unit that communicates with a plurality of the processor elements via a communication bus in a second state of the drive signal in which the data input unit does not input a digital signal;
The data input unit is an image detection unit,
The processing distribution unit monitors the states of the plurality of processor elements when the drive signal is in the second state, and distributes and processes the digital signals from the data input unit according to the monitoring result. have a means for determining the processor elements,
The drive signal is a synchronization signal, a signal period of the synchronization signal is a period of the second state of the drive signal, and a period other than the signal period of the synchronization signal is a period of the first state of the drive signal parallel data processing apparatus characterized by a. In claim 1,
Each of the processor elements is
A microprocessor for processing a digital signal from the data input unit;
A first monitoring unit that constantly monitors the state of the drive signal;
Storing state data indicating whether the microprocessor is processing or waiting, and when the drive signal is in the second state according to a monitoring result of the first monitoring unit, A processing state storage unit for transmitting state data to the processing distribution unit via the communication bus;
A determination command signal is received from the processing distribution unit via the communication bus according to a monitoring result of the first monitoring unit, and the data input unit via the data bus according to the determination command signal A distribution content storage unit that captures the digital signal transmitted from the processing unit and causes the microprocessor to process the processing unit.
A second monitoring unit that constantly monitors the state of the drive signal;
When the drive signal is in the second state from the monitoring result of the second monitoring unit, the state data sent from the processing state storage unit of each of the processor elements is fetched via the communication bus. A state management unit to hold;
When the driving signal is in the second state based on the monitoring result of the second monitoring unit, the data in the first state next to the driving signal is determined by the state data held in the state management unit. Distribution decision to determine the processor element to which the digital signal input at the input unit should be distributed, and to transmit the determination result as the determination command signal to the processor element that has determined distribution of the digital signal via the communication bus And a parallel data processing device. In claim 1 ,
Dividing the plurality of processor elements into a plurality of groups, and providing the processing distribution unit for each group;
A parallel data processing apparatus for processing a digital signal from the data input unit distributed to processor elements within each group . An apparatus for inspecting the appearance of a semiconductor wafer, a printed circuit board or the like using the parallel data processing apparatus according to claim 1,
An appearance inspection apparatus characterized in that the contents to be processed by each of the processor elements are changed based on an inspection result or an inspection condition . An apparatus for inspecting the appearance of a semiconductor wafer, a printed circuit board or the like using the parallel data processing apparatus according to claim 3 ,
Based on the test results and test conditions, change the contents to be processed in the respective processor element,
An appearance inspection apparatus characterized in that the number of groups and the number of processor elements forming the group are variable based on inspection results and inspection conditions .

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