JP3891456B2 - Integrated circuit failure verification method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an efficient and highly accurate failure verification method for integrated circuits.
[0002]
[Prior art]
In a manufacturing process of an integrated circuit, for example, when a fine foreign matter adheres to the mask, a defect such as a pattern bridge may occur at the attached portion. Such a defect is generally detected by examining input / output signals using a predetermined test pattern in an integrated circuit inspection process. An automatic test pattern generator (ATPG) that automatically generates such a test pattern based on information such as a circuit diagram is also well known.
[0003]
However, in a highly integrated circuit, the number of test patterns to be executed is limited due to the limitation of the inspection time corresponding to the cost. Therefore, it is important to detect an integrated circuit failure (hereinafter referred to as a failure) efficiently in a short time. Therefore, it is necessary to evaluate the probability of detecting a failure of the integrated circuit with a certain test pattern, that is, the failure detection rate. Such an evaluation of the failure detection rate is referred to as failure verification in this specification.
[0004]
Conventionally, a sampling method has been theoretically proven and used as a method for performing failure verification at high speed. In this technique, for example, a failure state is artificially created in advance in an integrated circuit, and this is applied to an inspection machine (or failure detector) to check whether or not the failure is normally detected (failure) simulation). Then, a plurality of failures are randomly sampled from all possible failures, the above-described failure simulation is performed for these failures, and the failure detection rate is estimated from the failure detection result. Alternatively, the automatic test pattern generation apparatus may have a function of estimating the failure detection rate based on the combination of generated test patterns as described above.
[0005]
In order to reduce the error between the failure detection rate estimated by the above sampling method and the actual failure detection rate, that is, the failure detection rate when all failures are simulated, the number of samplings may be increased. As described above, there is a limitation on the inspection time corresponding to the cost. Therefore, the number of samplings is determined so that the above error falls within a predetermined allowable range. In general, the larger the scale of an integrated circuit, the greater the number of possible failures. Conventionally, the sampling rate is determined based on the circuit size and the failure detection rate.
[0006]
[Problems to be solved by the invention]
However, in the physical area on the chip, when a phenomenon that causes a failure, for example, adhesion of foreign matter to the mask occurs, this leads to failure when foreign matter adheres to the part where the mask pattern exists. It is. There is a portion where no mask pattern exists on the chip, and even if foreign matter adheres to this portion, it does not lead to failure.
[0007]
Usually, the mask pattern does not exist uniformly on the chip, and a portion where the mask pattern is dense and a portion where the mask pattern is sparse are generated on the chip. Therefore, even if the phenomenon that causes the failure occurs almost uniformly on the chip, the probability of the actual failure occurring is not uniform on the chip, and the mask pattern is denser than the sparse part This increases the failure rate.
[0008]
Since the conventional failure detection rate is calculated using only the circuit netlist and the test pattern, there is a possibility that the calculated failure detection rate cannot guarantee the accuracy as an index of the actual failure occurrence rate.
[0009]
Therefore, the present invention pays attention to the distribution of the mask pattern density in the chip, and calculates a new failure detection rate according to the physical failure occurrence rate, thereby enabling highly accurate and highly efficient inspection. The purpose is to contribute to the reduction of failures (initial failures).
[0010]
[Means for Solving the Problems]
The failure verification method according to the present invention extracts the mask pattern density from the floor plan or layout information when the mask pattern of the integrated circuit to be inspected is created, and the obtained mask pattern density and the failure simulator or automatic test pattern generation device The calculating means calculates a new failure detection rate according to the physical failure occurrence rate based on the obtained failure detection rate.
[0011]
As a more specific configuration, the failure verification method according to the present invention divides a circuit included in one chip of an integrated circuit into a plurality of blocks in functional units, and creates a floor plan or layout when a mask pattern is created for each block. Extracts the mask pattern density from the information, calculates the failure weight of each block from the obtained mask pattern density and the number of failures in each block, and calculates the sampling rate in each block according to the failure weight of each block Then, determine the failure sampling value according to the physical failure occurrence rate, the failure verification device performs failure verification with random sampling using the sampling rate determined for each block, and finally each block The method includes a step of calculating failure verification results and calculating a result for one chip.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
As shown in FIG. 1, it is assumed that a portion where a mask pattern exists and a portion where a mask pattern does not exist are distributed on a rectangular chip. In FIG. 1, the shaded “part with mask” is the part where the mask pattern exists, and the white “part without mask” is the part where the mask pattern does not exist.
[0013]
Further, if the entire rectangular chip is divided into four blocks A, B, C, and D by dividing the entire chip vertically and horizontally, the mask pattern density in each block, that is, the ratio of the mask pattern to the total area is different. In the case of FIG. 1, the mask pattern density is highest in the block B, and decreases in the order of D, C, and A. In the portion where the mask pattern density is low, even if a phenomenon causing the failure occurs, the failure occurrence rate is low. On the other hand, a portion having a high mask pattern density has a high failure rate due to a phenomenon that causes the same failure. For example, in the case of FIG. 1, since the block B has a higher mask pattern density than the block A, the failure occurrence rate due to the phenomenon causing the failure is higher in the block B than in the block A.
[0014]
In general, the relationship between the failure occurrence rate based on the physical area of the chip and the mask pattern density is proportional as shown in FIG. As described above, the failure occurrence rate varies depending on the layout state of the mask pattern, and it is necessary to consider the density of the mask pattern in order to obtain an accurate failure occurrence rate.
[0015]
According to the failure verification method of the present invention, a failure detection rate with higher accuracy than the conventional failure detection rate is calculated by considering physical parameters obtained from the floor plan or layout information when creating the mask pattern. can do. A specific processing procedure of the failure verification method of the present invention will be described with reference to FIG.
[0016]
First, layout parameters are extracted from the floor plan or layout information when an integrated circuit mask pattern is created in step 303. Based on both the obtained layout parameter 304 and the failure detection rate 302 obtained from the conventional failure detection apparatus 301, the calculation means 305 considering the mask density has a high accuracy according to the physical failure occurrence rate. A failure detection rate 306 is newly calculated.
[0017]
Next, another embodiment of the present invention will be described. In this embodiment, the present invention is applied to a sampling method. As described in the description of the prior art, the sampling method samples a plurality of failures randomly from all failures included in one chip of an integrated circuit, and obtains a failure detection rate by the failure detection device for only those failures. This is a method of performing processing and estimating the failure detection rate for all failures from the result.
[0018]
As shown in FIG. 4, it is assumed that there are three blocks A, B, and C having different mask pattern densities on one chip. In this figure, the mask pattern density of block A is the highest, and the mask pattern density is lower in the order of B and C. As described above, the higher the mask pattern density, the higher the failure occurrence rate. In this embodiment, the sampling rate of each block is changed according to the failure occurrence rate, that is, the mask pattern density. As shown in FIG. 4, the sampling rate is increased as the block has a higher mask pattern density .
Thus, based on the physical parameters (mask pattern density) obtained from the floor plan or layout information when creating the mask pattern of the integrated circuit, an appropriate sampling rate that takes into account the failure rate of each block By performing the failure verification in step 1, it is possible to calculate a highly accurate failure detection rate. A specific processing procedure will be described with reference to the flowchart of FIG.
[0019]
First, the failure detection device 505 calculates the failure number 506 for the entire chip, and calculates the sampling rate for the entire chip according to the number of failures for the entire chip at 507. The sampling rate S for allowing the failure detection rate by sampling to fall within the range of the error ΔP with respect to the failure detection rate for all failures can be obtained from the following equation.
[0020]
ΔP = 3 × SQRT ((1-S) k (1-k) / SN)
In this equation, SQRT () represents a square root operation. k is the failure detection rate of one chip, and N is the total number of target failures. If the number of failures sampled at random is n, the sampling rate S = n / N.
[0021]
On the other hand, block division information 502 is obtained from the floor plan or layout when the integrated circuit mask pattern is created in processing 501, and the number of failures for each block is calculated at 508 based on this information. In addition, the mask pattern density is extracted as a physical parameter (layout parameter) from the floor plan or layout information when the mask pattern is created by processing 503, and the obtained layout parameter 504 and each block calculated in 508 are used. In step 509, the failure weight of each block is calculated using the number of failures. Next, in processing 510, the sampling rate for one chip calculated in 507 is corrected according to the failure weight of each block calculated in 509, and the sampling rate corresponding to the average weight of failure in each block is set. decide. Next, the failure detection device 511 performs verification at the sampling rate in each block, and finally, the detection rates obtained in each block in processing 512 are totaled to derive the failure detection rate in one chip.
[0022]
As described above, according to the present embodiment, it is possible to efficiently calculate a new failure detection rate corresponding to the physical failure occurrence rate by extracting and processing failures from all failures at random. . The method of this embodiment is particularly effective when a plurality of functional cores having different mask pattern layout densities are integrated into one chip, or when a functional core having a different process density is integrated into one chip. For example, when a high-mask pattern density multiplier and memory and a logic circuit with a low mask pattern density are included in one chip, the former has a higher failure rate than the latter. Make it higher than stuff. The present embodiment can also be applied to a case where DRAMs and logic circuits with different processes are mixedly mounted, or a case where blocks with different pattern miniaturization rates are mounted together.
[0023]
Further, when a block with a known failure detection rate is included in one chip of an integrated circuit, or when a block with a known failure detection rate is newly added to form one chip, re-verification by the failure detection device 511 in FIG. Can be omitted, and the detection rates obtained for each block in processing 512 can be tabulated to derive the failure detection rate for the last chip. Thereby, useless processing can be omitted and the failure detection rate can be calculated efficiently.
[0024]
【The invention's effect】
As described above, according to the present invention, by calculating a new failure detection rate according to the physical failure occurrence rate, it is possible to perform highly accurate and highly efficient inspection and contribute to the reduction of failures. it can. This is particularly effective when a plurality of functional cores having different mask pattern layout densities are integrated into one chip, or when a plurality of functional cores having different process densities are integrated into one chip.
[Brief description of the drawings]
FIG. 1 is a diagram schematically illustrating the distribution of a mask pattern of an integrated circuit to which a failure verification method according to the present invention is applied. FIG. 2 is a graph showing the relationship between mask pattern density and failure rate. FIG. 4 is a flow chart schematically illustrating a mask pattern density for each block of an integrated circuit to which the failure verification method according to the second embodiment of the present invention is applied. FIG. 5 is a flowchart of a failure verification method according to the second embodiment of the present invention.
301, 505 Failure detection device 303, 503 Parameter extraction means 305, 505, 511 Failure detection rate calculation means

Claims (1)

A circuit included in one chip of an integrated circuit is divided into a plurality of blocks in units of functions, and the mask pattern density obtained by extracting the mask pattern density from the floor plan or layout information when the mask pattern is created for each block. calculating a weight of a failure of each of the blocks from the density and the number of failures each block, calculates the sampling rate in each block according to the weight of the failure of each block was determined for a block of their respective sampling fault simulator performs fault simulation of random sampling with the rate, last fault simulation method to that current product circuit calculates the results of the one-chip by summing a fault simulation results for each block.

Images