JP3876870B2 - ELECTRO-OPTICAL DEVICE, ITS DRIVE CIRCUIT, ELEMENT DRIVE DEVICE, AND ELECTRONIC DEVICE - Google Patents

Description

  The present invention relates to an element driving apparatus that drives a plurality of driven elements, and more particularly, to an electro-optical apparatus that uses an electro-optical element that converts an electrical action into an optical action as the driven element. The present invention also relates to an electronic device using an element driving device and an electro-optical device.

  As display devices for various electronic devices such as mobile phones and PDAs (Personal Digital Assistants), devices using electro-optic elements that convert electrical action into optical action have been proposed. Typical examples of this type of display device are an organic EL display device using an organic EL as an electro-optical element and a liquid crystal display device using a liquid crystal as an electro-optical element.

These display devices include a pixel circuit for each pixel that is a minimum unit of display. This pixel circuit is a circuit for controlling the current or voltage supplied to the electro-optical element. Each pixel circuit includes a drive element formed on a silicon substrate, as disclosed in Patent Document 1.
JP 9-146477 A (paragraph 0013 and paragraph 0014)

  In order to improve display quality in this type of display device, it is desirable that the electrical characteristics of the pixel circuit be uniform across all pixels. However, low-temperature polysilicon is likely to vary in characteristics during recrystallization, and crystal defects may occur. For this reason, in a display device using thin film transistors made of low-temperature polysilicon, it has been extremely difficult to make the electrical characteristics of the pixel circuit uniform over all pixels. In particular, when the number of pixels is increased to increase the definition of the display image or to increase the screen size, the possibility of variations in the characteristics of each pixel circuit is further increased, and the problem of deterioration in display quality becomes even more pronounced.

  The present invention has been made in view of such circumstances, and an object thereof is to suppress variations in characteristics of active elements in an apparatus for driving driven elements such as electro-optical elements.

  In order to solve the above problems, an electro-optical device according to the present invention is provided for each of a plurality of electro-optical elements driven by a driving current specified by a data signal and one or a plurality of electro-optical elements, A plurality of data supply circuits including a first data supply circuit and a second data supply circuit, a reference current supply circuit that generates a reference current based on a reference current, and a reference current generated by the reference current supply circuit A plurality of data supply circuits each including a data signal output circuit that outputs a current value corresponding to the data signal based on the reference current supply circuit of the first data supply circuit. The reference current used to generate the reference current is output to the second data supply circuit, while the reference current supply circuit of the second data supply circuit is supplied from the first data supply circuit. It is to generate the reference current based on reference current was.

  In general, in an electro-optical device having a plurality of data supply circuits each outputting a data signal, a data signal is generated based on a reference current generated by each data supply circuit. However, under this configuration, if the characteristics of the active elements constituting each data supply circuit vary, the current value of the reference current may be different for each data supply circuit. In this case, since the current value of the data signal generated based on the reference current varies, the actual drive current differs for each data supply circuit even if an equal drive current is supplied to each electro-optic element. There was a problem that. For example, when an electro-optical device is used as a display device, color unevenness of a display image may occur due to variations in drive current.

  In order to solve this problem, in the electro-optical device according to the present invention, the reference current used in the reference current supply circuit of the first data supply circuit is output to the second data supply circuit, and the reference of the second data supply circuit The current supply circuit generates a reference current based on the reference current supplied from the first data supply circuit. That is, a data signal is generated based on a common reference current in the first data supply circuit and the second data supply circuit. Therefore, an error in current value is reduced between the data signal output from the first data supply circuit and the data signal output from the second data supply circuit.

  In a preferred aspect of the present invention, the reference current output from the first data supply circuit is supplied to each of the plurality of second data supply circuits in a time division manner. According to this aspect, the reference current used in the plurality of second data supply circuits is equal to the reference current used in the first data supply circuit.

  In this aspect, a configuration is also employed in which the reference current output from the first data supply circuit is supplied to each second data supply circuit via a current supply line having a common part for the plurality of second data supply circuits. Can be done. According to this configuration, since the common wiring is used for the plurality of second data supply circuits, the number of wirings is compared with the configuration in which the first data supply circuit and each of the plurality of second data supply circuits are individually connected. Is reduced.

  In another aspect, each of the plurality of data supply circuits includes a control circuit that switches whether to supply the reference current to the reference current supply circuit of the data supply circuit. According to this aspect, the reference current can be supplied to the reference current supply circuit of each data supply circuit at an arbitrary timing defined by the control circuit. In this aspect, the control circuit of each second data supply circuit switches whether the reference current is supplied to the reference current supply circuit based on the enable signal supplied from the control circuit of the preceding data supply circuit, and A configuration in which an enable signal is output to the control circuit of the data supply circuit at the next stage may be employed. For example, the control circuits of the respective second data supply circuits are cascade-connected (cascade connection). According to this configuration, the reference current is sequentially supplied to the reference current supply circuit of each second data supply circuit according to the enable signal.

  In a preferred aspect of the present invention, each data supply circuit includes a holding circuit that holds a reference current, and the reference current supply circuit of each data supply circuit generates a reference current based on the reference current held in the holding circuit. To do. In this aspect, since each data supply circuit includes a holding circuit, the reference current supply circuit can generate a reference current corresponding to the reference current at any time and output it to the data signal output circuit.

  By the way, if the period in which the data signal is output and the period in which the reference current is supplied to the reference current supply circuit overlap, the influence of the power supply noise accompanying the output of the data signal is given to the reference current, An error may occur in the current value. Therefore, in a desirable mode of the present invention, the reference current is supplied to the reference current supply circuit of each data supply circuit during a period other than the period during which the data signal output circuit of the data supply circuit outputs the data signal. This avoids an error in the current value of the reference current.

  In a more preferred aspect, the configuration of the first data supply circuit and the configuration of the second data supply circuit are the same. According to this aspect, it is not necessary to distinguish between the first data supply circuit and the second data supply circuit when arranging the data supply circuit. Therefore, compared to the case where the first data supply circuit and the second data supply circuit are configured separately, the production efficiency is increased and the manufacturing cost is reduced.

  Furthermore, in a preferred aspect of the present invention, an element driving IC chip having a plurality of unit circuits for supplying a driving current corresponding to the data signal to the electro-optical element is provided, and the data signal output circuit of each data supply circuit includes: The generated data signal is output to the unit circuit of the element driving IC chip. According to this aspect, since the unit circuit for driving the electro-optical element is included in the IC chip, variation in the characteristics of the unit circuit can be suppressed.

  The second feature of the present invention is applied to various devices including a plurality of driven elements. That is, an element driving device according to the present invention includes a plurality of driven elements each driven by a driving current specified by a data signal, and a first data supply circuit provided for each one or a plurality of driven elements. A plurality of data supply circuits including a second data supply circuit, the reference current supply circuit generating a reference current based on a reference current, and a data signal based on the reference current generated by the reference current supply circuit A plurality of data supply circuits each including a data signal output circuit for outputting a current value to be output, and the first data supply circuit is configured so that the reference current supply circuit of the first data supply circuit generates a reference current. Is output to a second data supply circuit other than the first data supply circuit, while the reference current supply circuit of the second data supply circuit is supplied from the first data supply circuit. Generating a reference current based on reference current that is. This element driving device also provides the same effect as the electro-optical device according to the second feature of the present invention.

  An electronic apparatus according to an aspect of the invention includes an electro-optical device having the characteristics described above. According to this electronic apparatus, variations in characteristics of active elements in the electro-optical device can be suppressed. In particular, in an electronic apparatus in which an electro-optical device is used as a display device, the display quality is maintained at a high level.

  As described above, according to the present invention, variations in characteristics of active elements are suppressed in a circuit that drives driven elements such as electro-optical elements.

    Embodiments of the present invention will be described below with reference to the drawings. The form shown below shows one mode of the present invention, does not limit the present invention, and can be arbitrarily changed within the scope of the present invention. Further, in the respective drawings shown below, the dimensions and ratios of the respective constituent elements are appropriately changed from the actual ones in order to make the respective constituent elements large enough to be recognized on the drawings.

<A: Configuration of electro-optical device>
First, a mode in which the electro-optical device according to the present invention is applied as a device for displaying an image will be described. FIG. 1 is a perspective view illustrating a configuration of an electro-optical device according to an embodiment of the invention. As shown in the figure, the electro-optical device D includes a support substrate 6, an organic EL layer 1, a wiring formation layer 2, and an electronic component layer 3. The support substrate 6 is a plate-like or film-like member made of glass, plastic, metal, ceramic, or the like. The electronic component layer 3 is provided on one surface of the support substrate 6. The wiring formation layer 2 is provided on the opposite side of the support substrate 6 as viewed from the electronic component layer 3, and the organic EL layer 1 is provided on the opposite side of the support substrate 6 as viewed from the wiring formation layer 2.

The organic EL layer 1 includes a large number of organic EL elements 10 as electro-optical elements.
These organic EL elements 10 are arranged in a matrix over the row direction (X direction) and the column direction (Y direction). Each organic EL element 10 is an element (driven element) that is driven by supplying current and emits light by this. The light emitted from each organic EL element 10 is emitted upward in FIG. 1 (that is, the direction opposite to the support substrate 6). In the present embodiment, it is assumed that m organic EL elements 10 are arranged in the column direction and n organic EL elements 10 are arranged in the row direction. Therefore, the total number of pixels is “m × n”.

  The electronic component layer 3 includes a large number of electronic components for driving each organic EL element 10. Specifically, various types such as semiconductor integrated circuits (IC chips) using CMOS (Complementary Metal-Oxide Semiconductor) or bipolar transistors, passive elements such as resistors or capacitors, TFT chips, or plate-shaped paper batteries. These electronic components are included in the electronic component layer 3. As shown in FIG. 1, the electronic component layer 3 in this embodiment includes a control IC chip 31, a plurality of scanning IC chips 33, a plurality of column data conversion IC chips 35, and a plurality of pixel driving elements. An IC chip 37 is included as an electronic component.

  On the other hand, the wiring formation layer 2 is located between the electronic component layer 3 and the organic EL layer 1. The wiring formation layer 2 includes a large number of wirings. Specifically, the wiring formation layer 2 has wiring for connecting electronic components included in the electronic component layer 3. As shown in FIG. 1, the wiring formation layer 2 includes a plurality of scan control line groups YL and a plurality of data lines DL. Each scanning control line group YL is a wiring that electrically connects each scanning IC chip 33 and a plurality of pixel driving IC chips 37. On the other hand, each data line is a wiring that electrically connects each column data conversion IC chip 35 and a plurality of pixel driving IC chips 37. Further, the wiring formation layer 2 includes a wiring that connects the electronic component included in the electronic component layer 3 and the organic EL element 10 included in the organic EL layer 1. For example, the wiring formation layer 2 includes a wiring (not shown in FIG. 1) that electrically connects one pixel driving IC chip 37 and the plurality of organic EL elements 10.

  Next, a specific configuration of the electronic component layer 3 will be described with reference to FIG. As shown in the figure, the plurality of pixel driving IC chips 37 are arranged in a matrix in the row direction (X direction) and the column direction (Y direction). Each pixel driving IC chip 37 is provided for each of a predetermined number of organic EL elements 10 among a large number of organic EL elements 10 included in the organic EL layer 1. The correspondence relationship between the pixel driving IC chip 37 and the organic EL element 10 is as follows.

  In the present embodiment, a total of “m × n” organic EL elements 10 included in the organic EL layer 1 are divided into a plurality of groups (hereinafter referred to as “element groups”). Specifically, as shown in FIG. 3, n organic EL elements 10 arranged in the row direction are divided into q pieces, and m organic EL elements 10 arranged in the column direction are divided into p pieces. Thus, “p × q” organic EL elements 10 belonging to one region form one element group. One pixel driving IC chip 37 is assigned to each element group. That is, as shown in FIG. 3, each pixel driving IC chip 37 is arranged so as to face “p × q” organic EL elements 10 belonging to one element group, and these organic EL elements 10. Is responsible for driving.

  As shown in FIG. 2, the plurality of scanning IC chips 33 are arranged along the one or two edges of the support substrate 6 in the column direction. Each scanning IC chip 33 has a circuit for sequentially selecting an IC chip that should drive the organic EL element 10 among the plurality of pixel driving IC chips 37. On the other hand, the plurality of column data conversion IC chips 35 are arranged along the other edge of the support substrate 6 in the row direction. Each column data conversion IC chip 35 controls a current flowing through each organic EL element 10 based on data representing an image (hereinafter referred to as “image data”) Xd. The image data Xd is data that designates the luminance (gradation) of each organic EL element 10.

  On the other hand, the control IC chip 31 is arranged at a portion where a row of the plurality of scanning IC chips 33 and a row of the plurality of column data conversion IC chips 35 intersect (that is, a corner portion of the support substrate 6). The control IC chip 31 comprehensively controls each scanning IC chip 33 and each column data conversion IC chip 35. Specifically, the control IC chip 31 is connected to an external device (not shown) such as a computer system, and from this external device, a control signal (for example, for defining the timing of the image data Xd and the display operation) Clock signal). The control IC chip 31 includes a display memory 31a. The display memory 31a is means for temporarily storing image data Xd supplied from an external device.

  Then, the control IC chip 31 is supplied with signals for selecting a plurality of scanning IC chips 33 one by one (a reset signal RSET, a clock signal YSCL, and a chip selection clock signal YECL described later) from an external device. These signals are generated based on the control signals, and these signals are supplied to each scanning IC chip 33 (see FIG. 5). Further, the control IC chip 31 supplies the image data Xd stored in the display memory 31a to each column data conversion IC chip 35 (see FIG. 9). Further, the control IC chip 31 generates a forced off signal Doff for forcibly stopping the operation of each pixel driving IC chip 37, and this signal is transmitted to each pixel via the wiring included in the wiring forming layer 2. Output to the driving IC chip 37.

  Next, the configuration and operation of each of the pixel driving IC chip 37, the scanning IC chip 33, and the column data conversion IC chip 35 will be described. Hereinafter, the configuration and operation of the column data conversion IC chip 35 will be described after the configuration and operation of the pixel driving IC chip 37 and the scanning IC chip 33 are described.

[Configuration of Pixel Driving IC Chip 37]
Each pixel driving IC chip 37 includes a circuit for driving the plurality of organic EL elements 10 assigned thereto. More specifically, as shown in FIG. 4, each pixel driving IC chip 37 includes a pixel decoder 371, a pixel counter 374, and a plurality of pixel circuits 377. Each pixel circuit 377 is arranged in a matrix so as to correspond to each of the plurality of organic EL elements 10 belonging to one element group. Therefore, each pixel driving IC chip 37 includes a total of “p × q” pixel circuits 377. Each pixel circuit 377 is a circuit for driving one organic EL element 10. Accordingly, the “p × q” organic EL elements 10 included in the organic EL layer 1 are driven by one pixel driving IC chip 37.

  As shown in FIG. 4, q pixel circuits 377 arranged in the row direction include one word line WLi (i is an integer satisfying 1 ≦ i ≦ m), one holding control signal line HLi, and 1 The light emission control signal lines GCLi are connected to each other. One end of each word line WLi, each holding control signal line HLi, and each light emission control signal line GCLi is connected to a pixel decoder 371. With this configuration, the q pixel circuits 377 arranged in the row direction have a selection signal XWi via a word line WLi, a holding control signal XHi via a holding signal line HLi, and a light emission control signal line GCLi. The light emission control signal XGCi is supplied from the pixel decoder 371, respectively. On the other hand, the p pixel circuits 377 arranged in the column direction are connected to the column data conversion IC chip 35 via one data line DLj (j is an integer satisfying 1 ≦ j ≦ n).

Further, all the pixel circuits 377 included in one pixel driving IC chip 37 are connected to the pixel decoder 371 via a common test signal line TSL.
With this configuration, each pixel circuit 377 is simultaneously supplied with the test signal TS from the pixel decoder 371 via the test signal line TSL. As a result, the operation test is performed on all the pixel circuits 377 simultaneously.

[Configuration of Scanning IC Chip 33]
Next, a specific configuration of the scanning IC chip 33 will be described with reference to FIG. Hereinafter, for convenience of explanation, a group composed of a plurality (“n / q”) of pixel driving IC chips 37 arranged in the row direction is referred to as a “pixel driving IC chip group”.

  As shown in FIG. 5, in this embodiment, one scanning IC chip 33 is provided for every two (that is, two rows) pixel driving IC chip groups. Each scanning IC chip 33 controls the operation of a plurality (“2n / q”) of pixel driving IC chips 37 belonging to two pixel driving IC chip groups. Hereinafter, for convenience of description, the number of scanning IC chips 33 is represented as “r (= m / 2p)”. One pixel driving IC chip group of the two pixel driving IC chip groups corresponding to one scanning IC chip 33 is referred to as a “first pixel driving IC chip group 370a”, and the other The pixel driving IC chip group is referred to as a “second pixel driving IC chip group 370b”.

  Each scanning IC chip 33 is driven by two pixels assigned to the scanning IC chip 33 via a scanning control line group YLk (k is an integer satisfying 1 ≦ k ≦ r) included in the wiring formation layer 2. Connected to the IC chip 37. Each scanning control line group YLk includes a first local clock signal line LCak, a second local clock signal line LCbk, and a local reset signal line LRS. More specifically, each scanning IC chip 33 is connected to a plurality of pixel driving IC chips 37 belonging to the first pixel driving IC chip group 370a via the first local clock signal line LCak. Yes. Similarly, each scanning IC chip 33 is connected to a plurality of pixel driving IC chips 37 belonging to the second pixel driving IC chip group 370b via the second local clock signal line LCbk. Two adjacent scanning IC chips 33 are electrically connected by wiring included in the wiring forming layer 2.

  Here, FIG. 6 is a timing chart showing waveforms of signals related to scanning of each pixel circuit 377. The reset signal RSET, the clock signal YSCL, and the chip selection clock signal EYCL shown in the figure are signals supplied from the control IC chip 31 to each scanning IC chip 33. Among these, the reset signal RSET is a signal for defining a time length of a period required to scan all “m × n” organic EL elements 10 (hereinafter referred to as “data writing period”). It rises to H level at the start of the data writing period. On the other hand, the clock signal YSCL is a signal having a period corresponding to the time length of one horizontal scanning period. This horizontal scanning period corresponds to a period in which n pixel circuits 377 belonging to one row are simultaneously selected. The chip selection clock signal EYCL is a signal for selecting the scanning IC chip 33 that should actually control the pixel driving IC chip 37 among the plurality of scanning IC chips 33. Therefore, the chip selection clock signal EYCL rises to H level “r” times corresponding to the number of scanning line IC chips in one data writing period.

  Each scanning IC chip 33 sequentially outputs a first local clock signal SCKak and a second local clock signal SCKbk when selected by the chip selection clock signal EYCL. The first local clock signal SCKak and the second local clock signal SCKbk are clock signals for selecting a plurality of pixel circuits 377 belonging to each pixel driving IC chip group for each row.

  More specifically, as shown in FIG. 6, the kth scanning IC chip 33 first has a plurality of pixel driving IC chips 37 belonging to the first pixel driving IC chip group 370a. The first local clock signal SCKak is output. The first local clock signal SCKak is supplied with the clock signal YSCL over a period corresponding to “p” horizontal scanning periods, which is the number of pixel circuits 377 arranged in the column direction in the first pixel driving IC chip group 370a. It is a signal whose level varies in the same cycle. When the selection of the pixel circuits 377 for p rows based on the first local clock signal SCKak is completed, the scanning IC chip 33 selected by the chip selection clock signal EYCL completes the second pixel driving IC chip group 370b. The second local clock signal SCKbk is output to the plurality of pixel driving IC chips 37 belonging to. The second local clock signal SCKbk is supplied to the clock signal YSCL over a period corresponding to “p” horizontal scanning periods, which is the number of pixel circuits 377 arranged in the column direction in the second pixel driving IC chip group 370b. It is a signal whose level varies in the same cycle. The first local clock signal SCKak and the second local clock signal SCKbk are transmitted via the first local clock signal line LCak and the second local clock signal line LCbk, respectively.

  On the other hand, when the selection of the pixel circuits 377 for p rows based on the second local clock signal SCKbk is completed, each scanning IC chip 33 outputs to the scanning IC chip 33 at the next stage as shown in FIG. Inverted enable signal EOk is inverted to H level. The enable signal EOk is a signal for notifying the next-stage scanning IC chip 33 that the selection of the pixel driving IC chip group for two rows by the scanning IC chip 33 has been completed. The (k + 1) -th scanning IC chip 33 to which the H level enable signal EOk is supplied receives the first local clock signal SCKak + 1 and the second local clock signal SCKbk + 1 in the same procedure as described above. Output.

[Configuration of Pixel Circuit 377]
Next, an electrical configuration of the pixel circuit 377 serving as a unit circuit will be described with reference to FIG. FIG. 7 shows one pixel circuit 377 located in the i-th row and the j-th column. This configuration is common to all the pixel circuits 377.

  The pixel circuit 377 includes a plurality of MOS transistors and one capacitor C0. Specifically, the pixel circuit 377 includes a pair of switching transistors Q1a and Q1b, a pair of reading transistors Q2a and Q2b, a capacitor C0, an issue control transistor Q3, test transistors Q8a and Q8b, an analog And a memory portion 377a. Of these, transistors Q1a, Q1b, Q2a, Q2b and Q3 are p-channel MOS transistors, and transistors Q8a and Q8b are n-channel MOS transistors. The transistor Q2b is a driving transistor for supplying a constant current to the organic EL element 10, and the transistor Q3 is a transistor for controlling conduction / non-conduction of this constant current.

  Transistor Q1a is connected to data line DLj and transistor Q1b, and its gate terminal is connected to word line WLi. The transistor Q1b is connected to one end of the capacitor C0 and the transistor Q1a, and its gate terminal is connected to the word line WLi. On the other hand, the other end of the capacitor C0 is connected to the power supply line L1. A power supply voltage VDD is applied to the power supply line L1.

Transistors Q2a and Q2b form a current mirror circuit. Specifically, the gate terminals of the transistors Q2a and Q2b are connected to one end of the capacitor C0. One transistor Q2a is connected to the transistor Q1a and the power supply line L1. Therefore, when select signal XWi supplied to word line WLi transitions to the L level, transistors Q1a and Q1b are both turned on. Thus, when the transistor Q1b is turned on, the transistor Q2b functions as a diode in which the gate terminal and the drain terminal are connected. Therefore, a current corresponding to the data signal Dj of the data line DLj flows through a path of the power supply line L1, the transistor Q2a, the transistor Q1a, and the data line DLj, and a charge corresponding to the gate voltage of the transistor Q2a is accumulated in the capacitor C0.
The other transistor Q2b is connected to the source terminal of the transistor Q3 and the power supply line L1. The transistor Q2b forms a current mirror circuit with the transistor Q2a, and allows the electric charge stored in the capacitor C0, that is, the current corresponding to the gate voltage of the transistor Q2b to flow through the transistor Q3.

The gate terminal of the transistor Q3 is connected to the light emission control signal line GCLi.
Further, the drain terminal of the transistor Q3 is connected to the organic EL element 10 via a wiring included in the wiring forming layer 2. Under this configuration, when the light emission control signal XGCi transitions to the L level, the transistor Q3 is turned on. At this time, the drive current Iel corresponding to the gate voltage of the transistor Q2b is supplied to the organic EL element 10 via the transistors Q2b and Q3. The organic EL element 10 emits light by supplying the drive current Iel. In the present embodiment, p-type transistors are used as the transistors Q2a, Q2b, and Q3. These transistors are appropriately n according to the connection relationship with the organic EL element 10 and the power supply line L1. It can be changed to a type transistor.

  On the other hand, the analog memory unit 377a is a circuit that keeps the electric charge stored in the capacitor C0 constant. Specifically, the analog memory unit 377a includes transistors Q4a, Q4b, Q5, Q6, and Q7. Of these, transistors Q4a and Q4b are n-channel MOS transistors, and transistors Q5, Q6 and Q7 are p-channel MOS transistors. Transistors Q4a and Q4b form a current mirror circuit. Similarly, transistors Q5 and Q6 form a current mirror circuit.

  The transistor Q5 is connected to the power supply line L1 and the transistor Q4a, and its gate terminal is connected to one end of the capacitor C0. The transistor Q6 is connected to the power supply line L1 and the transistor Q4b, and its gate terminal is connected to the transistor Q7. The transistor Q7 is connected to one end of the capacitor C0 and the transistor Q6, and its gate terminal is connected to the holding signal line HLi. Therefore, the transistor Q7 is turned on when the holding signal XHi becomes L level.

  On the other hand, the transistor Q4a is connected to the transistor Q5 and the ground line, and its gate terminal is connected to the transistor Q5. The transistor Q4b is connected to the transistor Q6 and the ground line, and its gate terminal is connected to the gate terminals of the transistor Q5 and the transistor Q4a.

  Under this configuration, the analog memory unit 377a operates as follows. That is, when charge corresponding to the data signal is accumulated in capacitor C0, a current corresponding to the gate voltage of transistor Q2b flows from transistor Q5 to transistor Q4a. Here, since the transistors Q4a and Q4b constitute a current mirror circuit having the same magnification, a current equal to the current flowing through the transistor Q4a flows through the transistor Q4b, and further, the current flows through the transistor Q6. When the transistor Q7 is turned on in this state, the gate voltage of the transistor Q6 is fed back to the capacitor C0 via the transistor Q7. Thereby, the electric charge stored in the capacitor C0 is kept constant. In other embodiments, a nonvolatile memory circuit may be employed instead of the analog memory unit 377a. The analog memory portion 377a is an effective circuit for quickly restarting the display once turned off for the purpose of reducing the power consumption or the hot start of the program, but is not essential to the present invention.

  Next, the pixel counter 374 and the pixel decoder 371 included in the pixel driving IC chip 37 will be described. The pixel counter 374 shown in FIG. 4 is means for sequentially specifying the pixel circuits 377 in each row included in one pixel driving IC chip 37 as selection targets. The pixel counter 374 is connected to the local reset signal line LRS and the first local clock signal line LCak or the second local clock signal line LCbk.

More specifically, the pixel counter 374 increases the count value by “1” each time the first local clock signal SCKak or the second local clock signal SCKbk supplied from the scanning IC chip 33 rises to the H level. Further, the pixel counter 374 resets the count value to “0” every time the local reset signal RS supplied from the scanning IC chip 33 rises to the H level.
Therefore, the count value by the pixel counter 374 can increase from “0” by “1” every horizontal scanning period to a value of “p” in one data writing period. The count value by the pixel counter 374 is output to the pixel decoder 371.

  The pixel decoder 371 is means for sequentially selecting the pixel circuits 377 in each row included in one pixel driving IC chip 37. The pixel decoder 371 is connected to the first local clock signal line LCak or the second local clock signal line LCbk. Then, the pixel decoder 371 selects a plurality of (q) pixel circuits 377 belonging to the row corresponding to the count value by the pixel counter 374 at a time. That is, the pixel decoder 371 controls the levels of the selection signal XWi, the holding control signal XHi, and the light emission control signal XGCi as shown below.

  As shown in FIG. 8, the selection signal XWi is a signal that becomes L level in one horizontal scanning period in the data writing period. That is, the selection signal XWi is inverted to the L level with the i-th rising edge of the first local clock signal LCak or the second local clock signal LCbk in the data writing period, and H with the (i + 1) -th rising edge. Invert to level. Therefore, the selection signals XW1, XW2,..., XWp are sequentially inverted to the L level in synchronization with the rising edge of the first local clock signal LCak or the second local clock signal LCbk. The holding control signal XHi is inverted to the H level when a predetermined time has elapsed after the selection signal XWi falls to the L level, and is inverted to the L level when a period corresponding to one horizontal scanning period has elapsed. Further, the light emission control signal XGCi is a signal obtained by inverting the level of the selection signal XWi. Therefore, the light emission control signals XGC1, XGC2,..., XGCp are sequentially inverted to the H level in synchronization with the rise of the first local clock signal LCak or the second local clock signal LCbk.

  On the other hand, as shown in FIG. 7, the gate terminals of the transistors Q8a and Q8b are connected to the test signal line TSL. Among these, the drain terminal of the transistor Q8a is connected to the drain terminal of the transistor Q3. In the mode for testing the operation of the pixel circuit 377 (test mode), the transistor Q3 is turned off in response to the forced-off signal Doff, and the transistor Q8a is turned on when the test signal TS is inverted to H level. . Thereby, the anode layer of the organic EL element 10 is connected to the ground line through the transistor Q8a. The drain terminal of the transistor Q8b is connected to the data line DL. Further, when test signal TS is inverted to H level in the test mode, transistor Q8b is turned on. Thereby, the data line DL is connected to the ground line via the transistor Q8b. At this time, when the transistors Qa1 and Qb1 are turned on, the gate voltage of the transistor Q2a is forced to the ground potential. In this test mode, by setting the selection signal XWi, the data signal Dj, or the holding signal XHi to a predetermined level, the leakage current of the pixel circuit 377, the potential holding property of the capacitor C0, and the like are inspected. In the test mode, the count value of the pixel counter 374 is set to a plurality of numerical values larger than “p”, and a test of contents assigned to each of these numerical values is executed. Note that p-channel transistors can also be employed as the transistors Q8a and Q8b.

  Next, the operation of each pixel circuit 377 will be described. Here, the operation will be described with a particular focus on one pixel circuit 377 located in the i-th row and the j-th column, but this operation is common to all the pixel circuits 377.

  First, when the selection signal XWi supplied from the pixel decoder 371 is inverted to the L level at the start of the horizontal scanning period, the transistors Q1a and Q1b of all the pixel circuits 377 belonging to the i-th row are turned on. As a result, a current corresponding to the data signal Dj flows through the transistor Q2a, and a charge corresponding to the current is stored in the capacitor C0. On the other hand, when the light emission control signal XGCi is inverted to H level at the start of the horizontal scanning period, the transistor Q3 is turned off. Therefore, no current flows through the organic EL element 10 during charging of the capacitor C0. Further, when a predetermined time elapses after the selection signal XWi is inverted to L level, the holding control signal XHi is inverted to H level, and the transistor Q7 is turned off.

  Subsequently, when the selection signal XWi is inverted to H level at the end of the horizontal scanning period, the transistors Q1a and Q1b of all the pixel circuits 377 belonging to the i-th row are turned off. On the other hand, when the light emission control signal XGCi is inverted to L level at the end of the horizontal scanning period, the transistors Q3 of all the pixel circuits 377 belonging to the i-th row are turned on. As a result, the drive current Iel corresponding to the voltage held in the capacitor C0 is supplied to the organic EL element 10 via the transistors Q2b and Q3. As a result, the organic EL element 10 emits light with a luminance corresponding to the magnitude of the drive current Iel.

  Further, when the holding control signal XHi is inverted to the L level at a time delayed by a predetermined time from the end of the horizontal scanning period, the transistors Q7 of all the pixel circuits 377 belonging to the i-th row are turned on. Therefore, the gate voltage of the transistor Q2b is kept constant by the analog memory unit 377a.

  On the other hand, as described above, the forced off signal Doff is supplied from the control IC chip 31 to the pixel decoder 371. When the forced off signal Doff is inverted to H level, the pixel decoder 371 inverts all the emission control signals XGC1, XGC2,..., XGCp to H level. As a result, the transistors Q3 in all the pixel circuits 377 in the pixel driving IC chip 37 are turned off. Accordingly, all the organic EL elements 10 stop emitting light in response to the forced off signal Doff.

[Selection Operation of Pixel Circuit 377]
Next, the selection operation of the pixel circuit 377 executed under the above configuration will be described in detail.

  First, as shown in FIG. 6, the reset signal RSET supplied from the control IC chip 31 to each scanning IC chip 33 is set to the H level over a predetermined period. Each scanning IC chip 33 sets the enable signal EOk supplied to the scanning IC chip 33 at the next stage to the L level in response to the rise of the reset signal RSET. Further, each scanning IC chip 33 inverts the local reset signal RS supplied to the first pixel driving IC chip group 370a and the second pixel driving IC chip group 370b to the H level over a predetermined period. As a result, the pixel counter 374 included in each pixel driving IC chip group resets the count value to “0”.

  On the other hand, when the chip selection clock signal EYCL is inverted to H level at the beginning of the data writing period, the first-stage scanning IC chip 33 is selected. The scanning IC chip 33 outputs a clock pulse of the first local clock signal SCKa 1 based on the clock signal YSCL supplied from the control IC chip 31. The first local clock signal SCKa1 is supplied to the first pixel driving IC chip group 370a via the first local clock signal line LCa1.

  In addition, the pixel counter 374 of the pixel circuit 377 belonging to the first pixel driving IC chip group 370a changes the count value from “0” to “1” triggered by the first rise of the clock pulse in the first local clock signal LCa1. Increase to. On the other hand, the pixel decoder 371 selects the pixel circuit 377 in the first row corresponding to the count value “1” and supplies current corresponding to the data signal Dj to the organic EL element 10 corresponding to these pixel circuits 377. An operation (hereinafter referred to as “selection operation”) is performed.

That is, the pixel decoder 371 inverts the selection signal XW1 corresponding to the count value “1” to the L level over one horizontal scanning period. As a result, the transistors Q1a and Q2a of all the pixel circuits 377 belonging to the first row are turned on. That is, all the pixel circuits 377 belonging to the first row are selected. Thereby, the electric charge according to the current of the data signal Dj is charged in the capacitor C0.
Further, in a period in which the pixel circuits 377 for one row are selected, the pixel decoder 371 sets the holding control signal XH1 to the H level to turn off the transistors and sets the light emission control signal XGC1 to the H level. As a result, the transistor Q3 is turned off.

On the other hand, when one horizontal scanning period elapses after the selection signal is inverted to L level, the pixel decoder 371 inverts the selection signal XW1 to H level. As a result, in all the pixel circuits 377 belonging to the first row, the transistors Q1a and Q1b are turned off. Further, the pixel decoder 371 inverts the holding control signal XH1 to L level at a time slightly delayed from the rising edge of the selection signal XW1. As a result, the transistor Q7 of the pixel circuit 377 belonging to the first row is turned on.
Further, the pixel decoder 371 inverts the light emission control signal XGC1 to L level simultaneously with the rise of the selection signal XW1. As a result, the transistor Q3 of the pixel circuit 377 belonging to the first row is turned on.

  With the above operation, in all the pixel circuits 377 belonging to the first row, a current Iel corresponding to the voltage held in the capacitor C0 flows between the source and drain of the transistor Q2b. Therefore, the organic EL element 10 emits light with luminance (gradation) corresponding to the data signal Dj.

When the selection operation for the pixel circuit 377 in the first row is completed in this way, the pixel counter 374 increases the count value from “1” to “2”. In the second horizontal scanning period, the same selection operation as described above is executed for the pixel circuits 377 in the second row belonging to the first pixel driving IC chip group 370a. Thereafter, the same selection operation is performed up to the pixel circuit 377 in the p-th row belonging to the first pixel driving IC chip group 370a. That is, every time the count value by the pixel counter 374 is incremented by “1” at the start of each horizontal scanning period, the selection operation is performed on the pixel circuits 377 in the row specified by the count value.
More generally, when the count value of the pixel counter 374 is “k”, the pixel circuit 377 in the k-th row belonging to the first pixel driving IC chip group 370a is selected, and these pixel circuits are selected. The organic EL element 10 corresponding to 377 emits light with a luminance corresponding to the data signal Dj.

  Next, when the selection operation is completed for all the pixel circuits 377 for p rows belonging to the first pixel driving IC chip group 370a, the first-stage scanning IC chip 33 is based on the clock signal YSCL. A clock pulse of the second local clock signal SCKb1 is output. The second local clock signal SCKb1 is supplied to the second pixel driving IC chip group 370b via the second local clock signal line LCb1. Then, in each pixel driving IC chip 37 belonging to the second pixel driving IC chip group 370b, the same selection operation as described above for the first pixel driving IC chip group 370a is repeated. That is, each row of the pixel circuits 377 belonging to the second pixel driving IC chip group 370b is selected for each horizontal scanning period, and the organic EL elements 10 corresponding to these pixel circuits 377 have a luminance according to the data signal Dj. Emits light.

  On the other hand, when the selection operation for the pixel circuit 377 in the p-th row belonging to the second pixel driving IC chip group 370b is completed, the first-stage scanning IC chip 33 is changed to the second-stage scanning IC chip. The enable signal EO1 supplied to 33 is inverted to H level. Thus, the first pixel driving IC chip group 370a (third row pixel driving IC chip 37) corresponding to the second-stage scanning IC chip 33, and the second pixel driving IC chip group. The above-described selection operations are sequentially executed for 370b (pixel driving IC chip 37 in the fourth row). Thereafter, similarly, the scanning IC chip 33 is selected by the chip selection clock signal EYCL and the enable signal EO, and the first pixel driving IC chip group 370a corresponding to the selected scanning IC chip 33, and Similar selection operations are sequentially performed on the second pixel driving IC chip group 370b. More generally, when the scanning IC chip 33 at the k-th stage is selected by the chip selection clock signal EYCL and the enable signal EOk-1, first, the first pixel driving IC chip group 370a (the first IC driving group 370a) The selection operation is sequentially performed on the pixel circuits 377 for p rows belonging to the (2k-1) -th row pixel drive IC chip group). When this is completed, p rows corresponding to the second pixel drive IC chip group 370b (the (2k) th pixel drive IC chip group) corresponding to the kth scanning IC chip 33 are obtained. A selection operation is sequentially performed on the pixel circuit 377. As a result of the above operation, an image corresponding to the image data Xd supplied from the external device is displayed.

  According to the scanning IC chip 33 and the pixel driving IC chip 37 according to the present embodiment, the following effects can be obtained.

(1) A pixel counter 374 and a pixel decoder 371 for sequentially selecting each pixel circuit 377 are provided in the pixel driving IC chip 37, and each pixel driving IC chip 37 is for scanning via the scanning control line group YLk. It is connected to the IC chip 33.
Therefore, it is not necessary to provide the scanning control line group YLk for each row of the pixel circuit 377. As a result, the number of scanning control line groups YLk is reduced and the space occupied by the scanning control line groups YLk is reduced as compared with the conventional configuration in which the scanning lines are provided for each row of the pixel circuits 377. On the other hand, the reduction in the number of scanning control line groups YLk means that a wide wiring can be formed in the same space as the conventional configuration. In this case, since the impedance of the wiring is reduced, even if the electro-optical device D has a large screen composed of a large number of pixels, a display device with good display quality and high luminance is realized. Further, since the number of pads for connecting the driving IC chip to the scanning IC chip 33 is reduced, the size of the pixel driving IC chip 37 is reduced.

(2) Since the test of each pixel circuit 377 is executed by the test signal TS, the pad (connection terminal) connected to the organic EL element 10 in the pixel driving IC chip 37 can be reduced. That is, when testing the pixel circuit 377 by bringing the probe needle mechanically into contact with the pad of the pixel driving IC chip 37, the pad of the pixel driving IC chip 37 has a sufficient size for contact with the probe needle. There is a need to. On the other hand, according to the present embodiment, the pixel circuit 377 is tested by supplying the test signal TS, so that the probe needle contacts the pad to be connected to the organic EL element 10 in the pixel driving IC chip 37. There is no need to let them. Therefore, the pad of the pixel driving IC chip 37 can be made sufficiently smaller than the size necessary for contact with the probe needle. As a result, the size of the pixel driving IC chip 37 is reduced, and the number of wirings for connecting the scanning IC chip 33 and each pixel driving IC chip 37 is reduced, so that even higher resolution is realized.

  5 exemplifies the configuration in which one scanning IC chip 33 controls the pixel driving IC chips 37 for two rows, the pixel driving IC chip assigned to one scanning IC chip 33 is illustrated. The number of 37 is not limited to this.

[Configuration of IC chip 35 for column data conversion]
Next, the configuration of each column data conversion IC chip 35 will be described. As shown in FIG. 2, in this embodiment, one column data conversion IC chip 35 is provided for each of a plurality of columns (here, a total of “s” columns) of pixel driving IC chips 37. . Each column data conversion IC chip 35 supplies a data signal Dj to the pixel circuit 377 included in these pixel drive IC chips 37 via the data line DLj.

  As shown in FIG. 9, each column data conversion IC chip 35 includes an enable control circuit 351, a first latch circuit 353, a second latch circuit 354, a D / A conversion circuit 356, and a reference current supply circuit 358. Have. In FIG. 9, only the configuration of the first column data conversion IC chip 35 is shown in detail, but the second and subsequent column data conversion IC chips 35 have the same configuration.

  Each column data conversion IC chip 35 is connected to the control IC chip 31 via a data control line LXD. The data control line LXD includes an enable signal line LXECL, an image data signal line LXd, a clock signal line LXCL, a reference current control line LBP, and a latch pulse signal line LLP.

Among them, the enable signal line LXECL is a wiring for supplying the enable control signal XECL from the control IC chip 31 to the enable control circuit 351 of the first-stage column data conversion IC chip 35. The enable control circuit 351 generates an enable signal EN based on the enable control signal XECL.
This enable signal EN indicates whether the operations of the first latch circuit 353 and the reference current supply circuit 358 are permitted or not permitted. The enable signal EN generated by the enable control circuit 351 is output to the input terminals of the AND gates 353a, 353b, and 359.

  The enable control circuit 351 of each column data conversion IC chip 35 is cascade-connected to the enable control circuit 351 of the column data conversion IC chip 35 at the next stage. With this configuration, the enable control circuits 351 of the second and subsequent column data conversion IC chips 35 receive the enable signal EN from the enable control circuit 351 of the preceding column data conversion IC chip 35, respectively. An enable signal EN is generated based on the signal.

  The first latch circuit 353 is connected to the output terminal of the AND gate 353a and the output terminal of the AND gate 353b. Among these, the image data Xd is input from the control IC chip 31 to the input terminal of the AND gate 353a via the image data signal line LXd. That is, the AND gate 353a outputs a logical product of the enable signal EN and the image data Xd to the first latch circuit 353. In other words, the image data Xd output from the control IC chip 31 is supplied to the first latch circuit 353 via the AND gate 353a only during the period when the enable signal EN is at the H level. On the other hand, the clock signal XCL is input from the control IC chip 31 to the input terminal of the AND gate 353b via the clock signal line LXCL. That is, the AND gate 353b outputs a logical product of the enable signal EN and the clock signal XCL to the first latch circuit 353. In other words, the clock signal XCL output from the control IC chip 31 is supplied to the first latch circuit 353 via the AND gate 353b only during a period when the enable signal EN is at the H level. The clock signal XCL is a so-called dot clock. With the above configuration, the first latch circuit 353 sequentially holds the image data Xd in synchronization with the clock signal XCL during the period when the enable signal EN is at the H level. On the other hand, the enable signal EN is inverted to the L level when the image data Xd for the “s” pixel circuits 377 is taken into the first latch circuit 353. Therefore, the first latch circuit 353 takes in the image data Xd for “s” pixel circuits 377.

  The output terminal of the first latch circuit 353 is connected to the input terminal of the second latch circuit 354. On the other hand, the output terminal of the second latch circuit 354 is connected to the input terminal of the D / A conversion circuit 356. The latch pulse signal LP is input from the control IC chip 31 to the second latch circuit 354 via the latch pulse signal line LLP. The latch pulse signal LP is a signal that is inverted to H level at the start of the horizontal scanning period. The second latch circuit 354 simultaneously captures the image data Xd of “s” pixel circuits 377 held in the first latch circuit 353 at the rising edge of the latch pulse signal LP, and the captured image data Xd is D. / A conversion circuit 356. That is, serial / parallel conversion is performed by the first latch circuit 353 and the second latch circuit 354.

  The D / A conversion circuit 356 is a circuit that outputs a current corresponding to the image data output from the second latch circuit 354 as a data signal Dj to “s” data lines. That is, the D / A conversion circuit 356 converts the image data Xd output from the second latch circuit 354 into a data signal Dj that is an analog signal, and outputs the data signal Dj to the data line DLj. The D / A conversion circuit 356 in the present embodiment converts the image data Xd into a data signal Dj based on the reference current Ir supplied from the reference current supply circuit 358.

  The reference current supply circuit 358 is connected to the output terminal of the AND gate 359 as shown in FIG. A reference current write signal BP is input from the control IC chip 31 to the input terminal of the AND gate 359 via the reference current control line LBP. The AND gate 359 calculates the logical product of the enable signal EN and the reference current write signal BP, and outputs the result as a control pulse signal CP. In other words, the reference current write signal BP output from the control IC chip 31 is supplied to the reference current supply circuit 358 as the control pulse signal CP via the AND gate 359 only during the period when the enable signal EN is at the H level. Is done. This reference current write signal BP is a signal for instructing the reference current supply circuit 358 to generate the reference current Ir. In the present embodiment, whether or not the first latch circuit 353 accepts the image data Xd and whether or not the reference current supply circuit 358 generates the reference current Ir is controlled by a common enable signal EN. . However, a configuration in which whether these operations are permitted or not is controlled by a separate signal may be employed.

  Next, FIG. 10 is a diagram showing a configuration of the reference current supply circuit 358 in each column data conversion IC chip 35. In the figure, only the reference current supply circuit 358 included in the first-stage and second-stage column data conversion IC chips 35 is shown, but the reference of other column data conversion IC chips 35 is shown. The current supply circuit 358 has the same configuration. In the following, the reference current supply circuit 358 included in the first-stage column data conversion IC chip 35 is simply referred to as “first-stage reference current supply circuit 358”, and a plurality of second-stage and subsequent stages. Each of the reference current supply circuits 358 included in the column data conversion IC chip 35 is simply referred to as “second-stage and subsequent reference current supply circuits 358”.

  As shown in FIG. 10, each reference current supply circuit 358 includes a constant current source 3581, a capacitor C1, and first to fourth switch means SW1 to SW4. Each reference current supply circuit 358 includes transistors Tsw, T1, T2, T3, and Tm. Of these, the transistors Tsw, T1, T2, and Tm are n-channel FETs (Field Effect Transistors). On the other hand, the transistor T3 is a p-channel FET.

  The configuration of the reference current supply circuit 358 in the second and subsequent stages is the same as the configuration of the reference current supply circuit 358 in the first stage. However, the connection state of the fourth switch means SW4 is different between the reference current supply circuit 358 in the second stage and the reference current supply circuit 358 in the first stage. In other words, in the first-stage reference current supply circuit 358, the high-potential power supply potential (VDD) is applied to the gate terminal of the transistor Tsw and the fourth switch means SW4. Therefore, in the first-stage reference current supply circuit 358, the transistor Tsw is always turned on, while the drain terminal of the transistor Tm and one end of the first switch means SW1 are connected via the fourth switch means SW4. Always connected. On the other hand, in the reference current supply circuit 358 in the second and subsequent stages, the lower power supply potential (ground potential) is applied to the gate terminal of the transistor Tsw and the fourth switch means SW4. Accordingly, in the reference current supply circuit 358 in the second and subsequent stages, the transistor Tsw is always turned off, while the drain terminal of the transistor Tm and one end of the first switch means are always disconnected. Therefore, in the reference current supply circuit 358 in the second and subsequent stages, the constant current source 3581, the transistor T1, and the transistor Tm are not involved in the operation.

  The constant current source 3581 generates a constant current Io and supplies the constant current Io to the drain terminal of the transistor Tsw. The source terminal of the transistor Tsw is connected to the drain terminal of the transistor T1. The transistor T1 is diode-connected, and its source terminal is grounded. The gate terminal of the transistor T1 is connected to the gate terminal of the transistor Tm. Therefore, the transistor T1 and the transistor Tm constitute a current mirror circuit. That is, the reference current Iref corresponding to the constant current Io flowing through the transistor T1 flows through the transistor Tm. The source terminal of the transistor Tm is grounded.

  The drain terminal of the transistor Tm is connected to one end of the first switch means SW1 via the fourth switch means SW4. The other end of the first switch means SW1 is connected to one end of the second switch means SW2 and the drain terminal of the transistor T3. The other end of the second switch means SW2 is connected to the gate terminal of the transistor T3. One end of the capacitor C1 is connected to the gate terminal of the transistor T3. The other end of the capacitor C1 and the source terminal of the transistor T3 are connected to a power supply line.

  On the other hand, the drain terminal of the transistor T3 is connected to one end of the third switch means SW3. The other end of the third switch means SW3 is connected to the drain terminal of the transistor T2. The source terminal of the transistor T2 is grounded.

  Further, the first switch means SW1 and the second switch means SW2 are switched to either the on state or the off state according to the control pulse signal CP (CP1, CP2,...). More specifically, each of the first and second switch means SW1 and SW2 is turned on when the control pulse signal CP is at H level, and is turned off when the control pulse signal CP is at L level.

The third switch means SW3 is switched to either the on state or the off state in accordance with the control inversion pulse signal CSW (CSW1, CSW2,...).
The control inversion pulse signal CSW is a signal that is delayed after the level of the control pulse signal CP is inverted. That is, the control pulse signal CP is input to the gate circuit composed of the delay circuit 3586 and the NOR gate 3585, and this output signal is supplied to the third switch means SW3 as the control inversion pulse signal CSW. More specifically, as shown in FIG. 11, when the control pulse signal CP is at H level, the control inversion pulse signal CSW is at L level. At this time, the third switch means SW3 is turned off. On the other hand, the control inversion pulse signal CSW becomes H level when the control pulse signal CP is slightly delayed from inversion to L level. At this time, the third switch means SW3 is turned on.

  With the configuration described above, when both the enable signal EN and the reference current write signal BP are at H level, the control pulse signal CP is at H level, and both the first and second switch means SW1 and SW2 are turned on. It becomes a state. At this time, in the first-stage current supply circuit 358, a current having a magnitude proportional to the constant current Io generated by the constant current source 3581 flows through the transistor Tm and the first and second switch means SW1 and SW2. The electric charge according to the current is stored in the capacitor C1. On the other hand, since the third switch means SW3 is in the off state, no current flows through the second transistor T2.

  Next, when the control pulse signal CP is inverted to L level, the first and second switch means SW1, SW2 are turned off, and the third switch means SW3 is turned on. As a result, the charge stored in the capacitor C1, that is, the reference current Ir1 corresponding to the gate voltage of the transistor T3 flows through the transistor T3. This reference current Ir1 is supplied to the transistor T2.

  On the other hand, one end of the first switch means SW1 in the first-stage reference current supply circuit 358 is connected to the fourth switch in all the second-stage and subsequent reference current supply circuits 358 via the reference current supply line Lr. Connected to one end of the means SW4. Therefore, when the first and second switch means SW1 and SW2 are turned off in the first-stage reference current supply circuit 358, the reference current Iref is supplied to all the second-stage and subsequent reference current supply circuits 358. It is supplied via the reference current supply line Lr. Then, the electric charge corresponding to the reference current Iref supplied through the reference current supply line Lr is stored in the capacitor C1 of each reference current supply circuit 358 in the second and subsequent stages.

  As described above, in this embodiment, the reference current Iref proportional to the constant current Io output from the constant current source 3581 of one column data conversion IC chip 35 is the reference of the other column data conversion IC chip 35. The current is supplied to the current supply circuit 358. Therefore, the magnitudes of the reference currents Ir used in all the column data conversion IC chips 35 are equal. Instead of the capacitor C1 shown in FIG. 10, other means having a function of holding the reference current Ir (for example, a non-volatile memory having a function equivalent to the capacitor C1) may be employed.

  Next, a specific configuration of the D / A conversion circuit 356 will be described with reference to FIGS. In FIG. 12, the D / A conversion circuit 356 of the first-stage column data conversion IC chip 35 is shown, but the D / A conversion circuits 356 of the other column data conversion IC chips 35 are also the same. It is the composition.

  As shown in FIG. 12, the D / A conversion circuit 356 of each column data conversion IC chip 35 has “s” D corresponding to the number of data lines allocated to the column data conversion IC chip 35. / A converter 356a. The current Ir1 output from the reference current supply circuit 358 is supplied to each of these “s” D / A converters 356a. Each D / A conversion unit 356 a receives image data Xd corresponding to one pixel circuit 377 from the second latch circuit 354. Each D / A converter 356a converts the image data into a data signal Dj based on the current Ir1, and outputs the obtained data signal Dj to the data line XLj. In the present embodiment, the image data Xd is 6-bit data.

  Next, FIG. 13 is a diagram illustrating a configuration of each D / A conversion unit 356a. As shown in the figure, the D / A converter 356a has six transistors Trc1 to Trc6 and six transistors Ts1 to Ts6.

  The gate terminals of the transistors Trc 1 to Trc 6 are connected to the gate terminal of the transistor T 2 in the reference current supply circuit 358. Therefore, each of the transistors Trc1 to Trc6 constitutes a current mirror circuit together with the transistor T2. With this configuration, the transistors Trc1 to Trc6 each function as a constant current source that outputs a predetermined current value. In the present embodiment, each of the transistors Trc1 to Trc6 is set so that the output current ratio (Ia: Ib: Ic: Id: Ie: If) of the transistors Trc1 to Trc6 is 1: 2: 4: 8: 16: 32. The size is selected.

  The drain terminals of the transistors Ts1 to Ts6 are connected to the transistors Trc1 to Trc6, respectively. The source terminals of the transistors Ts1 to Ts6 are connected to one data line XLj. On the other hand, each bit of the image data Xd output from the second latch circuit 354 is supplied to the transistors Ts1 to Ts6, respectively. Specifically, the least significant bit of the image data Xd is supplied to the transistor Ts1, and the most significant bit of the image data Xd is supplied to the transistor Ts6. With this configuration, the transistors Ts1 to Ts6 are switched to either the on state or the off state according to each bit of the image data supplied from the second latch circuit 354.

With the above configuration, currents output from the transistors Trc1 to Trc6 are selectively supplied to the data line XLj according to the states of the transistors Ts1 to Ts6.
As a result, a current corresponding to the contents of the image data Xd is supplied to the data line XLj as the data signal Dj. As is clear from the output current ratio of each of the transistors Trc1 to Trc6 described above, the current value of the data signal Dj can take 64 types of values. Therefore, the luminance of the organic EL element 10 is controlled to 64 gradations according to the 6-bit image data Xd.

[Operation of IC chip 35 for column data conversion]
Next, the supply operation of the data signal Dj executed under the above-described configuration will be described in detail. As described above, each pixel circuit 377 is sequentially selected over one data writing period. The supply of the data signal Dj from the column data conversion IC chip 35 to each pixel circuit 377 is sequentially executed over one frame (vertical scanning period) so as to be synchronized with the scanning of the pixel circuit 377. Further, in the present embodiment, as shown in FIG. 11, the charging of the capacitor C1 in each reference current supply circuit 358 is a period between data writing periods, that is, a period of a part of each frame (hereinafter referred to as “set period”). Are executed sequentially. Note that image display is performed in a period other than a period in which a data signal is supplied to the pixel circuit 377. That is, the image display may be performed both in the set period and in the data writing period.

  First, when the set period starts, both the reference current write signal BP supplied to the first-stage column data conversion IC chip 35 and the enable signal EN generated by the enable control circuit 351 are inverted to H level. To do. As a result, when the control pulse signal CP1 transitions to the H level, the first and second switch means SW1 and SW2 in the first-stage reference current supply circuit 358 are turned on. On the other hand, as shown in FIG. 11, with the level inversion of the control pulse signal CP1, the control inversion pulse signal CSW1 is inverted to the L level. Therefore, the third switch means SW3 in the first-stage reference current supply circuit 358 is turned off. As a result, a charge corresponding to the constant current Io supplied from the constant current source 3581 is stored in the capacitor C1 of the first-stage reference current supply circuit 358.

  Next, as shown in FIG. 11, the control pulse signal CP1 is inverted to the L level. As a result, the first and second switch means SW1 and SW2 in the first-stage reference current supply circuit 358 are turned off. At this time, the control inversion pulse signal CSW1 is inverted to H level. Therefore, the third switch means in the first-stage reference current supply circuit 358 is turned on. As a result, the charging of the capacitor C1 in the first-stage reference current supply circuit 358 is completed.

Subsequently, the reference current write signal BP supplied to the second-stage column data conversion IC chip 35 and the enable signal EN generated by the enable control circuit 351 of the column data conversion IC chip 35 are both included. Invert to H level.
As a result, when the control pulse signal CP2 is inverted to the H level, the first and second switch means SW1 and SW2 in the second-stage reference current supply circuit 358 are turned on. At this time, the control inversion pulse signal CSW2 is inverted to the L level, and the third switch means in the second-stage reference current supply circuit 358 is turned off. As a result, the reference current Iref corresponding to the constant current Io in the first-stage column data conversion IC chip 35 is supplied to the second-stage column data conversion IC chip 35 via the reference current supply line Lr. . Then, a charge corresponding to the reference current Iref is charged in the capacitor C1 of the second-stage column data conversion IC chip 35.

  Next, as shown in FIG. 11, the control pulse signal CP2 is inverted to the L level, and the control inverted pulse signal CSW2 is inverted to the H level. As a result, the first and second switch means SW1 and SW2 in the second-stage reference current supply circuit 358 are turned off, and the third switch means SW3 is turned on. As a result, the charging of the capacitor C1 in the second-stage reference current supply circuit 358 is completed.

  Thereafter, similar operations are performed in the other column data conversion IC chips 35. As a result, at the end of the set period, the charge corresponding to the reference current Iref supplied from the first-stage reference current supply circuit 358 is transferred to the capacitors of all the second-stage and subsequent reference current supply circuits 358. Stored in C1. That is, the reference current Iref supplied from the first-stage reference current supply circuit 358 is sequentially copied to the capacitor C1 of each reference current supply circuit 358 in a time division manner. In the present embodiment, the case where one set period is provided for each frame is illustrated, but a configuration in which one set period is provided for each of a plurality of frames may be employed. Alternatively, a configuration in which the capacitor C1 of each reference current supply circuit 358 is charged in a period between output of the data signal Dj by the D / A conversion circuit 356 (a period corresponding to a return of line sequential scanning) may be employed. That is, one set period may be distributed over a plurality of frames or distributed within one frame period, but charging of the capacitor C1 during the set period is performed during the retrace period. It is desirable to be executed.

  On the other hand, in the data writing period following the set period, the column data conversion IC chip 35 outputs a data signal in synchronization with the scanning of the pixel circuits 377 in each row. That is, in each column data conversion IC chip 35, the data signal Dj is generated using the reference current Ir (Ir1, Ir2,...) Corresponding to the charge of the capacitor C1 of the reference current supply circuit 358 as a reference value. Dj is supplied to the pixel circuit 377 that is currently selected. The operation of scanning the pixel circuit 377 and the operation of the pixel circuit 377 associated therewith are as described above.

  According to the column data conversion IC chip 35 according to the present embodiment, the following effects can be obtained.

(1) In this embodiment, the reference current Iref is supplied from the first-stage reference current supply circuit 358 to all the second-stage and subsequent reference current supply circuits 358.
Each reference current supply circuit 358 supplies a reference current Ir corresponding to the reference current Iref to the D / A conversion circuit 356. According to this configuration, the magnitudes of the reference currents Ir in all the reference current supply circuits 358 are the same. Therefore, an output error of the data signal Dj output from each column data conversion IC chip 35 is suppressed. As a result, it is possible to prevent the occurrence of vertical stripes in the portion corresponding to the boundary of the column data conversion IC chip 35 in the display image.

(2) In the present embodiment, the first-stage column data conversion IC chip 35 and the second-stage and subsequent column data conversion IC chips 35 have the same configuration. Therefore, when manufacturing the electro-optical device D, it is not necessary to distinguish between the first-stage column data conversion IC chip 35 and the second-stage and subsequent column data conversion IC chips 35. Therefore, although the configuration in which the reference current Iref is output from the first-stage column data conversion IC chip 35 to the other column data conversion IC chip 35 is adopted, it is compared with the conventional electro-optical device. Thus, the manufacturing cost does not increase significantly.

  The D / A conversion circuit 356 and the reference current supply circuit 358 may be provided in the pixel driving IC chip 37. With this configuration, the same effect as described above can be obtained.

<B: Laminated structure and manufacturing method of electro-optical device>
Next, a laminated structure of the electro-optical device D according to the present invention and a manufacturing method thereof will be described.
In the following, three types of electro-optical devices D having different manufacturing methods will be exemplified, and a laminated structure and a manufacturing method will be described for each. Hereinafter, when the pixel driving IC chip 37, the control IC chip 31, the scanning IC chip 33, and the column data conversion IC chip 35 are not particularly distinguished, they are collectively referred to as “IC chip 30”. ".

[Laminated structure by the first manufacturing method]
First, the laminated structure of the electro-optical device D obtained by the first manufacturing method will be described with reference to FIG. As shown in the figure, the electronic component layer 3 includes a base layer 301, a metal layer 302, an IC chip 30 and a filling layer 304. The IC chip 30 shown in FIG. 14 is a pixel driving IC chip 37.

  The underlayer 301 is a layer that covers one surface of the support substrate 6 as a whole, and is made of, for example, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The base layer 301 is a layer for preventing impurities eluted from the support substrate 6 from being mixed into electronic components such as the pixel driving IC chip 37.

  The metal layer 302 is a layer provided on the surface of the base layer 301 and is formed of a metal such as copper (Cu) or gold (Au). The metal layer 302 includes a mount portion 302a and an alignment mark 302b. Of these, the mount portion 302 a is a layer for improving the adhesion of the IC chip 30 to the support substrate 6 and blocking light entering the IC substrate 30 from the support substrate 6 side. Therefore, the mount portion 302a is provided so as to overlap with a region where the IC chip 30 is to be disposed. The mounting portion 302a prevents malfunction of the IC chip 30 due to light irradiation. On the other hand, the alignment mark 302b is a mark for adjusting the relative position of the IC chip 30 and the support substrate 6 to an intended position.

  The IC chip 30 has a plurality of pads P which are connection terminals. Each IC chip 30 is arranged on the mount portion 302a with the surface on which the pads P are formed (hereinafter referred to as “pad forming surface”) facing the opposite side to the support substrate 6. A metal layer 30a is formed on the surface of the IC chip 30 opposite to the pad forming surface, that is, on the surface facing the support substrate 6 when mounted on the support substrate 6 (hereinafter referred to as “substrate surface”). Is provided.

  FIG. 15 is a plan view showing a pad forming surface of the pixel driving IC chip 37. As shown in the figure, the plurality of pads P provided on the pixel driving IC chip 37 are classified into first pads P1 and second pads P2 having different sizes. Among these, the second pad P2 is a terminal for connecting the pixel driving IC chip 37 to another IC chip (control IC chip 31, scanning IC chip 33 and column data conversion IC chip 35) or a power supply line. is there. Each second pad P <b> 2 is large enough to mechanically contact the probe needle when inspecting the pixel driving IC chip 37. Specifically, the planar shape of each second pad P2 is a rectangle whose length in the vertical direction and the horizontal direction are both about 70 μm (micrometer) to 100 μm. On the other hand, the first pad P 1 is a terminal for connecting the pixel driving IC chip 37 to the organic EL element 10. Each first pad P1 is smaller than the second pad P2. Specifically, the planar shape of each first pad is a rectangle having a length in the vertical direction and a horizontal direction of about 10 μm to 30 μm.

  Thus, the pixel driving IC chip 37 in this embodiment has two types of pads P having different sizes. Therefore, the area of the pad formation surface in each IC chip 30 can be reduced as compared with the case where all the pads P have the same size as the second pads. In particular, since a large number of pixel driving IC chips 37 are provided for one electro-optical device D, a reduction in the size of each pixel driving IC chip 37 effectively contributes to a reduction in the overall size of the electro-optical device D. Can do. In order to obtain this effect, the area of the first pad is desirably 1/50 to 1/6 of the area of the second pad. The pads of the control IC chip 31, the scanning IC chip 33, and the column data conversion IC chip 35 are the same size as the second pad described above. However, some or all of the pads in these IC chips may be the same size as the first pad described above.

  As shown in FIG. 14, the filling layer 304 is a layer provided in a region between the IC chips 30. That is, the filling layer 304 is provided so as to fill a step between the surface of the support substrate 6 (more specifically, the surface of the base layer 301) and the pad formation surface of the IC chip 30. The filling layer 304 is formed of a material having high heat dissipation. Specifically, the filling layer 304 is made of a metal such as copper (Cu), nickel (Ni), or tin (Sn). As a result, the thermal uniformity of the entire electro-optical device D is improved, and problems caused by heat are eliminated.

Next, the wiring formation layer 2 includes the first insulating layer 41, the first wiring layer 43, the second insulating layer 45, the second wiring layer 47, the anode layer 49, the third insulating layer 50, the bank layer 52, and the conductive layer 54. A barrier layer 56 and a cathode layer 58. Of these, the first insulating layer 41, the second insulating layer 45, and the third insulating layer 50 are made of, for example, a material containing inorganic silicon or an organic material having heat resistance of 300 ° C. or higher. Among these insulating layers, at least the first insulating layer 41 includes a polyaryl ether resin (for example, SiLK), an aryl ether resin, an aromatic polymer, a polyimide, a fluorine-added polyimide, a fluorine resin, a benzocyclobutene, a polyphenylene resin, It consists of one or more materials selected from among polyparaphenylene resins. On the other hand, the second insulating layer 45 and the third insulating layer 50 are made of the same material as the first insulating layer 41, or a SiO ₂ film called TEOS (tetraethyloxysilane) / O ₂ film or spin-on glass film (SOG). Consists of. In a more preferred embodiment, the first insulating layer 41 and the second insulating layer 45 are made of an insulating material having a low dielectric constant. According to this, crosstalk between wirings is suppressed.

  The first insulating layer 41 is a layer that covers the entire surface of the support substrate 6 on which the IC chip 30 and the filling layer 304 are provided. A contact hole 41 a is provided in a portion of the first insulating layer 41 that overlaps the pad P of each IC chip 30. The size of the opening of each contact hole 41a is such that even if a manufacturing error (an error in the position where the IC chip 30 is arranged or an error in the position where the contact hole 41a is provided) occurs, The pad P is determined so as to be exposed through the contact hole 41a. As described above, the first pad and the second pad of the IC chip 30 have different sizes. Therefore, the size of the opening of the contact hole 41a corresponding to the first pad is different from the size of the opening of the contact hole 41a corresponding to the second pad. Specifically, when both the vertical and horizontal lengths of the first pad P1 are about 16 μm, the contact hole 41a corresponding to the pad P1 has both the vertical and horizontal lengths of the opening of 4 μm. It is desirable that the degree. On the other hand, when the vertical and horizontal lengths of the second pad P2 are both about 80 μm, the contact hole 41a corresponding to the pad P2 has both the vertical and horizontal lengths of the opening of about 60 μm. It is desirable.

  The first wiring layer 43 is provided on the surface of the first insulating layer 41 and is electrically connected to the pad P of each IC chip 30 through the contact hole 41a. The first wiring layer 43 is made of a highly conductive metal such as aluminum (Al) or an alloy containing the same. The first wiring layer 43 includes an anode wiring 43a and a cathode power supply line 43b. Among these, the anode wiring 43 a is connected to the anode layer 49. On the other hand, the cathode power supply line 43 b is connected to the cathode layer 58 of the organic EL element 10. The first wiring layer 43 includes a data line DL for supplying a data signal Dj from the column data conversion IC chip 35 to the pixel circuit 377, and a data control signal XD from the control IC chip 31 to the column data conversion IC chip 35. Including a data control line LXD for supplying (see FIG. 9).

  The second insulating layer 45 is provided so as to cover the surface of the first insulating layer 41 provided with the first wiring layer 43. A contact hole 45 a is provided in a portion of the second insulating layer 45 that overlaps a part of the first wiring layer 43. On the other hand, the second wiring layer 47 is provided on the surface of the second insulating layer 45 and is electrically connected to the first wiring layer 43 through the contact hole 45a. The second wiring layer 47 is made of a metal having high conductivity like the first wiring layer 43. The second wiring layer 47 in this embodiment has a structure in which a layer made of aluminum and a layer made of titanium (Ti) are laminated. According to this structure, since the aluminum layer is covered with the titanium layer, the situation in which the aluminum layer is oxidized by the oxide used as the anode layer 49 is avoided.

  The second wiring layer 47 includes a scanning control line group YL extending from the scanning IC chip 33 to the pixel driving IC chip 37. Further, the second wiring layer 47 has various wirings for supplying a forced off signal Doff from the control IC chip 31 to the pixel driving IC chip 37, and various types of wiring from the control IC chip 31 to the scanning IC chip 33. Wiring for supplying signals (reset signal RSET, clock signal YSCL, and chip selection clock signal EYCL) is included. Of the second wiring layer 47, the wiring connecting the column data conversion IC chip 35 and the pixel driving IC chip 37 connects the scanning IC chip 33 and the pixel driving IC chip 37 of the first wiring layer 43. It is formed to be orthogonal to the wiring to be performed.

The power supply line to which the higher power supply potential is applied and the power supply line to which the lower power supply potential (ground potential) is applied are formed by appropriately combining the first wiring layer 43 and the second wiring layer 47. Is done. Here, FIG. 16 is a plan view showing the configuration of the electro-optical device D. FIG. A sectional view taken along line XIVA-XIVB in FIG. 14 corresponds to FIG.
As shown in FIG. 16, the power supply line L composed of the first wiring layer 43 and the second wiring layer 47 is provided in the gap between the organic EL elements 10 arranged in a matrix. Therefore, the planar shape of the power supply line L is a lattice shape.

  The anode layer 49 is provided on the surface of the second wiring layer 47. The anode layer 49 includes an anode portion 49a and a connection intermediate portion 49b. Among these, the anode part 49a is a layer formed directly under the EL layer 13 described later. Therefore, the anode portions 49a are provided at positions corresponding to the plurality of organic EL elements 10 and are arranged in a matrix. On the other hand, the connection intermediate portion 49 b is a layer for connecting the cathode layer 58 and the first wiring layer 43. This connection intermediate part 49 b is located in the gap between the organic EL elements 10. Specifically, as shown in FIG. 16, the connection intermediate portion 49b is provided in the gap between the two organic EL elements 10 adjacent to each other in the oblique direction. Therefore, the plurality of connection intermediate portions 49b are arranged in a matrix. However, the connection intermediate portion 49b can be appropriately omitted depending on the current value used for driving the organic EL element 10.

The anode layer 49 is made of, for example, a work function such as a compound of indium oxide and tin oxide (ITO: Indium Tin Oxide), a compound of indium oxide and zinc oxide (In ₂ O ₃ —ZnO), or gold (Au). Made of a large conductive material. In addition, since the light emitted from the organic EL element 10 is emitted to the side opposite to the anode layer 49, the anode layer 49 does not need to have a property of transmitting light.

  Next, the third insulating layer 50 is provided so as to cover the second insulating layer 45 provided with the second wiring layer 47 and the anode layer 49. The third insulating layer 50 has a pixel opening 50a and a cathode contact portion 50b. Among these, the pixel opening 50a is a portion of the anode layer 49 that is opened so as to correspond to the anode 49a. On the other hand, the cathode contact portion 50b is a portion of the anode layer 49 that is opened corresponding to the connection intermediate portion 49b.

The bank layer 52 is a layer that covers the surface of the second insulating layer 45 on which the anode layer 49 and the second wiring layer 47 are formed. The bank layer 52 is made of an organic resin material such as photosensitive polyimide, acrylic, or polyamide. The bank layer 52 is a layer for partitioning the organic EL elements 10 adjacent to each other. Therefore, the bank layer 52 has a pixel opening 52 a that is open to correspond to the organic EL element 10.
Furthermore, the bank layer 52 in this embodiment has a cathode contact portion 52 b for electrically connecting the cathode layer 58 to the second wiring layer 47. As shown in FIG. 16, the cathode contact portion 52b is a portion opened to correspond to the connection intermediate portion 49b.

  The conductive layer 54 is a layer for connecting a part of the second wiring layer 47 and the cathode layer 58. Specifically, the conductive layer 54 extends from the surface of the bank layer 52 to the surface of the second wiring layer 47 via the cathode contact portion 52b and the cathode contact portion 50b of the third insulating layer 50. The conductive layer 54 is made of a highly conductive metal such as an aluminum alloy. The barrier layer 56 is a layer for preventing oxidation of the conductive layer 54, and is provided so as to cover the conductive layer 54. The barrier layer 56 has, for example, a structure in which a layer made of titanium and a layer made of gold are stacked.

  Next, the cathode layer 58 is a layer provided on the surface of the EL layer 13 constituting the organic EL element 10. The cathode layer 58 is electrically connected to the second wiring layer 47 through the barrier layer 56 and the conductive layer 54. The cathode layer 58 has a property of transmitting light emitted from the organic EL element 10 (transparency). In a more desirable embodiment, the cathode layer 58 is formed of a material having a low work function. Specifically, the cathode layer 58 includes a first film made of lithium fluoride (LiF) or barium fluoride, a second film made of calcium (Ca), and a third film made of gold. It has a structure. Of these, the materials of the first film and the second film are preferably selected from metals belonging to Group 2 or Group 3 of the periodic table, and alloys or compounds containing the metals. On the other hand, the third film is a film for reducing the resistance of the first film and the second film. As a material for the third film, Pt, Ni, or Pb is used in addition to Au. The third film can also be formed using an oxide containing In, Zn, or Sn.

  Next, the organic EL layer 1 includes an EL layer 13 and a sealing layer 15. Among these, the EL layer 13 is made of a known EL material. That is, the EL layer 13 has a structure in which a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are stacked by a known technique. The EL layer 13 is provided so as to be interposed between the anode layer 49 (anode portion 49 a) and the cathode layer 58 included in the wiring formation layer 2. Under this configuration, when a current flows between the anode layer 49 and the cathode layer 58, light is emitted from the EL layer 13 by recombination of holes and electrons. As a material for the EL layer 13, either an inorganic EL material or an organic EL material can be used. The organic EL material includes a low molecular material and a high molecular material.

The sealing layer 15 is a layer for blocking the EL layer 13 from the outside. The sealing layer 15 is light transmissive so that light emitted from the EL layer 13 is emitted to the outside. The sealing layer 15 has a structure in which a plurality of planarizing resin layers 151 and a plurality of barrier layers 152 are alternately stacked. Among these, the planarizing resin layer 151 is formed by polymerizing and curing an acrylic or vinyl resin monomer or resin oligomer. The barrier layer 152 is made of (metal) oxide such as Al ₂ O ₃ , SiO ₂ , or a nitride film. In addition, it is good also as a structure by which the protective material was affixed above this sealing layer 15. FIG. Or it is good also as a structure by which the protective material was affixed instead of the sealing layer 15 shown by FIG. As this protective material, for example, a plate-like (or film-like) member made of glass, hard plastic, or the like and having optical transparency can be used.

[First manufacturing method]
Next, a manufacturing method of the electro-optical device D shown in FIG. 14 will be described.
First, as shown in FIG. 17, the base layer 301 is formed on one surface of the support substrate 6. This foundation layer 301 is obtained, for example, by depositing silicon oxide by a plasma CVD method. The thickness of the underlayer 301 is about 100 nm (nanometer) to 300 nm. Next, a metal layer 302 is formed on the surface of the base layer 301. That is, first, a metal film made of copper, gold, or the like is formed by sputtering so as to cover the entire surface of the base layer 301. Then, a patterning process and an etching process using a photolithography technique are performed on the metal film. Thereby, as shown in FIG. 17, the metal layer 302 including the mount portion 302a and the alignment mark 302b is obtained.

  Next, as shown in FIG. 18, each IC chip 30 (here, the pixel driving IC chip 37) is arranged on the mount portion 302 a in a posture in which the pad forming surface is directed to the side opposite to the support substrate 6. For the placement of the IC chip 30, a high-precision bare chip mounter having a mounting accuracy within ± 5 μm is used. Further, the relative positional relationship between each IC chip 30 and the support substrate 6 is adjusted by observing the alignment mark 302b.

  Each IC chip 30 is processed in advance as shown below. That is, a protective tape (not shown) is affixed to a surface corresponding to the substrate surface of the wafer before being divided into IC chips 30 by dicing. This protective tape is made of an ultraviolet curable material. Therefore, a protective tape is affixed to the pad forming surface of each IC chip 30 arranged in the mount portion 302a. On the other hand, the surface corresponding to the pad forming surface of each IC chip 30 in the wafer is ground. By this grinding, each IC chip 30 has a thickness suitable for forming the wiring forming layer 2. Specifically, the thickness of the IC chip 30 is 100 μm or less (more preferably about 25 μm to 30 μm). Further, the wafer is diced after the metal layer 30a is formed on the surface corresponding to the pad forming surface. In another embodiment, a die bonding tape is attached instead of the metal layer 30a.

  Next, as shown in FIG. 19, a filling layer 304 is formed so as to fill the gaps between the IC chips 30 arranged on the support substrate 6. The filling layer 304 is obtained by electroplating using the IC chip 30 as a mask. The filling layer 304 is formed thinner than each IC chip 30. Specifically, the filling layer 304 is formed to be thinner than the IC chip 30 by 0.1 μm to 3 μm.

  Thereafter, the protective tape attached to the substrate surface of each IC chip 30 is removed. Specifically, first, the substrate surface of the IC chip 30 is irradiated with ultraviolet rays. Thereby, the adhesive force of a protective tape falls. Subsequently, the protective tape is completely removed by applying an organic solvent to the substrate surface of the IC chip 30.

Next, as shown in FIG. 20, the first insulating layer 41 is formed so as to cover the entire surface of the support substrate 6 on which the IC chip 30 and the filling layer 304 are provided. That is, first, an insulating film is formed so as to cover the entire surface of the support substrate 6 by plasma CVD using TEOS / O ₂ . The thickness of this insulating film is about 400 nm to 900 nm. Further, when the flatness of the insulating film formed by this method is not sufficient for forming the wiring, the insulating film is flattened by the CMP (Chemical Mechanical Polishing) method. This insulating film can also be formed by applying and baking an insulating material. That is, a solvent in which silanol (Si (OH) ₄ ) is dissolved in alcohol is applied onto the support substrate 6 and baked at a temperature of about 400 ° C. to obtain an insulating film. Each IC chip 30 is molded on the support substrate 6 through the above steps.

  Next, as shown in FIG. 20, a portion of the insulating film corresponding to the pad P of the IC chip 30 is removed to form a contact hole 41a. These contact holes 41a are collectively formed by a patterning process and an etching process using a photolithography technique. The first insulating layer 41 is obtained by the above process. Further, when the surface of the pad P is exposed through the contact hole 41a, the oxide film formed on the surface of the pad P is removed by reverse sputtering.

Subsequently, as shown in FIG. 21, a first wiring layer 43 is formed on the surface of the first insulating layer 41. That is, first, a metal film is formed so as to cover the first insulating layer 41. This metal film is obtained, for example, by depositing an aluminum alloy by sputtering. The thickness of the metal film is about 300 nm to 500 nm.
This metal film reaches the surface of the pad P of the IC chip 30 through the contact hole 41a. Next, a patterning process and an etching process using a photolithography technique are performed on the metal film. Thereby, as shown in FIG. 21, the first wiring layer 43 including the anode wiring 43a and the cathode power supply line 43b is obtained. The first wiring layer 43 can also be formed by an ink jet technique. That is, ink containing metal fine particles is ejected from the inkjet head onto the support substrate 6, and the first wiring layer 43 is obtained by drying the ink by heat treatment.

  Next, as shown in FIG. 22, the second insulating layer 45 is formed so as to cover the surface of the first insulating layer 41 on which the first wiring layer 43 is formed. The second insulating layer 45 is formed by the same method as the first insulating layer 41 described above. That is, first, an insulating film is formed by plasma CVD or sputtering. The thickness of this insulating film is about 500 nm to 900 nm. When the flatness of the insulating film is not sufficient for forming the anode, the surface is flattened by the CMP method. Subsequently, a contact hole 45a is collectively formed in a portion of the insulating film that overlaps a part of the first wiring layer 43, whereby the second insulating layer 45 is obtained. The contact hole 45a is formed in a portion overlapping with part of the anode wiring 43a and the cathode power supply line 43b.

  Next, as shown in FIG. 23, a metal film 701 to be the second wiring layer 47 is formed so as to cover the entire surface of the second insulating layer 45. The metal film 701 can be formed by, for example, sputtering, vacuum deposition, or the above-described inkjet method. The metal film 701 includes, for example, a first film formed on the surface of the second insulating layer 45 and a second film that covers the first film. Among these, the 1st film | membrane is formed in the thickness of about 300 nm-500 nm with an aluminum alloy, for example. On the other hand, the second film is formed to a thickness of about 50 nm to 100 nm with titanium, for example. Thereafter, as shown in FIG. 23, an anode material film 702 covering the metal film 701 is formed. The anode material film 702 is formed to a thickness of about 50 nm to 150 nm by sputtering, for example.

Subsequently, the anode material film 702 and a part of the metal film 701 are selectively removed by patterning and etching using a photolithography technique. Thereby, as shown in FIG. 24, the second wiring layer 47 and the anode layer 49 are obtained.
Among these, the anode layer 49 has an anode part 49 a that is located immediately below the EL layer 13 and a connection intermediate part 49 b that is located in the gap between the organic EL elements 10.

  Thereafter, as shown in FIG. 25, a third insulating layer 50 is formed. That is, first, silicon oxide is deposited to a thickness of about 150 nm to 300 nm by plasma CVD. Then, a region corresponding to the pixel opening 50a and the cathode contact portion 50b in the silicon oxide film is selectively removed by a photolithography technique, whereby the third insulating layer 50 is obtained. Note that when the silicon oxide film is selectively removed, a portion of the silicon oxide film located near the periphery of the support substrate 6 is also removed.

  Next, as shown in FIG. 26, a resin film 705 to be the bank layer 52 is formed. Specifically, a resin film 705 is obtained by applying an organic material such as photosensitive polyimide, acrylic, or polyamide, and curing the organic material by heating. The thickness of the resin film 705 is about 1.0 μm to 3.5 μm. The resin film 705 is opaque in the finished state so that light emitted from the EL layer 13 and directed to the IC chip is blocked. Thereafter, patterning processing and development processing using a photomask are performed on the resin film 705, and the cathode contact portion 52b is opened. As a result, as shown in FIG. 26, the connection intermediate portion 49b of the anode layer 49 is exposed. Further, when the cathode contact portion 52 b is formed, a portion of the resin film 705 located near the periphery of the support substrate 6 is also removed.

Subsequently, as shown in FIG. 27, a part of the connection intermediate portion 49b is removed by etching using the resin film 705 as a mask. As a result, the barrier layer (Ti layer) of the second wiring layer 47 is exposed. Thereafter, as shown in FIG. 28, a metal film 707 to be the conductive layer 54 is formed. The metal film 707 is obtained by depositing a metal such as aluminum by sputtering. The thickness of the metal film 707 is about 300 nm to 500 nm. Subsequently, as shown in FIG. 28, a metal film 708 to be the barrier layer 56 is formed. The metal film 708 is a laminate of an extremely thin film made of titanium and a film made of gold and having a thickness of about 5 nm to 15 nm. The metal film 708 is formed by sputtering, for example. Subsequently, a patterning process and an etching process using a photomask are performed on the metal film 707 and the metal film 708. As a result, as shown in FIG. 29, a conductive layer 54 and a barrier layer 56 are obtained. In addition, after this process, you may provide a black non-reflective layer so that parts other than the cathode contact part 52b among the resin films 705 may be covered. This non-reflective layer is a layer having a low light reflectance (that is, a layer having a high light absorption rate), for example, an oxide such as CrO ₃ , MnO ₂ , Mn ₂ O ₃ , NiO, Pr ₂ O ₅ , It consists of a resin material containing carbon particles.

  Subsequently, re-exposure and development are performed on the resin film 705 using the conductive layer 54 as a mask. As a result, as shown in FIG. 30, the pixel portion processing portion 52a is provided in the resin film 705 above the anode portion 49a. The bank shape is fixed by baking the resin film 705. The bank layer 52 is obtained by the above process. Next, the bank layer 52 is subjected to plasma treatment using tetrafluoromethane as a reactive gas, and liquid repellent groups are introduced to the surface thereof. As a result, the surface of the bank layer 52 exhibits liquid repellency. On the other hand, since the liquid repellent group is not introduced into the third insulating layer 50 and the anode layer 49, the surfaces of these layers are lyophilic.

  Next, as shown in FIG. 31, the EL layer 13 is formed in the pixel opening 52 a of the bank layer 52. When the EL layer 13 is formed of a polymer material, first, for example, PEDO (polythiophene) / PSS or PAni (polyanine) is applied as a hole injection layer. Next, a liquid in which a light emitting material such as polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), or polyfluorine is dissolved in a solvent is applied so as to overlap with the hole injection layer. As described above, the surfaces of the third insulating layer 50 and the anode layer 49 are lyophilic while the surface of the bank layer 52 is lyophobic. Therefore, the liquid of the EL layer 13 stays efficiently in the pixel opening 52 a of the bank layer 52. When the EL layer 13 is formed of a polymer material, a simple method such as an inkjet method, printing, or spin coating method is used for the formation. On the other hand, when the EL layer 13 is formed of a low molecular material, an evaporation method using a shadow mask or a transfer method is used for the formation. Further, if an EL layer 13 that emits light of one of the three primary colors is formed for each pixel opening 52a of the bank layer 52, color display is possible. Alternatively, a color filter may be formed above the EL layer 13 that emits white light. Of course, it may be configured to emit only a single color.

  Next, as shown in FIG. 32, a cathode layer 58 is formed so as to cover the entire surface of the bank layer 52 and the EL layer 13. That is, continuous deposition is performed in a vacuum by a multi-chamber type (cluster tool type) film forming apparatus. As a result, a cathode layer 58 having a structure in which a very thin fluoride film of alkali metal such as BaF or LiF, a Ca film of about 10 nm to 20 nm, and an Au film of about 2 nm to 15 nm is laminated. The cathode layer 58 is formed after the EL layer 13 is formed of an organic material having low heat resistance. Therefore, it is desirable that the cathode layer 58 be formed in an environment as low as possible.

Thereafter, as shown in FIG. 14, the sealing layer 15 including the planarizing resin layer 151 and the barrier layer 152 is formed. Specifically, first, a monomer or oligomer of resin such as acrylic or vinyl is sprayed in vacuum, and the cathode layer 58 is coated with the resin. Subsequently, the resin layer is irradiated with ultraviolet rays. As a result, the resin layer is polymerized and cured, and the above-described planarized resin layer 151 is obtained. Next, a thin film of metal oxide such as Al ₂ O ₃ or SiO ₂ is formed on the surface of the planarizing resin layer 151 by various film forming methods, and the barrier layer 152 is obtained. For this film formation, various film formation methods such as vacuum evaporation, sputtering, or ion plating are used. In the present embodiment, the planarizing resin layer 151 and the barrier layer 152 are formed a plurality of times. As a result, as shown in FIG. 14, a sealing layer 15 in which a plurality of planarizing resin layers 151 and a plurality of barrier layers 152 are alternately stacked is obtained. Thereafter, a protective material is attached to the surface of the uppermost barrier layer 152. The electro-optical device D is completed through the above steps.

According to the first manufacturing method, the following effects can be obtained.
(1) Since the electro-optical device D is obtained by sequentially stacking the electronic component layer 3, the wiring formation layer 2, and the organic EL layer 1 in order, the manufacturing process can be simplified and the manufacturing cost can be reduced. . In addition, since each layer is laminated without a gap, an electro-optical device that is very thin (thickness of about 1 mm (millimeter)) and lightweight can be obtained.

(2) The pixel driving IC chip 37 including the pixel circuit 377 for driving the organic EL element 10 is provided in the electronic component layer 3, while the organic EL element 10 is disposed in the organic EL layer 1 positioned above the electronic component layer 3. Is provided. Therefore, it is not necessary to consider the space where the pixel circuit 377 is to be disposed when selecting the position where the organic EL element 10 is to be disposed. That is, the aperture ratio can be improved without being restricted by the pixel circuit 377.

(3) Since various wirings are collectively formed in the wiring forming layer 2 located between the electronic component layer 3 and the organic EL layer 1, these wirings are included in the electronic component layer 3 or the organic EL layer 1. Compared with the case where it is not, the freedom degree of wiring layout design can be improved.

(4) The contact holes 41a of the first insulating layer 41 are collectively formed by a photolithography technique, and the first wiring layers 43 are collectively formed so as to fill the contact holes 41a. Therefore, even if the first pad P1 of the IC chip 30 has a minute size of about 16 μm in length × 16 μm in width, each first pad P1 and the first wiring layer 43 are reliably connected together. Further, even if the number of pads P is large, the time required for connection with the wiring does not change, so that the productivity can be improved and the wiring density can be increased.

[Laminated structure by the second manufacturing method]
Next, a stacked structure of the electro-optical device D obtained by the second manufacturing method will be described with reference to FIG. The same reference numerals as those in FIG. 14 are assigned to the same parts as those of the electro-optical device D according to the first manufacturing method among the parts shown in FIG. The planar configuration of the electro-optical device D is as shown in FIG. The electro-optical device D shown in FIG. 33 has the same configuration as the electro-optical device D shown in FIG. 14 except for the structure of the electronic component layer 3.

As shown in FIG. 33, the electronic component layer 3 of the electro-optical device D includes a filling layer 305, a light shielding layer 306, a base layer 307, and an IC chip (here, a pixel driving IC chip 37). Among these, the filling layer 305 is provided over the entire surface of the support substrate 6 so as to fill the gaps between the IC chips 30. The filling layer 305 is formed of a material having high heat dissipation. As a result, the thermal uniformity of the entire electro-optical device D is improved, and the occurrence of defects due to heat can be suppressed. The filling layer 305 is formed of a material whose linear expansion coefficient approximates that of the IC chip 30.
Therefore, the generation of thermal stress due to the difference in linear expansion coefficient between the filling layer 305 and the IC chip 30 can be suppressed. Specifically, the filling layer 305 is made of a heat-resistant resin material mixed with silica filler, low-melting glass, oxide, or metal such as copper.

  The light shielding layer 306 is provided on the surface of the filling layer 305 so as to cover the entire surface of the support substrate 6 including the region where the IC chip 30 is disposed. The light blocking layer 306 is a layer for blocking light incident from the support substrate 6 side and traveling toward the IC chip 30, and is made of a metal such as aluminum or copper. The light shielding layer 306 prevents malfunction of the IC chip 30 due to light irradiation. Note that when the filling layer 306 is made of a light-blocking conductive material, the light-blocking layer 306 can be omitted.

  On the other hand, the base layer 307 is provided on the surface of the light shielding layer 306 so as to cover the entire surface of the support substrate 6. This foundation layer 307 is a layer that serves as a foundation for forming the wiring formation layer 2 and is made of, for example, silicon oxide. The underlying layer 307 relieves stress generated as the filling layer 305 is deformed. Each IC chip 30 is disposed on the surface of the base layer 307 with the substrate surface facing the support substrate 6. Intrusion of impurities from the support substrate 6 or the filling layer 305 to the IC chip 30 is prevented by the base layer 307. The base layer 307 also has a role of electrically insulating the wiring included in the wiring forming layer 2 from the light shielding layer 42.

[Second manufacturing method]
Next, a method for manufacturing the electro-optical device D shown in FIG. 33 will be described.

  First, as shown in FIG. 34, a light peeling layer 712 is formed over the entire surface of the substrate 710. The substrate 710 is a light-transmitting plate member, and is made of, for example, glass. On the other hand, the light peeling layer 712 is obtained by depositing amorphous silicon by, for example, a plasma CVD method.

  Subsequently, as shown in FIG. 35, a metal layer 714 is formed on the surface of the light peeling layer 712. The metal layer 714 is obtained by depositing aluminum by a method such as sputtering. Thereafter, the metal layer 714 is subjected to patterning processing and etching processing using a photomask. Thereby, alignment marks for adjusting the position of each IC chip 30 are formed.

  Next, as shown in FIG. 35, a resin film 716 is formed so as to cover the light peeling layer 712. The resin film 716 is a layer that becomes the first insulating layer 41 in a later step, and is made of a heat-resistant organic material. The resin film 716 is formed by a method such as spin coating or coating. At this stage, the resin film 716 is in a semi-polymerized state and has adhesiveness. The thickness of the resin film 716 is about 0.1 μm to 5 μm.

  Next, as shown in FIG. 36, each IC chip 30 is arranged at a predetermined position of the resin film 716. At this time, each IC chip 30 is arranged on the surface of the resin film 716 in such a manner that the pad formation surface faces the substrate 710 side. Therefore, damage to the pad P in the subsequent process is prevented. Further, the relative positional relationship between each IC chip 30 and the substrate 710 is adjusted by observing the alignment marks on the metal layer 714. For the placement of the IC chip 30, a high-precision bare chip mounter having a mounting accuracy within ± 5 μm is used. After all the IC chips 30 are arranged, the resin film 716 is baked to be completely polymerized. Thereby, the adhesiveness between the resin film 716 and each IC chip 30 is improved.

Next, as shown in FIG. 37, a base layer 307 covering the entire surface of the substrate 710 on which the IC chip 30 is disposed is formed. The underlayer 307 is obtained by depositing SiO ₂ by, for example, a plasma CVD method. The thickness of the base layer 307 is about 100 nm to 500 nm. Subsequently, as shown in FIG. 37, a light shielding layer 306 covering the entire surface of the base layer 307 is formed. The light shielding layer 306 is obtained by depositing a metal such as copper or aluminum by sputtering, for example.

  Further, as shown in FIG. 38, hard resin is filled so as to fill the gaps between the IC chips 30. This hard resin is, for example, a heat-resistant resin material mixed with silica filler or low-melting glass. Subsequently, the support substrate 6 is attached to the substrate surface of the IC chip 30 through the hard resin. At this time, the IC chip 30 is used as a spacer for adjusting the distance between the support substrate 6 and the substrate 710. Thereafter, the filling layer 305 is obtained by solidifying the hard resin by heating.

  Next, as shown in FIG. 38, excimer laser light R, which is ultraviolet light, is irradiated from the substrate 710 side. As a result, the light peeling layer 712 is exploded. That is, hydrogen contained in the photodetachment layer 712 is gasified and a crack occurs in this layer. In this state, the substrate 710 is peeled off via the light peeling layer 712. Subsequently, the metal layer 714 and the light peeling layer 712 are removed by the etching solution. This etching solution is a liquid that dissolves the metal layer 714 and the light peeling layer 712 but does not affect the resin film 716 at all.

  Thereafter, as shown in FIG. 39, the support substrate 6 is turned upside down so that the surface on which the IC chip 30 is disposed faces upward. As a result, the electronic component layer 3 of the electro-optical device D shown in FIG. 33 is formed. In the electronic component layer 3 obtained by this manufacturing method, the pad forming surface of each IC chip 30 and the surface of the base layer 307 are located in substantially the same plane. Thereafter, a patterning process and an etching process are performed on the resin film 716, and the first insulating layer 41 is obtained. The subsequent manufacturing process is the same as the first manufacturing method shown in FIGS.

According to the second manufacturing method, the following effects can be obtained.
(1) Since the gap between the IC chips 30 is filled with the filling layer 305, it is not necessary to flatten the filling layer 305 according to the surface of each IC chip 30. Therefore, the manufacturing process can be simplified. Moreover, since it is not necessary to make the IC chip 30 thinner than in the first manufacturing method, the handling of each IC chip 30 is facilitated.
Therefore, it is possible to reduce the possibility that a defect of the IC chip 30 occurs during the manufacturing process.

(2) Since the base layer 307 and the filling layer 305 are formed with the pads P of each IC chip 30 facing the substrate 710, damage to the pads P during the formation of these layers is avoided. Therefore, poor electrical connection between each IC chip 30 and the first wiring layer 43 is prevented. As a result, the characteristics of the electro-optical device D can be maintained at a high level, and the yield can be improved.

(3) Since each IC chip 30 is fixed by the base layer 307 and the filling layer 305, it is not necessary to fix each IC chip 30 on the substrate 710. That is, since it is only necessary to arrange each IC chip 30, the time required for mounting each IC chip 30 is shortened.

(4) Since the wiring formation layer 2 is laminated on the electronic component layer 3 where the pads P are exposed, for example, the pads P of the IC chip 30 and the wirings of the wiring formation layer 2 can be connected together by a photolithography technique. it can. Therefore, it is not necessary to provide bumps or the like for connecting the pads P of each IC chip 30 and the wiring. As a result, the manufacturing process can be simplified and the manufacturing time can be shortened.

(5) Since the resin film 716 serving as the first insulating layer 41 is used as a layer for bonding the IC chips 30, the manufacturing process is simplified compared to a method of providing an adhesive layer separately from the insulating layer 41. Is done. However, a method of providing an adhesive layer separately from the first insulating layer 41 can also be adopted. That is, instead of the resin film 716 in FIG. 35, a method of providing an adhesive layer for bonding each IC chip and removing the adhesive layer after the substrate 710 is peeled can be employed. In this case, the first insulating layer 41 is formed after removing the adhesive layer.

  By the way, the power supply line to which the higher or lower power supply potential is applied can be formed in a process separate from the process of forming the first wiring layer 43 and the second wiring layer 47. For example, as shown below, the step of forming the power supply line can be executed immediately before the step of disposing each IC chip 30 in the second manufacturing method.

  First, as shown in FIG. 36, the power supply line 309 is formed on the surface of the resin film 716 before each IC chip 30 is arranged. In FIG. 40, the outline of each IC chip 30 disposed on the resin film 716 in a later step is indicated by a broken line. The power supply line 309 is formed at a position that does not overlap the alignment mark of the metal layer 714 in a region other than the region where each IC chip 30 is to be disposed.

  Specifically, first, a conductive layer made of a conductive material such as aluminum or copper is formed on the surface of the resin film 716. This conductive layer can be formed, for example, by electroless plating, sputtering or ink jet techniques. Next, a patterning process and an etching process are performed on the conductive layer, and the power supply line 309 shown in FIG. 40 is obtained. Thereafter, each IC chip 30 is disposed on the surface of the resin film 716 in the same manner as the process shown in FIG. 36, and then a light shielding layer 306 and a base layer 307 are formed so as to cover the power supply line 309 and the IC chip 30. Is done. The subsequent steps are as described above. In another example, the step of forming the power supply line 309 can be performed immediately after each IC chip 30 is disposed on the surface of the resin film 716. In the first manufacturing method described above and the third manufacturing method described below, the power supply line 309 can be formed by the same procedure.

  FIG. 41 is a diagram showing a laminated structure of the electro-optical device D obtained by this manufacturing method. As shown in the figure, in the electro-optical device D, the power supply line 309 is located between the base layer 307 and the first insulating layer 41. The power supply line 309 is connected to the first wiring layer 43 through a contact hole 41 a provided in the first insulating layer 41.

[Laminated structure by the third manufacturing method]
Next, with reference to FIG. 42, a laminated structure of the electro-optical device D obtained by the third manufacturing method will be described. The same reference numerals as those in FIG. 14 are assigned to the same parts as those of the electro-optical device D according to the first manufacturing method among the parts shown in FIG. The planar configuration of the electro-optical device D is as shown in FIG.

  As shown in FIG. 42, in the electro-optical device D obtained by the third manufacturing method, bumps (projection electrodes) 308 are formed on the pads P of the IC chip 30. The bump 308 is made of a metal such as indium (In) or gold (Au). The bump 308 is connected to the bump 42. The bumps 42 are connected to the first wiring layer 43 through contact holes 41 a that open in the first insulating layer 41. Similar to the bump 308, the bump 42 is made of a metal such as indium or gold.

[Third production method]
Next, a method for manufacturing the electro-optical device D shown in FIG. 42 will be described.

First, as shown in FIG. 43, an insulating layer 722 is formed so as to cover the entire surface of the substrate 720. This substrate 720 is a plate-like member having optical transparency, and is made of, for example, glass. On the other hand, the insulating layer 722 is obtained by depositing SiO ₂ by plasma CVD, for example. Further, when the flatness of the insulating layer 722 is insufficient, the insulating layer 722 is flattened by a CMP method. Subsequently, as shown in FIG. 43, a light peeling layer 724 is formed over the entire surface of the insulating layer 722. The photodetachment layer 724 is obtained by depositing amorphous silicon by, for example, a plasma CVD method.

Next, as shown in FIG. 44, an insulating film 726 is formed over the entire surface of the light peeling layer 724. This insulating film 726 is obtained by depositing SiO ₂ by plasma CVD. The insulating film 726 is a layer that becomes the third insulating layer 50 shown in FIG. Thereafter, as shown in FIG. 44, a conductive film 728 to be the anode layer 49 is formed on the surface of the insulating film 726. The conductive film 728 is obtained by depositing a conductive material having a large work function, such as ITO, by sputtering. Further, as shown in FIG. 44, a metal film 730 to be the second wiring layer 47 is formed so as to cover the conductive film 728. The metal film 730 is obtained by laminating a layer made of aluminum or the like on the surface of a layer made of titanium or the like. For example, sputtering is used to form the metal film 730. Next, as shown in FIG. 45, patterning processing and etching processing using a photomask are performed on the conductive film 728 and the metal film 730, and the anode layer 49 and the second wiring layer 47 shown in FIG. 42 are obtained. .

Next, as shown in FIG. 46, a second insulating layer 45 is formed. The second insulating layer 45 is formed by performing patterning processing and etching processing using a photomask after an insulating layer made of SiO ₂ or the like is formed so as to cover the anode layer 49 and the second wiring layer 47. can get. Subsequently, as shown in FIG. 47, a first wiring layer 43 is formed. The first wiring layer 43 is obtained by performing a patterning process and an etching process on a metal layer such as aluminum formed by sputtering.

Thereafter, as shown in FIG. 48, a first insulating layer 41 is formed. That is, first, an insulating film such as SiO ₂ is formed so as to cover the first wiring layer 43. And the part which should oppose the pad P of IC chip 30 among this insulating films is removed by the patterning process and the etching process, and the 1st insulating layer 41 is obtained. Subsequently, as shown in FIG. 49, bumps 42 are formed on portions of the first wiring layer 43 that should face the bumps 308 of the IC chip. The bumps 42 are formed to a thickness of about 0.5 μm to 5 μm, for example, by a lift-off method. The bump 42 is made of a metal such as indium or gold. When the bump 42 is formed of indium, its surface is covered with a metal such as gold. Thereby, the oxidation of the bump 42 is prevented.

  On the other hand, bumps 308 are formed on the pads P of each IC chip 30. The bump 308 is made of a metal such as indium or gold. The thickness of the bump 308 is about 2 μm to 10 μm. Thereafter, as shown in FIG. 50, each IC chip 30 is disposed on the first insulating layer 41 with the bumps 308 facing the bumps 42 on the first wiring layer 43. For the placement of each IC chip, a high-precision bare chip mounter having a mounting accuracy of within ± 5 μm is used. Subsequently, the bump 42 and the bump 308 are instantaneously heated. Thereby, the bump 42 and the bump 308 are joined.

  Next, as shown in FIG. 51, a resin material is filled so as to fill the gaps between the IC chips 30. This resin material contains carbon particles and has light shielding properties. Thereafter, as shown in FIG. 51, the support substrate 6 is attached to the substrate surface of the IC chip 30. Further, the resin material filled between the IC chips 30 is cured to obtain the filling layer 305.

  Subsequently, as shown in FIG. 51, excimer laser light R, which is ultraviolet light, is irradiated from the substrate 720 side. As a result, the light peeling layer 724 is exploded, and the substrate 720 is peeled off via the light peeling layer 724 as shown in FIG. Further, the amorphous silicon remaining on the insulating film 726 is removed by an etching process.

  Thereafter, patterning processing and etching processing using a photomask are performed on the insulating film 726, and the third insulating layer 50 shown in FIG. 42 is obtained. The subsequent manufacturing process is the same as the first manufacturing method shown in FIGS.

According to the third manufacturing method, the following effects can be obtained.
When the anode layer 49 is formed after the electronic component layer 3 and each wiring layer and each insulating layer are formed as in the first and second manufacturing methods described above, the surface of the anode layer 49 is formed by the steps of these layers. Flatness may be reduced. On the other hand, according to the third manufacturing method, since the conductive film 728 to be the anode layer 49 is formed on the flat substrate 720 before other elements, the flatness of the surface of the anode layer 49 is extremely high. Maintained at a high level. Thereby, since the uniformity of the thickness of the organic EL element 10 is maintained, the light emission luminance is uniform over the entire display surface. The third manufacturing method is the same when the IC chip 30 including the active element is used for the electro-optical device D, and when the active element formed of low-temperature polysilicon or the like is used for the electro-optical device D. Can be applied to.

<C: Electronic equipment>
Next, an electronic apparatus according to the present invention will be described.
[Personal computer]
FIG. 53 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus according to the invention. As shown in the figure, the personal computer 81 includes a main body portion 812 having a keyboard 811 and a display portion 814 having the above-described electro-optical device D.

  In this configuration, an IC chip having various functions related to image display can be included in the electronic component layer 3. As this type of IC chip, for example, an IC chip having a display buffer memory and a CPU, or an IC chip having a data expansion function compliant with MPEG (Motion Picture Experts Group), MP3 (MPEG Audio Layer-3), etc. and so on. When the display surface of the electro-optical device D is used as a touch panel, an IC chip having a function related to the input can be included in the electronic component layer 3.

[E-book]
Next, FIG. 54 is a perspective view showing a configuration of an electronic book as an example of an electronic apparatus according to the invention. As shown in the figure, the electronic book 83 includes a main body portion 830, a first display portion 831, and a second display portion 832. Of these, the main body 830 includes a keyboard that accepts user operations. The first display unit 831 includes the electro-optical device D described above, that is, the electro-optical device D that displays an image by light emission of the organic EL element 10. On the other hand, the second display unit 832 includes an electro-optical device D ′ that displays an image using a plurality of pixels. However, the pixels of the second display portion 832 do not emit light. Specifically, a non-light-emitting display such as an electrophoretic display, a reflective LCD (Liquid Crystal Display), a toner display, or a twist ball display is used as the electro-optical device D ′ of the second display unit 832.

  The first display portion 831 is attached to the periphery of the main body portion 830 via a hinge. Therefore, the first display portion 831 can rotate around the periphery of the main body portion 830. On the other hand, the second display portion 832 is attached to the periphery of the first display portion 831 opposite to the main body portion 830 via a hinge. Therefore, the second display portion 832 can rotate around the periphery of the first display portion 831.

  Under this configuration, display by the first display portion 831 is performed by causing the organic EL element 10 to emit light. On the other hand, when the display by the second display portion 832 is performed, the organic EL element 10 of the first display portion 831 emits light with substantially the same luminance. The light emitted from the first display portion 831 is reflected by the display surface of the second display portion 832 and then observed by the observer. In other words, the first display portion 831 not only functions as a display device itself, but also functions as an illumination device (so-called front light) when an image is displayed by the second display portion 832. According to this configuration, although the second display unit 832 is a non-light-emitting display, it is not necessary to provide an illumination device for ensuring the brightness of the display. As a result, the total thickness of the first display portion 831 and the second display portion 832 can be reduced to about 2 mm or less, which is thinner and lighter than a book using paper and yet has a high function. Is realized.

  Note that electronic devices to which the present invention can be applied are not limited to the devices shown in FIGS. That is, in addition to this, mobile phones, game machines, electronic paper, video cameras, digital still cameras, car navigation devices, car stereos, driving operation panels, printers, scanners, TVs, video players, pagers, electronic notebooks, calculators, The present invention can be applied to various devices having a function of displaying an image, such as a word processor.

<D: Modification>
The form shown above is an illustration to the last, and various deformation | transformation can be added with respect to these forms. An example of the deformation is as follows.
(1) The configuration in which the pixel driving IC chip 37, the scanning IC chip 33, the column data conversion IC chip 35, and the control IC chip 31 are arranged on one support substrate 6 is exemplified. 33, a part or all of the column data conversion IC chip 35 and the control IC chip 31 may be arranged on another substrate. Further, a part or all of the scanning IC chip 33, the column data conversion IC chip 35, and the control IC chip 31 may be configured as one IC chip.

(2) As shown for a personal computer as an example of an electronic device, by applying the present invention to various electronic devices, a systemized and integrated element substrate and package are realized. That is, in this element substrate, an electronic component layer having various active elements and passive elements is sealed by a wiring forming layer having wirings connected to connection terminals of the respective electronic components. As an example of the active element included in the electronic component layer, there are various components such as an IC chip (CMOS type or bipolar type), a memory, or a compound semiconductor for realizing various functions. On the other hand, examples of passive elements included in the electronic component layer include various chip components such as resistors, capacitors, and inductances. According to this element substrate, since various electronic components are systematized and integrated, electronic devices can be reduced in size, weight, and performance.

(3) The present invention can also be applied to electro-optical devices other than devices using EL elements. That is, the present invention is applied to any device provided with an electro-optic element that converts an electrical action into an optical action. This type of electro-optical device includes a liquid crystal display device using liquid crystal, an electrophoretic display device using microcapsules containing a colored liquid and white particles dispersed in the liquid, and each region having a different polarity Twisted ball display using twist balls painted in different colors, toner display using black toner, field emission display using phosphor, LED display using LED (Light Emitting Diode), helium, neon, etc. There are plasma display panels (PDP) using high pressure gas.

Further, the electro-optical device according to the present invention is not limited to a device for displaying an image.
For example, the present invention can be applied to an image forming apparatus using an organic EL, LED, or field emission element (FED), and an optical engine portion of an electrophotographic apparatus. In this type of apparatus, light corresponding to image data is irradiated onto a photosensitive member such as a photosensitive drum, and toner is adsorbed to the latent image formed thereby. Then, this toner is transferred to a recording material such as paper. The electro-optical device according to the present invention can also be applied to a device for irradiating a photoconductor with light according to image data. In other words, the electro-optical device in this case includes a light-emitting element (electro-optical element) that irradiates light to the photosensitive member, and a drive circuit that individually drives each light-emitting element. In a more desirable mode, a configuration is adopted in which line exposure is possible in accordance with the width of various recording materials such as A4 size and A3 size. According to the electro-optical device according to the present invention, a high-performance and thin printing device or a multifunction peripheral can be realized.

  Furthermore, the present invention can also be applied to an electro-optical device using an electro-optical element such as a CCD (Charge Coupled Device) that outputs a current or voltage corresponding to the amount of irradiation light. This electro-optical device is used as an optical sensor array device (imaging device) in a digital camera, for example. This type of optical sensor array device includes a CCD instead of the organic EL element 10 of the electro-optical device D according to the above embodiment, and an A / D conversion circuit that converts an analog signal output from the CCD into a digital signal. This is realized by providing instead of the D / A conversion circuit 356. In another aspect, an electro-optical device used as a display device and an electro-optical device used as an optical sensor array device are combined together. According to this device, the luminance of light emitted from the display device can be automatically adjusted according to the ambient brightness detected by the photosensor array device.

  The present invention can also be applied to an apparatus including elements other than electro-optical elements. That is, the present invention is also applied to an element driving device including a plurality of driven elements each arranged at a different position in the plane (for example, arranged in a matrix) and a unit circuit for driving each driven element. The invention can be applied. For example, if an element for detecting pressure or static electricity is used as a driven element instead of the electro-optical element (for example, the CCD of the optical sensor array described above) of the electro-optical device according to the present invention, an apparatus for detecting an operation by a user Is realized. The element driving device can be used as an input device such as a touch panel or a thin keyboard in various electronic devices.

1 is a perspective view illustrating a configuration of an electro-optical device according to an embodiment of the invention. It is a top view which shows the structure of an electronic component layer. It is a figure which shows the correspondence of a pixel drive IC chip and an organic EL element. It is a block diagram which shows the structure of the IC chip for pixel drive. It is a block diagram which shows the relationship between a scanning IC chip and a pixel drive IC chip. It is a timing chart for demonstrating operation | movement of the IC chip for a scan. It is a circuit diagram which shows the structure of a pixel circuit. 3 is a timing chart for explaining scanning of a pixel circuit. It is a block diagram which shows the structure of IC chip for column data conversion. It is a circuit diagram which shows the structure of a reference current supply circuit. It is a timing chart which shows operation in a setup period. It is a block diagram which shows the structure of a D / A conversion circuit. It is a circuit diagram which shows the structure of a D / A conversion part. It is sectional drawing which shows the structure of the electro-optical apparatus obtained by the 1st manufacturing method. It is a figure which shows the structure of the pad formation surface of an IC chip for pixel drive. It is a top view which shows the structure of an electro-optical apparatus. It is a figure which shows the process in which a base layer and a metal layer are formed among 1st manufacturing methods. It is a figure which shows the process by which an IC chip is arrange | positioned among the methods. It is a figure which shows the process in which the filling layer is formed among the methods. It is a figure which shows the process in which the 1st insulating layer is formed among the methods. It is a figure which shows the process in which the 1st wiring layer is formed among the methods. It is a figure which shows the process in which the 2nd insulating layer is formed among the methods. It is a figure which shows the process in which a metal film and an anode material film are formed among the methods. It is a figure which shows the process in which a 2nd wiring layer and an anode layer are formed among the methods. It is a figure which shows the process in which the 3rd insulating layer is formed among the methods. It is a figure which shows the process in which the resin layer is formed among the methods. It is a figure which shows the process of removing a part of anode layer among the methods. It is a figure which shows the process in which a conductive layer and a barrier layer are formed among the methods. It is a figure which shows the process in which a conductive layer and a barrier layer are formed among the methods. It is a figure which shows the process in which a bank layer is formed among the methods. It is a figure which shows the process in which EL layer is formed among the methods. It is a figure which shows the process in which a cathode layer is formed among the methods. It is sectional drawing which shows the structure of the electro-optical apparatus obtained by the 2nd manufacturing method. It is a figure which shows the process in which a light peeling layer is formed on a board | substrate among the methods. It is a figure which shows the process in which a metal layer and an adhesion layer are formed among the methods. It is a figure which shows the process by which an IC chip is arrange | positioned among the methods. It is a figure which shows the process in which a base layer and a light shielding layer are formed among the methods. It is a figure which shows the process in which a support substrate is affixed among the methods. It is a figure which shows the state by which the board | substrate was peeled in the same method. It is a figure which shows the process in which a power supply line is formed among the other examples of the method. It is sectional drawing which shows the structure of the electro-optical apparatus obtained by the other example of the method. It is sectional drawing which shows the structure of the electro-optical apparatus obtained by the 3rd manufacturing method. It is a figure which shows the process in which the light peeling layer is formed among the methods. It is a figure which shows the process in which an insulating layer and a conductive layer are formed among the methods. It is a figure which shows the process in which a 2nd wiring layer and an anode layer are formed among the methods. It is a figure which shows the process in which the 2nd insulating layer is formed among the methods. It is a figure which shows the process in which the 1st wiring layer is formed among the methods. It is a figure which shows the process in which the 1st insulating layer is formed among the methods. It is a figure which shows the process in which a bump is formed among the methods. It is a figure which shows the process by which an IC chip is arrange | positioned among the methods. It is a figure which shows the process in which a support substrate is affixed among the methods. It is a figure which shows the state by which the board | substrate was peeled in the same method. It is a perspective view which shows the structure of the personal computer which is an example of an electronic device. It is a perspective view which shows the structure of the electronic book which is an example of an electronic device.

Explanation of symbols

D: electro-optical device, 1 ... organic EL layer, 10 ... organic EL element (electro-optical element, driven element), 13 ... EL layer, 15 ... sealing layer, 2 ... wiring formation layer, 3 ... Electronic component layer, 30 ... IC chip, 31 ... Control IC chip, 33 ... Scanning IC chip (selection circuit), 35 ... Column data conversion IC chip (data supply circuit), 351 ... ... Enable control circuit (control circuit), 353 ... 1st latch circuit, 353a ... AND gate, 353b ... AND gate, 354 ... 2nd latch circuit, 356 ... D / A conversion circuit (data signal) Output circuit), 356a... D / A converter, 358... Reference current supply circuit, C1... Capacitor (holding circuit), 359... AND gate, 37. ) 370a ... first pixel driving IC chip group, 370b ... second pixel driving IC chip group, 371 ... pixel decoder (control circuit), 374 ... pixel counter (specific circuit), 377 ... pixel circuit, 377a: Analog memory section (sustain circuit), C0: Capacitor (hold circuit), 6: Support substrate, YLk: Scan control line group, LCak: First local clock signal line, LCbk: Second Local clock signal line, LRS ... local reset signal line, WLi ... word line, HLi ... holding signal line, GCLi ... issue control signal line, TSL ... test signal line, LXD ... data control line, LXECL ...... Enable signal line, LXd ... Image data signal line, LXCL ... Clock signal line, LBP ... Reference current control line, LLP ... Latch pulse signal line, Lr ... Current Supply line.

Claims (11)

A plurality of predetermined electro-optic elements driven by a drive current specified by a data signal;
A plurality of predetermined unit circuits for driving the predetermined plurality of electro-optic elements;
A control circuit for performing selection control for sequentially selecting one or more unit circuits of the plurality of predetermined unit circuits and causing the selected one or more unit circuits to perform an operation for driving an electro-optic element; A plurality of element driving IC chips provided in a matrix corresponding to the electro-optic elements;
A selection circuit that sequentially selects one or more element driving IC chips from among the plurality of element driving IC chips and causes the control circuit of the selected element driving IC chip to perform the selection control;
A plurality of data supply circuits provided for each of the one or more electro-optic elements and including a first data supply circuit and a second data supply circuit, wherein the reference current supply circuit generates a reference current based on a reference current; A plurality of data supply circuits each including a data signal output circuit that outputs a current value corresponding to the data signal based on a reference current generated by the reference current supply circuit;
Comprising
The first data supply circuit outputs the reference current used by the reference current supply circuit of the first data supply circuit to generate a reference current to the second data supply circuit,
The reference current supply circuit of the second data supply circuit is an electro-optical device that generates the reference current based on the reference current supplied from the first data supply circuit. The reference current output from the first data supply circuit is supplied to each of the plurality of second data supply circuits in a predetermined setting period, and a reference current is sequentially generated based on the supplied reference current the electro-optical device according to <br/> claim 1 being. 3. The reference current output from the first data supply circuit is supplied to each second data supply circuit via a current supply line having a portion common to the plurality of second data supply circuits. Electro-optic device. The electro-optical device according to claim 2, wherein each of the plurality of data supply circuits includes a control circuit that switches whether to supply the reference current to a reference current supply circuit of the data supply circuit. The control circuit of each of the second data supply circuits switches whether to supply the reference current to the reference current supply circuit based on an enable signal supplied from the control circuit of the previous data supply circuit and The electro-optical device according to claim 4, wherein an enable signal is output to a control circuit of the supply circuit. Each of the data supply circuits includes a holding circuit that holds a charge corresponding to the reference current, and the reference current supply circuit of each of the data supply circuits generates a reference current based on the reference current held in the holding circuit. The electro-optical device according to claim 1. 7. The electro-optical device according to claim 6, wherein the reference current is supplied to the reference current supply circuit of each data supply circuit in a period other than a period in which the data signal output circuit of the data supply circuit outputs a data signal. The electro-optical device according to claim 1, wherein a configuration of the first data supply circuit and a configuration of the second data supply circuit are the same. The electro-optical device according to claim 1, wherein the data signal output circuit of each of the data supply circuits outputs the generated data signal to a unit circuit of the element driving IC chip. A plurality of predetermined driven elements driven by a driving current specified by a data signal; a plurality of predetermined unit circuits for driving the predetermined plurality of driven elements;
A control circuit for performing selection control for sequentially selecting one or more unit circuits of the plurality of predetermined unit circuits and causing the selected one or more unit circuits to perform an operation for driving a driven element; A plurality of element driving IC chips provided in a matrix corresponding to the driven elements;
A selection circuit that sequentially selects one or more element driving IC chips from among the plurality of element driving IC chips and causes the control circuit of the selected element driving IC chip to perform the selection control;
A plurality of data supply circuits provided for each of one or a plurality of driven elements and including a first data supply circuit and a second data supply circuit, wherein the reference current supply circuit generates a reference current based on a reference current; A plurality of data supply circuits each including a data signal output circuit that outputs a current value corresponding to the data signal based on a reference current generated by the reference current supply circuit;
Comprising
The first data supply circuit outputs the reference current used by the reference current supply circuit of the first data supply circuit to generate a reference current to a second data supply circuit other than the first data supply circuit,
A reference current supply circuit of the second data supply circuit generates the reference current based on the reference current supplied from the first data supply circuit.   An electronic apparatus comprising the electro-optical device according to claim 1.

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