JP3876496B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a manufacturing method thereof, and in particular, a high-concentration first conductive semiconductor substrate and a low-concentration first conductive semiconductor layer formed on the first conductive semiconductor substrate. And a plurality of pixels formed on the substrate, wherein each pixel is operated by being supplied with power through the first conductive semiconductor substrate and the first conductive semiconductor layer in this order. And a manufacturing method thereof.
[0002]
[Prior art]
Conventionally, as this type of solid-state imaging device, for example, a paper titled “Development of a bipolar type area sensor“ BASIS ”by Shinohara et al.” (Magazine “Video Information INDUSTRIAL” (published by the Video Information Editor, Industrial Development Organization) 1989, May issue, pp. 41-46) is known.
[0003]
This conventional solid-state imaging device will be briefly described with reference to FIGS.
[0004]
FIG. 16 is a schematic plan view showing this conventional solid-state imaging device. FIG. 17 is a schematic cross-sectional view taken along line X11-X12 in FIG. 18 is a schematic sectional view taken along line X13-X14 in FIG. FIG. 19 is a schematic cross-sectional view taken along line Y11-Y12 in FIG. FIG. 20 is a circuit diagram showing the basic circuit configuration of the pixel and readout circuit system of this conventional solid-state imaging device. In FIG. 19, only one pixel is shown.
[0005]
As shown in FIGS. 16 to 19, this conventional solid-state imaging device includes a high-concentration N-type semiconductor substrate 301 and an N-type semiconductor layer 302 that is a low-concentration epitaxial layer formed on the semiconductor substrate 301. The base | substrate which consists of is provided. A plurality of pixels arranged in a two-dimensional matrix and a readout circuit are formed on the substrate.
[0006]
As shown in FIG. 20, each pixel includes an npn-type bipolar transistor Tr, a PMOSFET 303, and a capacitor Cox formed on the base of the bipolar transistor Tr.
[0007]
The read circuit includes a capacitor Ct for temporarily storing an output voltage from the emitter of the bipolar transistor Tr, a transfer MOSFET 304 for connecting the vertical output line VL and the capacitor Ct, and a vertical output line VL. And a reset MOSFET 305 for resetting.
[0008]
The operation of this pixel includes an accumulation operation, a read operation, and a reset operation.
[0009]
The accumulation operation starts when the reset operation is completed and the base-emitter of the bipolar transistor Tr is reverse-biased. In the depletion layer between the base region and the base-collector of the bipolar transistor Tr, holes generated by incident light are generated. The base potential rises as it accumulates in the base.
[0010]
The FET 305 is turned off to make the emitter of the bipolar transistor Tr floating. Next, when the potential φR of the horizontal drive line HL is positive and the base potential is raised in the positive direction by capacitive coupling through the capacitor Cox and the base and emitter of the bipolar transistor Tr are forward-biased, a read operation is performed. The emitter potential, which is a capacitive load, approaches the base potential up to a certain potential difference at the end of the read operation, so that the change in the base potential during the accumulation operation appears at the emitter terminal of the bipolar transistor Tr.
[0011]
The reset operation is a combination of two operations. The first reset functions to turn on the FET 305 and ground the base of the bipolar transistor Tr. Next, in the second reset, first, the gate potential φVC of the FET 305 is made positive, the emitter of the bipolar transistor Tr is grounded, and the potential φR is made positive. The base of the bipolar transistor Tr is lifted positive, the base and the emitter are forward biased, and the base potential is lowered by recombination of electrons and holes. When the potential φR returns to the ground level, the reset operation ends and the next accumulation operation starts.
[0012]
The structure of the pixel will be described with reference to FIGS. 16 to 19 again. 16 to 19, reference numeral 306 denotes a P-type diffusion region constituting a base, and 307 denotes a high-concentration N-type diffusion region constituting an emitter, which are an N-type semiconductor substrate 301 and an N-type semiconductor constituting a collector. The bipolar transistor Tr is configured together with the layer 302. A metal film 308 as a collector electrode is formed on the entire lower surface of the substrate 301. Therefore, the bipolar transistor Tr is an element that operates when power is supplied from the metal film 308 through the high-concentration N-type semiconductor substrate 301 and the low-concentration N-type semiconductor layer 302 in this order.
[0013]
Further, reference numeral 309 denotes relay wiring polysilicon, 310 denotes an Al wiring that constitutes the vertical output line VL, and 311 denotes a high-concentration N-type diffusion region that is arranged between pixels and serves as a pixel isolation region. Reference numeral 312 denotes polysilicon for driving the P-type diffusion region 306 serving as the base of the bipolar transistor Tr of the pixel by capacitive coupling via the oxide film capacitance Cox, and also functions as a gate electrode of the PMOSFET 303. The polysilicon 306 also constitutes the horizontal drive line HL. The PMOSFET 303 is formed in the pixel isolation region, and the polysilicon 312 which is the base thereof is shielded from light by the Al wiring 310. When the base (polysilicon 312) of the PMOSFET 303 is turned on, conduction is established between the bases (P-type diffusion layers 306) of the bipolar transistors Tr of adjacent pixels, and when the base of the PMOSFET 303 is turned off, the N-type diffusion region 311 serves as a pixel isolation region. Works. The overlapping portion of the polysilicon 312 and the P-type diffusion region 306 that is the base of the bipolar transistor Tr constitutes the capacitor Cox. In the figure, 313 is SiO. ₂ Membrane 314 is LOCOS.
[0014]
Thus, in the conventional solid-state imaging device, as described above, the bipolar transistor Tr is operated by being fed through the high-concentration N-type semiconductor substrate 301 and the low-concentration N-type semiconductor layer 302 in this order. Is done. As described above, only the N-type diffusion region 311 is formed between the pixels, and the cross-talk between the pixels is reduced by the N-type diffusion region 311, but the bipolar transistor Tr has a low concentration. A voltage cannot be applied without passing through the N-type semiconductor layer 302.
[0015]
[Problems to be solved by the invention]
In the conventional solid-state imaging device, when the detection sensitivity is to be extended to the longer wavelength side, the impurity concentration of the N-type semiconductor layer 302 is lowered to reduce the P-type base (P-type diffusion layer 306) of the bipolar transistor Tr. ) And the N-type collector (N-type semiconductor layer 302). However, in this case, since the resistance value increases by lowering the impurity concentration of the N-type semiconductor layer 302, the potential from the N-type semiconductor substrate 301 is not sufficiently transmitted to the N-type semiconductor layer 302, and the bipolar transistor As the performance of the Tr decreases, the variation increases, and the performance as a solid-state imaging device decreases.
[0016]
Such a situation is not limited to the conventional solid-state imaging device shown in FIGS. 16 to 20, but a high-concentration first conductive semiconductor substrate and a first low-concentration semiconductor substrate formed on the first conductive semiconductor substrate. A substrate comprising a conductive semiconductor layer is provided, a plurality of pixels are formed on the substrate, and each pixel is fed with power through the first conductive semiconductor substrate and the first conductive semiconductor layer in this order. The same applies to other solid-state imaging devices including elements that operate as described above, because the impurity concentration of the first conductivity type semiconductor substrate may need to be lowered for various reasons.
[0017]
The present invention has been made in view of the above circumstances, and can reduce the crosstalk between pixels, and the impurity concentration of a low-concentration semiconductor layer that forms an intermediate path for power feeding to elements constituting the pixel. It is an object of the present invention to provide a solid-state imaging device that can sufficiently supply power to the element even when the power is lowered to sufficiently exhibit the performance of the element.
[0018]
It is another object of the present invention to provide a manufacturing method suitable for manufacturing such a solid-state imaging device.
[0019]
[Means for Solving the Problems]
In order to solve the above-described problem, a solid-state imaging device according to a first aspect of the present invention includes a high-concentration first conductive semiconductor substrate and a low-concentration first conductive semiconductor formed on the first conductive semiconductor substrate. A plurality of pixels are formed on the substrate, and each pixel is operated by being supplied with power through the first conductive semiconductor substrate and the first conductive semiconductor layer in this order. In the solid-state imaging device including the element, a trench is formed in the base body from the surface of the first conductive semiconductor layer between the pixels, and the first conductive semiconductor substrate and the first conductive type are formed. One or more materials are embedded in the trench so that resistance between the semiconductor layer and the surface side region is reduced and crosstalk between the pixels is reduced. The high concentration and the low concentration do not necessarily mean that the impurity concentration is absolutely high or low, and the impurity concentration of the first conductivity type semiconductor layer is higher than the impurity concentration of the first conductivity type semiconductor substrate. Means relatively low. The order of feeding is not the order in which current flows, but the path for supplying a potential.
[0020]
According to the first aspect, in the base body, a trench is formed between the pixels from the surface of the first conductive semiconductor layer, and the first conductive semiconductor substrate and the first conductive semiconductor layer are formed on the base. One or more kinds of materials are embedded in the trench so that the resistance between the surface side region and the crosstalk between the pixels is reduced. Therefore, according to the first aspect, the resistance between the first conductivity type semiconductor substrate and the surface side region in the first conductivity type semiconductor layer is reduced in accordance with the characteristics of the one or more kinds of embedding materials. The potential drop between the two becomes small, and the crosstalk between the pixels is reduced. For this reason, not only can the crosstalk between the pixels be reduced, but also the impurities in the first-conductivity-type semiconductor layer having a low concentration that forms an intermediate path for supplying power to the elements constituting the pixels can be reduced for various reasons. Even so, sufficient power can be supplied to the element so that the performance of the element can be sufficiently exerted, and the performance as a solid-state imaging device is not impaired.
[0021]
The solid-state imaging device according to a second aspect of the present invention is the solid-state imaging device according to the first aspect, wherein the trench reaches the surface of the first conductive semiconductor layer side of the first conductive semiconductor substrate ( Including the case of exceeding the surface).
[0022]
A solid-state imaging device according to a third aspect of the present invention is the solid-state imaging device according to the first aspect, wherein the trench does not reach the surface of the first conductivity type semiconductor substrate.
[0023]
When the trench reaches the surface of the first conductivity type semiconductor substrate side of the first conductivity type semiconductor substrate as in the second aspect, the crosstalk and resistance can be reduced according to the characteristics of the one or more kinds of embedded materials. Since an effect increases further, it is preferable. However, as in the third aspect, the trench may not reach the surface of the first conductivity type semiconductor substrate on the first conductivity type semiconductor layer side. In this case, not only the effect of reducing crosstalk and resistance according to the depth of the trench can be obtained, but also the yield of the trench can be improved and the trench opening width can be reduced because the trench formation method is simplified. Become.
[0024]
The solid-state imaging device according to a fourth aspect of the present invention is the solid-state imaging device according to any one of the first to third aspects, wherein the trench has conductivity with respect to at least the first conductivity type semiconductor layer. It is embedded only with material. The conductive material having conductivity with respect to at least the first conductivity type semiconductor layer may be a complete conductor material such as a metal material, or may be a semiconductor or polysilicon having a first conductivity type impurity. In other words, any material may be used as long as it reduces the resistance when power is supplied to the element via the first conductive type semiconductor layer. This also applies to conductive materials in fifth to seventh embodiments described later.
[0025]
The solid-state imaging device according to a fifth aspect of the present invention is the solid-state imaging device according to any one of the first to third aspects, wherein the trench has conductivity with respect to at least the first conductivity type semiconductor layer. It is embedded with material and insulator.
[0026]
A solid-state imaging device according to a sixth aspect of the present invention is the solid-state imaging device according to any one of the first to third aspects, wherein the conductive material having conductivity with respect to at least the first conductivity type semiconductor layer is the trench. The trench is buried in a portion along the inner wall, and an insulator is buried in the remaining portion of the trench.
[0027]
A solid-state imaging device according to a seventh aspect of the present invention is the solid-state imaging device according to any one of the first to third aspects, wherein the portion along the bottom surface of the trench among the portions along the inner wall of the trench, and An insulating material is embedded in a portion other than a portion in the vicinity of the opening of the trench, and a conductive material having conductivity with respect to at least the first conductivity type semiconductor layer is embedded in the remaining portion of the trench.
[0028]
In the fourth to seventh aspects, examples of the embedding material and examples of arrangement in the trench are given.
[0029]
A solid-state imaging device according to an eighth aspect of the present invention is the solid-state imaging device according to any one of the fourth to eighth aspects, wherein the conductive material is polysilicon having a first conductivity type impurity.
[0030]
In the eighth aspect, polysilicon is used as an example of the conductive material. However, as described above, the conductive material is not limited to polysilicon.
[0031]
A solid-state imaging device according to a ninth aspect of the present invention is the solid-state imaging device according to any one of the fourth to eighth aspects, wherein the conductive material is disposed outside the trench along a portion along the inner wall of the trench. In addition, a first conductivity type diffusion layer is formed.
[0032]
When the first conductivity type diffusion layer is formed outside the trench as in the ninth aspect, the first conductivity type diffusion layer also promotes the effect of reducing the resistance, which is preferable. When polysilicon is used as at least one of the filling materials in the trench as in the eighth aspect, the first conductivity type diffusion layer is formed by annealing after filling the polysilicon.
[0033]
A solid-state imaging device according to a tenth aspect of the present invention is the solid-state imaging device according to any one of the first to ninth aspects, wherein the first conductivity type semiconductor layer is an epitaxial layer.
[0034]
In the tenth aspect, an example of the first conductivity type semiconductor layer is given. In the first to ninth aspects, the first conductivity type semiconductor layer is not limited to the epitaxial layer.
[0035]
A solid-state imaging device according to an eleventh aspect of the present invention is the solid-state imaging device according to any one of the first to tenth aspects, wherein the element is an amplification element.
[0036]
A solid-state imaging device including an amplifying element in a pixel accumulates a signal charge photoelectrically converted according to the amount of incident light in an amplifying element provided for each pixel, and amplifies and outputs a signal corresponding to the accumulated charge. Therefore, the sensitivity is increased, which is preferable.
[0037]
A solid-state imaging device according to a twelfth aspect of the present invention is a method of manufacturing the solid-state imaging device according to any one of the first to eleventh aspects, the step of forming the trench in the base, In addition, a step of forming one or more films each made of the one or more materials so as to fill the trench, and a step of removing a portion outside the trench in the one or more films by a CMP method And.
[0038]
According to the twelfth aspect, one or more films are formed so as to fill the trenches, and portions outside the trenches in the one or more films are removed by the CMP method. The one or more films can be removed at the same time, and the film inside the trench can be formed without over-etching, so that the upper part of the trench can be formed flat, and a subsequent process of forming Al wiring or the like The yield can also be improved.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a solid-state imaging device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings.
[0040]
[First Embodiment]
First, a solid-state imaging device according to a first embodiment of the present invention will be described with reference to FIGS.
[0041]
FIG. 1 is a schematic plan view showing a solid-state imaging device according to the present embodiment, and shows a state in which a plurality of pixels are arranged on a two-dimensional matrix. FIG. 2 is a schematic plan view showing unit pixels of the solid-state imaging device according to the present embodiment, and is an enlarged view of a part of FIG. FIG. 3 is a schematic cross-sectional view taken along line X1-X2 in FIG. 4 is a schematic cross-sectional view taken along line Y1-Y2 in FIG. FIG. 5 is a schematic cross-sectional view taken along line Y3-Y4 in FIG. FIG. 6 is a schematic cross-sectional view taken along line X3-X4 in FIG. In addition, FIG. 6 is not drawn in the magnitude | size proportional to FIGS. 3-5 which are other sectional drawings for easy understanding. FIG. 7 is a circuit diagram showing a schematic configuration of the solid-state imaging device according to the present embodiment. FIG. 8 is a pulse timing chart for explaining the operation of the solid-state imaging device according to the present embodiment.
[0042]
In the following description of the present embodiment, the description will be divided into “basic structure”, “circuit configuration”, “operation”, and “characteristic structure and manufacturing method”.
[0043]
(Basic structure)
As shown in FIGS. 1 to 6, the solid-state imaging device according to the present embodiment includes a high-concentration N-type semiconductor substrate 101 and a low-concentration N-type epitaxial layer formed on the semiconductor substrate 101. A base including the semiconductor layer 102 is provided. The substrate is formed with a plurality of pixels arranged in a two-dimensional matrix (in the present invention, it may be arranged in a one-dimensional manner), a readout circuit described later with reference to FIG. Yes.
[0044]
Each pixel (unit pixel) is shown in FIG. 1 to FIG. 7 (refer to FIG. 1 to FIG. 6 for the structure of the pixel, and FIG. 7 for the circuit configuration of the pixel). A photodiode 1 for generating and storing electric charge; a junction field effect transistor (hereinafter referred to as “JFET”) 2 as an amplifying element for receiving the electric charge of the photodiode 1 at the gate region 15 and amplifying and outputting the same; , A transfer gate 3 formed of a polysilicon film for transferring charges generated and stored in the photodiode 1 to the gate region 15 of the JFET 2, and charges generated excessively in the photodiode 1 are discharged, and the gate region 15 of the JFET 2 is discharged. A reset drain 4 that controls the potential of the photodiode, an overflow control region 6a that guides the charge generated excessively by the photodiode 1 to the reset drain 4, A reset gate 5 which by FET2 polysilicon film that controls an electrical connection state between the gate region 15 and the reset drain 4, is mainly composed.
[0045]
In the present embodiment, the JFET 2 is an element that operates when power is supplied through the N-type semiconductor substrate 100 and the N-type semiconductor layer 101 in this order. That is, the JFET 2 operates by supplying power to the N-type drain region 16 through the N-type semiconductor substrate 100 and the N-type semiconductor layer 101 in this order.
[0046]
The photodiode 1, JFET 2, reset drain 4 and overflow control region 6a are formed in an N-type semiconductor layer 101 formed on a high-concentration N-type semiconductor substrate 100, and the transfer gate 3 and the reset gate 5 are N-type. SiO on the semiconductor layer 101 ₂ It is formed through an insulating film 102 such as a film.
[0047]
The photodiode 1 includes a P-type charge storage region 12 formed in an N-type semiconductor layer 101 on a high-concentration N-type semiconductor substrate 100 and a high-concentration formed near the semiconductor surface above the P-type charge storage region 12. The N-type semiconductor region 13 and the N-type semiconductor layer 101 generate and store charges corresponding to incident light. In the present embodiment, the impurity concentration of the N-type semiconductor layer 101 is lowered in order to increase the sensitivity of the photodiode 1 by increasing the detection sensitivity on the long wavelength side by expanding the depletion layer. .
[0048]
The JFET 2 includes a P-type gate region 15 formed in the N-type semiconductor layer 101, an N-type source region 14 and an N-type channel region 17 formed in the P-type gate region 15, and the N-type channel region. An N-type drain region 16 formed at a position facing the source region 14 across 17 is received by the gate region 15 and amplified and output.
[0049]
The N-type drain region 16 of the JFET 2 is also formed in the peripheral region of the pixel (except for the vicinity of the semiconductor surface below the transfer gate 3 and the reset gate 5) and also serves as an isolation region. Along the portion of the N-type drain region 16 formed in the peripheral region of the pixel (except for some portions such as the vicinity of the overflow control region 6a), the drain region 16 is left on both sides in the width direction. A pixel isolation region 110 is formed by the trench 111 so as to remove the N-type drain region 16. The pixel isolation region 110 formed between the pixels reduces crosstalk between the pixels, and at the same time, the surface side region in the N-type semiconductor substrate 100 and the N-type semiconductor layer 101 (in this embodiment, the drain region of JFET 2). 16), which is particularly important in the present invention and will be described in detail later. Note that the drain region 16 where the pixel isolation region 110 is formed is not necessarily formed. The N-type drain region 16 of the JFET 2 is formed continuously with the high-concentration N-type semiconductor region 13 formed near the surface of the photodiode 1. Further, the N-type region (13, 101) of the PN junction constituting the photodiode 1 and the N-type drain region 16 of the JFET are electrically connected. Further, the N-type drain region 16 is electrically connected to the high-concentration N-type semiconductor substrate 100 via the N-type semiconductor layer 101 and the pixel isolation region 110. Although not shown in the drawing, a drain electrode (not shown) formed on the substrate surface side around a pixel region in which each pixel is arranged in a matrix is further passed through a high-concentration N-type semiconductor substrate 100 and further. The drain voltage (potential) is supplied to the drain region 16 of the JFET 2 of each pixel via the N-type semiconductor layer 101 and the pixel isolation region 110. However, as in the conventional solid-state imaging device shown in FIGS. 16 to 20 described above, a drain electrode may be formed on the back surface of the substrate 100, and a drain voltage may be supplied from this drain electrode to the JFET 2 of each pixel. Of course.
[0050]
The P-type gate region 15 of the JFET 2 is formed so as to sandwich the N-type channel region 17 from above and below, and has a structure that increases the gain of the source follower operation and suppresses gain variation.
[0051]
The transfer gate 3 is composed of a gate electrode formed through an insulating film on the boundary region between the P-type charge storage region 12 of the photodiode 1 and the P-type gate region 15 of the JFET 2, and the P-type charge of the photodiode 1 is formed. The charges accumulated in the accumulation region 12 are transferred to the P-type gate region 15 of the JFET 2.
[0052]
That is, a P-channel MOS transistor is formed by the P-type region (P-type charge storage region 12) of the PN junction constituting the photodiode 1, the transfer gate 3, and the P-type gate region 15 of the JFET 2.
[0053]
The reset drain 4 is composed of a P-type charge discharge region 18 formed in the N-type semiconductor layer 101, discharges an excessive charge generated by the photodiode 1, and also passes through the reset gate 5 to JFET 2. The potential of the P-type gate region 15 is controlled.
[0054]
The reset gate 5 is composed of a gate electrode formed on the boundary region between the P-type gate region 15 of the JFET 2 and the P-type charge discharging region 18 of the reset drain 4 via the insulating film 102, and the P-type gate region of the JFET 2 15 and the P-type charge discharge region 18 of the reset drain 4 are controlled.
[0055]
That is, the P-type MOS region is constituted by the P-type gate region 15 of the JFET 2, the reset gate 5, and the P-type charge discharging region 18 of the reset drain 4.
[0056]
The overflow control region 6a is composed of a P-type semiconductor region formed inside the semiconductor layer 101 in the boundary region between the P-type charge accumulation region 12 of the photodiode 1 and the P-type charge discharge region 18 of the reset drain 4. 1 controls the overflow operation that leads the charge generated excessively to 1 to the charge discharge region 18 of the reset drain 4. A high concentration N-type semiconductor region 16 (same as the N-type drain region 16 of JFET 2) is formed in the vicinity of the semiconductor surface above the overflow control region 6a.
[0057]
That is, the P-type charge accumulation region 12, the P-type overflow control region 6a of the photodiode 1 and the P-type charge discharge region 18 of the reset drain are used as a source region, a channel region, and a drain region, respectively, and a high-concentration N-type semiconductor region. A P-channel JFET having the gate region of 16 and the N-type semiconductor layer 101 is formed.
[0058]
This P-channel JFET is in a cut-off (cut-off) state when the photodiode 1 is performing a standard operation, and a certain amount of light is incident on the P-type charge storage region 12 when strong light is incident on the photodiode 1. When the above charges (in this case, positive charges due to holes) are accumulated, that is, when the potential of the P-type charge accumulation region 12 rises above a certain level, it is formed to be in a conductive (ON) state. .
[0059]
Therefore, the charge generated excessively by the photodiode 1 flows out to the P-type charge discharge region 18 of the reset drain 4 via the overflow control region 6a. This excess charge is discharged from the reset drain wiring 24 made of Al via the reset drain contact hole 30, the relay wiring 23 made of Al wiring, and the relay wiring connection hole 31.
[0060]
A high-concentration N-type semiconductor region 16 (same as the N-type drain region 16 of JFET 2) formed near the semiconductor surface above the overflow control region 6a is a high-concentration N-type formed near the surface of the photodiode 1. It is formed continuously with the semiconductor region 13.
[0061]
Therefore, the vicinity of the semiconductor surface of the P-type charge accumulation region 12 of the photodiode 1 is covered with the high-concentration N-type semiconductor regions (13 and 16) including the surrounding region. The photodiode 1 is an embedded photodiode. It has become.
[0062]
Note that the high-concentration N-type semiconductor regions (13 and 16) are not formed on the end of the photodiode 1 on the transfer gate 3 side and the lower part of the transfer gate 3, but the performance of the embedded photodiode (semiconductor Low dark current characteristics due to non-depletion of the surface) are maintained. This is because, during the period in which the photodiode 1 performs the signal charge accumulation operation by photoelectric conversion, the transfer gate 3 is cut off (off) and a high-level pulse voltage is applied. This is because electrons are induced in the vicinity of the semiconductor surface to form a high concentration N-type semiconductor region.
[0063]
As described above, the photodiode 1 is a buried type photodiode having a JFET type lateral overflow drain structure. Similar to the buried photodiode having a vertical overflow drain structure, the photodiode 1 has blooming, smearing, and the like. The blurring phenomenon such as the above can be suppressed, and the dark current is suppressed because the depletion layer generated in the PN junction does not reach the semiconductor surface by the embedded photodiode. In addition, since no charge remains in the photodiode after the charge is transferred (due to complete transfer or complete depletion), ideal characteristics with reduced afterimage and reset noise can be obtained.
[0064]
More preferably, the P-type charge accumulation region 12 and the P-type overflow control region 6a of the photodiode 1 are formed in the same manufacturing process. This is because the discontinuity of the impurity concentration does not occur at the connection portion between the P-type charge accumulation region 12 and the P-type overflow control region 6a of the photodiode 1 (the high concentration region does not occur due to the overlapping of both). This is because the complete depletion characteristic of the P-type charge storage region 12 can be easily obtained and the manufacturing process is simplified.
[0065]
In addition, a transfer gate wiring 20 made of a polysilicon film, a reset gate wiring 21 made of a polysilicon film, a relay wiring 23, a reset drain wiring 24, and a vertical signal line 22 made of an Al wiring are also formed as shown in the figure. That is, the N-type source region 14 of each JFET 2 is commonly connected in the vertical scanning direction by the vertical signal line 22. The transfer gate 3 is connected in common in the horizontal scanning direction by the transfer gate wiring 20 and the reset gate 5 by the reset gate wiring 21. The charge drain region 18 of the reset drain 4 is commonly connected in the horizontal scanning direction by the reset drain wiring 24 via the contact hole 30, the relay wiring 23, and the relay wiring connecting hole 31. The reset drain wiring 24 also serves as a light shielding film that shields light other than the photodiode 1.
[0066]
By the way, the P-type gate region 15 of the JFET 2 and the P-type charge discharging region 18 of the reset drain 4 are alternately arranged adjacent to each other in the horizontal scanning direction, and the reset gate 5 is interposed on the boundary region between them via an insulating film. Arranged without leaking. That is, two reset gates 5 are formed per pixel. A P-channel MOS transistor composed of a P-type gate region 15 of JFET 2, a reset gate 5 and a P-type charge drain region 18 of reset drain 4 is connected in series in the horizontal scanning direction. Yes.
[0067]
Therefore, when the reset gate 5 becomes conductive (ON), the P-type gate regions 15 of the JFETs 2 and the P-type charge discharge regions 18 of the reset drains 4 alternately arranged in the horizontal scanning direction All are electrically connected.
[0068]
As a result, even if a failure in the release mode in which the connection between the reset drain wiring 24 and the reset drain 4 becomes incomplete in a certain pixel occurs, the MOS from the reset drain 4 of another pixel arranged in the horizontal scanning direction. The gate region of the JFET is correctly controlled via the transistor.
[0069]
The P-type charge accumulation region 12 of the photodiode 1 and the P-type charge discharge region 18 of the reset drain 4 are alternately arranged adjacent to each other in the vertical scanning direction, and the overflow control region 6a is formed in the boundary region between them. ing. That is, when intense light is incident on the photodiode 1 of a certain pixel and excessive charge is generated, two overflow control regions 6a that lead the excessive charge to the reset drain 4 are formed in the vertical scanning direction. Overflow operation is possible in two paths for one photodiode.
[0070]
(Circuit configuration)
Next, the circuit configuration of the solid-state imaging device according to the present embodiment will be described with reference to FIG.
[0071]
As can be seen from the above description of the structure, each pixel serving as a unit pixel includes a photodiode 1, a JFET 2, a transfer gate 3, a reset drain 4, and a reset gate 5 present at a rate of two per pixel. Has been. The N-type region (101 and 13) of the photodiode 1 (not shown in FIG. 7) is electrically connected to the drain region 16 of JFET 2 (indicated by “D” in FIG. 7), and The P-type MOS transistor is constituted by the P-type region 13 (not shown in FIG. 7) of the photodiode 1 and the transfer gate 3 and the gate region 15 (not shown in FIG. 7) of the JFET 2. . Further, there are two P-channel MOS transistors composed of the gate region 15, the reset gate 5 and the reset drain 4 of the JFET 2 per pixel, and are connected in series in the horizontal scanning direction. .
[0072]
Although not explicitly shown in the circuit shown in FIG. 7, the photodiode 1 has a lateral type due to an overflow control region 6 a (not shown in FIG. 7) and a reset drain 4 that exist at a rate of two per pixel. An overflow drain structure is formed, and has a function of discharging excess charges to the reset drain 4 through two paths with respect to one photodiode 1. This excess charge is finally absorbed by the vertical scanning circuit 7 via the reset drain wirings 24a to 24c (corresponding to the reset drain wiring 24a in FIGS. 1 to 5).
[0073]
The source regions 14 of each JFET 2 (indicated by reference sign “S” in FIG. 7) are commonly connected by vertical signal lines 22a to 22d for each column of the matrix arrangement.
[0074]
As described above, the drain region 16 (D) of each JFET 2 is connected to the drain power supply VD in common for all pixels.
[0075]
The transfer gate 3 is connected in common in the horizontal scanning direction and connected to the vertical scanning circuit 7 by transfer gate wirings 20a to 20c (corresponding to the transfer gate wiring 20 in FIG. 5) for each row of the matrix arrangement. Then, the pulses φTG1 to φTG3 sent from the vertical scanning circuit 7 operate for each row.
[0076]
The reset gate 5 is commonly connected in the horizontal scanning direction for each row of the matrix arrangement by reset gate wirings 21a to 21c (corresponding to the reset gate wiring 21 in FIGS. 1, 2, 4, and 5). The reset gate lines 21a to 21c are all connected in common around the matrix arrangement (left end or right end). Then, all the pixels are operated simultaneously by the drive pulse φRG.
[0077]
The reset drain 4 is commonly connected in the horizontal scanning direction and connected to the vertical scanning circuit 7 by reset drain wirings 24a to 24c (corresponding to the reset drain wiring 24 in FIGS. 1 to 5) for each row of the matrix arrangement. ing. And it is driven by pulses φRD1 to φRD3 sent from the vertical scanning circuit 7.
[0078]
On the other hand, the vertical signal lines 22a to 22d (corresponding to the reset gate wiring 21 in FIGS. 1 to 4 and 6) include the optical signal output transfer MOS transistors TS1 to TS4 and the dark output transfer MOS transistors TD1 to TD4. Are connected to the optical signal output storage capacitors CS1 to CS4 and the dark output storage capacitors CD1 to CD4 through the horizontal selection MOS transistors THS1 to THS4 and THD1 to THD4, and then to the horizontal signal lines 27a (signal output lines) and 27b. (Dark output line).
[0079]
The MOS transistors TS1 to TS4 and TD1 to TD4 are operated by drive pulses φTS and φTD, respectively. Further, the MOS transistors THS1 to THS4 and THD1 to THD4 are sequentially operated by pulses φH1 to φH4 sent from the horizontal scanning circuit 8.
[0080]
Output buffer amplifiers 28a and 28b and horizontal signal line reset MOS transistors TRHS and TRHD are connected to the horizontal signal lines 27a and 27b. The MOS transistors TRHS and TRHD are operated by the drive pulse φRH. Further, parasitic capacitances CHS and CHD exist in the horizontal signal lines 27a and 27b.
[0081]
On the other hand, the vertical signal lines 22a to 22d are connected to the reset signal MOS transistors TRV1 to TRV4 and the constant current sources 26a to 26d of the vertical signal line. The reset signal MOS transistors TRV1 to TRV4 of the vertical signal line are operated by the drive pulse φRV.
[0082]
(Operation)
Next, the operation of the solid-state imaging device according to the present embodiment will be described with reference to FIGS. As already described, since the transfer gate 3 and reset gate 5 of each pixel constituting the unit pixel are P-channel type, in FIGS. 7 and 8, φTG1 to φTG3 and φRG are polarities of other pulses. Is reversed. That is, when these pulses are at a low level, the corresponding transfer gate 3 or reset gate 5 is turned on (on), and when these pulses are at a high level, they are turned off (off).
[0083]
In FIG. 8, the period from t11 to t15 indicates the pixel readout operation of the first row, and the period from t21 to t25 and t31 to t35 corresponds to the second row and the third row, respectively. is doing. In addition, t11 to t14, respectively, t11 is a row selection operation and an initialization operation of JFET2, t12 is a source follower operation of JFET2 in the first row after initialization, t13 is a first-row photodiode 1 to JFET2 The signal charge transfer operation to, and t14 is a period corresponding to the source follower operation of the JFET 2 in the first row after the signal charge transfer, and these four operations are performed within the horizontal blanking period. T15 is a video signal output period.
[0084]
First, at the beginning of the period t11, the drive pulse φRD1 is set to the high level (the drive pulses φRD2 and φRD3 remain at the low level), and the high-level voltage is applied to the reset drain 4 of the pixels in the first row. A low level voltage is applied to the reset drain 4 in the third row. Then, a high level voltage is applied to the gate region of the JFET 2 of the pixel in the first row via the reset gate 5 of all the pixels to which the low level φRG is applied and is already conductive (ON). The low level voltage is transmitted to the gate region of the JFET 2 of the pixels in the second and third rows, the JFET 2 in the first row is turned on (selected), and each JFET 2 in the second row and thereafter is turned off ( (Not selected) state.
[0085]
Then, at the end of the period t11, the drive pulse φRG is set to the high level and the reset gates 5 of all the pixels are turned off (off), whereby the gate region of each JFET 2 is turned on (selected) and turned off (selected). The non-selected state is kept floating. That is, the gate region 15 of the JFET 2 in the selected row is initialized to the high level potential, and the gate region 15 of the JFET 2 in the non-selected row is initialized to the low level potential.
[0086]
In the operation during this period t11, the solid-state imaging device according to the present embodiment has the P-channel MOS transistor constituted by the gate region 15, the reset gate 5 and the reset drain 4 of the JFET 2 connected in series in the horizontal scanning direction. Even if a failure in the release mode in which the connection between the reset drain 4 and the reset drain wirings 24a to 24c is incomplete in a certain pixel occurs, the MOS transistor is connected to another reset drain 4 arranged in the horizontal scanning direction. Via, the gate region 15 of the JFET 2 is correctly controlled, and is initialized to a high level potential for a selected row and to a low level for a non-selected row.
[0087]
In the period t12, the drive pulse φRV is set to a low level to turn off the reset transistors TRV1 to TRV4, and each JFET 2 in the first row performs a source follower operation. During this period t12, the drive pulse φTD is at a high level and the dark output transfer MOS transistors TD1 to TD4 are in a conductive (ON) state, corresponding to the potential immediately after the initialization of the gate region 15 of each JFET2. The output (dark output) voltage is charged to the dark output storage capacitors CD1 to CD4.
[0088]
In the period t13, the driving pulse φTG1 is set to the low level (the driving pulses φTG2 and φTG3 remain at the high level), the transfer gates 3 of the pixels in the first row are turned on, and the photodiodes in the first row are set. The signal charge generated and accumulated in 1 is transferred to the gate region 15 of JFET 2. Note that the potential of the gate region 15 of the JFET 2 after transferring the signal charge changes (in this case, rises) by the amount of signal charge / gate capacitance.
[0089]
At the end of the period t13, when the drive pulse φTG1 is set to the high level to turn off the transfer gate 3, the photodiode 1 in the first row enters the next signal charge accumulation operation by photoelectric conversion. In FIG. 8, tLI indicates the charge accumulation time of the photodiode.
[0090]
In the period t14, similarly to the period t12, the drive pulse φRV is set to the low level to turn off the reset transistors TRV1 to TRV4, and each JFET 2 in the first row performs the source follower operation. During this period t14, the drive pulse φTS is at a high level and the optical signal output transfer MOS transistors TS1 to TS4 are in a conductive (ON) state, corresponding to the potential after the charge is transferred to the gate region 15 of each JFET2. The output (signal output) voltage is charged in the optical signal output storage capacitors CS1 to CS4.
[0091]
The constant current sources 26a to 26d serve as loads for the source follower operation in the periods t12 and t14, and control the operating point and operating speed of the JFET.
[0092]
The charge amplification factor of the source follower operation is determined by the ratio (CS / Cg) between the optical signal output storage capacitors CS1 to CS4 and the gate capacitance Cg of the JFET, and obtains a high amplification factor of several hundred times to a thousand times or more. Is possible.
[0093]
In addition, since this source follower operation is performed for each row in the horizontal blanking period, the time for the amplification operation is longer than that for pixels amplified for each pixel in synchronization with horizontal scanning (for example, φH1 to φH4). The operating band can be narrowed by one to two digits by increasing the capacitance values of the optical signal output storage capacitors CS1 to CS4 and the dark output storage capacitors CD1 to CD4. Therefore, it is possible to significantly suppress noise accompanying the amplification operation.
[0094]
In the period t15, the driving pulses φH1 to φH4 are sequentially output from the horizontal scanning circuit 8, and the charges accumulated in the optical signal output storage capacitors CS1 to CS4 and the dark output storage capacitors CD1 to CD4 are respectively transferred to the horizontal signal line 27a. (Signal output lines) and 27b (dark output lines), and the video signals are output from the output terminals VOS and VOD via the output buffer amplifiers 28a and 28b. In addition, the drive pulse φRH is sequentially output to reset the horizontal signal lines (27a, 27b).
[0095]
Video signals obtained from the output terminals VOS and VOD are subtracted by an external arithmetic circuit (not shown). This is because the video signal obtained from the output terminal VOS contains an optical signal component (S) and a dark component (D), and the video signal obtained from the output terminal VOD contains only a dark component (D). Therefore, by subtracting the video signals obtained from the output terminals VOS and VOD (VOS-VOD), only the video signal corresponding to the optical signal component is extracted.
[0096]
Dark components included in both VOS and VOD include fixed pattern noise due to variations in threshold voltage of each JFET 2, and reset noise generated when the gate region 15 of JFET 2 is initialized from the reset drain 4 through the reset gate 5. , 1 / f noise and the like generated during the source follower operation by the JFET 2 and the constant current source (26a to 26d).
[0097]
That is, by subtracting VOS and VOD, it is possible to extract only the optical signal component from which the noise component has been removed, and the S / N ratio is improved.
[0098]
The reading operation of the first row for the period t11 to the period t15 described above is repeated for the second row and the third row in the periods t21 to t25 and the periods t31 to t35, respectively. Is called.
[0099]
In FIG. 8, the drive pulse (φRD1 to φRD3) of the reset drain 4 is at the low level for most of the period, and the excessive charge generated in the photodiode 1 is reset to the low level via the overflow control region 6a. It flows out to the drain 4.
[0100]
However, during the period t11 to t14, the drive pulse φRD1 is at the high level (φRD2 and φRD3 are in the low level state), so the overflow operation for the reset drain 4 in the first row is stopped (or the state is changed). To do.
[0101]
The overflow operation for the reset drain 4 in the second and third rows at t21 to t24 and t31 to t34 is the same.
[0102]
However, in the solid-state imaging device according to the present embodiment in which an overflow operation is possible in two paths in the vertical scanning direction with respect to one photodiode 1, a case where one path temporarily stops the overflow operation However, since the overflow operation is normally performed in the other path, the bleeding phenomenon such as blooming and smear can be suppressed.
[0103]
As described above, the photodiode 1, JFET 2, transfer gate 3, reset drain 4, two reset gates 5 per pixel, and two overflow control regions 6 a per pixel are arranged in a matrix. Since the solid-state imaging device according to the present embodiment employs a buried photodiode with a lateral overflow drain structure, dark current, afterimage, reset noise, blooming and smear are suppressed, and optical signal output accumulation is performed. The narrow-band source follower operation of the JFET 2 using the capacitor and the dark output storage capacitor as a load realizes a high charge amplification factor and suppresses noise during the amplification operation. Furthermore, by subtracting VOS and VOD, fixed pattern noise due to variations in the threshold voltage of JFET2, reset noise generated when the gate region of JFET2 is initialized, 1 / f noise during source follower operation, and the like. Be suppressed. Therefore, a video signal with high sensitivity and low noise (high S / N ratio) can be obtained.
[0104]
Further, in the solid-state imaging device according to the present embodiment, since the drain wiring is deleted, the defect due to the short circuit mode between the drain wiring and the vertical signal line is eliminated, and the manufacturing yield is improved.
[0105]
In addition, even if a failure occurs in the release mode where the connection between the reset drain and the reset drain wiring is incomplete, the gate region of the JFET is correctly controlled, thereby reducing vertical line-shaped image defects and improving the manufacturing yield. To do.
[0106]
Further, since the light receiving aperture ratio of the photodiode 1 increases, the sensitivity is improved.
[0107]
In addition, since charges generated in the deep part of the photodiode 1 by photoelectric conversion are also accumulated in the photodiode 1, sensitivity (particularly sensitivity to light having a long wavelength) is improved.
[0108]
(Characteristic structure and manufacturing method)
Next, the pixel isolation region 110 by the trench 111, which is a characteristic structure of the solid-state imaging device according to the present embodiment, will be described in detail with reference to FIG. 1, FIG. 2, FIG.
[0109]
As already described, in the present embodiment, the pixel isolation region 110 is a portion of the N-type drain region 16 formed in the peripheral region of the pixel (however, the overflow control region 6a as shown in FIGS. 1 and 2). The N-type drain region 16 is formed so as to remove the N-type drain region 16 except for both side portions of the drain region 16 in the width direction. The drain region 16 where the pixel isolation region 110 is formed is not necessarily formed. In this case, the area of the photodiode 1 can be enlarged, which is preferable.
[0110]
In the present embodiment, as shown in FIGS. 4 and 6, the pixel isolation region 110 is composed of polysilicon 112 containing N-type impurities embedded in the trench 111 and an N-type diffusion layer 113. .
[0111]
The trench 111 is formed in the N-type semiconductor layer 101 at a depth just reaching the surface on the N-type semiconductor layer 101 side of the N-type semiconductor substrate 100 from the surface of the N-type semiconductor layer 101. However, the trench 111 may be further deepened so that the trench 111 reaches the inside of the N-type semiconductor substrate 100.
[0112]
The trench 111 is filled only with polysilicon 112 containing N-type impurities. In the present embodiment, the N-type diffusion layer 113 is due to the N-type impurities contained in the polysilicon 112. N-type diffusion layer 113 is formed outside trench 111 along a portion of polysilicon 112 along the inner wall of trench 111. That is, in this embodiment, since the trench 111 is embedded only with the polysilicon 112, the N-type diffusion layer 113 is formed outside the trench 111 along the entire inner wall of the trench 111.
[0113]
By forming the pixel isolation region 110, crosstalk between pixels is reduced (that is, pixel isolation), and the surface side region in the N-type semiconductor substrate 100 and the N-type semiconductor layer 101 (in this embodiment, Reduction of the resistance between the drain region 16 and the like of the JFET 2 is achieved at the same time.
[0114]
That is, since the carrier diffusion length in the polysilicon 112 is extremely short, the amount of photogenerated charges generated in adjacent pixels, that is, the amount of mixed carriers, that is, the amount of crosstalk can be significantly reduced. This is a significant advantage over the conventional pixel separation technique in which the pixel separation region is formed by a diffusion region.
[0115]
Further, since the polysilicon 112 containing the N-type impurity serves as a connection path for electrically connecting the high-concentration N-type semiconductor substrate 100 and the N-type drain region 16 of the JFET 2, the N-type semiconductor substrate 100 and the drain region Compared with the case where 16 is electrically connected via the low-concentration N-type semiconductor layer 101, the resistance between the two is remarkably reduced. Therefore, in this embodiment, the drain voltage is supplied from the N-type semiconductor substrate 100 as described above, but the potential drop to the drain region 16 is reduced. Therefore, as described above, the impurity concentration of the N-type semiconductor layer 101 is lowered in order to increase the detection sensitivity on the long wavelength side by expanding the depletion layer and increase the sensitivity of the photodiode 1, but the characteristics of the JFET 2 are There is no risk of instability. The impurity concentration of polysilicon 112 is preferably high.
[0116]
Instead of the polysilicon 112, another conductive material having conductivity with respect to at least the N-type semiconductor layer 101, such as a metal, may be embedded.
[0117]
By the way, the pixel isolation region 110 may be modified as shown in FIGS.
[0118]
9 to 11 are schematic cross-sectional views showing other structural examples of the pixel isolation region 110, and correspond to the cross-sectional view of FIG. 9 to 11, elements that are the same as or correspond to those in FIG. 6 are given the same reference numerals, and redundant descriptions thereof are omitted.
[0119]
The pixel isolation region 110 shown in FIG. 9 is different from the pixel isolation region 110 shown in FIG. 6 only in that the trench 111 does not reach the surface of the N-type semiconductor substrate 100 on the N-type semiconductor layer 101 side. In this case, not only the effect of reducing crosstalk and resistance according to the depth of the trench 111 is obtained, but also the method of forming the trench 111 is simplified compared to the pixel isolation region 110 shown in FIG. In addition, the yield can be improved and the opening width of the trench 111 can be reduced.
[0120]
The pixel isolation region 110 shown in FIG. 10 is different from the pixel isolation region 110 shown in FIG. 6 in that polysilicon 112 is embedded in a portion along the inner wall of the trench 111 and an oxide film or nitride film is formed in the remaining portion of the trench 111. It is only a point where the insulator 114 such as is embedded. In this case, a reduction in resistance is achieved by the polysilicon 112, and a complete suppression of crosstalk is achieved by the insulator 114. Crosstalk is completely suppressed by the insulating film 114 because carriers generated deeper than the high-concentration N-type semiconductor substrate 100 are absorbed by the high-concentration N-type semiconductor substrate 100 and substantially act as signal charges. This is because the carriers generated at a relatively shallow depth from the N-type semiconductor substrate 100 are completely separated from the adjacent pixels by the insulating film 114, so that the carriers are not mixed into the adjacent pixels.
[0121]
The pixel isolation region 110 shown in FIG. 11 differs from the pixel isolation region 110 shown in FIG. The only difference is that an insulator 114 such as an oxide film or a nitride film is buried in the removed portion, and polysilicon 112 is buried in the remaining portion of the trench 111. The N-type diffusion layer 113 made of N-type impurities contained in the polysilicon 112 is formed outside the trench 111 along a portion along the inner wall of the trench 111 in the polysilicon 112. In this case, as in the case of the pixel isolation region 110 shown in FIG. 10, the resistance is reduced by the polysilicon 112 and the crosstalk is completely suppressed by the insulator 114.
[0122]
Next, an example of a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS. 12 and 13, focusing on the method for forming the pixel isolation region 110. However, FIGS. 12 and 13 show a manufacturing method in the case where the pixel separation region 110 having the structure shown in FIG. 10 is adopted, and shows a cross section corresponding to FIG. 10 (and hence FIG. 6).
[0123]
First, an N-type semiconductor layer 101 is grown as a low-concentration epitaxial layer on a high-concentration N-type semiconductor substrate 100. Next, the trench 111 is formed by dry etching using the oxide film mask 201 as a trench formation mask (FIG. 12A).
[0124]
Next, a polysilicon film 112 is deposited on the substrate in the state shown in FIG. In this example, this deposition is performed so that the polysilicon film 112 is formed in a portion along the inner wall of the trench 111 (FIG. 12B). As described above, when the trench 111 is not completely filled with the polysilicon film 112, the N-type impurity is doped into the polysilicon film 112 by the diffusion using the liquid source source or the like after the deposition even when the deposition is performed. May be. On the other hand, when the pixel isolation region 110 shown in FIG. 6 is formed, the polysilicon film 112 is completely buried in the trench 111. In this case, N-type impurities are doped into the polysilicon film 112 at the time of deposition. It is preferable to do.
[0125]
Next, an oxide film 114 is formed on the substrate in the state shown in FIG. 12B so that the remaining portion of the trench 111 is completely buried (FIG. 12C). This step may be an oxide film deposition by a CVD method or dry oxidation of the polysilicon film 112, but long-time dry oxidation is not preferable because it may induce defects.
[0126]
Thereafter, the oxide film 114 is removed by the CMP method (FIG. 13A), and then the polysilicon film 112 and the oxide film 201 outside the trench 111 are simultaneously removed by the CMP method (FIG. 13B). ). The two-stage CMP may be performed under the same conditions, but at least in the latter CMP, the polishing rates of the oxide film 201 and the polysilicon film 112 are equal, or the polishing rate of the oxide film 201 is slightly low. preferable.
[0127]
Further, although not shown in the drawing, the P-type charge accumulation region 12 of the photodiode 1 is formed by a normal photolithography, implantation, cleaning, and annealing process. By this annealing, the polysilicon film 112 in the trench 111 is removed from the N film. The type impurities are diffused outside the trench 111, and an N-type first conductivity type isolation diffusion region 113 is further formed (FIG. 10). Furthermore, the above-described components of the solid-state imaging device according to the present embodiment are formed in accordance with a normal semiconductor device manufacturing process, thereby completing the solid-state imaging device according to the present embodiment. However, some elements can be formed before or during the formation of the pixel isolation region 110 by the trench 111 described above. For example, regions such as the P-type charge accumulation region 12 and the N-type drain region 16 may be formed before the trench 111 is formed.
[0128]
According to this manufacturing process, in the process of removing the polysilicon 112 and the oxide films 114 and 201 outside the trench 111, the CMP method is used to remove the polysilicon film 112 and the oxide films 114 and 201 in the same process of the same apparatus. 201 can be removed at the same time, and the films 112 and 114 inside the trench 111 can be formed without over-etching, so that the upper portion of the trench 111 can also be formed flat, and the subsequent formation of the Al wiring 22 The yield can be improved also in the process and the like.
[0129]
Even when the pixel isolation regions 110 shown in FIGS. 6, 9 and 11 are formed, a manufacturing method similar to the manufacturing method described above can be employed. When forming the pixel isolation region 110 shown in FIG. 11, the oxide film 114 is formed on the substrate in the state shown in FIG. 12A so as to be formed along the inner wall of the trench 111. After that, the portion of the oxide film 114 along the bottom surface of the trench 111 and the portion near the opening of the trench 111 are removed by anisotropic dry etching or the like, and then the remaining portion of the trench 111 is formed on the substrate. What is necessary is just to deposit the polysilicon film 112 by CVD method so that it may be completely embedded.
[0130]
[Second Embodiment]
Next, a solid-state imaging device according to a second embodiment of the present invention will be described with reference to FIGS.
[0131]
FIG. 14 is a schematic plan view showing the solid-state imaging device according to the present embodiment. FIG. 15 is a schematic cross-sectional view taken along line X13-X14 in FIG. 14 and 15, elements that are the same as or correspond to those in FIGS. 16 to 19 are given the same reference numerals, and redundant descriptions thereof are omitted.
[0132]
14 is the same as FIG. 17 and the schematic cross-sectional view along the Y11-Y12 line in FIG. 14 is the same as FIG. 19, and the solid state according to the present embodiment. A circuit diagram showing a basic configuration of a pixel and a readout circuit system of the imaging device is the same as FIG.
[0133]
The solid-state imaging device according to the present embodiment is different from the conventional solid-state imaging device shown in FIGS. 16 to 20 described above in that the pixel separation region 210 excludes a part of the surrounding region of each pixel between the pixels. Thus, it is only a point formed in place of the high concentration N-type diffusion region 311 as the pixel separation region. Similar to the pixel isolation region 110 shown in FIG. 6 described above, the pixel isolation region 210 includes a polysilicon 112 containing N-type impurities embedded in the trench 111 and an N-type diffusion layer 113. The pixel isolation region 210 may be configured similarly to the pixel isolation region 110 shown in FIG. 9, FIG. 10, or FIG. 11 instead of such a configuration.
[0134]
Therefore, in the present embodiment, the formation of the pixel isolation region 210 reduces crosstalk between pixels (that is, pixel isolation), and improves the surface side of the N-type semiconductor substrate 301 and the N-type semiconductor layer 302. Both the reduction of the resistance between the regions is achieved at the same time.
[0135]
Also in the solid-state imaging device according to the present embodiment, as in the conventional solid-state imaging device shown in FIGS. 16 to 20, the bipolar transistor Tr has a high-concentration N-type semiconductor substrate 301 and a low-concentration N-type semiconductor layer 302 in this order. In this embodiment, as described above, since the reduction of the resistance is achieved by the pixel isolation region 210, the impurity concentration of the N-type semiconductor layer 302 is lowered. Even so, the potential from the N-type semiconductor substrate 301 is sufficiently transmitted to the N-type semiconductor layer 302, and the performance of the bipolar transistor Tr is not lowered and the variation thereof is not increased. There is nothing to do. Therefore, the impurity concentration of the N-type semiconductor layer 302 can be lowered, the detection sensitivity can be extended to the long wavelength side, and crosstalk can be suppressed without degrading the performance as a solid-state imaging device. .
[0136]
Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.
[0137]
For example, in each of the embodiments described above, it goes without saying that the N type and the P type may be reversed.
[0138]
【The invention's effect】
As described above, according to the present invention, crosstalk between pixels can be reduced, and the impurity concentration of a low-concentration semiconductor layer that forms a path along the way of feeding power to elements constituting the pixel can be reduced. In addition, it is possible to provide a solid-state imaging device that can sufficiently supply power to the element and sufficiently exhibit the performance of the element.
[0139]
Further, according to the present invention, it is possible to provide a manufacturing method suitable for manufacturing such a solid-state imaging device.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is a schematic plan view showing unit pixels of the solid-state imaging device according to the first embodiment.
3 is a schematic sectional view taken along line X1-X2 in FIG.
4 is a schematic sectional view taken along line Y1-Y2 in FIG.
5 is a schematic sectional view taken along line Y3-Y4 in FIG.
6 is a schematic sectional view taken along line X3-X4 in FIG.
FIG. 7 is a circuit diagram showing a schematic configuration of the solid-state imaging device according to the first embodiment.
FIG. 8 is a pulse timing chart for explaining the operation of the solid-state imaging device according to the first embodiment.
FIG. 9 is a schematic cross-sectional view showing another structural example of the pixel isolation region.
FIG. 10 is a schematic cross-sectional view showing still another structural example of the pixel isolation region.
FIG. 11 is a schematic cross-sectional view showing still another structural example of the pixel isolation region.
12 is a diagram showing a manufacturing process of the solid-state imaging device according to the first embodiment; FIG.
13 is a diagram showing a step that follows the step shown in FIG. 12. FIG.
FIG. 14 is a schematic plan view showing a solid-state imaging device according to a second embodiment of the present invention.
15 is a schematic sectional view taken along line X13-X14 in FIG.
FIG. 16 is a schematic plan view showing a conventional solid-state imaging device.
17 is a schematic sectional view taken along line X11-X12 in FIG.
18 is a schematic sectional view taken along line X13-X14 in FIG.
19 is a schematic cross-sectional view taken along line Y11-Y12 in FIG.
FIG. 20 is a circuit diagram illustrating a basic circuit configuration of a pixel and a readout circuit system of the conventional solid-state imaging device.
[Explanation of symbols]
1 Photodiode
2 Junction Field Effect Transistor (JFET)
3 Transfer gate
4 Reset drain
5 Reset gate
6a Overflow control area
7 Vertical scanning circuit
8 Horizontal scanning circuit
12 P-type charge storage region
13 N-type semiconductor region
14 N-type source region
15 P-type gate region
16 N-type drain region
17 N-type channel region
18 P-type charge discharge area
20, 20a-20c Transfer gate wiring
21, 21a-21c Reset gate wiring
22, 22a-22d Vertical signal line
23 Relay wiring
24, 24a-24c Reset drain wiring
26a-26d constant current source
27a, 27b Horizontal signal line
28a, 28b Output buffer amplifier
30 Contact hole for reset drain
31 Relay wiring connection hole
100,301 High-concentration N-type semiconductor substrate
101,302 Low-concentration N-type semiconductor layer (epitaxial layer)
110,210 pixel separation region
111 trench
112 Polysilicon
113 N-type diffusion layer
114 Insulator
Tr bipolar transistor
Cox, Cr capacity
303 PMOSFET
304 Transfer MOSFET
305 Reset MOSFET
VL vertical output line
306 P-type diffusion region (base)
307 N-type diffusion region (emitter)
308 Metal film (collector electrode)
309 Polysilicon for relay wiring
310 Al wiring
311 N-type diffusion region

Claims (5)

A substrate having a first conductive semiconductor substrate having a high concentration and a first conductive semiconductor layer having a low concentration formed on the first conductive semiconductor substrate, wherein a plurality of pixels are formed on the substrate; A solid-state imaging device, wherein the pixel includes an element that operates when power is supplied through the first conductive semiconductor substrate and the first conductive semiconductor layer in this order,
In the base, a trench is formed from the surface of the first conductivity type semiconductor layer between the pixels,
One or more materials are used for the trench so that resistance between the first conductive semiconductor substrate and a surface side region of the first conductive semiconductor layer is reduced and crosstalk between the pixels is reduced. Is embedded ,
Of the portion along the inner wall of the trench, an insulator is embedded in a portion other than a portion along the bottom surface of the trench and a portion in the vicinity of the opening of the trench, and at least the first conductive is provided in the remaining portion of the trench. A solid-state imaging device, wherein a conductive material having conductivity is embedded in a type semiconductor layer . Wherein the conductive material is solid-state imaging device according to claim 1, wherein the polysilicon of the first conductivity type impurity. 3. The solid-state imaging device according to claim 1, wherein a first conductivity type diffusion layer is formed outside the trench along a portion along the inner wall of the trench in the conductive material. The solid-state imaging device according to any one of claims 1 to 3, wherein the first conductive semiconductor layer is an epitaxial layer. The solid-state imaging device according to any one of claims 1 to 4, wherein the element is an amplification element.

Images