JP3870566B2 - EL display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an EL display device including, for example, a timing controller as a data processing circuit for inputting and processing command address data, command data, and image data.
[0002]
[Prior art]
When command address data, command data, and image data are sent from the 8-bit MPU to the timing controller, a data processing method is considered as described below. In this case, command address data and command data are distributed to the upper and lower parts of 8-bit data and sent together (simultaneously), and image data is sent as 8-bit data. Thus, since only two types of data need be identified, the identification data is 1 bit. In the case of this configuration, when the timing controller is configured by, for example, one IC and the identification data is input from the outside to the IC, an input terminal for inputting the identification data (ie, signal) is provided. It is sufficient to provide one.
[0003]
In the above configuration, when the command address data and command data are distributed to the upper and lower parts of the 8-bit data, the upper 4 bits are used as command address data and the lower 4 bits are used as command data. In this case, the maximum amount of command data is 16 × 4 = 64 bits.
[0004]
[Problems to be solved by the invention]
In recent years, it has been considered to enlarge the display screen of the EL display device. In this case, it is necessary to considerably increase the amount of command data. On the other hand, in the timing controller having the above-described configuration, the maximum amount of command data is 64 bits, which is considerably small. Therefore, the amount of data needs to be expanded. Here, the present inventor first tried to increase the amount of command data by changing the upper and lower sorting amounts of 8-bit data.
[0005]
Specifically, assuming that the upper 6 (or 7) bits are command address data and the lower 2 (or 1) bits are command data, the maximum amount of command data is 64 × 2 = 128 (or 128 × 1). = 128) bits. However, in the method of distributing the upper and lower bits of 8-bit data, the 128-bit data amount is the limit. For this reason, it has been found that the method of distributing the upper and lower order of the above 8-bit data cannot be used when it is desired to further increase the amount of command data.
[0006]
Therefore, the present inventor considered the following method in order to increase the amount of command data. That is, it is considered that the command address data, command data, and image data are each 8-bit data, and these three types of 8-bit data are sent from the 8-bit MPU to the timing controller. According to this configuration, the maximum amount of command data is 256 × 8 = 2048 bits, which is a sufficient amount.
[0007]
However, in the case of the above configuration, since three types of data must be identified, the identification data is 2 bits. Therefore, in the above configuration, in order to input identification data from the outside to the IC for the timing controller, two input terminals for inputting identification data (ie, signals) must be provided in the IC. Don't be. If the hardware is changed such that the number of input terminals (pins) of the IC is changed in this way, the configuration of the entire EL display device must be changed, and the scale of the change becomes considerably large. .
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to provide an EL display device that does not require hardware changes such as the number of input terminals of an IC for a data processing circuit, while the configuration is such that the amount of command data is increased. Is to provide.
[0009]
[Means for Solving the Problems]
According to the first aspect of the present invention, the command address data is set as one data, the command data and the image data are input as the other data, and a part of the addresses indicated by the command address data are set. By assigning to the image data and assigning other addresses to the command data, when a part of the addresses is instructed by the command address data, it is determined that the image data is input as the other data. According to this configuration, the command address data is, for example, 8-bit data, a part of the addresses indicated by the command address data is assigned to the image data, and the other addresses are assigned to the command data. As a result, the amount of command data can be increased sufficiently. In this configuration, it is only necessary to identify two pieces of data, so that it is not necessary to change hardware such as the number of input terminals of an IC for a data processing circuit.
[0010]
In the invention of claim 2, when an address other than the part of the addresses is indicated by the command address data, the command data input as the other data is stored in the command register corresponding to the address indicated by the command address data. The image data input as the other data is determined on the basis of the command data stored in the command register when the partial address is instructed by the command address data. The image data is stored in an area in the image memory corresponding to the image memory address. According to this configuration, a configuration for storing command data and image data in a desired command register and a desired area in the image memory can be easily realized with a simple configuration.
[0011]
According to the invention of claim 3, the command address data, the command data, and the image data are each 8 bits of data, and addresses “00H” to “FFH” (where H is a hexadecimal number) indicated by the command address data. Address "FFH" is assigned to the image data, and the other addresses "00H" to "FEH" are assigned to the command data, and the addresses "00H" to "FEH" are associated. The configuration is such that 255 command registers are provided. In this configuration, the maximum amount of command data is 255 × 8 = 2040 bits, which is a sufficient amount.
[0012]
According to the invention of claim 4, when determining the image memory address based on the command data stored in the command register, the updating means for automatically updating the image memory address every time the image data is input. Since it is provided, the time required to store a large amount of image data in the image memory can be reduced.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, FIG. 2 is a block diagram showing a schematic electrical configuration of the EL display device of this embodiment. In FIG. 2, the EL display device 1 includes, for example, an 8-bit MPU 2, a timing controller 3 as a data processing circuit, a power supply circuit 4, an EL display panel 5, a column driver 6, and a row driver 7. Has been.
[0014]
The MPU 2 has a function of supplying image data to be displayed on the EL display panel 5, command data representing various commands such as display negative / positive reversal and dimming, and command address data to the timing controller 3. . Here, the image data, command data, and command address data are each configured as 8-bit data.
[0015]
The addresses “00H” to “FEH”, which are the majority of the addresses “00H” to “FFH” (where H represents a hexadecimal number) indicated by the command address data, are assigned to the command data. The address “FFH” which is the address of the copy is assigned to the image data. The addresses “00H” to “FEH” assigned to the command data indicate that the data sent from the MPU 2 is command data, and the number of the command register 8 (see FIG. 1) that stores the command data. Is shown. The command register 8 will be described later. The address “FFH” assigned to the image data indicates that the data sent from the MPU 2 is image data.
[0016]
Further, the MPU 2 is configured to provide the timing controller 3 with a control signal RS for data identification and a control signal WR for data capture. When the control signal RS is at a low level, for example, command address data is sent from the MPU 2 to the timing controller 3 as one data. When the control signal RS is at a high level, command data or image data, for example, is sent from the MPU 2 to the timing controller 3 as the other data.
[0017]
Further, the timing controller 3 internally processes the data sent from the MPU 2 to generate control signals for controlling the driving of the column driver 6 and the row driver 7 and supply them to the drivers 6 and 7 as well as image data. Is supplied to the column driver 6. Data processing executed inside the timing controller 3 will be described later. The timing controller 3 is connected to a CERALOCK (ceramic oscillator) 9.
[0018]
The power supply circuit 4 supplies power to the timing controller 3, the column driver 6, and the row driver 7. The column driver 6 applies a display voltage corresponding to display data (image data) to each column line of the EL display panel 5. The row driver 7 sequentially applies scanning voltages to the row lines of the EL display panel 5 from the upper part to the lower part (or from the lower part to the upper part). Further, the EL display panel 5 is composed of capacitive EL elements arranged in a matrix, and each element is configured to emit light when a potential difference of a certain level or more occurs at both ends (column line and row line). Has been.
[0019]
Now, a specific configuration of the timing controller 3 will be described with reference to FIG. As shown in FIG. 1, the timing controller 3 includes an address register 10, a decoder 11, for example, 255 command registers 8, an image memory 12, and an address generation circuit 13.
[0020]
In this configuration, when the control signal WR becomes high level when the control signal RS is low level (RS = L), the signal on the MPU data bus 14 (8-bit data sent from the MPU 2, specifically, Command address data) is taken into the address register 10. If the control signal WR becomes high level when the control signal RS is at high level (RS = H), the signal on the MPU data bus 14 (8-bit data sent from the MPU 2, specifically command data) Or image data) is taken into the command register 8 or the image memory 12 selected by the decoder 11.
[0021]
The decoder 11 is connected to the address register 10 and transmits the control signal WR to one of the 256 outputs Q00H to QFFH in accordance with the contents (8-bit data) of the address register 10. Is configured to do. Specifically, 8-bit data “00H” to “FFH” (where H represents a hexadecimal number), which is the content of the address register 10, is made to correspond to the outputs Q00H to QFFH of the decoder 11 on a one-to-one basis. Yes.
[0022]
Of the outputs Q00H to QFFH of the decoder 11, 255 outputs Q00H to QFEH correspond to 255 command registers 8 on a one-to-one basis. That is, when the content of the address register 10 is “00H”, a signal (that is, command data) on the MPU data bus 14 is taken into the “00H” -th command register 8 and the content of the address register 10 is “01H”. At this time, the signal on the MPU data bus 14 is taken into the “01H” -th command register 8..., When the content of the address register 10 is “FEH”, the MPU data bus is sent to the “FEH” -th command register 8. 14 is captured. In the case of this configuration, the maximum amount of command data stored in the 255 command registers 8 is 255 × 8 = 2040 bits.
[0023]
Further, when the content of the address register 10 is “FFH”, the output QFFH of the decoder 11 is selected, and the signal (that is, image data) on the MPU data bus 14 is taken into the image memory 12. In this case, the “00H” -th command register 8 and the “01H” -th command register 8 are the X address register 8 and the Y address register 8, and are generated by the X address register 8, the Y address register 8, and the address generation circuit 13. The signal on the MPU data bus 14 (that is, image data) is stored in an area in the image memory 12 designated by the designated image memory address.
[0024]
Therefore, in the above configuration, for example, the address “FFH”, which is a part of the addresses “00H” to “FFH” indicated by the command address data, is assigned to the image data, and the other addresses “00H” to “00H” to “FEH” is assigned to command data. The timing controller 3 is further provided with a control signal generation circuit (not shown) for generating a control signal for controlling the column driver 6, the row driver 7, and the like. The timing controller 3 has functions as input means, determination means, command data storage means, image data storage means, and update means.
[0025]
Next, the operation of the above configuration will be described with reference to FIG. First, an operation when command data is stored in the command register 8 group will be described. In this case, as shown in FIG. 3, when the control signal WR becomes high level at time t1, since the control signal RS is low level at this time, the data “00H” on the MPU data bus 14 is stored in the address register. Set to 10.
[0026]
Subsequently, when the control signal WR becomes high level at time t2, since the control signal RS is high level at this time, the data “00H” on the MPU data bus 14 is set (stored) in the command register 8. Is done. In this case, the command register 8 to be set is the command register 8 (that is, the X address register) of “00H” because the content of the address register 10 is “00H”. Thereafter, it is possible to store desired command data in the desired command register 8 by repeating the above-described operation. In this case, the maximum amount of command data that can be stored is 255 × 8 = 2040 bits.
[0027]
Next, an operation when image data is stored in the image memory 12 will be described. In this case, as shown in FIG. 3, when the control signal WR becomes high level at time t3, since the control signal RS is low level at this time, the data “FFH” on the MPU data bus 14 is stored in the address register. Set to 10.
[0028]
Subsequently, at time t4, when the control signal WR becomes high level, at this time, the control signal RS is at high level and the content of the address register 10 is “FFH”. Data “01H” is set (stored) in the image memory 12, not in the command register 8. In this case, the address in the image memory 12 (that is, the image memory address) to be set is the X address register 8 (command register 8 of “00H”) and the Y address register 8 (“01H”) set by the above-described method. The address generation circuit 13 generates an address based on the contents of the command register 8). Thereafter, by repeating the above-described operation, desired image data can be stored in a desired area in the image memory 12.
[0029]
In this embodiment, for example, commands such as X address auto increment, X address auto decrement, Y address auto increment, Y address auto decrement, XY address linked auto increment, and XY address linked auto decrement are prepared as commands. Yes. When these commands are used, when determining the image memory address based on the command data stored in the command register, the image memory address is automatically set by the data length of the image data every time the image data is input (captured). Can be updated. According to this configuration, it is only necessary to input the image memory address once at the beginning. After that, if the image data is continuously input, the image memory address becomes the data of the image data every time the image data is input. The length is automatically updated, and the image data is sequentially stored at the updated address. In this configuration, the time required to store the image data in the image memory 12 can be considerably shortened, and the setting work of command data, image data, control signals, etc. can be considerably simplified.
[0030]
According to this embodiment having such a configuration, the command address data is one data (ie, data when RS = L), and the command data and image data are the other data (ie, when RS = H). Data). Then, a part of addresses (specifically, “FFH”) among the addresses (specifically, “00H” to “FFH”) indicated by the command address data is assigned to the image data, and the rest By assigning addresses (specifically, “00H” to “FEH”) to command data, when some addresses (“FFH”) are instructed by the command address data, image data is input as the other data. It was configured to be judged to have been.
[0031]
According to the above configuration, since a part of the addresses indicated by the command address data is assigned to the image data and the other addresses are assigned to the command data, the amount of command data is increased. be able to. For example, when command address data is, for example, 8-bit data and addresses “00H” to “FEH” are assigned to command data, the amount of command data is 255 × 8 = 2040 bits. In the case of the above configuration, it is only necessary to identify two types of data, specifically, whether the control signal RS is high level or low level. It is not necessary to change the hardware such as the number of terminals. That is, the number of input terminals of the IC may be the same as the conventional configuration. Therefore, it is not necessary to change the configuration of the entire EL display device, and the change is simple and easy.
[0032]
In the above embodiment, an address designated by the command address data, specifically, a part of addresses “00H” to “FFH”, specifically “FFH” is assigned to the image data, The other address is configured to be assigned to the command data. Alternatively, an address other than “FFH” may be allocated to the image data, and the other address may be allocated to the command data. In addition, an address having an appropriate number of bits (two) or more of two bits (two) or more may be assigned to the image data, and other addresses may be assigned to the command data. Furthermore, in the above embodiment, the image data, command data, and command address data are configured as 8-bit data, but the present invention is not limited to this, and data having an appropriate data length of 9 bits or more or 7 bits or less is used. It may be configured.
[Brief description of the drawings]
FIG. 1 is a block diagram of a timing controller showing an embodiment of the present invention. FIG. 2 is a block diagram of an EL display device. FIG. 3 is a time chart for explaining data processing.
1 is an EL display device, 2 is an MPU, 3 is a timing controller (data processing circuit), 5 is an EL display panel, 8 is a command register, 9 is a Ceralock, 10 is an address register, 11 is a decoder, 12 is an image memory, 14 Indicates an MPU data bus.

Claims (4)

In an EL display device comprising a data processing circuit for inputting command address data, command data, and image data, storing the command data in a command register, and storing the image data in an image memory.
The data processing circuit includes:
Input means for inputting the command address data as one data and inputting the command data and the image data as the other data;
By assigning a part of the addresses indicated by the command address data to the image data and assigning other addresses to the command data, the part of the addresses is indicated by the command address data. In some cases, the EL display device further includes a determination unit that determines that the image data is input as the other data. The data processing circuit includes:
A command that stores command data input as the other data in a command register corresponding to the address indicated by the command address data when an address other than the part of the addresses is indicated by the command address data Data storage means;
When the command address data indicates the partial address, the image data input as the other data corresponds to the image memory address determined based on the command data stored in the command register. 2. An EL display device according to claim 1, further comprising image data storage means for storing in an area in the image memory. The command address data, the command data, and the image data are each 8-bit data,
Of the addresses “00H” to “FFH” (where H represents a hexadecimal number) indicated by the command address data, the address “FFH” is assigned to the image data, and the other addresses “00H” to “FEH” Is assigned to the command data,
3. The EL display device according to claim 2, further comprising 255 command registers corresponding to the addresses “00H” to “FEH”. When determining the image memory address based on the command data stored in the command register, the image memory address is provided with update means for automatically updating the image memory address each time the image data is input. The EL display device according to claim 2 or 3.

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