JP2000047628A - El display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make no change in the number of input terminals of a data processing circuit IC while increasing the amount of command data. SOLUTION: The EL display device is provided with a data processing circuit 3 which receives command address data, command data and picture data and which stores the command data in a command register 8 and the picture data in a picture memory 12. The EL display device is constituted such that the command address data are set in a group, the command data and the picture data are set in another group and these groups of data are inputted. A part of the addresses specified by the command address data are assigned to the picture data. Remaining addresses are assigned to the command data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an EL display device having, for example, a timing controller as a data processing circuit for inputting command address data, command data and image data and processing the data.

[0002]

2. Description of the Related Art When sending command address data, command data, and image data from an 8-bit MPU to a timing controller, a method of processing data as described below has been considered. In this case, the command address data and the command data are divided into upper and lower 8-bit data and transmitted together (simultaneously), and the image data is transmitted as 8-bit data. As a result, only two types of data need to be identified, and the data for identification is one bit. In the case of this configuration, when the timing controller is configured by, for example, one IC and configured to input identification data from outside to the IC, an input terminal for inputting identification data (that is, a signal) is provided. One may be provided.

[0003] In the above configuration, when the command address data and the command data are divided into upper and lower 8-bit data, the upper 4 bits are used as the command address data and the lower 4 bits are used as the command data. In this case, the data amount of the command data is 16 × 4 = 64 bits at maximum.

[0004]

In recent years, it has been considered to enlarge the display screen of the EL display device. In this case, it is necessary to considerably increase the amount of command data. On the other hand, in the timing controller having the above-described configuration, the data amount of the command data is 64 bits at the maximum and is considerably small, so it is necessary to expand the data amount. Here, the inventor first tried to increase the data amount of command data by changing the upper and lower distribution amounts of 8-bit data.

More specifically, if the upper 6 (or 7) bits are used as command address data and the lower 2 (or 1) bits are used as command data, the data amount of command data is 64 × 2 = 128 (or at most). 128 × 1 = 1
28) Bits. However, in the method of sorting upper and lower 8-bit data, the above-mentioned 128-bit data amount is the limit. For this reason, it has been found that it is not possible to further increase the data amount of the command data by the above-described method of sorting the upper and lower bits of 8-bit data.

The present inventor has considered the following method to increase the amount of command data. That is, the command address data, the command data, and the image data are each set to 8-bit data, and these three types of 8 bits are used.
It is considered that a configuration is adopted in which bit data is transmitted from an 8-bit MPU to a timing controller. According to this configuration, the data amount of the command data is 256 × 8 at the maximum.
= 2048 bits, which is a sufficient amount.

However, in the case of the above configuration, since three types of data must be identified, the identification data is 2 bits. Therefore, in the above configuration, in order to input the identification data from the outside to the IC for the timing controller, two input terminals for inputting the identification data (that is, signals) must be provided to the IC. No. If the hardware is changed such that the number of input terminals (pins) of the IC is changed, the configuration of the entire EL display device must be changed, and the scale of the change becomes considerably large. .

Therefore, an object of the present invention is to provide a configuration in which the amount of command data is changed so as to increase the data amount.
An object of the present invention is to provide an EL display device which does not need to change hardware such as the number of input terminals of an IC for a data processing circuit.

[0009]

According to the first aspect of the present invention, the command address data is used as one data, the command data and the image data are input as the other data, and designated by the command address data. By allocating some of the addresses to the image data and allocating the other addresses to the command data, when some of the addresses are designated by the command address data, the image data is input as the other data. It was configured to judge. According to this configuration, the command address data is, for example, 8-bit data, a part of the addresses specified by the command address data is assigned to the image data, and the other addresses are assigned to the command data. Therefore, the amount of command data can be increased sufficiently. In this configuration, since it is only necessary to identify two data, it is not necessary to change hardware such as the number of input terminals of the IC for the data processing circuit.

According to the second aspect of the present invention, when an address other than the partial address is designated by the command address data, the command data input as the other data corresponds to the address designated by the command address data. It is configured to be stored in a command register, and when the partial address is designated by command address data, the image data input as the other data is converted to the command data stored in the command register. The image data is stored in an area in the image memory corresponding to the image memory address determined based on the image data. According to this configuration, a configuration for storing command data and image data in a desired command register and a desired area in the image memory can be easily realized with a simple configuration.

According to the third aspect of the present invention, the command address data, the command data, and the image data are each 8-bit data, and the addresses designated by the command address data are "00H" to "FFH" (where H is Hexadecimal number)) "FF
H is assigned to the image data, the other addresses “00H” to “FEH” are assigned to the command data, and 255 command registers corresponding to the addresses “00H” to “FEH” are provided. did. In the case of this configuration, the data amount of the command data is 255 × 8 = 2040 bits at the maximum, which is a sufficient amount.

According to the present invention, when determining the image memory address based on the command data stored in the command register, the image memory address is automatically updated every time the image data is input. Since the updating means is provided, the time required to store a large amount of image data in the image memory can be reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. First, FIG. 2 is a block diagram showing a schematic electrical configuration of the EL display device of the present embodiment. In FIG. 2, the EL display device 1 has, for example, 8
Bit MPU 2, timing controller 3 as a data processing circuit, power supply circuit 4, EL display panel 5
, A column driver 6, and a row driver 7.

The MPU 2 has a function of supplying image data to be displayed on the EL display panel 5, command data representing various commands such as display negative / positive inversion and dimming, and command address data to the timing controller 3. are doing. Here, image data, command data,
The command address data is configured as 8-bit data.

Then, the addresses "00H" to "FFH" (where H
Indicates a hexadecimal number).
0H ”to“ FEH ”are assigned to command data,
An address “FFH”, which is a part of the address, is assigned to image data. The addresses “00H” to “FEH” assigned to the command data indicate that the data sent from the MPU 2 is command data, and indicate the number of the command register 8 (see FIG. 1) for storing the command data. Is shown. The command register 8 will be described later. The address “FFH” assigned to the image data indicates that the data sent from the MPU 2 is image data.

The MPU 2 is configured to supply the timing controller 3 with a control signal RS for data identification and a control signal WR for data capture.
When the control signal RS is at a low level, for example, command address data is sent from the MPU 2 to the timing controller 3 as one of the data. When the control signal RS is at a high level, the other data, for example, command data or image data is sent from the MPU 2 to the timing controller 3.

Further, the timing controller 3 controls the MP
By internally processing the data sent from U2,
A control signal for driving and controlling the column driver 6 and the row driver 7 is generated and supplied to each of the drivers 6 and 7, and
The image data is supplied to the column driver 6. The data processing executed inside the timing controller 3 will be described later. A ceramic lock (ceramic oscillator) 9 is connected to the timing controller 3.

The power supply circuit 4 supplies power to the timing controller 3, column driver 6, and row driver 7. The column driver 6 applies a display voltage corresponding to display data (image data) to each of the column lines of the EL display panel 5. The row driver 7 sequentially applies a scanning voltage to the row lines of the EL display panel 5 from the top to the bottom (or from the bottom to the top). Further, the EL display panel 5 is configured by capacitive EL elements arranged in a matrix, and each element is configured to emit light when a potential difference of not less than a predetermined value is generated between both ends (column lines and row lines). Have been.

Now, a specific configuration of the timing controller 3 will be described with reference to FIG. As shown in FIG. 1, the timing controller 3 includes an address register 10, a decoder 11, for example, 255 command registers 8, an image memory 12, and an address generation circuit 13.
It is comprised including.

In this configuration, when the control signal WR goes high when the control signal RS is low (RS = L), the signal on the MPU data bus 14 (8-bit data sent from the MPU 2, specifically Is configured to take command address data) into the address register 10. When the control signal WR goes high when the control signal RS is high (RS = H), the signal on the MPU data bus 14 (8-bit data sent from the MPU 2, specifically command data , Or image data) is taken into the command register 8 or the image memory 12 selected by the decoder 11.

The decoder 11 has an address register 1
0, and 256 outputs Q00H according to the contents (8-bit data) of the address register 10.
To QFFH to the output terminal of the control signal WR.
Is configured to be transmitted. Specifically, 8-bit data “00” that is the content of the address register 10
H ”to“ FFH ”(where H indicates a hexadecimal number) correspond to the outputs Q00H to QFFH of the decoder 11 on a one-to-one basis.

The outputs Q00H to Q00 of the decoder 11
255 outputs Q00H to QFEH of FFH are 2
There is a one-to-one correspondence with 55 command registers 8.
That is, when the content of the address register 10 is “00H”, a signal (that is, command data) on the MPU data bus 14 is taken into the “00H” th command register 8, and the content of the address register 10 is “01H”. At this time, the signal on the MPU data bus 14 is taken into the “01H” th command register 8..., And when the contents of the address register 10 are “FEH”, the “PUH” 14 is configured to be captured. In the case of this configuration, the data amount of the command data stored in the 255 command registers 8 is a maximum of 255 × 8 = 204.
It becomes 0 bits.

Further, if the contents of the address register 10 are "F
At the time of “FH”, the output QFFH of the decoder 11 is selected, and a signal (that is, image data) on the MPU data bus 14 is taken into the image memory 12. In this case, the “00H” th command register 8
And the “01H” -th command register 8 are the X address register 8 and the Y address register 8,
A signal (that is, image data) on the MPU data bus 14 is stored in an area in the image memory 12 specified by the address register 8, the Y address register 8, and the image memory address generated by the address generation circuit 13. It is configured.

Therefore, in the above configuration, the addresses "00H" to "00H" designated by the command address data
For example, an address “FFH” which is a partial address of “FFH” is allocated to image data, and the other addresses “00H” to “FEH” are allocated to command data. The timing controller 3 further includes a control signal generation circuit (not shown) for generating a control signal for controlling the column driver 6, the row driver 7, and the like. Further, the timing controller 3 has respective functions as an input unit, a determination unit, a command data storage unit, an image data storage unit, and an update unit.

Next, the operation of the above configuration will be described with reference to FIG. First, an operation for storing command data in the command register group 8 will be described. In this case, as shown in FIG. 3, when the control signal WR goes high at time t1, at this time, the control signal RS
Is low level, the data “00H” on the MPU data bus 14 is set in the address register 10.

Subsequently, at time t2, the control signal WR
Becomes high level, at this time, since the control signal RS is at high level, the data “00H” on the MPU data bus 14 is set (stored) in the command register 8. In this case, the set command register 8 is:
Since the content of the address register 10 is “00H”,
The command register 8 is "00H" (that is, the X address register). Hereinafter, the desired command data can be stored in the desired command register 8 by repeating the above operation. In this case, the maximum amount of command data that can be stored is 255 × 8 = 2.
040 bits.

Next, the operation of storing image data in the image memory 12 will be described. In this case, as shown in FIG. 3, when the control signal WR goes high at time t3, the control signal RS is low at this time, so that the data “FFH” on the MPU data bus 14
Is set in the address register 10.

Subsequently, at time t4, the control signal WR
Becomes high level, at this time, the control signal RS is at high level and the content of the address register 10 is “FFH”, so that the data “01H” on the MPU data bus 14 is And is set (stored) in the image memory 12. In this case, the set addresses in the image memory 12 (that is, the image memory addresses) are the X address register 8 ("00H" command register 8) and the Y address register 8 ("01H") set in the above-described manner. Command register 8)
Is an address generated by the address generation circuit 13 based on the content of the address. Hereinafter, by repeating the above operation, desired image data can be stored in a desired area in the image memory 12.

In this embodiment, the commands include, for example, X-address automatic increment, X-address automatic decrement, Y-address automatic increment,
Commands are provided for Y address automatic decrement, XY address linked automatic increment, and XY address linked automatic decrement. When these commands are used, when determining the image memory address based on the command data stored in the command register, the image memory address is automatically set by the data length of the image data every time the image data is input (taken). Can be updated dynamically. According to this configuration, the image memory address is input only once at the beginning, and thereafter, if the image data is continuously input, the image memory address becomes the data of the image data every time the image data is input. It is configured such that the data is automatically updated by the length, and the image data is sequentially stored at the updated address. In this configuration,
The time required to store the image data in the image memory 12 can be shortened considerably, and the work of setting command data, image data, control signals, and the like is also considerably simplified.

According to this embodiment having such a configuration, the command address data is one data (ie, data when RS = L), and the command data and image data are the other data (ie, RS = H). ). Then, the address specified by the command address data (specifically, “00”
H ”to“ FFH ”), a part of addresses (specifically,“ FFH ”) is assigned to image data, and the other addresses (specifically,“ 00H ”to“ FEH ”) are commanded. By allocating the data, when a part of the address (“FFH”) is specified by the command address data, it is determined that the image data is input as the other data.

According to the above configuration, a part of the addresses specified by the command address data is assigned to the image data, and the other addresses are assigned to the command data. Can be more. For example, when the command address data is 8-bit data and addresses “00H” to “FEH” are assigned to the command data, the amount of command data is 255 × 8 = 204.
It becomes 0 bits. In the case of the above configuration, it is only necessary to identify two types of data, specifically, to identify whether the control signal RS is at a high level or a low level. It is not necessary to change hardware such as the number of terminals. That is, the number of input terminals and the like of the IC may be the same as the conventional configuration. Therefore, it is not necessary to change the configuration of the entire EL display device, and the change is simple and easy.

In the above embodiment, the address specified by the command address data, specifically, "00"
H) to “FFH”, specifically, “FFH” is assigned to the image data, and the other addresses are assigned to the command data. May be assigned to image data, and other addresses may be assigned to command data. Alternatively, an address having an appropriate number of bits of two bits (two) or more may be assigned. It may be configured to assign to image data and other addresses to command data. Further, in the above embodiment, the image data, the command data, and the command address data are configured as 8-bit data.
The present invention is not limited to this, and may be configured as data having an appropriate data length of 9 bits or more or 7 bits or less.

[Brief description of the drawings]

FIG. 1 is a block diagram of a timing controller showing one embodiment of the present invention.

FIG. 2 is a block diagram of an EL display device.

FIG. 3 is a time chart illustrating data processing.

[Explanation of symbols]

1 is an EL display device, 2 is an MPU, 3 is a timing controller (data processing circuit), 5 is an EL display panel, 8 is a command register, 9 is a seralock, 10 is an address register, 11 is a decoder, 12 is an image memory, 14 Is M
2 shows a PU data bus.

Claims (4)

[Claims] 1. An EL comprising a command processing circuit for inputting command address data, command data, and image data, storing the command data in a command register, and storing the image data in an image memory. In the display device, the data processing circuit may include an input unit configured to input the command address data as one data, the command data and the image data as the other data, and an address specified by the command address data. By allocating some addresses to the image data and allocating other addresses to the command data, when the part of addresses was indicated by the command address data, the image data was input as the other data. Means for determining An EL display device comprising: 2. The data processing circuit according to claim 2, wherein, when an address other than said partial address is designated by said command address data, the command data inputted as the other data is converted to an address designated by said command address data. Command data storage means for storing in a command register corresponding to, when the command address data indicates the partial address, image data input as the other data is stored in the command register 2. The EL display device according to claim 1, further comprising image data storage means for storing the image data in an area in the image memory corresponding to the image memory address determined based on the command data. 3. The command address data, the command data, and the image data are each 8-bit data, and addresses “00H” to “FFH” (where H indicates a hexadecimal number) designated by the command address data. ) Is assigned to the image data, and the other addresses “00H” to “FEH” are assigned to the command data. 255 corresponding to the addresses “00H” to “FEH”
3. The EL display device according to claim 2, comprising a plurality of command registers. 4. An update unit for automatically updating the image memory address each time the image data is input, when determining the image memory address based on command data stored in the command register. The EL display device according to claim 2, further comprising: