JP3870272B2 - Ternary logic function circuit and multi-value logic function circuit - Google Patents

Description

  The present invention relates to a ternary logic function circuit that performs a two-variable ternary logic operation and a multi-value logic function circuit that performs a two-variable multi-value logic operation.

  In recent years, with the improvement in performance of information processing apparatuses such as computers, various types of applications that need to perform complicated logical operations such as public key infrastructure (PKI) have been developed. Conventionally, various proposals have been made for multi-valued logic function circuits using MOS (Metal Oxide Semiconductor) elements. Among them, ternary logic function circuits have excellent characteristics due to the relationship between the number of required elements and performance. It is getting attention as a thing.

  As a conventional method for realizing a ternary logic function circuit using MOS elements, a method using a transistor whose threshold voltage is changed by adjusting the channel dope amount of the MOS transistor is known. However, such a method uses a p-type MOS transistor or an n-type MOS transistor. In other words, there is currently no efficient ternary logic function circuit using a CMOS (Comlementary MOS) circuit, and no current flows except during switching, which is a feature of CMOS. Only current mode CMOS multi-valued logic function circuits in which current always flows, not operating characteristics, have been proposed (see, for example, Patent Document 1 and Non-Patent Documents 1 to 3).

Japanese Patent Laid-Open No. 7-212220 WU X W, PROSSER F P, “CMOS ternary logic circuits”, IEE Proc PartG JN: A0160B; ISSN: 0143-7089; CODEN: IPGSEB VOL. 137 NO. 1; PAGE. 21-27; (1990/02) CHANG Y-J, LEE C L, “Synthesis of Multi-Variable MVL Functions Using Hybrid Mode CMOSLogic”, Proc IEEE Int Symp Multiple-Valued Logic JN: B0822B; ISSN: 0195-623XVOL. 24th; PAGE. 35-41; (1994) TEMEL T, MORGUL A, “Multi-valued logic function implementation with novel current-modelogic gates”, IEEE Int Symp Circuits Syst JN: A0757AVOL. 2002 NO.Vol.1; PAGE.I.881-I.884; (2002)

  Under such circumstances, the invention disclosed in Patent Document 2 was made by Olson Edgar Danny. According to the present invention, by using a plurality of types of p-type MOS transistors and n-type MOS transistors whose threshold voltages are changed by adjusting the channel dope amounts of the p-type MOS transistor and the n-type MOS transistor, A multi-valued logic function circuit configuration having an operation characteristic that current does not flow except during operation, which is a feature, has become possible.

JP-T-2002-517937

Here, a case where the technique disclosed in Patent Document 2 is applied to a ternary logic function circuit will be described. That is, in this ternary logic function circuit, if the three logic values are represented as -1, 0, 1 and correspond to a negative voltage, a ground voltage (0 volt), and a positive voltage, respectively, FIG. As shown in FIG. 1, a single or a plurality of MOS transistors are respectively connected between a power supply that supplies a positive voltage and an output terminal, between a ground and an output terminal, and between a power supply that supplies a negative voltage and an output terminal. The configured switch circuits SW1, SW2, and SW3 are inserted. These switch circuits SW1, SW2, and SW3 are p-type MOS transistors and n-type MOS transistors so as to be in an exclusive conductive state in accordance with input voltages corresponding to input logical values of -1, 0, and 1, respectively. It is composed of a MOS transistor circuit in which the array and the threshold voltage are appropriately set. Further, in the technique disclosed in Patent Document 2, there are 3 ^{3 ^ 2} = 3 ⁹ = 19683 types even if only such a configuration is used, and all of them are realized. Since it is impossible, all three-valued logic operations can be realized by applying two special types of inverters (1, -1,1) and (1,1, -1) to the input. Yes.

  However, in the technique disclosed in Patent Document 2, it is necessary to prepare thousands of individual logic function circuits in order to realize all ternary logic operations. This means that when ternary logic operations are realized by an integrated circuit, thousands of basic patterns that must be prepared as a library are required. Therefore, in this method, it is practically impossible to design a ternary logic integrated circuit.

  In this technique, a p-type MOS transistor and an n-type MOS transistor are connected in parallel as a switch circuit inserted between each of a power supply for supplying a negative voltage, a ground, and a power supply for supplying a positive voltage and the output terminal. In addition, since a complex connection in series is used, there is a problem that the switching time characteristics of the rising and falling edges become asymmetric due to the asymmetry of the characteristics of the p-type MOS transistor and the n-type MOS transistor. . That is, in this technique, the change time from the logical value −1 to the logical value 1 and the change time from the logical value 1 to the logical value −1 are greatly different. In a synchronous digital logic function circuit, it is desirable that this switching time asymmetry is as small as possible in order to facilitate timing design.

The present invention has been made in view of such a situation, and 3 ^{3 ^ 2} = 19683 kinds of basic circuits required for realizing all the two-variable ternary logic function circuits are markedly different. An object of the present invention is to provide a ternary logic function circuit that can reduce the asymmetry of switching time and reduce the asymmetry of the switching time, and a multi-value logic function circuit that is an extension of the ternary logic function circuit.

  The ternary logic function circuit according to the present invention that achieves the above-described object is a ternary logic function circuit that performs a two-variable ternary logic operation, and is the first of the three logic values constituting the first input. A first transfer gate that is turned on in accordance with the logic value of the first transfer gate; a second transfer gate that is turned on in accordance with the second logic value of the three logic values constituting the first input; A third transfer gate that is turned on in accordance with a third logic value of the three logic values constituting the first input; and a control terminal connected to one control terminal of the first transfer gate; A first one-variable ternary logic function circuit for obtaining a first output with respect to one input, and the other control terminal of the first transfer gate, and the first input with respect to the first input; A second output complementary to the output of 1 And a third one-variable three-value logic function circuit, and a third one-variable three-value logic circuit that is connected to one control terminal of the second transfer gate and obtains a third output with respect to the first input. A fourth variable that is connected to the value logic function circuit and the other control terminal of the second transfer gate and obtains a fourth output that is complementary and symmetrical to the third output with respect to the first input. A ternary logic function circuit; a fifth one-variable ternary logic function circuit connected to one control terminal of the third transfer gate to obtain a fifth output with respect to the first input; A sixth one-variable ternary logic function circuit connected to the other control terminal of the third transfer gate and obtaining a sixth output complementary to the fifth output with respect to the first input; The second input is connected to the input terminal of the first transfer gate. Connected to the input terminal of the second transfer gate, the seventh one-variable ternary logic function circuit for obtaining a seventh output in accordance with the first logic value of the three logic values, Connected to an input terminal of the third transfer gate, and an eighth one-variable ternary logic function circuit for obtaining an eighth output in accordance with a second logic value among the three logic values constituting the input of And a ninth one-variable ternary logic function circuit for obtaining a ninth output in accordance with a third logic value among the three logic values constituting the second input, wherein the first to third Each of the output terminals of the transfer gate is wired or connected.

  Such a ternary logic function circuit according to the present invention has the first to third univariate ternary logic function circuits by the first to sixth univariate ternary logic function circuits in accordance with the three logic values constituting the first input. The transfer gate is turned on or off, and the outputs of the seventh to ninth univariate ternary logic function circuits connected to the second input are selected. Therefore, in the ternary logic function circuit according to the present invention, the types of basic circuits required for realizing all the two-variable ternary logic function circuits can be remarkably reduced, and all the ternary logic functions can be reduced. Since the element is configured by using only a univariate ternary logic function circuit, the asymmetry of the rising and falling switching times can be remarkably reduced.

  Specifically, the first transfer gate is in a conductive state in accordance with a logical value -1 out of three logical values -1, 0, 1 constituting the first input, The second transfer gate is in a conductive state according to a logical value 0 among the three logical values −1, 0, and 1 constituting the first input, and the third transfer gate is the first transfer gate. One of the three logical values −1, 0, 1 constituting one input is brought into conduction according to the logical value 1. The first one-variable ternary logic function circuit obtains an output (1, -1, -1) with respect to the first input (-1, 0, 1). The two one-variable ternary logic function circuit obtains an output (-1, 1, 1) with respect to the first input (-1, 0, 1). The ternary logic function circuit obtains an output (−1, 1, −1) with respect to the first input (−1, 0, 1), and the fourth univariate ternary logic function. The circuit obtains an output (1, -1, 1) with respect to the first input (-1, 0, 1), and the fifth univariate ternary logic function circuit has the first The output (-1, -1, 1) is obtained for one input (-1, 0, 1), and the sixth univariate ternary logic function circuit has the first input ( -1, 0, 1) for output (1, 1, -1 It can be configured as obtained.

  Here, the ternary logic function circuit according to the present invention is connected to the other control terminal of the first transfer gate in place of the second one-variable ternary logic function circuit. An inverter that inverts the output of the variable ternary logic function circuit may be provided.

  Further, the ternary logic function circuit according to the present invention is connected to one control terminal of the third transfer gate instead of the fifth univariate ternary logic function circuit, and An inverter that inverts the output of the ternary logic function circuit may be provided.

  Further, the ternary logic function circuit according to the present invention is connected to one control terminal of the second transfer gate instead of the third univariate ternary logic function circuit, and An inverter that inverts the output of the ternary logic function circuit may be provided.

  Thereby, in the ternary logic function circuit according to the present invention, the number of necessary elements can be reduced.

  In the ternary logic function circuit according to the present invention, the seventh to ninth univariate ternary logic function circuits output (0, 0, 1) with respect to the second input (-1, 0, 1). −1, −1), a second inverting circuit for obtaining an output (0, 0, −1) for the second input (−1, 0, 1), the second A third inverting circuit for obtaining an output (1, -1, -1) with respect to the input (-1, 0, 1), and an output (1 with respect to the second input (-1, 0, 1). , 0, -1), a fifth inverting circuit for obtaining an output (1, 0, 0) with respect to the second input (-1, 0, 1), A sixth inverting circuit for obtaining an output (1, 1, -1) with respect to the input (-1, 0, 1); an output (1, 1 with respect to the second input (-1, 0, 1); , 0), a seventh inverting circuit for obtaining the second input ( 1, 0, 1) is a first non-inverting circuit that obtains an output (0, -1, 0), and the second input (-1, 0, 1) is output (0, -1, 0). 1) a second non-inverting circuit for obtaining, a third non-inverting circuit for obtaining an output (1, -1, 0) with respect to the second input (-1, 0, 1), the second input A fourth non-inverting circuit that obtains an output (1, -1, 1) with respect to (-1, 0, 1), an output (1, 0 with respect to the second input (-1, 0, 1) , 1), a first non-inverting circuit complementary to the output of the first non-inverting circuit, and an output complementary to the output of the second non-inverting circuit. A second complementary symmetric circuit to obtain, a third complementary symmetric circuit to obtain an output complementary to the output of the third non-inverting circuit, and a fourth to obtain an output complementary to the output of the fourth non-inverting circuit. Complementary symmetric circuit, and Of the fifth complementary symmetry circuit that obtains an output complementary symmetrical output of the non-inverting circuit in the fifth, as long either.

  That is, the ternary logic function circuit according to the present invention can be systematically realized by using only 17 types of binary variable ternary logic function circuits among 27 types of binary variable ternary logic function circuits. it can. In these 17 types of univariate ternary logic function circuits, all transistors are turned off and no current flows except during the switching operation. Therefore, in the ternary logic function circuit according to the present invention, the power consumption can be extremely reduced as in the case of a normal CMOS binary logic function circuit.

  A ternary logic function circuit according to the present invention that achieves the above-described object is a ternary logic function circuit that performs a two-variable ternary logic operation, out of three logic values constituting the first input. A first transfer gate that is turned on according to either the first logic value or the second logic value, and a third logic value among the three logic values that constitute the first input. A second transfer gate that is in a conducting state, and is connected to one control terminal of the first transfer gate and the other control terminal of the second transfer gate, and has a first output with respect to the first input. A first one-variable ternary logic function circuit that obtains a second one-variable ternary logic function circuit that obtains a second output with respect to the first input. A variable ternary logic function circuit and the first transfer gate; A fourth variable which is connected to the other control terminal of the second transfer gate and one control terminal of the second transfer gate and obtains a third output complementary to the first output with respect to the first input. A sixth product obtained by ANDing a ternary logic function circuit and a fifth one-variable ternary logic function circuit that obtains a fourth output complementary to the second output with respect to the first input. A fifth variable output is obtained in accordance with the first logic value among the three logic values that are connected to the input terminal of the first variable transfer gate and the first transfer gate. An eighth univariate ternary logic function for obtaining a sixth output in accordance with the second logic value among the three logic values constituting the seventh univariate ternary logic function circuit and the second input A ninth univariate ternary logic function circuit integrated with the circuit, and an input terminal of the second transfer gate. And a tenth one-variable ternary logic function circuit that obtains a seventh output in accordance with a third logic value among the three logic values constituting the second input, Each of the output terminals of the transfer gates 2 is wired or connected.

  In such a ternary logic function circuit according to the present invention, when any two of the three one-variable ternary logic function circuits that obtain an output according to the logic value of the second input are the same, These same one-variable ternary logic function circuits are integrated into one to form a ninth one-variable ternary logic function circuit. In the ternary logic function circuit according to the present invention, the first and second transfer are performed by the third and sixth univariate ternary logic function circuits according to the three logic values constituting the first input. The gate is turned on or off, and the outputs of the ninth and tenth univariate ternary logic function circuits connected to the second input are selected. Therefore, in the ternary logic function circuit according to the present invention, the types of basic circuits required for realizing all the two-variable ternary logic function circuits can be remarkably reduced, and all the ternary logic functions can be reduced. Since the element is configured by using only a univariate ternary logic function circuit, the asymmetry of the rising and falling switching times can be remarkably reduced.

  Here, the ternary logic function circuit according to the present invention is configured such that, instead of the sixth univariate ternary logic function circuit, one of the other control terminal of the first transfer gate and the second transfer gate. And an inverter for inverting the output of the third one-variable ternary logic function circuit.

  Further, the ternary logic function circuit according to the present invention is configured such that one control terminal of the first transfer gate and the other of the second transfer gate are used instead of the third univariate ternary logic function circuit. An inverter connected to the control terminal and inverting the output of the sixth one-variable ternary logic function circuit may be provided.

  Thereby, in the ternary logic function circuit according to the present invention, the number of necessary elements can be reduced.

  Furthermore, the multi-value logic function circuit according to the present invention that achieves the above-described object is a multi-value logic function circuit that performs a two-variable multi-value logic operation, and any of the N logic values constituting the first input. N transfer gates which are in a conductive state according to the above and m = (N−1) / 2 when N is odd, while m = N / 2 when N is even Are connected to one control terminal of each of the N transfer gates, and the first input (−m, −m + 1,..., −1, 0, 1,..., M−1, For m), for i with 1 ≦ i ≦ N, N is output only for the i-th logic value, and -m is output for other logic values. A first circuit group including a function circuit and the other control terminal of each of the N transfer gates; And the first circuit group is configured with respect to the first inputs (−m, −m + 1,..., −1, 0, 1,..., M−1, m). A second circuit group consisting of N univariate N-value logic function circuits that obtain complementary and symmetrical outputs to the outputs of N univariate N-value logic function circuits, and inputs of the N transfer gates, respectively. A third circuit group consisting of N univariate ternary logic function circuits connected to the terminal and obtaining an output in accordance with each of the N logic values constituting the second input, Each of the output terminals of the transfer gate is wired or connected.

  Such a multi-value logic function circuit according to the present invention has 2N univariate ternary logics constituting the first and second circuit groups in accordance with the N logic values constituting the first input. The N transfer gates are turned on or off by the function circuit, and the outputs of N univariate ternary logic function circuits constituting the third circuit group connected to the second input are selected. Therefore, in the multi-value logic function circuit according to the present invention, the types of basic circuits required for realizing all the two-variable multi-value logic function circuits can be remarkably reduced, and all the multi-value logic elements can be reduced. Is configured using only a single variable multi-valued logic function circuit, the asymmetry of the switching time between the rising edge and the falling edge can be remarkably reduced.

According to the present invention, it is possible to significantly reduce the types of basic circuits required to realize all the 3 ^{3 ^ 2} = 19683 types of binary variable ternary logic function circuits, and to rise and fall. The asymmetry of the switching time can be remarkably reduced.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

This embodiment is a ternary logic function circuit that performs a two-variable ternary logic operation. In particular, this ternary logic function circuit significantly reduces the number of basic circuits required to realize all the binary variable ternary logic function circuits of 3 ^{3 ^ 2} = 19683, It provides guidelines that can be systematically realized using only variable ternary logic function circuits. In addition, this ternary logic function circuit can significantly reduce the asymmetry of the rising and falling switching times by configuring all the ternary logic elements using only one variable ternary logic function circuit. It can be done.

  As shown in FIG. 1, the ternary logic function circuit includes three transfer gates T1, T2, and T3 each composed of a p-type MOS (Metal Oxide Semiconductor) transistor and an n-type MOS transistor. That is, the ternary logic function circuit includes three transfer gates T1, T2, and T3 that are turned on or off in accordance with an input, and the three transfer gates T1, T2, and T3 are turned on or off to output terminals. The value output from Y is determined. Specifically, the ternary logic function circuit selects the output for the input a = −1 by the transfer gate T1, selects the output for the input a = 0 by the transfer gate T2, and selects the output for the input a = 1 by the transfer gate T3. Configured to select an output.

  The two control terminals C-T1 and DT1 of the transfer gate T1 have three variables for obtaining the output (1, -1, -1) for the input a = (-1, 0, 1), respectively. The value logic function circuit C1 is connected to a univariate ternary logic function circuit D1 that is complementary and symmetrical to the value logic function circuit C1. Further, the two control terminals C-T2 and D-T2 of the transfer gate T2 respectively change to obtain an output (-1, 1, -1) with respect to the input a = (-1, 0, 1). The ternary logic function circuit C2 and a univariate ternary logic function circuit D2 that is complementary and symmetric to this are connected. Further, the two control terminals C-T3 and D-T3 of the transfer gate T3 are transformed to obtain an output (-1, -1, 1) with respect to the input a = (-1, 0, 1), respectively. The ternary logic function circuit C3 is connected to a univariate ternary logic function circuit D3 that is complementary and symmetric to this.

  Further, univariate ternary logic function circuits B1, B2, and B3 for obtaining an output with respect to the input b are respectively provided at the input terminals XT1, XT2, and XT3 of the transfer gates T1, T2, and T3. The output terminals Y-T1, Y-T2, and Y-T3 of the transfer gates T1, T2, and T3 are wired or connected as the output terminal Y of the ternary logic function circuit.

  Each of such transfer gates T1, T2, T3 is configured by connecting an enhancement type n-type MOS transistor and an enhancement type p-type MOS transistor in parallel, as shown in FIG. The control terminal CT of the n-type MOS transistor is turned on at the control input 1 and turned off at the control input-1. The control terminal DT of the p-type MOS transistor is complementary to the control terminal CT. It is symmetrical, and is turned on at control input-1 and turned off at control input-1.

  Here, the univariate ternary logic function circuits B1, B2, and B3 are respectively (p, q, r), (s, t, u) with respect to the input b = (− 1, 0, 1). , (X, y, z). However, p, q, r, s, t, u, x, y, and z each take a value of -1, 0, or 1, respectively. A two-variable ternary logic function that can be realized by such a ternary logic function circuit is given as shown in Table 1 below.

The univariate ternary logic function circuit implements one of 27 types of univariate ternary logic functions shown in Table 2 below. The ternary logic function circuits C1, D1, C2, D2 connected to the control terminals C-T1, D-T1, C-T2, DT2, C-T3, and DT3 shown in FIG. , C3, and D3 realize functions f ₁₉ , f ₀₉ , f ₀₇ , f ₂₁ , f ₀₃ , and f ₂₅ , respectively.

Of these univariate ternary logic functions, the function f ₀₁ is identically −1, the function f ₁₄ is identically 0, and the function f ₂₇ is identically 1. Therefore, no special circuit is required.

Also, functions f ₀₂ and f ₂₆ , functions f ₀₃ and f ₂₅ , functions f ₀₄ and f ₂₄ , functions f ₀₅ and f ₂₃ , functions f ₀₆ and f ₂₂ , functions f ₀₇ and f ₂₁ , functions f ₀₈ and f ₂₀ , Functions f ₀₉ and f ₁₉ , functions f ₁₀ and f ₁₈ , functions f ₁₁ and f ₁₇ , functions f ₁₂ and f ₁₆ , and functions f ₁₃ and f ₁₅ are complementary to each other. Among these, the function f ₀₆ takes (-1, ₀ , 1) as input and (-1, 0, 1) as output. In other words, the function f ₀₆ is output = input and passing (Through). The function f ₂₂ has (-1, 0, 1) as input and (1, 0, -1) as output. That is, the function f ₂₂ is equivalent to a binary logic inverter because output = negative input. Therefore, there are 12 types of functions f _{15 to} f _{26 for} the one-variable three-logic function circuit to be realized by the MOS transistor. The functions f _{02 to} f ₀₄ and the functions f _{06 to} f ₁₃ can be realized by providing an inverter in the subsequent stage of the functions f _{26 to} f ₂₄ and the functions f _{22 to} f ₁₅ that are complementary and symmetric to the functions f _{02 to} f ₀₄ , respectively. Depending on the logic function, when the output is copying the only two values of the three values of -1, 0, 1 is the inverter f ₂₂ no can be realized by a simple circuit. This will be described later.

  Next, specific implementation methods for these 12 types of one-variable three-logic function circuits will be described.

  Let the ternary be (-1, 0, 1). Consider a configuration in which there are three types of source logical values -1, 0, and 1, and a switch is provided between each input terminal and output terminal as shown in FIGS. 3 (a) to 3 (c). Note that -1 volts is assumed for the logic value -1, 0 volts is assumed for the logic value 0, and +1 volts is assumed for the logic value 1.

  First, consider the case where the source logical value is -1.

When the source electrode of the MOS transistor is connected to −1 volt and the gate voltage is +1 volt, the gate-source voltage V _gs becomes 2 volt. At this time, in order to turn on the MOS transistor, as shown in FIG. 4A, an enhancement type n-type MOS transistor is used and the threshold voltage is set to 1.5 volts. This enhancement type n-type MOS transistor is abbreviated as NE.

In addition, when the source electrode of the MOS transistor is connected to -1 volt and the gate voltage is 0 volt, the gate-source voltage _Vgs is 1 volt. At this time, in order to turn on the MOS transistor, as shown in FIG. 4B, an enhancement type n-type MOS transistor is used and the threshold voltage is set to 0.5 volts. Since the threshold voltage is 0.5 volts, the switch is turned on for both input 0 (V _gs = 1.0) and input 1 (V _gs = 2.0). This enhancement type n-type MOS transistor is abbreviated as ne.

  These are summarized in Table 3 below.

  Next, consider the case where the source logical value is 1.

When the source electrode of the MOS transistor is connected to +1 volt, and the gate voltage is −1 volt, the gate-source voltage V _gs is −2 volt. At this time, in order to turn on the MOS transistor, as shown in FIG. 5A, an enhancement type p-type MOS transistor is used and the threshold voltage is set to −1.5 volts. This enhancement type p-type MOS transistor is abbreviated as PE.

When the source electrode of the MOS transistor is connected to +1 volt and the gate voltage is 0 volt, the gate-source voltage V _gs is −1 volt. At this time, in order to turn on the MOS transistor, as shown in FIG. 5B, an enhancement type p-type MOS transistor is used and the threshold voltage is set to −0.5 volts. Since this switch has a threshold voltage of −0.5 volts, it is turned on for both input 0 (V _gs = −1.0) and input 1 (V _gs = −2.0). . This enhancement type p-type MOS transistor is abbreviated as pe.

  These are summarized in Table 4 below.

  Next, consider a case where the source logical value is zero.

When the source electrode of the MOS transistor is connected to 0 volt and the gate voltage is +1 volt, the gate-source voltage V _gs is 1 volt. At this time, in order to turn on the MOS transistor, as shown in FIG. 6A, an enhancement type n-type MOS transistor is used and the threshold voltage is set to 0.5 volts. The enhancement-type n-type MOS transistor is an enhancement-type n-type MOS transistor ne defined with reference to FIG. This enhancement type n-type MOS transistor is abbreviated as ne0.

Further, when the source electrode of the MOS transistor is connected to 0 volt and the gate voltage is −1 volt, the gate-source voltage V _gs is −1 volt. At this time, in order to turn on the MOS transistor, as shown in FIG. 6B, an enhancement type p-type MOS transistor is used and the threshold voltage is set to −0.5 volts. The enhancement type p-type MOS transistor is an enhancement type p-type MOS transistor pe defined with reference to FIG. This enhancement type p-type MOS transistor is abbreviated as pe0.

Further, when the source electrode of the MOS transistor is connected to 0 volt and the gate voltage is 0 volt, the gate-source voltage V _gs becomes 0 volt. At this time, in order to turn on the MOS transistor, as shown in FIG. 6C, a depletion type n-type MOS transistor (or p-type MOS transistor) is used and the threshold voltage is set to −0.5. A bolt (or +0.5 volts) may be used. This depletion type n-type MOS transistor (or p-type MOS transistor) is abbreviated as nd (pd).

When the depletion type n-type MOS transistor nd is used, the switch is turned on when both the input 0 (V _gs = 0.0) and the input 1 (V _gs = 1.0). Become. In addition, when the depletion type p-type MOS transistor pd is used, the switch has both input 0 (V _gs = 0.0) and input −1 (V _gs = −1.0). Is turned on.

  These are summarized in Table 5 below.

  From Table 5 above, when the source logical value is 0, as a circuit that outputs output 0 only when the input is 0, as shown in the following Table 6 and FIG. It can be seen that a depletion type n-type MOS transistor nd and a depletion type p-type MOS transistor pd are connected in series between the output terminal and the output terminal.

  Further, from the above table 5, when the source logic value is 0, as shown in the following table 7 and FIG. It can be seen that an enhancement type n-type MOS transistor ne0 and an enhancement type p-type MOS transistor pe0 may be connected in parallel between the input terminal and the output terminal of the value 0.

  Here, in such a circuit, connection of the back gate electrode (base bias) of the MOS transistor will be described.

  The back gate electrode is usually connected to a power source. This method may be used for the n-type MOS transistors NE and ne connected to the power source that supplies the negative voltage and the p-type MOS transistors PE and pe connected to the power source that supplies the positive voltage. However, when the back gate electrodes of the MOS transistors nd, pd, ne0, and pe0 having a power supply of 0 volt are connected to a power supply of 0 volt, when the voltage at the output terminal is positive or negative, A large current flows through a junction diode formed between the back gate electrode and the drain electrode. For example, for the n-type MOS transistors nd and ne, when the output terminal voltage is negative, the source voltage and the drain voltage are reversed, and the n-type MOS transistors nd and ne are sequentially forwarded through a PN junction formed between the back gate electrode and the drain electrode. Directional current will flow. For the p-type MOS transistors pd and pe, when the output terminal voltage is positive, the source voltage and the drain voltage are reversed, and the PN formed between the source electrode, the back gate electrode, and the drain electrode is formed. A forward current flows through the junction.

  In order to prevent the occurrence of such a phenomenon, even if the MOS transistor is connected to a 0 volt power supply, the n-type MOS transistor is connected to a power supply that supplies a negative voltage, and the p-type MOS transistor is Connect to a power supply that supplies positive voltage. Thereby, even when the voltage at the output terminal becomes positive or negative, it is possible to avoid a situation in which a forward current flows through the PN junction between the back gate electrode and the drain electrode.

  Now, the 27 types of univariate ternary logic functions shown in Table 2 can be classified as follows.

Of the above Table 2, what can be realized by a single-stage CMOS (Comlementary MOS) circuit is that the logic function f (x) is f (−1) ≧ f (0) ≧ f with respect to the input x. This is only when there is a relationship of (1). Hereinafter, such a function is referred to as a reverse function. That is, the inversion function is obtained by reversing the magnitude relation of the input x and the magnitude relation of the logical function f (x). The inversion functions are the functions f ₁₀ , f ₁₃ , f ₁₉ , f ₂₂ , f ₂₃ , f ₂₅ , and f ₂₆ among the 27 types of univariate ternary logic functions shown in Table 2 above. This is class 1.

Among the 27 types of univariate ternary logic functions shown in Table 2 above, the functions f _{02 to} f ₀₅ , functions f _{07 to} f ₀₉ , functions f _{15 to} f ₁₈ , functions f ₂₀ , f ₂₁ , and f ₂₄ are Since it is not an inversion function, it cannot be realized by a single-stage CMOS circuit. Among these univariate ternary logic functions, the functions f _{02 to} f ₀₅ and the functions f _{07 to} f ₀₉ are complementary and symmetrical to the functions f _{26 to} f ₂₃ and the functions f _{21 to} f ₁₉ , respectively. In principle, the functions f _{26 to} f ₁₉ may be realized, and the inverter f ₂₂ may be provided in the subsequent stage. This is class 2.

The function _{f 15} is inverse functions _{f 13} and is complementary symmetry, further, the function _{f 18} is inverted function because it is complementary symmetric and _{f 10,} inverse functions _{f 13, f} each subsequent stage inverter f _{10 23} may be provided. This is also classified as Category 2.

Further, among the 27 types of univariate ternary logic functions shown in Table 2 above, the functions f ₁₁ and f ₁₇ and the functions f ₁₂ and f ₁₆ are in a complementary symmetrical relationship, but are not inversion functions. Therefore, it cannot be realized by a one-stage CMOS circuit. Here, the functions f ₁₁ and f ₁₂ are each realized by a two-stage CMOS circuit. This is class 3.

Furthermore, the functions f ₁₇ and f ₁₆ can be realized by providing an inverter at the subsequent stage of the functions f ₁₁ and f ₁₂ , respectively, but a three-stage CMOS circuit is obtained. Therefore, when attention is paid to the complementary symmetry of the functions f ₁₁ and f ₁₇ and the functions f ₁₂ and f ₁₆ , it can be directly realized by a two-stage CMOS circuit. This is class 3 ′.

Further, since the remaining functions f ₂₀ , f ₂₁ , and f ₂₄ are not inversion functions, they are realized by a two-stage CMOS circuit. This is also classified as Category 3. Furthermore, the functions f ₀₈ , f ₀₇ , and f ₀₄ can be realized by a two-stage CMOS circuit directly from the complementary symmetry with the functions f ₂₀ , f ₂₁ , and f ₂₄ , respectively. This is also classified as category 3 ′.

From the above, the circuits to be realized are seven types of inverters f ₁₀ , f ₁₃ , f ₁₉ , f ₂₂ , f ₂₃ , f ₂₅ , and f ₂₆ , and f ₁₁ , f ₁₂ , and f ₂₀ that are not inverters. , F ₂₁ , f ₂₄ , a total of 12 types. Furthermore, in addition to these 12 types of circuits, a total of 17 types are realized by adding five types of functions f ₀₄ , f ₀₇ , f ₀₈ , f ₁₆ , and f _{17 that} can be realized directly by a two-stage CMOS circuit from complementary symmetry. do it.

Of the functions f _{02 to} f ₀₉ classified as classification 2, the rest are functions f ₀₂ , f ₀₃ , f ₀₅ , and f ₀₉ . Among these, the function f ₀₂ = (− 1, −1, 0) is realized by providing an inverter f ₁₃ = (0, 0, −1) in the subsequent stage of the function f ₂₆ = (1, 1, 0). be able to. Further, the function f ₀₃ = (− 1, −1,1) is realized by providing an inverter f ₁₉ = (1, −1, −1) after the function f ₂₅ = (1,1, −1). can do. Furthermore, the function f ₀₅ = (− 1, 0, 0) can be realized by providing an inverter f ₁₃ = (0, 0, −1) after the function f ₂₃ = (1, 0, 0). it can. Furthermore, the function f ₀₉ = (− 1, 1, 1) is realized by providing an inverter f ₂₅ = (1, 1, −1) after the function f ₁₉ = (1, −1, −1). can do.

Each of these functions f ₀₂ , f ₀₃ , f ₀₅ , and f ₀₉ has six ways of realization. Of these, there are four ways of realization, except for those using the most common inverter f ₂₂ = (1, 0, −1). For example, the function f ₀₃ may set the subsequent inverter to f ₂₅ = (1, 1, −1). In the circuit described in JP-T-2002-517937, the front of the device function _f 25 = (1,1, -1) or function _{f 19 = (1, -1,} -1) either It is unified.

  In summary, the following Table 8 is obtained.

  Each function classified in this way can be realized as follows.

First, an implementation method of seven types of inversion functions f ₁₀ , f ₁₃ , f ₁₉ , f ₂₂ , f ₂₃ , f ₂₅ , and f ₂₆ that can be realized by a one-stage CMOS circuit classified as category 1 will be described. .

Function _{f 10} is (- 1, 0, 1) as input, and outputs (0, -1, -1). Therefore, as shown in FIG. 9, the function f ₁₀ drives the enhancement-type p-type MOS transistor pe0 with the input b so that the source logic value 0 is turned on when the input is −1. For the source logical value −1, the enhancement-type n-type MOS transistor ne can be driven by the input b so that the source logical value −1 is turned on when the inputs are 0 and 1.

The function _{f 13} is (- 1, 0, 1) as input, and outputs the (0,0, -1). Therefore, as shown in FIG. 10, the function f ₁₃ sets the depletion type p-type MOS transistor pd at the input b so that the source logic value 0 is turned on when the input is −1, 0. It can be realized by driving the enhancement-type n-type MOS transistor NE with the input b so that the source logical value −1 is turned on when the input is 1, for the source logical value −1.

Further, the function f ₁₉ has (-1, 0, 1) as input and (1, -1, -1) as output. Therefore, as shown in FIG. 11, the function f ₁₉ drives the enhancement-type p-type MOS transistor PE with the input b so that the source logical value 1 is turned on when the input is −1. For the source logical value −1, the enhancement-type n-type MOS transistor ne can be driven by the input b so that the source logical value −1 is turned on when the inputs are 0 and 1.

Furthermore, the function f ₂₂ has (-1, 0, 1) as input and (1, 0, -1) as output. Therefore, as shown in FIG. 12, the function f ₂₂ drives the enhancement-type p-type MOS transistor PE with the input b so that the source logic value 1 is turned on when the input is −1. For a source logical value 0, a series circuit of a depletion type n-type MOS transistor nd and a depletion type p-type MOS transistor pd is driven by an input b so that the source logical value 0 is turned on when the input is 0. Furthermore, the enhancement type n-type MOS transistor NE is driven by the input b so that the source logical value −1 is turned on when the input is 1, and this can be realized.

The function _{f 23} is (- 1, 0, 1) as input, and outputs (1,0,0). Therefore, as shown in FIG. 13, the function f ₂₃ drives the enhancement type p-type MOS transistor PE with the input b so that the source logical value 1 is turned on when the input is −1. The source logical value 0 can be realized by driving the depletion type n-type MOS transistor nd with the input b so that the source logical value 0 is turned on when the inputs are 0 and 1.

Further, the function f ₂₅ has (-1, 0, 1) as input and (1, 1, -1) as output. Therefore, as shown in FIG. 14, the function f ₂₅ drives the enhancement type p-type MOS transistor pe with the input b so that the source logical value 1 is turned on when the input is −1, 0. At the same time, the enhancement type n-type MOS transistor NE is driven by the input b so that the source logical value −1 is turned on when the input is 1, and can be realized.

Furthermore, the function f ₂₆ takes (−1, 0, 1) as input and (1, 1, 0) as output. Therefore, as shown in FIG. 15, the function f ₂₆ drives the enhancement type p-type MOS transistor pe with the input b so that the source logic value 1 is turned on when the input is −1, 0. At the same time, the enhancement n-type MOS transistor ne0 is driven by the input b so that the source logical value 0 is turned on when the input is 1, and this can be realized.

As described above, the seven types of inversion functions f ₁₀ , f ₁₃ , f ₁₉ , f ₂₂ , f ₂₃ , f ₂₅ , and f ₂₆ classified as class 1 can be realized by a single-stage CMOS circuit.

Next, a method for realizing five types of functions f ₁₁ , f ₁₂ , f ₂₀ , f ₂₁ , and f ₂₄ that cannot be realized by a one-stage CMOS circuit classified as category 3 will be described. These functions f ₁₁ , f ₁₂ , f ₂₀ , f ₂₁ , and f ₂₄ require an additional circuit on the input side, and become a two-stage CMOS circuit.

Function _{f 11} is (- 1, 0, 1) as input, and outputs (0, -1,0). Therefore, as shown in FIG. 16, the function f ₁₁ passes the input b through the inversion function f ₂₅ = (1, 1, −1) and sets its output to ¬ b, and for the source logical value 0, the input −1, The parallel circuit of two enhancement-type p-type MOS transistors pe is inserted so that the on-state is turned on when it is 1, one p-type MOS transistor pe1 is driven by the input b, and the other p-type MOS transistor The pe2 is configured to be driven by the inverted output ¬b of the input b. The function f ₁₁ inserts a series circuit of two enhancement type n-type MOS transistors ne so that the source logic value −1 is turned on when the input is 0, and one n-type MOS transistor This can be realized by driving ne1 with the input b and driving the other n-type MOS transistor ne2 with the inverted output ¬b of the input b. The operation of the function f ₁₁ is shown in the following Table 9.

The function _{f 12} is (- 1, 0, 1) as input, and outputs (0, -1,1). Therefore, as shown in FIG. 17, the function f ₁₂ passes the input b through the inversion function f ₂₅ = (1, 1, −1) and sets its output to ¬ b. The enhancement type p-type MOS transistor pe is configured to be driven by the input b so as to be turned on in some cases. The function f ₁₂ inserts a series circuit of two enhancement type n-type MOS transistors ne so that the source logic value −1 is turned on when the input is 0, and one n-type MOS transistor The ne1 is driven by the input b, and the other n-type MOS transistor ne2 is driven by the inverted output ¬b of the input b. The function f ₁₂ drives one of the enhancement-type p-type MOS transistors PE and pe with the inverted output ¬b of the input b so that the source logic value 1 is turned on when the input is the input 1. This can be realized. The operation of the function _{f 12} is shown in the following Table 10.

Furthermore, the function f ₂₀ has (-1, 0, 1) as input and (1, -1, 0) as output. Therefore, as shown in FIG. 18, the function f ₂₀ passes the input b through the inversion function f ₂₅ = (1, 1, −1) and sets its output to ¬ b. The enhancement type p-type MOS transistor PE is configured to be driven by the input b so as to be turned on in some cases. The function f ₂₀ inserts a series circuit of two enhancement type n-type MOS transistors ne so that the source logic value −1 is turned on when the input is 0, and one n-type MOS transistor The ne1 is driven by the input b, and the other n-type MOS transistor ne2 is driven by the inverted output ¬b of the input b. Note that the n-type MOS transistor driven by the inverted output ¬b of the input b may be NE. The function f ₂₀ inputs either the enhancement-type p-type MOS transistor pe or the depletion-type p-type MOS transistor pd so that the source logic value 0 is turned on when the input is the input 1. This can be realized by driving with the inverted output b of b. The operation of the function f ₂₀ is as shown in the following table 11.

Furthermore, the function _{f 21} is (- 1, 0, 1) as input, and outputs (1, -1,1). Accordingly, as shown in FIG. 19, the function f ₂₁ passes the input b through the inversion function f ₂₅ = (1, 1, −1) and sets the output to ¬ b. The parallel circuit of two enhancement-type p-type MOS transistors PE is inserted so that the on-state is turned on in the case of 1, one p-type MOS transistor PE1 is driven by the input b, and the other p-type MOS transistor The PE2 is configured to be driven with an inverted output ¬b of the input b. Note that the p-type MOS transistor driven by the inverted output ¬b of the input b may be pe. The function f ₂₁ inserts a series circuit of two enhancement type n-type MOS transistors ne so that the source logical value −1 is turned on when the input is 0, and one n-type MOS transistor This can be realized by driving ne1 with the input b and driving the other n-type MOS transistor ne2 with the inverted output ¬b of the input b. Note that the n-type MOS transistor driven by the inverted output ¬b of the input b may be NE. The operation of the function f ₂₁ is as shown in Table 12 below.

The function f ₂₄ has (-1, 0, 1) as input and (1, 0, 1) as output. Therefore, as shown in FIG. 20, the function f ₂₄ passes the input b through the inversion function f ₂₅ = (1, 1, −1) and sets its output to ¬b. The parallel circuit of two enhancement-type p-type MOS transistors PE is inserted so that the on-state is turned on in the case of 1, one p-type MOS transistor PE1 is driven by the input b, and the other p-type MOS transistor The PE2 is configured to be driven with an inverted output ¬b of the input b. Note that the p-type MOS transistor driven by the inverted output ¬b of the input b may be pe. The function f ₂₄ inserts a series circuit of two depletion-type n-type MOS transistors nd so that the source logic value 0 is turned on when the input is 0, and one n-type MOS transistor This can be realized by driving the transistor nd1 with the input b and driving the other n-type MOS transistor nd2 with the inverted output ¬b of the input b. The n-type MOS transistor driven by the inverted output ¬b of the input b may be ne. The operation of the function f ₂₄ is as shown in Table 13 below.

As described above, the five types of functions f ₁₁ , f ₁₂ , f ₂₀ , f ₂₁ , and f ₂₄ classified into the classification 3 can be realized by a two-stage CMOS circuit.

Next, five types of functions f ₁₇ , f ₁₇ , classified as classification 3 ′, as complementary symmetrical circuits of five types of functions f ₁₁ , f ₁₂ , f ₂₀ , f ₂₁ , f ₂₄ that are not inverted functions classified as classification 3 are used. It will be described _{f 16, f 08, f 07} , f 04 of the realization method. These functions f ₁₇ , f ₁₆ , f ₀₈ , f ₀₇ , and f ₀₄ require an additional circuit on the input side as in the case of the function that is not an inversion function, resulting in a two-stage CMOS circuit.

The function f ₁₇ has (−1, 0, 1) as input and (0, 1, 0) as output. Therefore, as shown in FIG. 21, the function f ₁₇ passes the input b through the inversion function f ₁₉ = (1, −1, −1) and sets the output to ¬b. , 1, a parallel circuit of two enhancement type n-type MOS transistors ne is inserted so that one n-type MOS transistor ne1 is driven by the input b and the other n-type MOS transistor is turned on. The transistor ne2 is configured to be driven with an inverted output ¬b of the input b. Note that the n-type MOS transistor driven by the inverted output ¬b of the input b may be nd. The function f ₁₇ inserts a series circuit of two enhancement type p-type MOS transistors pe so that the source logical value 1 is turned on when the input is 0, and one p-type MOS transistor pe1 is inserted. Is driven by the input b, and the other p-type MOS transistor pe2 is driven by the inverted output ¬b of the input b. The p-type MOS transistor driven by the inverted output ¬b of the input b may be a PE. The operation of the function f ₁₇ is as shown in Table 14 below.

The function f ₁₆ has (-1, 0, 1) as input and (0, 1, -1) as output. Therefore, as shown in FIG. 22, the function f ₁₆ passes the input b through the inversion function f ₁₉ = (1, −1, −1) and sets the output to ¬b. In this case, either the enhancement type n-type MOS transistor ne or the depletion type n-type MOS transistor nd is driven by the inverted output ¬b of the input b. The function f ₁₆ inserts a series circuit of two enhancement type p-type MOS transistors pe so that the source logic value 1 is turned on when the input is 0, and one p-type MOS transistor pe1 is inserted. Is driven by the input b, and the other p-type MOS transistor pe2 is driven by the inverted output ¬b of the input b. The p-type MOS transistor driven by the inverted output ¬b of the input b may be a PE. The function f ₁₆ can be realized by driving the enhancement type n-type MOS transistor NE with the input b so that the source logic value −1 is turned on when the input is 1. The operation of the function _{f 16} is shown in the following Table 15.

Further, the function f08 takes (-1, ₀ , 1) as input and (-1, 1, ₀ ) as output. Therefore, as shown in FIG. 23, the function f ₀₈ passes the input b through the inversion function f ₁₉ = (1, −1, −1) and sets the output to ¬b, and the input − The enhancement type n-type MOS transistor NE is configured to be driven with the inverted output ¬b of the input b so that the on-state is turned on when 1. The function _{f 08} is the source logic value 1, so that the ON state when the input is zero, insert the series circuit of two enhancement p-type MOS transistor pe, one p-type MOS transistor pe1 Is driven by the input b, and the other p-type MOS transistor pe2 is driven by the inverted output ¬b of the input b. The p-type MOS transistor driven by the inverted output ¬b of the input b may be a PE. Then, the function f _08, for the source logic value 0, so that the ON state when the input 1, by driving the enhancement type n-type MOS transistor ne by an input b, can be achieved. The operation of the function f ₀₈ is as shown in the following table 16.

Furthermore, the function f ₀₇ takes (−1, 0, 1) as an input and (−1, 1, −1) as an output. Therefore, as shown in FIG. 24, the function f ₀₇ passes the input b through the inversion function f ₁₉ = (1, −1, −1) and sets the output to ¬b, and the input − The parallel circuit of two enhancement-type n-type MOS transistors NE is inserted so that the on-state is turned on in the case of 1, 1 and one n-type MOS transistor NE1 is driven by the input b, while the other n-type MOS transistor NE1 is driven. The MOS transistor NE2 is configured to be driven with an inverted output ¬b of the input b. The n-type MOS transistor driven by the inverted output ¬b of the input b may be ne. The function f ₀₇ inserts a series circuit of two enhancement-type p-type MOS transistors pe so that the source logic value 1 is turned on when the input is 0, and one p-type MOS transistor pe 1 Is driven by the input b, and the other p-type MOS transistor pe2 is driven by the inverted output ¬b of the input b. Note that the p-type MOS transistor driven by the inverted output ¬b of the input b may be a PE. The operation of this function f ₀₇ is as shown in Table 17 below.

The function f ₀₄ has (-1, 0, 1) as input and (-1, 0, -1) as output. Therefore, as shown in FIG. 25, the function f ₀₄ passes the input b through the inversion function f ₁₉ = (1, −1, −1) and sets the output to ¬b, and the input − The parallel circuit of two enhancement-type n-type MOS transistors NE is inserted so that the on-state is turned on in the case of 1, 1 and one n-type MOS transistor NE1 is driven by the input b, while the other n-type MOS transistor NE1 is driven. The MOS transistor NE2 is configured to be driven with an inverted output ¬b of the input b. The n-type MOS transistor driven by the inverted output ¬b of the input b may be ne. The function f ₀₄ inserts a series circuit of two depletion-type p-type MOS transistors pd so that the source logic value 0 is turned on when the input is 0, and one p-type MOS is inserted. This can be realized by driving the transistor pd1 with the input b and driving the other p-type MOS transistor pd2 with the inverted output ¬b of the input b. Note that the p-type MOS transistor driven by the inverted output ¬b of the input b may be pe. The operation of the function f ₀₄ is as shown in Table 18 below.

As described above, the five types of functions f ₁₇ , f ₁₆ , f ₀₈ , f ₀₇ , and f ₀₄ classified into the classification 3 ′ can be realized by a two-stage CMOS circuit.

Next, an implementation method of the six types of functions f ₀₂ , f ₀₃ , f ₀₅ , f ₀₉ , f ₁₅ , and f ₁₈ classified into the classification 2 will be described. As described above, these functions f ₀₂ , f ₀₃ , f ₀₅ , f ₀₉ , f ₁₅ , and f ₁₈ are respectively subsequent to the functions f ₂₆ , f ₂₅ , f ₂₃ , f ₁₉ , f ₁₃ , and f ₁₀ . This can be realized by providing an inverter.

That is, the function f ₀₂ takes (-1, 0, 1) as input and (-1, 1, 0) as output. Therefore, as shown in FIG. 26, the function f ₀₂ can be realized by providing an inverter f ₁₃ = (0, 0, −1) subsequent to the function f ₂₆ = (1, 1, 0).

The function f ₀₃ has (-1, 0, 1) as input and (-1, -1, 1) as output. Therefore, as shown in FIG. 27, the function f ₀₃ can be realized by providing an inverter f ₁₉ = (1, −1, −1) in the subsequent stage of the function f ₂₅ = (1,1, −1). it can.

Further, the function f ₀₅ takes (-1, 0, 1) as an input and (-1, 0, 0) as an output. Therefore, as shown in FIG. 28, the function f ₀₅ can be realized by providing an inverter f ₁₃ = (0, 0, −1) after the function f ₂₃ = (1, 0, 0).

Furthermore, the function f ₀₉ takes (−1, ₀ , 1) as input and (−1, 1, 1) as output. Therefore, as shown in FIG. 29, the function f ₀₉ can be realized by providing an inverter f ₂₅ = (1,1, −1) in the subsequent stage of the function f ₁₉ = (1, −1, −1). it can.

The function _{f 15} is (- 1, 0, 1) as input, and outputs (0,0,1). Therefore, as shown in FIG. 30, the function f ₁₅ can be realized by providing an inverter f ₂₃ = (1, 0, 0) after the function f ₁₃ = (0, 0, −1).

Further, the function f ₁₈ takes (-1, 0, 1) as input and (0, 1, 1) as output. Therefore, as shown in FIG. 31, the function f ₁₈ can be realized by providing the inverter f ₂₃ = (1, 0, 0) in the subsequent stage of the function f ₁₀ = (0, −1, −1). .

As described above, the six types of functions f ₀₂ , f ₀₃ , f ₀₅ , f ₀₉ , f ₁₅ , and f ₁₈ classified into the classification 2 can be realized by the complementary symmetric circuit and the inverter.

  Now, a specific configuration of a ternary logic function circuit that performs a two-variable ternary logic operation using such a one-variable ternary logic function will be described below. Specifically, the ternary logic function circuit shown in FIG. 1 can be configured as shown in FIG.

That is, in this ternary logic function circuit, the function f ₁₉ shown in FIG. 11 is used as the univariate ternary logic function circuit C1 connected to the control terminal C-T1 of the transfer gate T1, and the transfer is performed. as the control terminal D-T1 variable three-valued logic function circuit D1 connected to the gate T1, it may be used function f ₀₉ shown in FIG. 29 above. In this ternary logic function circuit, the function f ₀₇ shown in FIG. 24 is used as the univariate ternary logic function circuit C2 connected to the control terminal C-T2 of the transfer gate T2, and the transfer _f07 is used. as the control terminal D-T2 variable three-valued logic function circuit D2 connected to the gate T2, it may be used function f ₂₁ shown in FIG. 19 above. Further, in this ternary logic function circuit, the function f ₀₃ shown in FIG. 27 is used as the univariate ternary logic function circuit C3 connected to the control terminal C-T3 of the transfer gate T3, and the transfer is performed. as the control terminal D-T3 variable three-valued logic function circuit D3 connected to the gate T3, it may be used function f ₂₅ shown in FIG. 14 above.

Here, in this three-valued logic function circuit, one-variable three-valued logic function circuit D1 configured as the function f _09, as described above, it downstream of the function f ₁₉ is provided with a inverter f ₂₅ from it can be realized by connecting the output of the one-variable three-valued logic function circuit C1 to the inverter f _25. Similarly, in the three-valued logic function circuit, one-variable three-valued logic function circuit C3 configured as the function f _03, as described above, in which the inverter f ₁₉ disposed downstream of the function f ₂₅ from it can be realized by connecting the output of the one-variable three-valued logic function circuit D3 to the inverter f _19. Therefore, the ternary logic function circuit can be simplified as shown in FIG.

That is, in this ternary logic function circuit, the function f ₁₉ previously shown in FIG. 11 is used as the one-variable ternary logic function circuit C1 connected to the control terminal C-T1 of the transfer gate T1, and this connect the function f ₂₅ shown earlier as an variable three-valued logic subsequent to the variable three-valued logic function circuit of function circuit C1 D1 'in FIG. 14, which the control terminal D-T1 of the transfer gate T1 Connecting. In this ternary logic function circuit, the function f ₂₅ shown in FIG. 14 is used as the one-variable ternary logic function circuit D3 connected to the control terminal D-T3 of the transfer gate T3. The function f ₁₉ shown in FIG. 11 as the one variable ternary logic function circuit C3 ′ is connected to the subsequent stage of the one variable ternary logic function circuit D3, and this is connected to the control terminal C-T3 of the transfer gate T3. Connecting.

  In such a ternary logic function circuit, the number of necessary elements can be reduced by four compared to the configuration shown in FIG. Further, in this ternary logic function circuit, the delay time can be made equal for an arbitrary input pattern, as will be described later.

Further, the ternary logic function circuit shown in FIG. 33 can be further simplified. In the three-valued logic function circuit shown in FIG. 33, since the one-variable three-valued logic function circuit C2 composed as a function f ₀₇ is obtained by providing the inverter f ₂₅ at the subsequent stage of the function f _21, univariate The output of the ternary logic function circuit D2 can be realized by connecting either of the inverters f ₂₅ and f ₁₉ .

Therefore, in this ternary logic function circuit, as shown in FIG. 34, the function shown in FIG. 19 is used as the one-variable ternary logic function circuit D2 connected to the control terminal DT2 of the transfer gate T2. f ₂₁ is used, and the function f ₂₅ shown in FIG. 14 as the one variable ternary logic function circuit C 2 ′ is connected to the subsequent stage of the one variable ternary logic function circuit D 2, which is connected to the transfer gate T 2. To the control terminal C-T2. Note that in the three-valued logic function circuits, shown 'in place of the function f ₂₅ as one-variable three-valued logic function circuit C2' one-variable three-valued logic function circuit C2 in FIG. 11 previously as a 'function it may be connected to f _19.

  In such a ternary logic function circuit, the number of necessary elements can be further reduced by four compared to the configuration shown in FIG.

  Thus, in the ternary logic function circuit, the circuit can be simplified by utilizing the complementary symmetry of the function to be used.

  Further, when performing a logical operation, a degenerate operation is often performed using a one-variable ternary logic function having the same output with respect to the input. That is, in the two-variable ternary logic function shown in Table 1 above, there is a case where an operation is performed based on a function in which there are rows or columns composed of the same elements. The ternary logic function circuit can cope with such a degenerate binary variable ternary logic operation.

  First, in the binary variable ternary logic function shown in Table 1 above, when the output (p, q, r) for the input a = −1 is equal to the output (s, t, u) for the input a = 0. That is, when (p, q, r) = (s, t, u), the above table 1 is as shown in the following table 19.

  A ternary logic function circuit that performs such a degenerate two-variable ternary logic operation can be configured as shown in FIG. 35 by modifying the configuration shown in FIG.

That is, in this ternary logic function circuit, among the three transfer gates T1, T2, and T3 shown in FIG. 32, one variable ternary logic function circuit B1 = (p, q , R) and the transfer gate T2 that outputs the univariate ternary logic function circuit B2 = (s, t, u) with respect to the input a = 0. One transfer gate T12 is assumed. In this ternary logic function circuit, the univariate ternary logic function circuit C12 obtained by ORing the univariate ternary logic function circuits C1 and C2 is connected to one control terminal C-T12 of the transfer gate T12. At the same time, a one-variable ternary logic function circuit D12 obtained by ANDing the univariate ternary logic function circuits D1 and D2 is connected to the other control terminal D-T12 of the transfer gate T12. Here, the univariate ternary logic function circuit C12 is configured as a function f ₂₅ = (1,1, −1), and the univariate ternary logic function circuit D12 is a function f complementary to the function f _{25. 03} = configured as (-1, -1, 1).

In this ternary logic function circuit, the control signals supplied to the control terminals C-T3 and D-T3 of the transfer gate T3 to which the remaining univariate ternary logic function circuit B3 is connected are respectively (- 1, -1,1) and (1,1, -1), which are none other than the functions f ₀₃ and f ₂₅ . Therefore, in this ternary logic function circuit, the control signal input to the control terminal D-T12 of the transfer gate T12 is input to the control terminal C-T3 of the transfer gate T3, and the control terminal C-T12 of the transfer gate T12. Is input to the control terminal DT3 of the transfer gate T3.

  In this manner, a ternary logic function circuit that performs a degenerate two-variable ternary logic operation with (p, q, r) = (s, t, u) can be configured.

  Next, in the binary variable ternary logic function shown in Table 1 above, when the output (s, t, u) for the input a = 0 is equal to the output (x, y, z) for the input a = 1. That is, when (s, t, u) = (x, y, z), the above table 1 becomes as shown in the following table 20.

  Such a degenerate binary variable ternary logic operation can be configured as shown in FIG. 36 by modifying the configuration shown in FIG.

That is, in this ternary logic function circuit, among the three transfer gates T1, T2 and T3 shown in FIG. 32, the univariate ternary logic function circuit B2 = (s, t, The functions of the transfer gate T2 that outputs u) and the transfer gate T3 that outputs the univariate ternary logic function circuit B3 = (x, y, z) with respect to the input a = 1 are integrated to 1 One transfer gate T23 is assumed. In this ternary logic function circuit, the univariate ternary logic function circuit C23 obtained by ORing the univariate ternary logic function circuits C2 and C3 is connected to one control terminal C-T23 of the transfer gate T23. At the same time, the one-variable ternary logic function circuit D23 obtained by ANDing the univariate ternary logic function circuits D2 and D3 is connected to the other control terminal D-T23 of the transfer gate T23. Here, one-variable three-valued logic function circuit C23, the function _f 09 = - is configured as a (1,1,1), one-variable three-valued logic function circuit D23, the function _{f 09} complementary symmetric function f ₁₉ = (1, -1, -1).

In this ternary logic function circuit, the control signals supplied to the control terminals C-T1 and DT1 of the transfer gate T1 to which the remaining univariate ternary logic function circuit B1 is connected are (1 , -1, -1) and (-1, 1, 1), these are none other than the functions f ₁₉ and f ₀₉ . Therefore, in this ternary logic function circuit, the control signal input to the control terminal D-T23 of the transfer gate T23 is input to the control terminal C-T1 of the transfer gate T1, and the control terminal C-T23 of the transfer gate T23. Is input to the control terminal DT1 of the transfer gate T1.

  In this manner, a ternary logic function circuit that performs a degenerate two-variable ternary logic operation with (s, t, u) = (x, y, z) can be configured.

  Next, in the binary variable ternary logic function shown in Table 1 above, the output (x, y, z) for the input a = 1 and the output (p, q, r) for the input a = −1 are equal. When, that is, (x, y, z) = (p, q, r), the above table 1 is as shown in the following table 21.

  The ternary logic function circuit that performs such a degenerate two-variable ternary logic operation can be configured as shown in FIG. 37 by modifying the configuration shown in FIG.

That is, in this ternary logic function circuit, among the three transfer gates T1, T2, T3 shown in FIG. 32, the univariate ternary logic function circuit B3 = (x, y, The roles of the transfer gate T3 that outputs z) and the transfer gate T1 that outputs the univariate ternary logic function circuit B1 = (p, q, r) with respect to the input a = −1 are integrated. One transfer gate T31 is assumed. In this ternary logic function circuit, the univariate ternary logic function circuit C31 obtained by ORing the univariate ternary logic function circuits C3 and C1 is connected to one control terminal C-T31 of the transfer gate T31. At the same time, a one-variable ternary logic function circuit D31 obtained by ANDing the univariate ternary logic function circuits D3 and D1 is connected to the other control terminal D-T31 of the transfer gate T31. Here, one-variable three-valued logic function circuit C31, the function _f 21 = (1, -1,1) is configured as one-variable three-valued logic function circuit D31, the function _{f 21} complementary symmetric function f ₀₇ = (-1,1, -1).

In this ternary logic function circuit, the control signals supplied to the control terminals C-T2 and DT2 of the transfer gate T2 to which the remaining univariate ternary logic function circuit B2 is connected are respectively (- 1,1, -1) and (1, -1), but is, they are nothing but the function _{f 07, f 21.} Therefore, in this ternary logic function circuit, the control signal input to the control terminal D-T31 of the transfer gate T31 is input to the control terminal C-T2 of the transfer gate T2, and the control terminal C-T31 of the transfer gate T31. Is input to the control terminal DT2 of the transfer gate T2.

  In this way, it is possible to configure a ternary logic function circuit that performs a degenerate two-variable ternary logic operation in which (x, y, z) = (p, q, r).

  The degenerate ternary logic function circuit as described above can be generalized and expressed as shown in FIG.

  First, when any two of the three one-variable ternary logic function circuits B1, B2, and B3 that obtain outputs according to the logical values -1, 0, and 1 of one input b are the same, these are the same. The one variable ternary logic function circuits Bi and Bj are integrated into one variable ternary logic function circuit Bij, and the remaining one variable ternary logic function circuit Bj is defined as Bk.

  Subsequently, of the three transfer gates T1, T2, and T3 that are turned on according to the logical values −1, 0, and 1 of the other input a, they are connected to the univariate ternary logic function circuits Bi and Bj. The transfer gates Ti and Tj are integrated into one transfer gate Tij, and the transfer gate Tij is connected to the integrated single variable ternary logic function circuit Bij. The transfer gate connected to the remaining univariate ternary logic function circuit Bk is Tk, the two control terminals of the transfer gate Tij are C-Tij, D-Tij, and the two control terminals of the transfer gate Tk. Are C-Tk and D-Tk.

  Further, the one-variable ternary logic function circuit connected to the control terminal C-Tij of the integrated transfer gate Tij is set to Cij obtained by ORing the one-variable ternary logic function circuits Ci and Cj, and the control is performed. The univariate ternary logic function circuit connected to the terminal D-Tij is assumed to be Dij obtained by ANDing the univariate ternary logic function circuits Di and Dj.

  Then, one control terminal C-Tk of the remaining transfer gate Tk is connected to the output of the univariate ternary logic function circuit Dij, and the other control terminal D-Tk is connected to the univariate ternary logic function circuit. Connect to the output of Cij.

  In this way, a generalized degenerate ternary logic function circuit as shown in FIG. 38 can be configured.

  Such a degenerated ternary logic function circuit can also be simplified.

  That is, in the configuration shown in FIG. 38, the univariate ternary logic function circuits Bij and Bk connected to the input b are in a complementary symmetrical relationship and are connected to the control terminals T-Cij and T-Dij of the transfer gate Tij. Focusing on the fact that the outputs of the univariate ternary logic function circuits Cij and Dij are complementary and symmetrical, instead of either of the univariate ternary logic function circuits Dij and Cij, It can be seen that one of the inverting circuits of the logic function circuits Cij and Dij may be used. Therefore, the degenerated ternary logic function circuit can be simplified as shown in FIG.

First, in the case of the configuration in which the single variable ternary logic function circuit Cij is left, as shown in FIG. 39, the univariate ternary logic function circuit connected to the control terminal C-Tij of the integrated transfer gate Tij is changed. The univariate ternary logic function circuit Ci, Cj obtained by ORing the univariate ternary logic function circuits Ci and Cj, and the univariate ternary logic function circuit connected to the control terminal D-Tij An inverter D′ ij (= f ₂₅ ) that inverts the output of Cij is used.

  Then, one control terminal C-Tk of the remaining transfer gate Tk is connected to the output of the inverter D′ ij, and the other control terminal D-Tk is connected to the output of the univariate ternary logic function circuit Cij. To do.

On the other hand, in the configuration in which the single variable ternary logic function circuit Dij is left, as shown in FIG. 40, the univariate ternary logic function circuit connected to the control terminal D-Tij of the integrated transfer gate Tij is changed. , A uni-value ternary logic function circuit Di, Dj, and a uni-value ternary logic function circuit connected to the control terminal C-Tij. An inverter C ″ ij (= f ₂₅ ) that inverts the output of Dij is used.

  Then, one control terminal C-Tk of the remaining transfer gate Tk is connected to the output of the one-variable ternary logic function circuit Dij, and the other control terminal D-Tk is connected to the output of the inverter C ″ ij. Connecting.

  Thus, the degenerated ternary logic function circuit can be simplified and configured.

  As described above, the configuration of the ternary logic function circuit that realizes all the two variable ternary logic functions using a plurality of one variable ternary logic function circuits and three transfer gates has been described. Such a ternary logic function circuit can be configured such that the rising switching time and the falling switching time are symmetric while using both the n-type MOS transistor and the p-type MOS transistor. This will be described below.

First, among the 17 types of univariate ternary logic function circuits that must be realized, 7 types of inverting circuits f ₁₀ , f ₁₃ , f ₁₉ , f ₂₂ , f ₂₃ , f ₂₅ , and f ₂₆ will be described. To do.

In these inverting circuits, except for the function f ₂₂ which is a ternary inverter, the source terminals of the n-type MOS transistor and the p-type MOS transistor are respectively connected to two different source logics, that is, two different power sources. At the same time, the drain terminal is coupled to form an output terminal, which has the same structure as a binary CMOS inverter.

  Here, it is known that the asymmetry of the switching time is caused by a difference in carrier mobility between the n-type MOS transistor and the p-type MOS transistor. In the binary CMOS inverter, each of the n-type MOS transistor and the p-type MOS transistor is compensated so as to compensate for the asymmetry of the switching time due to the difference in carrier mobility between the n-type MOS transistor and the p-type MOS transistor. The rising switching time and the falling switching time are made equal by adjusting the width of the gate forming the channel and equalizing the resistance (on-resistance) when the n-type MOS transistor and the p-type MOS transistor are conductive. It is possible.

Therefore, even in the three-valued logic function circuit, similarly to the case of binary, the inverting circuits except for three-valued inverter of the function f _22, by adjusting the gate width of the n-type MOS transistor and p-type MOS transistor, The rising switching time and the falling switching time can be made equal.

On the other hand, in the ternary inverter of the function f ₂₂ , in addition to two source logical values of −1 and +1, a depletion type n-type MOS transistor and a p-type MOS connected in series to the source logical value 0 There is a transistor. This transistor has an effect of pulling to 0 when the output terminal is -1 or +1. The rise or fall time depends on the on-resistance of the depletion type n-type MOS transistor and the p-type MOS transistor connected in series. The on-resistance is determined by the n-type MOS transistor and the p-type MOS transistor. By adjusting the respective gate widths, the design target value can be obtained. Therefore, in the ternary logic function circuit, for the inverting circuit f ₂₂ , the rising switching time and the falling switching time of the n-type MOS transistor and the p-type MOS transistor connected to the source logical values 1 and −1 Can be made equal.

Next, asymmetry of switching time in the case of five types of non-inverting circuits f ₁₁ , f ₁₂ , f ₂₀ , f ₂₁ , f ₂₄ and their complementary symmetric circuits f ₁₇ , f ₁₆ , f ₀₈ , f ₀₇ , f _04. A method for removing the property will be described.

First, the non-inverting circuits f ₁₁ , f ₁₂ , f ₂₀ , f ₂₁ , and f ₂₄ are roughly classified into the non-inverting circuits f ₁₁ , f ₂₁ , and f ₂₄ and the non-inverting circuits f ₁₂ and f ₂₀ according to their configurations. Is done. As shown in FIG. 41, the former includes two p-type MOS transistors P1 and P2 connected in parallel to the source logic value A and two n-type MOS transistors N1 and N2 connected in series to the source logic value B. It consists of. On the other hand, the latter is connected in series to the p-type MOS transistor P1 connected to the source logic value A, the p-type MOS transistor P2 connected to the source logic value C, and the source logic value B, as shown in FIG. The two n-type MOS transistors N1 and N2 are formed.

In the non-inverting circuits f ₁₁ , f ₂₁ , and f _{24 having the} former configuration shown in FIG. 41, one p-type MOS transistor P2 among the p-type MOS transistors connected in parallel and the n-type MOS connected in series. One n-type MOS transistor N2 of the transistors is driven by an inverted output ¬b obtained through an inverting circuit that inverts the input b, whereas the other p-type MOS transistor P1 and the n-type MOS transistor P1 The MOS transistor N1 is directly driven by the input b.

  Here, in the n-type MOS transistors N1 and N2 connected in series, even if the n-type MOS transistor N1 is directly driven by the input b, the n-type MOS transistor N2 driven by the inverted output ¬b is delayed. Therefore, the timing for turning on is determined by the n-type MOS transistor N2.

  On the other hand, in the p-type MOS transistors P1 and P2 connected in parallel, since the p-type MOS transistor P1 is directly driven by the input b, the on-state timing is advanced by the delay time by the inverting circuit. Become.

Therefore, in the non-inverting circuits f ₁₁ , f ₂₁ , and f ₂₄ , among the outputs (X, Y, X) for the input (−1, 0, 1), the output X for the input −1 is the other input 0, 1 earlier than the outputs Y and X for 1 by the delay time by the inverting circuit.

Therefore, in these non-inverting circuits f ₁₁ , f ₂₁ , and f ₂₄ , the response speed of the p-type MOS transistor P 1 that is directly driven by the input b is reduced in order to remove such output asymmetry. Specifically, the on-resistance may be increased in the non-inverting circuits f ₁₁ , f ₂₁ , and f ₂₄ . However, in the non-inverting circuits f ₁₁ , f ₂₁ , and f _24, it is necessary to keep the gate capacitance constant in order not to affect other circuits.

  Here, the on-resistance is proportional to the gate length and inversely proportional to the gate width. On the other hand, the gate capacitance is proportional to the gate area, that is, the product of the gate length and the gate width.

Therefore, in the non-inverting circuits f ₁₁ , f ₂₁ , and f ₂₄ , the p-type MOS transistor P 1 is configured to increase the gate length and reduce the gate width on condition that the gate area is kept constant. .

Thereby, in the non-inverting circuits f ₁₁ , f ₂₁ , and f ₂₄ , the asymmetry of the switching time can be eliminated. Note that power consumption in the MOS transistor is proportional to the gate capacitance. In this respect, in the non-inverting circuits f ₁₁ , f ₂₁ , and f ₂₄ , the gate capacitance is kept constant even when the gate length and the gate width of the p-type MOS transistor P 1 are changed. There is no change.

On the other hand, in the non-inverting circuits f ₁₂ and f _{20 having the} latter configuration shown in FIG. 42, the transistor directly driven by the input b is a p-type MOS transistor P 1 connected to the source logic value A. In the non-inverting circuits f ₁₂ and f ₂₀ , the timing at which the p-type MOS transistor P1 is turned on is an n-type MOS transistor driven by the inverted output ¬b obtained through the inverting circuit that inverts the input b. Compared to N2 and the p-type MOS transistor P2, it is earlier by the delay time by the inverting circuit.

Therefore, in these non-inverting circuits f ₁₂ and f ₂₀ , in order to remove such output asymmetry, the gate area of the p-type MOS transistor P 1 directly driven by the input b is kept constant as described above. On this condition, the gate length is increased and the gate width is reduced to reduce the response speed.

Thereby, in the non-inverting circuits f ₁₂ and f ₂₀ , the asymmetry of the switching time can be eliminated. Even in the non-inverting circuits f ₁₂ and f ₂₀ , the power consumption does not change because the gate capacitance of the p-type MOS transistor P1 is kept constant.

Next, a method for removing asymmetry of switching time in the case of complementary symmetric circuits f ₁₇ , f ₁₆ , f ₀₈ , f ₀₇ , and f ₀₄ of the non-inverting circuits f ₁₁ , f ₁₂ , f ₂₀ , f ₂₁ , and f _24. explain.

Complementary symmetry circuits _{f 17, f 16, f 08} , f 07, f 04 , similarly to the non-inverting circuit _{f 11, f 12, f 20} , f 21, f 24, by its configuration, complementary symmetry circuits _{f 17,} It is roughly divided into f ₀₇ and f ₀₄ and complementary symmetrical circuits f ₁₆ and f ₀₈ . The former is the same as the non-inverting circuits f ₁₁ , f ₂₁ , and f ₂₄ previously shown in FIG. 41, and the latter is the same as the non-inverting circuits f ₁₂ and f ₂₀ previously shown in FIG. Therefore, in these complementary symmetric circuits f ₁₇ , f ₁₆ , f ₀₈ , f ₀₇ , and f ₀₄ , the rising switching time is obtained in the same manner as the non-inverting circuits f ₁₁ , f ₁₂ , f ₂₀ , f ₂₁ , and f _24. And the asymmetry of the falling switching time can be eliminated. In these complementary symmetric circuits f ₁₇ , f ₁₆ , f ₀₈ , f ₀₇ , and f ₀₄ , the power consumption does not change because the gate capacitance of the p-type MOS transistor P 1 is kept constant.

  As described above, in the ternary logic function circuit, the rising switching time and the falling switching time can be made symmetric while using both the n-type MOS transistor and the p-type MOS transistor.

  By the way, in the ternary logic function circuit, the anonymity of the rising switching time and the falling switching time can be removed in this way, but the rising switching time and the falling switching time are equal. Even in this case, a difference in delay time may occur due to a change in the input pattern.

  However, in the ternary logic function circuit, it can be guaranteed that the delay times are equal for an arbitrary input pattern. The reason will be described below.

  First, the ternary logic function circuit having the configuration shown in FIG. 32 will be described.

In this ternary logic function circuit, a univariate ternary logic function circuit C1 for driving the control terminal C-T1 of the transfer gate T1 and a univariate ternary logic function for driving the control terminal DT3 of the transfer gate T3. The circuit D3 is inverting circuits f ₁₉ and f ₂₅ , respectively. Each of these inverting circuits f ₁₉ and f ₂₅ can be realized by a single-stage transistor circuit, as shown in FIGS. Therefore, the delay time is shorter than that of a non-inverting circuit that requires a two-stage transistor circuit or its complementary symmetric circuit.

However, the control terminal C-T2, D-T2 several three-valued transformed drives the logic function circuit C2, D2 of the transfer gate T2 is or noninverting circuit _{f 21,} and its complementary symmetry circuits _{f 07,} the 2-stage Since it is constituted by a transistor, the delay time becomes longer than that of the inverting circuit. Further, the univariate ternary logic function circuits D1 (= f ₀₉ ) and C3 (= f ₀₃ ) for driving the transfer gates T1 and T3 are constituted by a two-stage inverting circuit, that is, a two-stage transistor circuit. The

  Eventually, the timing at which the three transfer gates T1, T2, T3 are turned on or off is determined by a control signal having a large delay time. Therefore, in the ternary logic function circuit, the delay time of the signal passing through these transfer gates T1, T2, T3 is determined from a circuit constituted by two stages of transistors regardless of the input pattern, and becomes constant.

  Next, the ternary logic function circuit having the simplified configuration shown in FIG. 33 will be described.

FIG three-valued logic function circuit shown in 33, instead of the variable three-valued logic function circuit D1 in the three-valued logic function circuit shown in FIG. 32, the inverting circuit f ₂₅ to one-variable three-valued logic function circuit C1 with the series connection, instead of the one-variable three-valued logic function circuit C3, since it is intended to inverter circuits f ₂₅ to one-variable three-valued logic function circuit D3 connected in series, one-variable three-valued logic function From the circuits D1 and C3, the configuration of the univariate ternary logic function circuits C1 and D3, which are common parts, is summarized.

  The operation timing in such a ternary logic function circuit is exactly the same as that of the ternary logic function circuit shown in FIG. 32, and the delay time of the signal passing through the three transfer gates T1, T2, T3 depends on the input pattern. Regardless, it is determined from a circuit constituted by two stages of transistors and is constant.

Note that in the three-valued logic function circuit having the configuration further simplified as shown in FIG. 34, the transfer one of the control terminals T-C2 gate T2 is inverted circuit f ₂₁ is a one-variable three-valued logic function circuit D2 Inverter circuit f ₂₅ is driven by a signal that has passed through a circuit connected in series. This configuration is a three-stage transistor configuration, and the signal passing through the transfer gate T2 becomes slower than the signals passing through the other transfer gates T1 and T3, and it cannot be guaranteed that the delay time is constant.

  However, as described above, this configuration can reduce the number of required transistors by four from 12 to 8, compared with the configuration shown in FIG. 33, and when the purpose of downsizing is emphasized. It is valid.

  As described above, the ternary logic function circuit shown as an embodiment of the present invention includes three transfer gates T1, T2, and T3 and a plurality of single variables that conduct or block these transfer gates T1, T2, and T3. It is configured using a ternary logic function circuit. The operation of such a ternary logic function circuit will be described below using the configuration shown in FIG.

  First, in the ternary logic function circuit, when the input a is -1, the univariate ternary logic function circuit D1 outputs 1 by the univariate ternary logic function circuit C1 and inverts the output. To get output -1. In this ternary logic function circuit, -1 is output by the univariate ternary logic function circuits C2 and D3, and -1 is output by the univariate ternary logic function circuits D2 and C3 'that invert the output. Get. The output of the univariate ternary logic function circuit C1 and the output of the univariate ternary logic function circuit D1 ′ make the transfer gate T1 conductive, while the outputs of the univariate ternary logic function circuits C2 and D3. And the outputs of the univariate ternary logic function circuits D2 and C3 ′ turn off the transfer gates T2 and T3, and the univariate ternary logic function circuit B1 = (p, q, r) connected to the input b. Select the output.

  Therefore, the output Y of this ternary logic function circuit becomes p, q, r according to the values -1, 0, 1 of the input b.

  Further, in the ternary logic function circuit, when the input a is 0, the univariate ternary logic circuit outputs 1 by the univariate ternary logic function circuit C2 and obtains an output complementary to the signal. The function circuit D2 outputs -1. The outputs of the univariate ternary logic function circuit C2 and the univariate ternary logic function circuit D2 make the transfer gate T2 conductive, and the univariate ternary logic function circuit B2 = connected to the input b. Select the output of (s, t, u).

  Therefore, the output Y of this ternary logic function circuit becomes s, t, u according to the values -1, 0, 1 of the input b.

  Further, in the ternary logic function circuit, when the input a is 1, the univariate ternary logic function circuit C3 outputs -1 by the univariate ternary logic function circuit D3 and inverts the signal. 1 is output by '. The outputs of the univariate ternary logic function circuit D3 and the univariate ternary logic function circuit C3 ′ make the transfer gate T3 conductive, and the univariate ternary logic function circuit B3 connected to the input b. = Select the output of (x, y, z).

  Therefore, the output Y of this ternary logic function circuit becomes x, y, z according to the values -1, 0, 1 of the input b.

  As a result, it was shown that in the ternary logic function circuit, all the two-variable ternary logic functions shown in Table 1 above can be realized.

Thus, in the ternary logic function circuit, it is not necessary to individually implement all the three variable ternary logic function circuits existing in 3 ^{3 ^ 2} = 19683, and the three transfer gates T1, T2, T3, , Four kinds of univariate ternary logic function circuits f ₁₉ , f ₂₅ , f ₀₇ , f ₂₁ connected to the control terminal and three arbitrary univariate ternary logic functions B 1, B 2, B 3. Can be configured.

Here, as shown in Table 8 above, the arbitrary one-variable ternary logic function circuit includes seven types of inverting circuits f ₁₀ , f ₁₃ , f ₁₉ , f ₂₂ , f ₂₃ , f out of 27 types. ₂₅ , f ₂₆ , five types of non-inverting circuits f ₁₁ , f ₁₂ , f ₂₀ , f ₂₁ , f ₂₄ , and their complementary symmetric circuits f ₀₄ , f ₀₇ , f ₀₈ , f ₁₆ , f ₁₇ in total 17 types Only need to be realized.

The functions f ₀₂ , f ₀₃ , f ₀₅ , f ₀₉ , f ₁₅ , and f ₁₈ are respectively a series connection of the functions f ₂₆ and f _13, a series connection of the functions f ₂₅ and f ₁₉ , and a function f ₂₃ and f _13. Can be realized by serial connection of functions f ₁₉ and f ₂₅ , series connection of functions f ₁₃ and f ₂₃ , and series connection of functions f ₁₀ and f ₂₃ .

Of the 27 types of univariate ternary logic function circuits, the function f ₀₁ is identically −1, the function f ₁₄ is identically 0, and the function f ₂₇ is identical. Therefore, the function f ₀₆ does not need to be realized for these four types because the input is the output as it is.

  As described above, in the ternary logic function circuit, all the two-variable ternary logic functions are systematically constituted by the three transfer gates T1, T2, T3 and the 17 kinds of univariate ternary logic function circuits. Can be realized.

  In these 17 types of one-variable three-value logic function circuits, all the transistors are turned off and no current flows except during the switching operation. It can be made extremely small.

  Assuming realization with 0.1 μm CMOS technology, the logical value 1 corresponds to 0.3 volts, the logical value 0 corresponds to 0 volts, and the logical value −1 corresponds to −0.3 volts. When the channel dope amount of the enhancement type and depletion type MOS transistors in this case is obtained, it is as shown in Table 22 below.

  As described above, each of the above-described MOS transistors can be actually realized, and a ternary logic function circuit can be sufficiently realized.

  Also, in the ternary logic function circuit, all ternary logic elements can be configured using only a univariate ternary logic function circuit and a transfer gate, so that the asymmetry of the rising and falling switching times. Can be significantly reduced.

  Actually, the effect of removing the asymmetry of the switching time is shown by the symmetric ternary addition circuit (without carry) shown in the following Table 23.

First, FIG. 43 shows, as a comparison object, an adder circuit configured using the invention described in JP-T-2002-517937. That is, this adder circuit connects three circuits P, Q, and R, to which source logic values −1, 0, and 1 are input, in series, and inputs a, b, inputs a, An output obtained by inverting b by a function f ₁₉ = (1, −1, −1) and an output obtained by inverting an input a and b by a function f ₂₅ = (1,1, −1) are provided. The output a + b is obtained by wired-ORing the outputs of Q and R.

  In this addition circuit, as shown in FIG. 44, the circuit P includes a circuit in which two enhancement type n-type MOS transistors ne and one n-type MOS transistor NE are connected in series, and one enhancement type n-type. A circuit in which a MOS transistor NE and two n-type MOS transistors ne are connected in series and a circuit in which two enhancement-type n-type MOS transistors NE are connected in series are connected in parallel. Further, as shown in FIG. 45, the circuit Q includes a circuit in which an enhancement type p-type MOS transistor pe and an n-type MOS transistor ne are connected in series, an enhancement type p-type MOS transistor pe, and two n-type MOS transistors. A circuit in which a transistor ne and a p-type MOS transistor pe are connected in series and a circuit in which an enhancement type n-type MOS transistor ne and a p-type MOS transistor pe are connected in series are connected in parallel. Further, as shown in FIG. 46, the circuit R includes a circuit in which two enhancement type p-type MOS transistors pe and one p-type MOS transistor PE are connected in series, and one enhancement type p-type MOS transistor PE. And a circuit in which two p-type MOS transistors pe are connected in series and a circuit in which two enhancement type p-type MOS transistors PE are connected in series.

On the other hand, the adder circuit using the ternary logic function circuit shown as the embodiment of the present invention is configured as shown in FIG. 47 when configured using 32 transistors as in the adder circuit shown in FIG. That is, this adder circuit uses the function f ₁₉ = (1, -1, -1) as the univariate ternary logic function circuit C1 in the circuit shown in FIG. D1 'as a function _f 25 = (1,1, -1) using a one-variable three-valued logic function circuit C2' function _f 25 = (1,1, -1) as used, one-variable three-valued logic The function f ₂₁ = (1, −1,1) is used as the function circuit D2, and the function f ₁₉ = (1, −1, −1) is used as the one-variable ternary logic function circuit C3 ′. A function f ₂₅ = (1,1, −1) is used as the value logic function circuit D3, and a univariate ternary logic function circuit B1 = (1, −1,0) is provided, and a univariate ternary value is provided. The logic function circuit B3 = (0, 1, −1) is provided, and the one variable ternary logic function circuit B2 is not provided.

  For these two adder circuits, the output waveforms when the inputs a and b having the pattern as shown in FIG. As a result, the output waveform of the adder circuit shown in FIG. 43 is as shown in FIG. 49, and the output waveform of the adder circuit shown in FIG. 47 is as shown in FIG. In the waveform shown in FIG. 48, the solid line indicates the input a composed of the patterns 1,1, -1, -1,0,0, and the broken line indicates 1, -1,1,0, -1,0,1. The input b which consists of these patterns is shown.

  As is apparent from this result, the conventional adder circuit has a ternary value shown as an embodiment of the present invention, while the rising and falling edges are both largely asymmetric as shown in FIG. As shown in FIG. 50, it can be understood that the switching time of the adder circuit using the logic function circuit is substantially symmetric at both the rising and falling edges.

  Thus, in the ternary logic function circuit shown as the embodiment of the present invention, the asymmetry of the rising and falling switching times can be remarkably reduced.

  The present invention is not limited to the embodiment described above. For example, in the above-described embodiment, it has been described that the two-variable ternary logic operation is performed. However, the present invention can be easily applied to the case where the two-variable multi-value logic operation is performed.

  As an example, a quinary logic function circuit that realizes the two-variable quinary logic function shown in the following table 24 will be described with reference to FIG.

  As shown in FIG. 51, this quinary logic function circuit includes five transfer gates T1, T2, T3, T4, and T5 each composed of a p-type MOS transistor and an n-type MOS transistor. That is, in this quinary logic function circuit, the value output from the output terminal Y is determined by conducting or blocking the five transfer gates T1, T2, T3, T4, and T5 that are turned on or off according to the input. The Specifically, the quinary logic function circuit selects the output for the input a = −2 by the transfer gate T1, selects the output for the input a = −1 by the transfer gate T2, and inputs a = 0 by the transfer gate T3. The output for the input a = 1 is selected by the transfer gate T4, and the output for the input a = 2 is selected by the transfer gate T5.

  The two control terminals C-T1 and DT1 of the transfer gate T1 have outputs (2, -2, -2,-, with respect to the input a = (-2, -1, 0, 1, 2), respectively. 2, -2) is connected to a univariate quinary logic function circuit C1 complementary to the univariate quinary logic function circuit D1. The two control terminals C-T2 and DT2 of the transfer gate T2 have outputs (−2, 2, −2) with respect to the input a = (− 2, −1, 0, 1, 2), respectively. , -2, -2) is connected to a univariate quinary logic function circuit C2 which is complementary to and symmetrical to the univariate quinary logic function circuit D2. Furthermore, the two control terminals C-T3 and D-T3 of the transfer gate T3 have outputs (−2, −2, 2) with respect to the input a = (− 2, −1, 0, 1, 2), respectively. , -2, -2) are connected to a univariate quinary logic function circuit C3 complementary to this and a univariate quinary logic function circuit D3 that is complementary and symmetric. Furthermore, the two control terminals C-T4 and D-T4 of the transfer gate T4 have outputs (-2, -2, -2) with respect to the input a = (-2, -1, 0, 1, 2), respectively. A univariate quinary logic function circuit C4 that obtains -2, 2, -2) and a complementary symmetric univariate quinary logic function circuit D4 are connected. The two control terminals C-T5 and D-T5 of the transfer gate T5 have outputs (−2, −2, −−) with respect to the input a = (− 2, −1, 0, 1, 2), respectively. 2, -2, 2) is connected to a univariate quinary logic function circuit C5 and a complementary symmetric univariate quinary logic function circuit D5.

  Further, the input terminals X-T1, X-T2, X-T3, X-T4, and X-T5 of the transfer gates T1, T2, T3, T4, and T5 are each changed to obtain an output with respect to the input b. Several quinary logic function circuits B1, B2, B3, B4, B5 are connected, and output terminals Y-T1, Y-T2, Y-T3, Y-T4 of these transfer gates T1, T2, T3, T4, T5. Y-T5 is wired or connected as an output terminal Y of the quinary logic function circuit.

  Here, the univariate quinary logic function circuits B1, B2, B3, B4, and B5 are respectively (p1, q1, r1) for the input b = (− 2, −1, 0, 1, 2). , S1, t1), (p2, q2, r2, s2, t2), (p3, q3, r3, s3, t3), (p4, q4, r4, s4, t4), (p5, q5, r5, s5) , T5). However, pi, qi, ri, si, and ti (1 ≦ i ≦ 5) take values of −2, −1, 0, 1 and 2, respectively.

  In this way, the quinary logic function circuit includes five transfer gates T1, T2, T3, T4, and T5 that are turned on or off according to the input, and the conduction or cutoff of these transfer gates T1, T2, T3, T4, and T5. Realizing a two-variable quinary logic function by using ten univariate quinary logic function circuits C1, D1, C2, D2, C3, D3, C4, D4, C5 and D5 Can do.

  Of course, the configuration method of such a multi-value logic function circuit can be easily extended to a general two-variable N-value logic function.

  First, the case where N is an odd number will be described. Here, m = (N−1) / 2. This multi-valued logic function circuit includes N transfer gates T1, T2, T3,... TN composed of p-type MOS transistors and n-type MOS transistors. Control terminals C-T1, D-T1, C-T2, D-T2, C-T3, D-T3,..., C-TN, D of the transfer gates T1, T2, T3,. −TN includes i ≦ N with respect to input a = (− m, −m + 1,..., −1, 0, 1,..., M−1, m), respectively. , A one-variable N-value logic function circuit Ci that outputs m only for the i-th logic value and outputs -m for other logic values, and a one-variable N-value logic function circuit that is complementary and symmetric to this Di is connected.

  Further, the input terminals X-T1, X-T2, X-T3,..., X-TN of the transfer gates T1, T2, T3,. BN is connected to one variable N-value logic function circuits B1, B2, B3,..., BN, and output terminals Y-T1, Y-T2, Y-T3 of these transfer gates T1, T2, T3,. ,..., Y-TN are wired or connected as output terminals Y of the multi-valued logic function circuit.

  On the other hand, if N is an even number, m = N / 2. In this multi-valued logic function circuit, N transfer gates T1, T2, T3,..., TN control terminals C-T1, D-T1, C-T2, DT2, C-T3, As a single variable N-value logic function circuit Ci connected to each of D-T3,..., C-TN, D-TN, inputs a = (− m, −m + 1,..., −1, 0, 1,..., M−1, m), for 1 ≦ i ≦ N, output m only for the i-th logic value, and −m for other logic values. What is necessary is just to use what is output, and to use a one-variable N-value logic function circuit Di that is complementary and symmetric to this.

  As described above, the present invention includes N transfer gates T1, T2, T3,..., TN that are turned on or off according to the input, and conduction of these transfer gates T1, T2, T3,. Or any two-variable N-value logic function is realized by using 2N one-variable N-value logic function circuits C1, D1, C2, D2, C3, D3,. can do.

  In the above-described embodiment, the example applied to the adder circuit has been described. However, the present invention can be applied to other circuits as well, and hardware for performing so-called public key encryption. It is suitable to be applied to wear and large scale multipliers.

  Thus, it goes without saying that the present invention can be modified as appropriate without departing from the spirit of the present invention.

It is a figure explaining the structure of the ternary logic function circuit shown as embodiment of this invention. It is a figure explaining the structure of the transfer gate in the ternary logic function circuit. It is a figure explaining the structure of the switch in the case of the source logical value 1. It is a figure explaining the structure of the switch in case the source logical value is 0. It is a figure explaining the structure of the switch in case it is source logical value -1. It is a figure explaining the structure of the enhancement type n-type MOS transistor whose threshold voltage which becomes an ON state when it is the source | sauce logic value -1 is 1.5 volts. It is a figure explaining the structure of the enhancement type n-type MOS transistor whose threshold voltage which becomes an ON state when it is the source | sauce logic value -1 is 0.5 volts. It is a figure explaining the structure of the enhancement type p-type MOS transistor whose threshold voltage which turns into an ON state when it is the source | sauce logic value 1 is -1.5 volts. It is a figure explaining the structure of the enhancement type p-type MOS transistor whose threshold voltage which will be in an ON state when it is the source | sauce logic value 1 is -0.5 volts. It is a figure explaining the structure of the enhancement type n-type MOS transistor whose threshold voltage which will be in an ON state when the source logic value is 0 is 0.5 volts. It is a figure explaining the structure of the enhancement type p-type MOS transistor whose threshold voltage which will be in an ON state when it is the source | sauce logic value 0 is -0.5 volts. It is a figure explaining the structure of a depletion-type n-type MOS transistor or p-type MOS transistor whose threshold voltage which turns on when the source logic value is 0 is −0.5 volts or 0.5 volts. It is a figure explaining the structure which outputs the output 0 only when it is the input 0. It is a figure explaining the structure which outputs the output 0 in any case of input -1,1. It is a diagram illustrating a circuit configuration for realizing the function f _10. It is a diagram illustrating a circuit configuration for realizing the function f _13. It is a diagram illustrating a circuit configuration for realizing the function f _19. It is a diagram illustrating a circuit configuration for realizing the function f _22. It is a diagram illustrating a circuit configuration for realizing the function f _23. It is a diagram illustrating a circuit configuration for realizing the function f _25. It is a diagram illustrating a circuit configuration for realizing the function f _26. It is a diagram illustrating a circuit configuration for realizing the function f _11. It is a diagram illustrating a circuit configuration for realizing the function f _12. It is a diagram illustrating a circuit configuration for realizing the function f _20. It is a diagram illustrating a circuit configuration for realizing the function f _21. It is a diagram illustrating a circuit configuration for realizing the function f _24. It is a diagram illustrating a circuit configuration for realizing the function f _17. It is a diagram illustrating a circuit configuration for realizing the function f _16. It is a diagram illustrating a circuit configuration for realizing the function f _08. It is a diagram illustrating a circuit configuration for realizing the function f _07. It is a diagram illustrating a circuit configuration for realizing the function f _04. It is a diagram illustrating a circuit configuration for realizing the function f _02. It is a diagram illustrating a circuit configuration for realizing the function f _03. It is a diagram illustrating a circuit configuration for realizing the function f _05. It is a diagram illustrating a circuit configuration for realizing the function f _09. It is a diagram illustrating a circuit configuration for realizing the function f _15. It is a diagram illustrating a circuit configuration for realizing the function f _18. It is a figure explaining the specific structure of the ternary logic function circuit shown in FIG. FIG. 33 is a diagram illustrating a specific configuration of a ternary logic function circuit in which the configuration illustrated in FIG. 32 is simplified. It is a figure explaining the specific structure of the ternary logic function circuit which simplified the structure shown in FIG. It is a figure explaining the specific structure of the ternary logic function circuit which performs the degenerate two-variable ternary logic operation which is (p, q, r) = (s, t, u). It is a figure explaining the specific structure of the ternary logic function circuit which performs the degenerate 2 variable ternary logic operation which is (s, t, u) = (x, y, z). It is a figure explaining the specific structure of the ternary logic function circuit which performs the degenerate two-variable ternary logic operation which is (x, y, z) = (p, q, r). It is a figure explaining the generalized structure of the degenerated ternary logic function circuit. FIG. 39 is a diagram illustrating a configuration of a ternary logic function circuit in which the configuration illustrated in FIG. 38 is simplified. FIG. 40 is a diagram illustrating a configuration of a ternary logic function circuit in which the configuration illustrated in FIG. 38 is simplified, and illustrates a configuration different from the configuration illustrated in FIG. 39. It is a figure explaining the structure of a non-inverting circuit. It is a figure explaining the structure of a non-inverting circuit, Comprising: It is a figure explaining the structure different from the structure shown in FIG. It is a figure explaining the structure of the addition circuit comprised using the conventional ternary logic function circuit. FIG. 44 is a diagram illustrating a configuration of a circuit P illustrated in FIG. 43. FIG. 44 is a diagram illustrating a configuration of a circuit Q illustrated in FIG. 43. FIG. 44 is a diagram illustrating a configuration of a circuit R illustrated in FIG. 43. It is a figure explaining the structure of the addition circuit comprised using the ternary logic function circuit shown in FIG. It is a figure explaining the waveform of the inputs a and b experimentally given with respect to the addition circuit shown in FIG.43 and FIG.47. FIG. 49 is a diagram illustrating an output waveform when the input shown in FIG. 48 is given to the adder circuit shown in FIG. 43. FIG. 49 is a diagram illustrating an output waveform when the input shown in FIG. 48 is given to the adder circuit shown in FIG. 47. It is a figure explaining the structure of the quinary logic function circuit shown as embodiment of this invention. It is a figure explaining the structure of the conventional ternary logic function circuit.

Explanation of symbols

B1, B2, B3, C1, C2, C3, D1, D2, D3 One-variable ternary logic function circuit C-T1, C-T2, C-T3, D-T1, DT2, DT3 control terminal T1, T2, T3 Transfer gates X-T1, X-T2, X-T3 Input terminals Y, Y-T1, Y-T2, Y-T3 Output terminals nd, ne, ne0, NE n-type MOS transistors pd, pe, pe0, PE p-type MOS transistor

Claims (10)

A ternary logic function circuit that performs a two-variable ternary logic operation,
A first transfer gate that is rendered conductive in accordance with the first logic value of the three logic values constituting the first input;
A second transfer gate that is rendered conductive in accordance with a second logic value of the three logic values constituting the first input;
A third transfer gate that is rendered conductive in accordance with a third logic value of the three logic values constituting the first input;
A first one-variable ternary logic function circuit connected to one control terminal of the first transfer gate and obtaining a first output with respect to the first input;
A second one-variable ternary logic function circuit connected to the other control terminal of the first transfer gate and obtaining a second output complementary to the first output with respect to the first input; ,
A third one-variable ternary logic function circuit connected to one control terminal of the second transfer gate and obtaining a third output with respect to the first input;
A fourth one-variable ternary logic function circuit connected to the other control terminal of the second transfer gate and obtaining a fourth output complementary to the third output with respect to the first input; ,
A fifth one-variable ternary logic function circuit connected to one control terminal of the third transfer gate and obtaining a fifth output with respect to the first input;
A sixth one-variable ternary logic function circuit connected to the other control terminal of the third transfer gate and obtaining a sixth output complementary to the fifth output with respect to the first input; ,
A seventh one-variable ternary logic function connected to the input terminal of the first transfer gate and obtaining a seventh output according to the first logic value among the three logic values constituting the second input Circuit,
An eighth variable ternary logic connected to the input terminal of the second transfer gate and obtaining an eighth output in accordance with a second logic value among the three logic values constituting the second input A functional circuit;
A ninth one-variable ternary logic circuit connected to the input terminal of the third transfer gate and obtaining a ninth output in accordance with a third logic value among the three logic values constituting the second input. A functional circuit,
Each of the output terminals of the first to third transfer gates is wired OR connected. The first transfer gate is in a conductive state according to a logical value -1 out of three logical values -1, 0, 1 constituting the first input,
The second transfer gate is in a conductive state according to a logical value 0 among three logical values −1, 0, 1 constituting the first input,
The third transfer gate is in a conductive state in accordance with a logical value 1 out of three logical values −1, 0, 1 constituting the first input,
The first one-variable ternary logic function circuit obtains an output (1, -1, -1) with respect to the first input (-1, 0, 1).
The second one-variable ternary logic function circuit obtains an output (-1, 1, 1) with respect to the first input (-1, 0, 1).
The third one-variable ternary logic function circuit obtains an output (-1, 1, -1) with respect to the first input (-1, 0, 1).
The fourth one-variable ternary logic function circuit obtains an output (1, -1, 1) with respect to the first input (-1, 0, 1).
The fifth one-variable ternary logic function circuit obtains an output (-1, -1, 1) with respect to the first input (-1, 0, 1);
The sixth univariate ternary logic function circuit obtains an output (1, 1, -1) with respect to the first input (-1, 0, 1). Item 3. A ternary logic function circuit according to item 1. Instead of the second univariate ternary logic function circuit, an inverter connected to the other control terminal of the first transfer gate and inverting the output of the first univariate ternary logic function circuit. The ternary logic function circuit according to claim 1, further comprising: Instead of the fifth univariate ternary logic function circuit, an inverter connected to one control terminal of the third transfer gate and inverting the output of the sixth univariate ternary logic function circuit. The ternary logic function circuit according to claim 1, wherein the ternary logic function circuit is provided. Instead of the third univariate ternary logic function circuit, an inverter connected to one control terminal of the second transfer gate and inverting the output of the fourth univariate ternary logic function circuit. The ternary logic function circuit according to claim 1, 3, or 4. The seventh to ninth univariate ternary logic function circuits are first inverting circuits that obtain outputs (0, -1, -1) with respect to the second inputs (-1, 0, 1). , A second inverting circuit for obtaining an output (0, 0, −1) with respect to the second input (−1, 0, 1), and with respect to the second input (−1, 0, 1). A third inverting circuit for obtaining an output (1, -1, -1) and a fourth inverting circuit for obtaining an output (1, 0, -1) with respect to the second input (-1, 0, 1) A fifth inverting circuit for obtaining an output (1, 0, 0) with respect to the second input (-1, 0, 1), and an output with respect to the second input (-1, 0, 1). A sixth inverting circuit for obtaining (1, 1, -1), a seventh inverting circuit for obtaining an output (1, 1, 0) with respect to the second input (-1, 0, 1), Output (0, -1, 0) for 2 inputs (-1, 0, 1) A first non-inverting circuit, a second non-inverting circuit for obtaining an output (0, -1, 1) with respect to the second input (-1, 0, 1), and the second input (-1, A third non-inverting circuit that obtains an output (1, -1,0) with respect to 0,1), and an output (1, -1,1) with respect to the second input (-1, 0,1) A fourth non-inverting circuit for obtaining a first non-inverting circuit, a fifth non-inverting circuit for obtaining an output (1, 0, 1) with respect to the second input (-1, 0, 1), A first complementary symmetric circuit for obtaining an output complementary to the output; a second complementary symmetric circuit for obtaining an output complementary to the output of the second non-inverting circuit; and a complementary symmetric to the output of the third non-inverting circuit. A third complementary symmetric circuit that obtains a complementary output, a fourth complementary symmetric circuit that obtains an output that is complementary to the output of the fourth non-inverting circuit, and an output that is complementary to the output of the fifth non-inverting circuit. That of the fifth complementary symmetry circuit, three-valued logic function circuit according to any one of claims 2 to 5, characterized in that either. A ternary logic function circuit that performs a two-variable ternary logic operation,
A first transfer gate that is rendered conductive in accordance with either the first logic value or the second logic value of the three logic values constituting the first input;
A second transfer gate that is rendered conductive in accordance with a third logic value of the three logic values constituting the first input;
A first variable ternary logic connected to one control terminal of the first transfer gate and the other control terminal of the second transfer gate to obtain a first output with respect to the first input A third one-variable ternary logic function circuit obtained by ORing a function circuit and a second one-variable ternary logic function circuit that obtains a second output with respect to the first input;
Connected to the other control terminal of the first transfer gate and one control terminal of the second transfer gate to obtain a third output complementary to the first output with respect to the first input. Logical product of a fourth univariate ternary logic function circuit and a fifth univariate ternary logic function circuit that obtains a fourth output complementary to the second output with respect to the first input. A sixth one-variable ternary logic function circuit taking
A seventh one-variable ternary logic function connected to the input terminal of the first transfer gate and obtaining a fifth output in accordance with the first logic value among the three logic values constituting the second input A ninth variable integrating a circuit and an eighth one-variable ternary logic function circuit for obtaining a sixth output in accordance with the second logic value among the three logic values constituting the second input; A number ternary logic function circuit;
A tenth one-variable ternary logic circuit connected to the input terminal of the second transfer gate and obtaining a seventh output in accordance with a third logic value among the three logic values constituting the second input. A functional circuit,
Each of the output terminals of the first and second transfer gates is wired OR connected. Instead of the sixth one-variable ternary logic function circuit, the third one-variable is connected to the other control terminal of the first transfer gate and one control terminal of the second transfer gate. The ternary logic function circuit according to claim 7, further comprising an inverter that inverts the output of the ternary logic function circuit. Instead of the third one-variable ternary logic function circuit, the sixth one-variable is connected to one control terminal of the first transfer gate and the other control terminal of the second transfer gate. The ternary logic function circuit according to claim 7, further comprising an inverter that inverts the output of the ternary logic function circuit. A multi-value logic function circuit that performs a two-variable multi-value logic operation,
N transfer gates that are rendered conductive in response to any of the N logic values comprising the first input;
When N is an odd number, m = (N−1) / 2, while when N is an even number, m = N / 2, and one control terminal in each of the N transfer gates. And for the first input (−m, −m + 1,..., −1, 0, 1,..., M−1, m), for 1 ≦ i ≦ N, a first circuit group consisting of N univariate N-value logic function circuits that outputs m only for the i-th logic value and outputs -m for other logic values;
The first input (−m, −m + 1,..., −1, 0, 1,..., M−1, m) is connected to the other control terminal of each of the N transfer gates. On the other hand, a second circuit comprising N univariate N-value logic function circuits that obtain complementary outputs symmetrically to the outputs of the N univariate N-value logic function circuits constituting the first circuit group. Group,
A third circuit comprising N univariate ternary logic function circuits connected to respective input terminals of the N transfer gates and obtaining an output in accordance with each of the N logical values constituting the second input. And a circuit group of
The output terminal of each of the N transfer gates is wired-OR connected.