JP3721373B2

JP3721373B2 - Multi-valued logic circuit

Info

Publication number: JP3721373B2
Application number: JP2003393650A
Authority: JP
Inventors: 勇治大住; 樋口　　拓也; 裕明藤田; 真也都鳥
Original assignee: Dai Nippon Printing Co Ltd; Tokai University Educational Systems
Current assignee: Dai Nippon Printing Co Ltd; Tokai University Educational Systems
Priority date: 2003-11-25
Filing date: 2003-11-25
Publication date: 2005-11-30
Anticipated expiration: 2023-11-25
Also published as: JP2005159612A

Description

本発明は、多値論理回路に関し、特に、ＦＥＴにより構成した多値論理回路に関する。 The present invention relates to a multi-value logic circuit, and more particularly to a multi-value logic circuit constituted by FETs.

従来の論理回路の殆どは２値の論理信号を扱ってきた。これは主に、安定かつ高速のオン・オフ動作に基づく２値論理素子の実現が比較的容易であったためである。
しかし、システムの大規模化に伴い、２値論理回路について、入出力ピン数の制限、内部配線数の増加等が問題となっている。
これらの問題点を解決するために１線当りの情報伝達量を増大させようとする多値論理システムが注目されている。
特別なプロセスを必要とせずに、汎用のＦＥＴを利用した多値論理回路の一つとしては、非特許文献１に見られるような回路（図１）が提案されている。 Most conventional logic circuits have dealt with binary logic signals. This is mainly because it is relatively easy to realize a binary logic element based on a stable and high-speed on / off operation.
However, with an increase in the scale of the system, there are problems with the binary logic circuit, such as a limitation on the number of input / output pins and an increase in the number of internal wires.
In order to solve these problems, a multi-valued logic system that attempts to increase the amount of information transmitted per line has attracted attention.
As one of multi-value logic circuits using general-purpose FETs without requiring a special process, a circuit (see FIG. 1) as shown in Non-Patent Document 1 has been proposed.

中島、都鳥、藤田、「符号付き３値全加算器の構成」、電気関係学会北海道支部連合大会、平成１３年１０月Nakajima, Totori, Fujita, “Structure of signed ternary full adder”, Hokkaido Association of Electrical Engineering Association, October 2001

しかしながら、非特許文献１に開示された回路では、３値多入力論理回路の１以上の入力端子を制御端子として扱うことによって、当該回路をハードウェア的には全く変更せずに、制御端子からの信号に従って、種々の異なった論理動作を実行する論理回路を実現することは、開示ないし示唆されていない。 However, in the circuit disclosed in Non-Patent Document 1, by handling one or more input terminals of a ternary multi-input logic circuit as a control terminal, the circuit is not changed at all in hardware, and the control terminal is connected. It is not disclosed or suggested to implement a logic circuit that performs various different logic operations in accordance with these signals.

また、抵抗を用いているために集積化が困難であるとともに、動作速度にも難点があった。
また、０（Ｖ）入力時の消費電流が大きい上、０（Ｖ）に対する入力レンジが狭いという問題点があった。 Further, since resistors are used, integration is difficult and operation speed is also difficult.
In addition, the current consumption at the time of 0 (V) input is large, and the input range for 0 (V) is narrow.

本発明の目的は、３値多入力論理回路の１以上の入力端子を制御端子として扱うことによって、当該回路をハードウェア的には全く変更せずに、制御端子からの信号に従って、種々の異なった論理動作を実行する論理回路を実現することである。
本発明の他の目的は、更に、ＦＥＴ構造を利用して、集積度が大きく、動作速度が速い、ＦＥＴ多値論理回路を提供することである。
本発明の更に他の目的は、０（Ｖ）入力時の消費電流が小さく、０（Ｖ）に対する入力レンジが広いＦＥＴ多値論理回路を提供することである。 The object of the present invention is to treat one or more input terminals of a ternary multi-input logic circuit as a control terminal, so that the circuit does not change at all in hardware, and varies according to the signal from the control terminal. It is to realize a logic circuit that executes the logical operation.
Another object of the present invention is to provide an FET multi-valued logic circuit that uses a FET structure and has a high degree of integration and a high operating speed.
Still another object of the present invention is to provide an FET multi-level logic circuit that consumes less current at 0 (V) input and has a wide input range for 0 (V).

前記の本発明の目的は、以下の各構成によって達成される。つまり、好ましい態様としては、
ゲート電極が第ｊ（０＜ｊ，ｊは整数）の入力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第１の出力端子に接続された第ｊのＰ型ＦＥＴと、ゲート電極が第ｊの入力端子に接続され、ドレイン電極が第１の出力端子に接続され、ソース電極が負極性の電源端子に接続された第ｊのＮ型ＦＥＴ、を有し、第ｊのＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第ｊのＮ型ＦＥＴの導通状態のチャンネル抵抗値が実質的に等しい、単位回路をｊ＝１からｍまでのｍ個（０＜ｍ，ｍは整数）備えた、多値論理回路（発明１）、が挙げられる。
この回路によれば、簡単な回路構成と最少のＦＥＴの数によって３値多入力論理回路が構成できる。さらに、３値多入力論理回路の１以上の入力端子を制御端子として扱うことによって、当該回路をハードウェア的には全く変更せずに、制御端子からの信号に従って、種々の異なった論理動作を実行する論理回路を実現することが可能である The object of the present invention is achieved by the following configurations. That is, as a preferable aspect,
A jth P-type having a gate electrode connected to a jth input terminal (0 <j, j is an integer), a source electrode connected to a positive power supply terminal, and a drain electrode connected to a first output terminal. A FET, a jth N-type FET having a gate electrode connected to the jth input terminal, a drain electrode connected to the first output terminal, and a source electrode connected to a negative power supply terminal; The number of unit circuits from j = 1 to m (0 <m) where the channel resistance value of the jth P-type FET in the conducting state and the channel resistance value of the jth N-type FET in the conducting state are substantially equal. , M is an integer), and a multi-value logic circuit (Invention 1).
According to this circuit, a ternary multi-input logic circuit can be configured with a simple circuit configuration and the minimum number of FETs. Further, by handling one or more input terminals of the ternary multi-input logic circuit as a control terminal, various different logic operations can be performed according to the signal from the control terminal without changing the circuit in hardware. It is possible to implement a logic circuit to execute

また、別の好ましい態様としては、ゲート電極が第ｊ（０＜ｊ，ｊは整数）の入力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（２ｊ−１）の節点に接続された第（２ｊ−１）のＰ型ＦＥＴと、ゲート電極が負極性の電源端子に接続され、ソース電極が第（２ｊ−１）の節点に接続され、ドレイン電極が第１の出力端子に接続された第２ｊのＰ型ＦＥＴと、
ゲート電極が正極性の電源端子に接続され、ドレイン電極が第１の出力端子に接続され、ソース電極が第２ｊの節点に接続された第（２ｊ−１）のＮ型ＦＥＴと、ゲート電極が第ｊの入力端子に接続され、ドレイン電極が第２ｊの節点に接続され、ソース電極が負極性の電源端子に接続された第２ｊのＮ型ＦＥＴ、を有し、第（２ｊ−１）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第２ｊのＮ型ＦＥＴの導通状態のチャンネル抵抗値とが実質的に等しく、第２ｊのＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｊ−１）のＮ型ＦＥＴの導通状態のチャンネル抵抗値と、が実質的に等しい、単位回路をｊ＝１からｍまでのｍ個（０＜ｍ，ｍは整数）備えた、多値論理回路（発明２）が挙げられる。
この回路によれば、能動負荷としている２つのＭＯＳトランジスタは抵抗によって置き換えることもでき、発明１の回路に比べ電流値を制限している（電流値を少なくしている。即ち、消費電力値を制限している）。また、出力電圧が０Ｖ近傍での入力レンジを発明１に比較し広く取ることができる。 In another preferred embodiment, the gate electrode is connected to the j-th (0 <j, j is an integer) input terminal, the source electrode is connected to the positive power supply terminal, and the drain electrode is (2j−1). ) Node (2j-1) connected to the node, the gate electrode is connected to the negative power supply terminal, the source electrode is connected to the (2j-1) node, and the drain electrode is A 2j P-type FET connected to the output terminal of 1;
A (2j-1) th N-type FET having a gate electrode connected to a positive power supply terminal, a drain electrode connected to the first output terminal, and a source electrode connected to the 2j node, and a gate electrode A second j-th n-type FET connected to the j-th input terminal, having a drain electrode connected to the second j-th node, and having a source electrode connected to the negative-polarity power supply terminal; The channel resistance value of the conductive state of the P-type FET and the channel resistance value of the conductive state of the 2j N-type FET are substantially equal, and the channel resistance value of the conductive state of the 2j P-type FET and the (2j -1) a multi-valued logic circuit comprising m unit circuits from j = 1 to m (0 <m, where m is an integer), which is substantially equal to the channel resistance value of the N-type FET in the conductive state. (Invention 2).
According to this circuit, the two MOS transistors serving as active loads can be replaced by resistors, and the current value is limited as compared with the circuit of the first aspect (the current value is reduced. That is, the power consumption value is reduced). Limit). Further, the input range in the vicinity of the output voltage of 0V can be widened as compared with the first aspect.

また、別の態様としては、ゲート電極が第ｊ（０＜ｊ，ｊは整数）の入力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（２ｊ−１）の節点に接続された第（２ｊ−１）のＰ型ＦＥＴと、ソース電極が第（２ｊ−１）の節点に接続され、ドレイン電極が第１の出力端子に接続された第２ｊのＰ型ＦＥＴと、ドレイン電極が第１の出力端子に接続され、ソース電極が第２ｊの節点に接続された第（２ｊ−１）のＮ型ＦＥＴと、ゲート電極が第ｊの入力端子に接続され、ドレイン電極が第２ｊの節点に接続され、ソース電極が負極性の電源端子に接続された第２ｊのＮ型ＦＥＴを有し、第（２ｊ−１）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第２ｊのＮ型ＦＥＴの導通状態のチャンネル抵抗値、が実質的に等しく、第２ｊのＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｊ−１）のＮ型ＦＥＴの導通状態のチャンネル抵抗値と、が実質的に等しい、単位回路をｊ＝１からｍまでのｍ個（０＜ｍ，ｍは整数）備え、第２ｊ（０＜ｊ＜ｍ＋１、の全てのｊについて）のＰ型ＦＥＴのゲートが第（２ｍ＋１）の節点に接続され、第（２ｊ−１）のＮ型ＦＥＴのゲートが第（２ｍ＋２）の節点に接続され、ゲート電極とドレイン電極が第（２ｍ＋１）の節点に接続され、ソース電極が正極性の電源端子に接続された、第（２ｍ＋１）のＰ型ＦＥＴと、ゲート電極及びドレイン電極が第（２ｍ＋２）の節点に接続され、ソース電極が負極性の電源端子に接続された、第（２ｍ＋１）のＮ型ＦＥＴと、を更に備え、第（２ｍ＋１）の節点から負極性の電源に向かって定電流源によって一定電流が流され、正極性の電源端子から第（２ｍ＋２）の節点に向かって定電流源によって一定電流が流され、第（２ｍ＋１）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｍ＋１）のＮ型ＦＥＴの導通状態のチャンネル抵抗値、が実質的に等しい、多値論理回路（発明３）が挙げられる。
この回路によれば、出力電圧が０Ｖとなるときの電流値を制限することが可能である。また、出力電圧が０Ｖ近傍での入力レンジを広く取ることができる。 As another aspect, the gate electrode is connected to the jth (0 <j, j is an integer) input terminal, the source electrode is connected to the positive power supply terminal, and the drain electrode is (2j-1) th. A (2j-1) th P-type FET connected to the first node, a second jth P-type having a source electrode connected to the (2j-1) th node and a drain electrode connected to the first output terminal An FET, a drain electrode connected to the first output terminal, a source electrode connected to the 2j node, a (2j-1) th N-type FET, a gate electrode connected to the jth input terminal, A channel resistance value of the conduction state of the (2j-1) th P-type FET having a second jth N-type FET having a drain electrode connected to the 2j-th node and a source electrode connected to a negative power supply terminal And the channel resistance value of the conductive state of the 2j N-type FET is substantially In the unit circuit, j = 1 to m, where the channel resistance value of the 2j P-type FET in the conducting state is substantially equal to the channel resistance value of the (2j−1) -th N-type FET in the conducting state. Up to m (0 <m, where m is an integer), the gate of the 2nd j (for all j of 0 <j <m + 1) is connected to the (2m + 1) th node, and the (2j -1) the gate of the N-type FET is connected to the (2m + 2) -th node, the gate electrode and drain electrode are connected to the (2m + 1) -th node, and the source electrode is connected to the positive power supply terminal. A (2m + 1) th P-type FET, and a (2m + 1) th N-type FET whose gate electrode and drain electrode are connected to the (2m + 2) th node and whose source electrode is connected to the negative power supply terminal. From the (2m + 1) -th node A constant current is passed by the constant current source toward the source, and a constant current is passed by the constant current source from the positive power supply terminal toward the (2m + 2) node, and the conduction state of the (2m + 1) th P-type FET And a multi-value logic circuit (invention 3) in which the channel resistance value of the (2m + 1) th N-type FET is substantially equal to the channel resistance value of the (2m + 1) th N-type FET.
According to this circuit, it is possible to limit the current value when the output voltage becomes 0V. Further, it is possible to widen the input range when the output voltage is around 0V.

更に別の実施態様としては、ゲート電極が第１の入力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第１の出力端子に接続されたＰ型ＦＥＴと、ゲート電極が第２の入力端子に接続され、ドレイン電極が第１の出力端子に接続され、ソース電極が負極性の電源端子に接続されたＮ型ＦＥＴ、を有し、Ｐ型ＦＥＴの導通状態でのチャンネル抵抗値と、Ｎ型ＦＥＴの導通状態でのチャンネル抵抗値、とが実質的に同一である、多値論理回路（発明４）がある。
この回路によれば、少ない数のＦＥＴによって３値多入力論理回路が構成できる。ただし、実現できる論理動作は制限される（先の発明１から３のように、３値多入力論理回路の１以上の入力端子を制御端子として扱うことによって、当該回路をハードウェア的には全く変更せずに、制御端子からの信号に従って、種々の異なった論理動作を実行する論理回路を実現することはできない）。
また、更なる態様には、ゲート電極が第ｊ（０＜ｊ，ｊは整数）の入力端子に接続され、ドレイン電極が第1の出力端子に接続され、ソース電極が負極性の電源端子に接続された第ｊのＮ型ＦＥＴを、ｊ＝１からｍまでのｍ個（０＜ｍ，ｍは整数）備え、更に、ゲート電極に接地電極が接続され、ソース電極に正極性の電源端子が接続され、ドレイン電極に第1の出力端子が接続されたＰ型ＦＥＴを備え、第ｊのＮ型ＦＥＴ（０＜ｊ＜ｍ）の導通状態のチャンネル抵抗値と、Ｐ型ＦＥＴの導通状態のチャンネル抵抗値、が実質的に同一である、多値論理回路（発明５）が含まれる。
この回路によれば、少ない数のＦＥＴによって、先の発明４で実現できる論理動作とは異なる３値多入力論理回路が構成できる。ただし、実現できる論理動作が制限される（先の発明１から３のように、３値多入力論理回路の１以上の入力端子を制御端子として扱うことによって、当該回路をハードウェア的には全く変更せずに、制御端子からの信号に従って、種々の異なった論理動作を実行する論理回路を実現することはできない）。 In still another embodiment, a P-type FET having a gate electrode connected to the first input terminal, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the first output terminal; An N-type FET having an electrode connected to the second input terminal, a drain electrode connected to the first output terminal, and a source electrode connected to a negative power supply terminal; There is a multi-value logic circuit (invention 4) in which the channel resistance value of the N-type FET and the channel resistance value in the conductive state of the N-type FET are substantially the same.
According to this circuit, a ternary multi-input logic circuit can be configured with a small number of FETs. However, the logic operation that can be realized is limited (as in the first to third aspects of the invention, by treating one or more input terminals of a ternary multi-input logic circuit as a control terminal, the circuit is completely implemented in hardware. Without modification, it is not possible to implement a logic circuit that performs various different logic operations according to the signal from the control terminal).
In a further aspect, the gate electrode is connected to the jth input terminal (0 <j, j is an integer), the drain electrode is connected to the first output terminal, and the source electrode is connected to the negative power supply terminal. Provided m j-th FETs from j = 1 to m (0 <m, where m is an integer), a ground electrode is connected to the gate electrode, and a positive power supply terminal is connected to the source electrode Is connected, and the drain electrode is connected to the first output terminal, and the channel resistance value of the j-th N-type FET (0 <j <m) and the conduction state of the P-type FET are included. The multi-value logic circuit (Invention 5) is included in which the channel resistance values of the two channels are substantially the same.
According to this circuit, a ternary multi-input logic circuit different from the logic operation that can be realized in the above invention 4 can be configured by a small number of FETs. However, the logic operation that can be realized is limited (as in the first to third aspects of the invention, by treating one or more input terminals of a ternary multi-input logic circuit as a control terminal, the circuit is completely implemented in hardware. Without modification, it is not possible to implement a logic circuit that performs various different logic operations according to the signal from the control terminal).

また別の好ましい態様としては、ゲート電極が第ｊ（０＜ｊ，ｊは整数）の入力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第1の出力端子に接続された第ｊのＰ型ＦＥＴを、ｊ＝１からｍまでのｍ個（０＜ｍ，ｍは整数）備え、更に、ゲート電極に接地電極が接続され、ドレイン電極に第1の出力端子が接続され、ソース電極に負極性の電源端子が接続されたＮ型ＦＥＴを備え、第ｊのＰ型ＦＥＴ（０＜ｊ＜ｍ、ｍは整数）の導通状態のチャンネル抵抗値と、Ｎ型ＦＥＴの導通状態のチャンネル抵抗値、が実質的に同一である、多値論理回路（発明６）がある。
この回路によれば、少ない数のＦＥＴによって、先の発明４、５で実現できる論理動作とは異なる、３値多入力論理回路が構成できる。ただし、実現できる論理動作は制限される（先の発明１から３のように、３値多入力論理回路の１以上の入力端子を制御端子として扱うことによって、当該回路をハードウェア的には全く変更せずに、制御端子からの信号に従って、種々の異なった論理動作を実行する論理回路を実現することはできない）。 In another preferred embodiment, the gate electrode is connected to the jth input terminal (0 <j, j is an integer), the source electrode is connected to the positive power supply terminal, and the drain electrode is connected to the first output terminal. The number of connected jth P-type FETs is m from j = 1 to m (0 <m, where m is an integer), the ground electrode is connected to the gate electrode, and the first output terminal is connected to the drain electrode. Is connected, and the channel resistance value of the conduction state of the j-th P-type FET (0 <j <m, m is an integer) and the N-type FET with the negative-polarity power supply terminal connected to the source electrode, There is a multi-value logic circuit (invention 6) in which the channel resistance values of the conductive states of the FETs are substantially the same.
According to this circuit, a ternary multi-input logic circuit different from the logic operation that can be realized in the above inventions 4 and 5 can be configured by a small number of FETs. However, the logic operation that can be realized is limited (as in the first to third aspects of the invention, by treating one or more input terminals of a ternary multi-input logic circuit as a control terminal, the circuit is completely implemented in hardware. Without modification, it is not possible to implement a logic circuit that performs various different logic operations according to the signal from the control terminal).

更なる態様としては、発明１乃至６のいずれかに記載の多値論理回路を備え、更に、ゲート電極が第１の出力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第２の出力端子に接続された、第（２ｍ＋２）のＰ型ＦＥＴと、ゲート電極が第１の出力端子に接続され、ドレイン電極が第２の出力端子に接続され、ソース電極が負極性の電源端子に接続された第（２ｍ＋２）のＮ型ＦＥＴ、を備え、第（２ｍ＋２）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｍ＋２）のＮ型ＦＥＴの導通状態のチャンネル抵抗値、が実質的に等しい、多値論理回路（発明７）が含まれる。
このように、正規化回路を後段に接続することによって、前段の回路（入力演算部）の出力の「ずれ」を補正することが可能となる。また、この回路は簡単な回路構成と最少のＦＥＴの数によって回路構成が可能である。 As a further aspect, the multi-value logic circuit according to any one of the inventions 1 to 6 is provided, the gate electrode is connected to the first output terminal, the source electrode is connected to the positive power supply terminal, and the drain A (2m + 2) -th P-type FET whose electrode is connected to the second output terminal, a gate electrode is connected to the first output terminal, a drain electrode is connected to the second output terminal, and a source electrode is the negative electrode A (2m + 2) -th N-type FET connected to a power supply terminal, and a (2m + 2) -th N-type FET conduction state channel and a (2m + 2) -th N-type FET conduction state channel. A multi-value logic circuit (invention 7) in which the resistance values are substantially equal is included.
In this way, by connecting the normalization circuit to the subsequent stage, it becomes possible to correct the “deviation” of the output of the previous stage circuit (input operation unit). This circuit can be configured with a simple circuit configuration and the minimum number of FETs.

また、別の態様として、発明１乃至６のいずれかに記載の多値論理回路を備え、更に、ゲート電極が第１の出力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（２ｍ＋３）の節点に接続された第（２ｍ＋２）のＰ型ＦＥＴと、ゲート電極が負極極性の電源端子に接続され、ソース電極が第（２ｍ＋３）の節点に接続され、ドレイン電極が第２の出力端子に接続された第（２ｍ＋３）のＰ型ＦＥＴと、ゲート電極が正極性の電源端子に接続され、ドレイン電極が第２の出力端子に接続され、ソース電極が第（２ｍ＋４）の節点に接続された第（２ｍ＋２）のＮ型ＦＥＴと、ゲート電極が第１の出力端子に接続され、ドレイン電極が第（２ｍ＋４）の節点に接続され、ソース電極が負極性の電源端子に接続された第（２ｍ＋３）のＮ型ＦＥＴ、を有し、第（２ｍ＋２）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｍ＋３）のＮ型ＦＥＴの導通状態のチャンネル抵抗値と、が実質的に等しく、第（２ｍ＋３）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｍ＋２）のＮ型ＦＥＴの導通状態のチャンネル抵抗値と、が実質的に等しい、
多値論理回路（発明８）が含まれる。
このように正規化回路を接続することによって、前段の回路（入力演算部）の出力の「ずれ」を補正することが可能となる。さらに、この回路は発明７の回路構成に比較し電流値を制限している（消費電力値を制限している）。 Further, as another aspect, the multi-value logic circuit according to any one of the inventions 1 to 6 is provided, the gate electrode is connected to the first output terminal, the source electrode is connected to the positive power supply terminal, The drain electrode is connected to the (2m + 3) node, the gate electrode is connected to the negative polarity power supply terminal, the source electrode is connected to the (2m + 3) node, and the drain electrode Is connected to the second output terminal, the gate electrode is connected to the positive power supply terminal, the drain electrode is connected to the second output terminal, and the source electrode is (2m + 4). ) Node (2m + 2) N-type FET connected to the node, the gate electrode is connected to the first output terminal, the drain electrode is connected to the (2m + 4) node, and the source electrode is a negative power supply terminal Connected to (2m + 3) N-type FET, and the (2m + 2) -th P-type FET conduction state channel resistance value and the (2m + 3) -th N-type FET conduction state channel resistance value are substantially equal to each other. The channel resistance value of the conductive state of the (2m + 3) th P-type FET and the channel resistance value of the conductive state of the (2m + 2) th N-type FET are substantially equal.
A multi-value logic circuit (Invention 8) is included.
By connecting the normalization circuit in this way, it is possible to correct the “deviation” of the output of the preceding circuit (input operation unit). Further, this circuit limits the current value (limits the power consumption value) compared to the circuit configuration of the seventh aspect.

更に別の態様として、発明１乃至６のいずれかに記載の多値論理回路を備え、更に、ゲート電極が第１の出力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（２ｍ＋３）の節点に接続された第（２ｍ＋２）のＰ型ＦＥＴと、ゲート電極が第（２ｍ＋４）の節点に接続され、ソース電極が第（２ｍ＋３）の節点に接続され、ドレイン電極が第２の出力端子に接続された第（２ｍ＋３）のＰ型ＦＥＴと、ゲート電極が第（２ｍ＋５）の節点に接続され、ドレイン電極が第２の出力端子に接続され、ソース電極が第（２ｍ＋６）の節点に接続された第（２ｍ＋２）のＮ型ＦＥＴと、ゲート電極が第１の出力端子に接続され、ドレイン電極が第（２ｍ＋６）の節点に接続され、ソース電極が負極性の電源端子に接続された第（２ｍ＋３）のＮ型ＦＥＴと、
ゲート電極及びドレイン電極が第（２ｍ＋４）の節点に接続され、ソース電極が正極性の電源端子に接続された第（２ｍ＋４）のＰ型ＦＥＴと、ゲート電極及びドレイン電極が第（２ｍ＋５）の節点に接続され、ソース電極が負極性の電源端子に接続された第（２ｍ＋４）のＮ型ＦＥＴ、
を備え、第（２ｍ＋４）の節点から負極性の電源に向かって定電流源によって一定電流が流され、正極性の電源端子から第（２ｍ＋５）の節点に向かって定電流源によって一定電流が流され、第（２ｍ＋２）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｍ＋３）のＮ型ＦＥＴの導通状態のチャンネル抵抗値と、が実質的に等しく、第（２ｍ＋３）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｍ＋２）のＮ型ＦＥＴの導通状態のチャンネル抵抗値と、が実質的に等しく、第（２ｍ＋４）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｍ＋４）のＮ型ＦＥＴの導通状態のチャンネル抵抗値、が実質的に等しい、多値論理回路（発明９）が挙げられる。
同様に、このように正規化回路を接続することによって、前段の回路（入力演算部）の出力の「ずれ」を補正することが可能となる。さらに、この回路は消費電流値を制限することが可能な回路構成となっている。 As yet another aspect, the multi-value logic circuit according to any one of the first to sixth aspects of the present invention is provided, the gate electrode is connected to the first output terminal, the source electrode is connected to the positive power supply terminal, and the drain A (2m + 2) th P-type FET whose electrode is connected to the (2m + 3) th node, a gate electrode is connected to the (2m + 4) th node, a source electrode is connected to the (2m + 3) th node, and a drain electrode Is connected to the second output terminal (2m + 3) P-type FET, the gate electrode is connected to the (2m + 5) node, the drain electrode is connected to the second output terminal, and the source electrode is ( The (2m + 2) -th N-type FET connected to the (2m + 6) node, the gate electrode is connected to the first output terminal, the drain electrode is connected to the (2m + 6) -node, and the source electrode is a negative power source Connected to terminal And N-type FET of the (2m + 3) was,
A (2m + 4) -th node having a gate electrode and a drain electrode connected to a (2m + 4) -th node, a source electrode connected to a positive power supply terminal, and a (2m + 5) -th node having a gate electrode and a drain electrode. A (2m + 4) th N-type FET having a source electrode connected to a negative power supply terminal,
A constant current is supplied from the (2m + 4) node to the negative power source by the constant current source, and a constant current is supplied from the positive power supply terminal to the (2m + 5) node by the constant current source. The channel resistance value of the conduction state of the (2m + 2) th P-type FET and the channel resistance value of the conduction state of the (2m + 3) th N-type FET are substantially equal, and the (2m + 3) th P-type FET is substantially equal. The channel resistance value of the conductive state of the second and the channel resistance value of the conductive state of the (2m + 2) th N-type FET are substantially equal, and the channel resistance value of the conductive state of the (2m + 4) th P-type FET is substantially equal to There is a multi-value logic circuit (invention 9) in which the channel resistance values of the conductive state of the (2m + 4) N-type FET are substantially equal.
Similarly, by connecting the normalization circuit in this way, it is possible to correct the “deviation” of the output of the preceding circuit (input calculation unit). Further, this circuit has a circuit configuration capable of limiting the current consumption value.

また、別の態様によれば、発明１乃至６のいずれかに記載の多値論理回路を備え、更に、ゲート電極が第１の出力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（２ｍ＋３）の節点に接続された第（２ｍ＋２）のＰ型ＦＥＴと、ゲート電極が第１の出力端子に接続され、ドレイン電極が第（２ｍ＋３）の節点に接続され、ソース電極が負極性の電源端子に接続された第（２ｍ＋２）のＮ型ＦＥＴと、からなる第１のインバータであって、第１の出力端子に印加された正、負の電圧に対しそれぞれ、負、正、の電圧を第（２ｍ＋３）の節点に出力する第１のインバータと、ゲート電極が第１の出力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（２ｍ＋５）の節点に接続された第（２ｍ＋３）のＰ型ＦＥＴと、ゲート電極が第１の出力端子に接続され、ドレイン電極が第（２ｍ＋５）の節点に接続され、ソース電極が負極性の電源端子に接続された第（２ｍ＋３）のＮ型ＦＥＴと、からなる第２のインバータであって、第１の出力端子に印加された正、負の電圧に対しそれぞれ、負、正、の電圧を第（２ｍ＋５）の節点に出力する第２のインバータと、入力端子が第（２ｍ＋３）の節点に接続され、出力端子が第（２ｍ＋４）の節点に接続された第３のインバータと、入力端子が第（２ｍ＋５）の節点に接続され、出力端子が第（２ｍ＋６）の節点に接続された第４のインバータと、ゲート電極が第（２ｍ＋４）の節点に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第２の出力端子に接続された第（２ｍ＋４）のＰ型ＦＥＴと、ゲート電極が第（２ｍ＋６）の節点に接続され、ドレイン電極が第２の出力端子に接続され、ソース電極が負極性の電源端子に接続された第（２ｍ＋４）のＮ型ＦＥＴ、を有し、更に、（１）第１のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より小さく、第２のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より大きい、または、（２）第１のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より大きく、第２のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より小さく、第３のインバータ、および、第４のインバータの論理閾値電圧値がともに、正極性の電源電圧値と負極性の電源電圧値の略中間値であり、第（２ｍ＋４）のＰ型ＦＥＴの導通状態のチャネル抵抗値と、第（２ｍ＋４）のＮ型ＦＥＴの導通状態のチャネル抵抗値が実質的に等しい、多値論理回路（発明１０）が得られる。
同様に、このように正規化回路を接続することによって、前段の回路（入力演算部）の出力の「ずれ」を補正することが可能となる。さらに、この回路は発明７の回路構成に比較し電流値を制限している（消費電力値を制限している）。 According to another aspect, the multi-value logic circuit according to any one of the inventions 1 to 6 is provided, the gate electrode is connected to the first output terminal, and the source electrode is connected to the positive power supply terminal. The drain electrode is connected to the (2m + 3) node, the (2m + 2) P-type FET, the gate electrode is connected to the first output terminal, the drain electrode is connected to the (2m + 3) node, A first inverter composed of a (2m + 2) -th N-type FET whose source electrode is connected to a negative-polarity power supply terminal, with respect to positive and negative voltages applied to the first output terminal, A first inverter that outputs negative and positive voltages to the (2m + 3) node, a gate electrode connected to the first output terminal, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the first Connected to the node of (2m + 5) The (2m + 3) P-type FET, the gate electrode is connected to the first output terminal, the drain electrode is connected to the (2m + 5) node, and the source electrode is connected to the negative power supply terminal (2m + 3) The N-type FET is a second inverter that outputs negative and positive voltages to the (2m + 5) node for positive and negative voltages applied to the first output terminal, respectively. A second inverter, an input terminal connected to the (2m + 3) node, an output terminal connected to the (2m + 4) node, and an input terminal connected to the (2m + 5) node The fourth inverter having the output terminal connected to the (2m + 6) node, the gate electrode connected to the (2m + 4) node, the source electrode connected to the positive power supply terminal, and the drain electrode to the second Connected to the output terminal of The (2m + 4) th P-type FET, the gate electrode connected to the (2m + 6) node, the drain electrode connected to the second output terminal, and the source electrode connected to the negative power supply terminal ( 2m + 4) N-type FET, and (1) the logical threshold voltage value of the first inverter is smaller than the intermediate value between the positive power supply voltage value and the negative power supply voltage value. The logical threshold voltage value is greater than the intermediate value between the positive power supply voltage value and the negative power supply voltage value, or (2) the first inverter logical threshold voltage value is a positive power supply voltage value and a negative power supply. The logic threshold voltage value of the second inverter is greater than the intermediate value of the voltage values, and is smaller than the intermediate value of the positive power supply voltage value and the negative power supply voltage value. The logic of the third inverter and the fourth inverter Both power supply with positive threshold voltage The channel value of the conduction state of the (2m + 4) th P-type FET and the channel resistance value of the conduction state of the (2m + 4) th N-type FET are substantially intermediate values between the voltage value and the negative power supply voltage value. Multi-valued logic circuit (invention 10) is obtained.
Similarly, by connecting the normalization circuit in this way, it is possible to correct the “deviation” of the output of the preceding circuit (input calculation unit). Further, this circuit limits the current value (limits the power consumption value) compared to the circuit configuration of the seventh aspect.

また、発明１乃至６のいずれかに記載の多値論理回路を備え、更に、ゲート電極が第１の出力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（２ｍ＋３）の節点に接続された第（２ｍ＋２）のＰ型ＦＥＴと、ゲート電極が第１の出力端子に接続され、ドレイン電極が第（２ｍ＋３）の節点に接続され、ソース電極が負極性の電源端子に接続された第（２ｍ＋２）のＮ型ＦＥＴと、からなる第１のインバータであって、第１の出力端子に印加された正、負の電圧に対しそれぞれ、負、正の電圧を第（２ｍ＋３）の節点に出力する第１のインバータと、ゲート電極が第１の出力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（２ｍ＋５）の節点に接続された第（２ｍ＋３）のＰ型ＦＥＴと、ゲート電極が第１の出力端子に接続され、ドレイン電極が第（２ｍ＋５）の節点に接続され、ソース電極が負極性の電源端子に接続された第（２ｍ＋３）のＮ型ＦＥＴと、からなる第２のインバータであって、第１の出力端子に印加された正、負の電圧に対しそれぞれ、負、正の電圧を第（２ｍ＋５）の節点に出力する第２のインバータと、入力が第（２ｍ＋３）の節点に接続され、出力が第（２ｍ＋４）の節点に接続された第３のインバータと、入力が第（２ｍ＋５）の節点に接続され、出力が第（２ｍ＋６）の節点に接続された第４のインバータと、ゲート電極が第（２ｍ＋４）の節点に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第２の出力端子に接続された第（２ｍ＋４）のＰ型ＦＥＴと、ゲート電極が第（２ｍ＋６）の節点に接続され、ドレイン電極が第２の出力端子に接続され、ソース電極が負極性の電源端子に接続された第（２ｍ＋４）のＮ型ＦＥＴと、ゲート電極が第（２ｍ＋５）の節点に接続され、ドレイン電極が第２の出力端子に接続され、ソース電極が第（２ｍ＋７）の節点に接続された第（２ｍ＋５）のＮ型ＦＥＴと、ゲート電極が第（２ｍ＋４）の節点に接続され、ドレイン電極が第（２ｍ＋７）の節点に接続され、ソース電極がゼロ電位の接地電極に接続された第（２ｍ＋６）のＮ型ＦＥＴ、を有し、更に、（１）第１のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より小さく、第２のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より大きく、または、（２）第１のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より大きく、第２のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より小さく、第３のインバータ、および、第４のインバータの論理閾値電圧値がともに、正極性の電源電圧値と負極性の電源電圧値の略中間値であり、第（２ｍ＋４）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｍ＋４）のＮ型ＦＥＴの導通状態のチャンネル抵抗値、が実質的に等しく、第（２ｍ＋５）のＮ型ＦＥＴの導通状態のチャンネル抵抗値、と第（２ｍ＋６）のＮ型ＦＥＴの導通状態のチャンネル抵抗値、が実質的に等しい、多値論理回路（発明１１）という態様も含まれる。
このように正規化回路を接続することによって、前段の回路（入力演算部）の出力の「ずれ」を理想的に補正することが可能となる。 Further, the multi-value logic circuit according to any one of the inventions 1 to 6 is provided, the gate electrode is connected to the first output terminal, the source electrode is connected to the positive power supply terminal, and the drain electrode is the first ( The (2m + 2) th P-type FET connected to the (2m + 3) node, the gate electrode is connected to the first output terminal, the drain electrode is connected to the (2m + 3) node, and the source electrode is a negative power source A first inverter composed of a (2m + 2) -th N-type FET connected to the terminal, wherein the negative and positive voltages are applied to the positive and negative voltages applied to the first output terminal, respectively. The first inverter that outputs to the (2m + 3) node, the gate electrode is connected to the first output terminal, the source electrode is connected to the positive power supply terminal, and the drain electrode is connected to the (2m + 5) node. (2m + 3) P type ET, a (2m + 3) N-type FET having a gate electrode connected to the first output terminal, a drain electrode connected to the (2m + 5) node, and a source electrode connected to the negative power supply terminal; A second inverter that outputs negative and positive voltages to the (2m + 5) node for each of positive and negative voltages applied to the first output terminal, and an input Is connected to the (2m + 3) node, the output is connected to the (2m + 4) node, the input is connected to the (2m + 5) node, and the output is connected to the (2m + 6) node. The connected fourth inverter, the gate electrode connected to the (2m + 4) node, the source electrode connected to the positive power supply terminal, and the drain electrode connected to the second output terminal (2m + 4) P-type FET and A (2m + 4) N-type FET having an electrode connected to the (2m + 6) node, a drain electrode connected to the second output terminal, a source electrode connected to a negative power supply terminal, and a gate electrode The (2m + 5) -th node is connected to the (2m + 5) node, the drain electrode is connected to the second output terminal, the source electrode is connected to the (2m + 7) -th node, and the gate electrode is (2m + 4). ), A drain electrode connected to the (2m + 7) th node, a source electrode connected to a zero-potential ground electrode, and a (2m + 6) th N-type FET, and (1) The logical threshold voltage value of the first inverter is smaller than the intermediate value between the positive power supply voltage value and the negative power supply voltage value, and the logical threshold voltage value of the second inverter is the positive power supply voltage value and the negative power supply. Greater than intermediate voltage value (2) The logic threshold voltage value of the first inverter is greater than the intermediate value between the positive power supply voltage value and the negative power supply voltage value, and the logical threshold voltage value of the second inverter is a positive power supply. Less than the intermediate value between the voltage value and the negative power supply voltage value, and the logical threshold voltage values of the third inverter and the fourth inverter are both substantially intermediate between the positive power supply voltage value and the negative power supply voltage value. The channel resistance value of the conduction state of the (2m + 4) th P-type FET and the channel resistance value of the conduction state of the (2m + 4) th N-type FET are substantially equal, and the (2m + 5) th N-type. A mode of a multi-value logic circuit (invention 11) in which the channel resistance value of the conductive state of the FET and the channel resistance value of the conductive state of the (2m + 6) th N-type FET are substantially equal is also included.
By connecting the normalization circuit in this way, it is possible to ideally correct the “deviation” of the output of the preceding circuit (input calculation unit).

更なる態様として、発明１乃至６のいずれかに記載の多値論理回路を備え、
更に、入力が第１の出力端子に接続され、出力が第（２ｍ＋４）の節点に接続された、第１の制御手段と、入力が第１の出力端子に接続され、出力が第（２ｍ＋６）の節点に接続された第２の制御手段と、ゲート電極が第（２ｍ＋４）の節点に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第２の出力端子に接続され、第（２ｍ＋４）のＰ型ＦＥＴと、ゲート電極が第（２ｍ＋６）の節点に接続され、ドレイン電極が第２の出力端子に接続され、ソース電極が負極性の電源端子に接続された、第（２ｍ＋４）のＮ型ＦＥＴ、を備え、第（２ｍ＋４）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（２ｍ＋４）のＮ型ＦＥＴの導通状態のチャンネル抵抗値が、実質的に等しく、第１の制御手段は、第１の入力端子の電位が、ＶｓｓからＶｓｓ＋｛（Ｖｄｄ−Ｖｓｓ）／Ｎ｝、（ここでＶｓｓは、負極性の電源端子の電圧値であり、Ｖｄｄは正極性の電源端子の電圧値であり、Ｎは２以上の実数である）の間のとき、第（２ｍ＋４）のＰ型ＦＥＴをオンする電圧を出力し、それ以外の場合には、第（２ｍ＋４）のＰ型ＦＥＴをオフする電圧を出力し、第２の制御手段は、第１の入力端子の電位が、Ｖｄｄ−｛（Ｖｄｄ−Ｖｓｓ）／Ｐ｝からＶｄｄ、（ここで、Ｐは２以上の実数である）の間のとき、第（２ｍ＋４）のＮ型ＦＥＴをオンする電圧を出力し、それ以外の場合には、第（２ｍ＋４）のＮ型ＦＥＴをオフする電圧を出力する、多値論理回路（発明１２）が含まれる。
このように正規化回路を接続することによって、前段の回路（入力演算部）の出力の「ずれ」を理想的に補正することが可能となる。 As a further aspect, the multi-value logic circuit according to any one of the inventions 1 to 6 is provided,
Furthermore, the input is connected to the first output terminal, the output is connected to the (2m + 4) th node, the first control means, the input is connected to the first output terminal, and the output is the (2m + 6) th. The second control means connected to the node, the gate electrode is connected to the (2m + 4) node, the source electrode is connected to the positive power supply terminal, the drain electrode is connected to the second output terminal, A (2m + 4) th P-type FET, a gate electrode connected to a (2m + 6) th node, a drain electrode connected to a second output terminal, a source electrode connected to a negative power supply terminal, 2m + 4) N-type FET, the channel resistance value of the conduction state of the (2m + 4) th P-type FET and the channel resistance value of the conduction state of the (2m + 4) th N-type FET are substantially equal, The control means 1 is connected to the first input terminal Vss to Vss + {(Vdd−Vss) / N}, where Vss is the voltage value of the negative power supply terminal, Vdd is the voltage value of the positive power supply terminal, and N is 2 or more Output a voltage that turns on the (2m + 4) th P-type FET, and otherwise outputs a voltage that turns off the (2m + 4) th P-type FET. When the potential of the first input terminal is between Vdd − {(Vdd−Vss) / P} and Vdd (where P is a real number equal to or greater than 2), ) Outputs a voltage for turning on the N-type FET, and in other cases, outputs a voltage for turning off the (2m + 4) -th N-type FET (Invention 12).
By connecting the normalization circuit in this way, it is possible to ideally correct the “deviation” of the output of the preceding circuit (input calculation unit).

更に、第（２ｍ＋４）のＰ型ＦＥＴをオンする電圧が、Ｖｄｄ−（Ｖｄｄ-Ｖｓｓ）／３からＶｄｄまでの間の電位であり、第（２ｍ＋４）のＰ型ＦＥＴをオフする電圧が、ＶｓｓからＶｄｄ−（Ｖｄｄ−Ｖｓｓ）／３までの間の電位であり、第（２ｍ＋４）のＮ型ＦＥＴをオンする電圧が、ＶｓｓからＶｓｓ＋（Ｖｄｄ-Ｖｓｓ）／３の間の電位であり、第（２ｍ＋４）のＮ型ＦＥＴをオフする電圧がＶｓｓ＋（Ｖｄｄ-Ｖｓｓ）／３からＶｄｄまでの間の電位である、発明１２に記載の多値論理回路（発明１３）が含まれる。
この場合も同様に、正規化回路を接続することによって、前段の回路（入力演算部）の出力の「ずれ」を理想的に補正することが可能となる。 Further, the voltage for turning on the (2m + 4) th P-type FET is a potential between Vdd− (Vdd−Vss) / 3 and Vdd, and the voltage for turning off the (2m + 4) th P-type FET is Vss. To Vdd− (Vdd−Vss) / 3, and the voltage for turning on the (2m + 4) th N-type FET is the potential between Vss and Vss + (Vdd−Vss) / 3. The multi-value logic circuit according to invention 12 (invention 13), wherein the voltage for turning off the N-type FET of (2m + 4) is a potential between Vss + (Vdd−Vss) / 3 and Vdd.
In this case as well, by connecting a normalization circuit, it is possible to ideally correct the “deviation” of the output of the preceding circuit (input arithmetic unit).

また別の態様によれば、ゲート電極が第ｊ（０＜ｊ，ｊは整数）の入力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（５ｊ−４）の節点に接続された第（５ｊ−４）のＰ型ＦＥＴと、ゲート電極が第ｊの入力端子に接続され、ドレイン電極が第（５ｊ−４）の節点に接続され、ソース電極が負極性の電源端子に接続された第（５ｊ−４）のＮ型ＦＥＴと、からなる第（５ｊ−４）のインバータであって、第ｊの入力端子に印加された正、負の電圧に対しそれぞれ、負、正の電圧を第（５ｊ−４）の節点に出力する第（５ｊ−４）のインバータと、ゲート電極が第ｊの入力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（５ｊ−３）の節点に接続された第（５ｊ−３）のＰ型ＦＥＴと、ゲート電極が第ｊの入力端子に接続され、ドレイン電極が第（５ｊ−３）の節点に接続され、ソース電極が負極性の電源端子に接続された第（５ｊ−３）のＮ型ＦＥＴと、からなる第（５ｊ−３）のインバータであって、第ｊの入力端子に印加された正、負の電圧に対しそれぞれ、負、正の電圧を第（５ｊ−３）の節点に出力する第（５ｊ−３）のインバータと、ゲート電極が第（５ｊ−４）の節点に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第１の出力端子に接続された第（５ｊ−２）のＰ型ＦＥＴと、ゲート電極が第（５ｊ−３）の節点に接続され、ドレイン電極が第１の出力端子に接続され、ソース電極が負極性の電源端子に接続された第（５ｊ−２）のＮ型ＦＥＴと、からなる第（５ｊ−１）のインバータと、入力端子が第（５ｊ−３）の節点に接続され、出力端子が第（５ｊ−２）の節点に接続された第（５ｊ−２）のインバータと、ゲート電極が第（５ｊ−２）の節点に接続され、ドレイン電極が第（５ｊ−１）の節点に接続され、ソース電極が第（５ｊ）の節点に接続された第（５ｊ−１）のＮ型ＦＥＴと、ゲート電極が第（５ｊ−４）の節点に接続され、ドレイン電極が第（５ｊ）の節点に接続され、ソース電極が第（５ｊ＋１）の節点に接続された第５ｊのＮ型ＦＥＴ、を有する単位回路をｊ＝１からｍまでのｍ個（０＜ｍ，ｍは整数）備え、第４の節点が第１の出力端子に接続され、第（５ｍ＋１）の節点がゼロ電位に接地され、第（５ｊ−２）のＰ型ＦＥＴの導通状態のチャンネル抵抗値と、第（５ｊ−２）のＮ型ＦＥＴの導通状態のチャンネル抵抗値と、が実質的に等しく、第（５ｊ−１）のＮ型ＦＥＴの導通状態のチャンネル抵抗値と、および第５ｊのＮ型ＦＥＴの導通状態のチャンネル抵抗値と、が実質的に等しく、更に、（１）第（５ｊ−４）のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より小さく、第（５ｊ−３）のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より大きい、または、（２）第（５ｊ−４）のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より大きく、第（５ｊ−３）のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より小さく、第（５ｊ−２）のインバータ、および、第（５ｊ−１）のインバータの論理閾値電圧値がともに、正極性の電源電圧値と負極性の電源電圧値の略中間値である、多値論理回路（発明１４）が得られる。
この場合も同様に、正規化回路を接続することによって、前段の回路（入力演算部）の出力の「ずれ」を理想的に補正することが可能となる。また、回路中の節点が電圧的に「浮いた」状態になるのを防ぐ回路を追加することで、回路動作がより安定する。さらに、入力レンジを広く取ることができ、消費電流が少ない回路となっている。 According to another aspect, the gate electrode is connected to the jth (0 <j, j is an integer) input terminal, the source electrode is connected to the positive power supply terminal, and the drain electrode is (5j-4) th. The (5j-4) th P-type FET connected to the node, the gate electrode connected to the jth input terminal, the drain electrode connected to the (5j-4) node, and the source electrode negative polarity A (5j-4) th N-type FET connected to the power supply terminal of (5j-4), and a (5j-4) th inverter, respectively, for positive and negative voltages applied to the jth input terminal The (5j-4) inverter that outputs negative and positive voltages to the (5j-4) th node, the gate electrode is connected to the jth input terminal, and the source electrode is connected to the positive power supply terminal And the drain electrode is connected to the (5j-3) -th node and the (5j-3) -th P-type. ET, a (5j-3) th N terminal whose gate electrode is connected to the jth input terminal, whose drain electrode is connected to the (5j-3) node, and whose source electrode is connected to the negative power supply terminal A (5j-3) th inverter comprising a type FET, wherein the negative and positive voltages are respectively applied to the positive and negative voltages applied to the jth input terminal. The (5j-3) inverter that outputs to the gate, the gate electrode is connected to the (5j-4) node, the source electrode is connected to the positive power supply terminal, and the drain electrode is connected to the first output terminal The (5j-2) th P-type FET, the gate electrode is connected to the (5j-3) node, the drain electrode is connected to the first output terminal, and the source electrode is connected to the negative power supply terminal A (5j-1) -th N-type FET connected thereto, An inverter, an input terminal connected to the (5j-3) -th node, an output terminal connected to the (5j-2) -th node, a (5j-2) -th inverter, and a gate electrode (5j--) A (5j-1) th N-type FET having a drain electrode connected to the (5j-1) th node, a source electrode connected to the (5j) th node, and a gate electrode Is connected to the (5j-4) -th node, the drain electrode is connected to the (5j) -th node, and the source circuit is connected to the (5j + 1) -th node. , J = 1 to m (0 <m, where m is an integer), the fourth node is connected to the first output terminal, the (5m + 1) th node is grounded to zero potential, 5j-2) P-type FET conduction state channel resistance value and (5j-2) -th N-type FE The channel resistance value of the conductive state of T is substantially equal, and the channel resistance value of the conductive state of the (5j−1) th N-type FET and the channel resistance value of the conductive state of the 5j N-type FET are Are substantially equal, and (1) the logic threshold voltage value of the (5j-4) th inverter is smaller than the intermediate value between the positive power supply voltage value and the negative power supply voltage value. ) Is greater than the intermediate value between the positive and negative power supply voltage values, or (2) the logical threshold voltage value of the (5j-4) th inverter is positive. Greater than the intermediate value between the power supply voltage value and the negative power supply voltage value, and the logic threshold voltage value of the (5j-3) th inverter is smaller than the intermediate value between the positive power supply voltage value and the negative power supply voltage value; (5j-2) inverter and (5j-1) Both the logical threshold voltage of the inverter, a substantially intermediate value of the positive polarity of the power supply voltage and the negative supply voltage values, multivalued logic circuit (Invention 14) is obtained.
In this case as well, by connecting a normalization circuit, it is possible to ideally correct the “deviation” of the output of the preceding circuit (input arithmetic unit). In addition, the circuit operation is further stabilized by adding a circuit that prevents the nodes in the circuit from becoming “floating” in terms of voltage. Furthermore, the input range can be widened, and the circuit consumes less current.

また、別の態様として、ゲート電極が第ｊ（０＜ｊ，ｊは整数）の入力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（５ｊ−４）の節点に接続された第（５ｊ−４）のＰ型ＦＥＴと、ゲート電極が第ｊの入力端子に接続され、ドレイン電極が第（５ｊ−４）の節点に接続され、ソース電極が負極性の電源端子に接続された第（５ｊ−４）のＮ型ＦＥＴと、からなる第（５ｊ−４）のインバータであって、第ｊの入力端子に印加された正、負の電圧に対しそれぞれ、負、正の電圧を第（５ｊ−４）の節点に出力する第（５ｊ−４）のインバータと、ゲート電極が第ｊの入力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第（５ｊ−３）の節点に接続された第（５ｊ−３）のＰ型ＦＥＴと、ゲート電極が第ｊの入力端子に接続され、ドレイン電極が第（５ｊ−３）の節点に接続され、ソース電極が負極性の電源端子に接続された第（５ｊ−３）のＮ型ＦＥＴと、からなる第（５ｊ−３）のインバータであって、第ｊの入力端子に印加された正、負の電圧に対しそれぞれ、負、正の電圧を第（５ｊ−３）の節点に出力する第（５ｊ−３）のインバータと、ゲート電極が第（５ｊ−４）の節点に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第１の出力端子に接続され、第（５ｊ−２）のＰ型ＦＥＴと、ゲート電極が第（５ｊ−３）の節点に接続され、ドレイン電極が第１の出力端子に接続され、ソース電極が負極性の電源端子に接続され、第（５ｊ−２）のＮ型ＦＥＴと、入力端子が第（５ｊ−３）の節点に接続され、出力端子が第（５ｊ−２）の節点に接続された第（５ｊ−２）のインバータと、を有し、第（５ｊ−２）のＰ型ＦＥＴの導通状態のチャンネル抵抗と、第（５ｊ−２）のＮ型ＦＥＴの導通状態のチャンネル抵抗と、が実質的に同一であり、更に、（１）第（５ｊ−４）のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より小さく、第（５ｊ−３）のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より大きい、または、（２）第（５ｊ−４）のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より大きく、第（５ｊ−３）のインバータの論理閾値電圧値が正極性の電源電圧値と負極性の電源電圧値の中間値より小さい、単位回路をｊ＝１からｍ、までのｍ個（０＜ｍ、ｍは整数）備え、更に、第１の出力端子とゼロ電位の接地端子の間に接続された短絡開放手段であって、当該短絡開放手段は、ｊ＝１からｍまでの全てのｊについて、第（５ｊ−４）の節点の電位および第（５ｊ−２）の節点の電位が全てゼロ電位となったときに、第１の出力端子とゼロ電位の接地端子を短絡し、それ以外の場合には、第１の出力端子とゼロ電位の接地端子を開放する短絡開放手段、を備えた、多値論理回路（発明１５）が含まれる。
この場合も同様に、正規化回路を接続することによって、前段の回路（入力演算部）の出力の「ずれ」を理想的に補正することが可能となる。また、回路中の節点が電圧的に「浮いた」状態になるのを防ぐ回路を追加することで、回路動作がより安定する。 As another aspect, the gate electrode is connected to the jth (0 <j, j is an integer) input terminal, the source electrode is connected to the positive power supply terminal, and the drain electrode is the (5j-4) th. The (5j-4) th P-type FET connected to the node, the gate electrode is connected to the jth input terminal, the drain electrode is connected to the (5j-4) th node, and the source electrode is negative A (5j-4) th inverter composed of a (5j-4) th N-type FET connected to the power supply terminal, respectively, for positive and negative voltages applied to the jth input terminal, The (5j-4) inverter that outputs negative and positive voltages to the (5j-4) node, the gate electrode is connected to the jth input terminal, and the source electrode is connected to the positive power supply terminal. The drain electrode is connected to the (5j-3) -th node and the (5j-3) -th P-type. ET, a (5j-3) th N terminal whose gate electrode is connected to the jth input terminal, whose drain electrode is connected to the (5j-3) node, and whose source electrode is connected to the negative power supply terminal A (5j-3) th inverter comprising a type FET, wherein the negative and positive voltages are respectively applied to the positive and negative voltages applied to the jth input terminal. The (5j-3) inverter that outputs to the gate, the gate electrode is connected to the (5j-4) node, the source electrode is connected to the positive power supply terminal, and the drain electrode is connected to the first output terminal The (5j-2) th P-type FET, the gate electrode is connected to the (5j-3) node, the drain electrode is connected to the first output terminal, and the source electrode is connected to the negative power supply terminal. Connected, the (5j-2) th N-type FET and the input terminal (5j-3) And a (5j-2) th inverter connected to the (5j-2) th node and having an output terminal connected to the (5j-2) th node. The resistance and the channel resistance of the conductive state of the (5j-2) th N-type FET are substantially the same, and (1) the logic threshold voltage value of the (5j-4) th inverter is positive. Less than the intermediate value of the negative power supply voltage value and the logic threshold voltage value of the (5j-3) th inverter is higher than the intermediate value of the positive power supply voltage value and the negative power supply voltage value. Or (2) the logical threshold voltage value of the (5j-4) th inverter is greater than the intermediate value between the positive power supply voltage value and the negative power supply voltage value, and the logical threshold voltage of the (5j-3) th inverter. The value is smaller than the intermediate value between the positive power supply voltage value and the negative power supply voltage value. Short-circuit opening means provided with m unit circuits from j = 1 to m (0 <m, where m is an integer) and connected between a first output terminal and a zero-potential ground terminal; The short-circuit opening means is configured such that for all j from j = 1 to m, the potentials of the (5j-4) -th node and the (5j-2) -th node are all zero potentials. A multi-value logic circuit comprising short-circuit opening means for short-circuiting one output terminal and a zero-potential ground terminal, and otherwise opening the first output terminal and the zero-potential ground terminal (Invention 15) ) Is included.
In this case as well, by connecting a normalization circuit, it is possible to ideally correct the “deviation” of the output of the preceding circuit (input arithmetic unit). In addition, the circuit operation is further stabilized by adding a circuit that prevents the nodes in the circuit from becoming “floating” in terms of voltage.

更に、好ましい態様としては、ゲート電極が第１の入力端子に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第１の出力端子に接続されたＰ型ＦＥＴと、ゲート電極が接地電極に接続され、ドレイン電極が第１の出力端子に接続され、ソース電極が負極性の電源端子に接続されたＮ型ＦＥＴ、を有し、Ｐ型ＦＥＴの導通状態のチャンネル抵抗値と、Ｎ型ＦＥＴの導通状態のチャンネル抵抗値、が実質的に同一である、多値論理回路（発明１６）が含まれる。
この回路によれば、最少のＦＥＴの数によって、３値インバータが構成できる。（消費電流は他の回路に比べ大きいが）この３値インバータを接続することにより、前段の回路（入力演算部）の出力の「ずれ」を理想的に補正することが可能となる。 Further, as a preferred embodiment, a P-type FET having a gate electrode connected to the first input terminal, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the first output terminal, and a gate electrode Is connected to the ground electrode, the drain electrode is connected to the first output terminal, the source electrode is connected to the negative power supply terminal, and the channel resistance value of the conductive state of the P-type FET is , A multi-value logic circuit (invention 16) in which the channel resistance values of the N-type FETs in the conductive state are substantially the same.
According to this circuit, a ternary inverter can be configured with the minimum number of FETs. By connecting this ternary inverter (although the current consumption is larger than that of other circuits), it is possible to ideally correct the “deviation” of the output of the preceding circuit (input arithmetic unit).

更に、好ましい態様としては、ゲート電極が接地電極に接続され、ソース電極が正極性の電源端子に接続され、ドレイン電極が第１の出力端子に接続されたＰ型ＦＥＴと、ゲート電極が第１の入力端子に接続され、ドレイン電極が第１の出力端子に接続され、ソース電極が負極性の電源端子に接続されたＮ型ＦＥＴ、を有し、Ｐ型ＦＥＴの導通状態のチャンネル抵抗値と、Ｎ型ＦＥＴの導通状態のチャンネル抵抗値、が実質的に同一である、多値論理回路（発明１７）が含まれる。
この場合も同様に、最少のＦＥＴの数によって、３値インバータが構成できる。（消費電流は他の回路に比べ大きいが）この３値インバータを接続することにより、前段の回路（入力演算部）の出力の「ずれ」を理想的に補正することが可能となる。 Further, as a preferred embodiment, a P-type FET in which the gate electrode is connected to the ground electrode, the source electrode is connected to the positive power supply terminal, the drain electrode is connected to the first output terminal, and the gate electrode is the first. A channel resistance value of a conductive state of the P-type FET, and an N-type FET having a drain electrode connected to the first output terminal and a source electrode connected to the negative power supply terminal. , A multi-value logic circuit (invention 17) in which the channel resistance values of the N-type FETs in the conductive state are substantially the same.
In this case as well, a ternary inverter can be configured with a minimum number of FETs. By connecting this ternary inverter (although the current consumption is larger than that of other circuits), it is possible to ideally correct the “deviation” of the output of the preceding circuit (input arithmetic unit).

別の態様としては、正極性の電源電圧と、負極性の電源電圧の絶対値が、実質的に等しい、以上のいずれかの発明に記載の多値論理回路（発明１８）が挙げられる。
このように、電源電圧値を０ｖを中心に対称にすることにより、プラス側およびマイナス側の回路の設計が容易となる。また、真理値表で表す論理値（−１，０，１）と電源電圧値（−３ｖ，０ｖ，３ｖ）の極性とが一致をすることにより、理論と回路出力との一対一対応が付けやすい。さらに、正負の数を取り扱う時、補数表示、符号桁、符号変換などが不要で、加算器を構成するとそのまま減算を行える、端数の切り捨てがそのまま丸めの効果を有するので、特別に丸め回路を必要としない、などの利点がある。 Another aspect is the multi-value logic circuit (invention 18) according to any one of the above inventions, in which the absolute values of the positive power supply voltage and the negative power supply voltage are substantially equal.
In this way, by making the power supply voltage value symmetrical about 0v, it is easy to design the plus side and minus side circuits. In addition, since the logical values (−1, 0, 1) represented in the truth table and the polarities of the power supply voltage values (−3 v, 0 v, 3 v) coincide, a one-to-one correspondence between the theory and the circuit output is attached. Cheap. In addition, when dealing with positive and negative numbers, complement display, sign digit, sign conversion, etc. are unnecessary, and if an adder is configured, subtraction can be performed as it is, and rounding off of fractions has the effect of rounding, so a special rounding circuit is required. There are advantages such as not.

更に、別の態様として、各ＦＥＴが全てノーマリオフタイプのＦＥＴである、以上のいずれかの発明に記載の多値論理回路（発明１９）が挙げられる。
ノーマリーオフの素子を利用することで、回路構成が簡易となる。 Furthermore, as another aspect, there is a multi-value logic circuit (Invention 19) according to any one of the above inventions, wherein each FET is a normally-off type FET.
By using a normally-off element, the circuit configuration is simplified.

更なる態様としては、各ＦＥＴが全てＭＯＳＦＥＴである、以上のいずれかの発明に記載の多値論理回路（発明２０）が含まれる。
ＭＯＳＦＥＴは最も広く用いられている素子であり、汎用的な多値回路が構成できる。さらに、集積回路化が容易で、ＦＥＴを構成する大きさ（シリコンウエハー上のデザイン）によってその特性が設計できる事により安定した回路を製造できる。また、製造に掛かるプロセスがすでに完成している。現在はより高速にするため、及びより小さい電圧で動作するＦＥＴ素子を設計するという段階に達している。 As a further aspect, the multi-value logic circuit (Invention 20) according to any one of the above inventions, in which each FET is a MOSFET, is included.
The MOSFET is the most widely used element and can constitute a general-purpose multi-value circuit. Furthermore, it is easy to make an integrated circuit, and a stable circuit can be manufactured by designing its characteristics according to the size (design on the silicon wafer) constituting the FET. In addition, the manufacturing process has already been completed. Currently, the stage of designing FET devices that operate at lower voltages and higher speeds has been reached.

なお、本明細書中、インバータ、とは“ＮＯＴ回路（ＮＯＴゲート）”のことである。また、ゲートとは、論理回路を構成する最小単位（最少の機能を持つ回路）のことを意味し、２値論理ではＡＮＤゲート、ＯＲゲート、ＮＯＴゲート（インバータ）、ＮＡＮＤゲート、ＮＯＲゲートなどがある。 In this specification, an inverter is a “NOT circuit (NOT gate)”. A gate means a minimum unit (a circuit having a minimum function) constituting a logic circuit. In binary logic, an AND gate, an OR gate, a NOT gate (inverter), a NAND gate, a NOR gate, and the like are included. is there.

「チャネル抵抗が実質的に等しい」とは、製造プロセス等の原因により各FETのチャネル抵抗値がばらついても、多値論理の各論理値を表現可能な範囲のことを言う。特に問題となるのが論理値0を表現する場合である。バラツキが大きくなるにつれ、論理値が１や-1に変動してしまう。これらのチャネル抵抗値のバラツキを吸収する回路が出力正規化回路である。 “Channel resistance is substantially equal” means a range in which each logic value of multi-value logic can be expressed even if the channel resistance value of each FET varies due to a manufacturing process or the like. Particularly problematic is the case where the logical value 0 is expressed. As the variation increases, the logical value fluctuates to 1 or -1. A circuit that absorbs variations in these channel resistance values is an output normalization circuit.

インバータの論理閾値電圧Vinvとは、論理が切り替わるときの閾値電圧のことである。スイッチ閾値電圧とも呼ぶ。論理閾値電圧Vinvでは、Ｐ型ＦＥＴおよびＮ型ＦＥＴが飽和領域で動作し、そのとき、各FETに流れる電流も等しくなる。よって、論理閾値電圧Vinvは、次式より求められる。
(1/2)×βn×（Vinv−Vthn）＾2 ＝ (1/2)×βp×（VinvーVdd−Vthp）＾2 （式１）
∴Vinv ＝｛βp＾(1/2)×（Vdd＋Vthp）＋βn＾(1/2)×Vthn｝/｛βp＾(1/2)＋
βn＾(1/2)｝（式２）
ただし、上式は、電源がVｄｄからGNDの場合に成立する。
ノーマリーオフとは、次のような意味である。即ち、図２の（ａ）にＮ型ＦＥＴのＶｇｓ（Gate−Source間の電圧）対Ｉｄ（Drain電流）の特性を示す。（Ｐ型ＦＥＴはＶｇｓ，Ｉｄの極性がちょうどこの逆になる）。この図の(1)の曲線と(2)の曲線の違いについて、
１の曲線：エンハンスメント型と呼ばれるＦＥＴの特性で横軸Ｖｇｓ＝０ｖのとき、Ｉｄ＝０より、このＦＥＴをノーマリーオフ型と言う。
２の曲線：デプレッション型と呼ばれるＦＥＴの特性で横軸Ｖｇｓ＝０ｖのとき、Ｉｄ＝０でない（ある電流が流れている）より、このＦＥＴをノーマリーオン型と言う。 The logic threshold voltage Vinv of the inverter is a threshold voltage when the logic is switched. Also called a switch threshold voltage. At the logic threshold voltage Vinv, the P-type FET and the N-type FET operate in the saturation region, and at this time, the currents flowing through the FETs are also equal. Therefore, the logical threshold voltage Vinv is obtained from the following equation.
(1/2) × βn × (Vinv−Vthn) ^ 2 = (1/2) × βp × (Vinv−Vdd−Vthp) ^ 2 (Formula 1)
∴Vinv = {βp ^ (1/2) × (Vdd + Vthp) + βn ^ (1/2) × Vthn} / {βp ^ (1/2) +
βn ^ (1/2)} (Formula 2)
However, the above formula is established when the power source is Vdd to GND.
Normally-off means the following. That is, FIG. 2A shows the characteristics of Vgs (voltage between Gate and Source) versus Id (Drain current) of the N-type FET. (P-type FETs have the opposite polarity of Vgs and Id). Regarding the difference between curve (1) and curve (2) in this figure,
Curve 1: A characteristic of an FET called an enhancement type. When the horizontal axis Vgs = 0v, this FET is called a normally-off type from Id = 0.
Curve 2: A FET characteristic called a depletion type. When the horizontal axis Vgs = 0v, Id is not 0 (a certain current flows), so this FET is called a normally-on type.

ＦＥＴのスレッシュホールド電圧（閾値電圧ＶＴ）とは、Ｖｇｓがある電圧を超えるとＩｄが流れ始めるところの電圧をいう。（図２のａ） The FET threshold voltage (threshold voltage VT) is a voltage at which Id starts to flow when Vgs exceeds a certain voltage. (A in FIG. 2)

本発明によって、３値多入力論理回路の１以上の入力端子を制御端子として扱うことによって、当該回路をハードウェア的には全く変更せずに、制御端子からの信号に従って、種々の異なった論理動作を実行する論理回路を実現することが可能となる。
また、ＦＥＴ構造を利用して、集積度が大きく、動作速度が速い、ＦＥＴ多値論理回路を提供することが可能となる。
更に、０（Ｖ）入力時の消費電流が小さく、０（Ｖ）に対する入力レンジが広いＦＥＴ多値論理回路を提供可能である。 By treating one or more input terminals of a ternary multi-input logic circuit as a control terminal according to the present invention, various different logics can be selected according to the signal from the control terminal without changing the circuit in hardware. It is possible to realize a logic circuit that executes an operation.
In addition, it is possible to provide an FET multilevel logic circuit having a high degree of integration and a high operation speed by using an FET structure.
Further, it is possible to provide an FET multilevel logic circuit that consumes less current when 0 (V) is input and has a wide input range for 0 (V).

以下、本発明を実施するための最良の形態について説明する。なお、本発明は、以下の実施の形態および実施例に限定されるものではなく、種々の変形、修正、均等物との置換等が可能であり、本発明の技術的範囲は特許請求の範囲によってのみ規定される。
実施例１から８までの回路の動作シミュレーションに用いたシミュレータの緒元を表１に示す。

Hereinafter, the best mode for carrying out the present invention will be described. The present invention is not limited to the following embodiments and examples, and various modifications, corrections, substitutions with equivalents, and the like are possible. The technical scope of the present invention is the scope of the claims. Defined only by.
Table 1 shows the specifications of the simulators used for the operation simulation of the circuits of Examples 1 to 8.

表１シミュレータの緒元

Table 1 Origin of the simulator

＜入力演算部＞
以下、多値入力に対して論理演算を加えて多値出力する入力演算部のうち、多値インバータを例にとって、説明する。 <Input calculation unit>
Hereinafter, a multi-value inverter will be described as an example of an input operation unit that performs a multi-value output by applying a logical operation to a multi-value input.

本発明の第１の実施例を図３−Ａに示す。
本実施例はバイアス条件を除けば、ＦＥＴを用いた通常のインバータ回路と同様である。（なお、図中において、3.3/0.5等は、デバイスのＷ／Ｌ比を表す。以下同様である。）
本回路には＋３Ｖと−３Ｖの２種類の直流電圧によるバイアスがかかっている。入力端子301に−３Ｖが印加されると、Ｐ型ＦＥＴ303が導通し、Ｎ型ＦＥＴ307はオフとなり、出力端子305は＋３Ｖとなる。入力端子に＋３Ｖが印加されると、Ｎ型ＦＥＴ307が導通し、Ｐ型ＦＥＴ303はオフとなり、出力端子305は−３Ｖとなる。そして、入力端子301が０Ｖとなると、Ｐ型ＦＥＴ303及びＮ型ＦＥＴ307の双方が導通し、出力端子305は０Ｖとなる。
この入力と出力の関係を、表２に示す。 A first embodiment of the present invention is shown in FIG.
This embodiment is the same as a normal inverter circuit using FETs except for bias conditions. (In the figure, 3.3 / 0.5 etc. represents the W / L ratio of the device. The same applies hereinafter.)
This circuit is biased by two types of DC voltages, + 3V and -3V. When -3V is applied to the input terminal 301, the P-type FET 303 becomes conductive, the N-type FET 307 is turned off, and the output terminal 305 becomes + 3V. When + 3V is applied to the input terminal, the N-type FET 307 conducts, the P-type FET 303 is turned off, and the output terminal 305 becomes -3V. When the input terminal 301 becomes 0V, both the P-type FET 303 and the N-type FET 307 become conductive, and the output terminal 305 becomes 0V.
Table 2 shows the relationship between this input and output.

表２実施例１における入出力関係

Table 2 Input / output relationships in Example 1

このように、本実施例においては、３値の入力（−１，０，１）に対して、反転出力（１，０，−１）が得られており、３値１入力のインバータが実現できている。
ここで、上述の非特許文献１では、３値動作を実現するために抵抗を用いていたが、本実施例ではＦＥＴのみを使用しているため、回路の集積度も上がり、動作速度も向上できる。
次に本実施例において、横軸を入力電圧、縦軸を出力電圧、とした場合の動作シミュレーションの結果を図３−Ｂに、横軸を入力電圧、縦軸を電流値とした場合の動作シミュレーションの結果を図３−Ｃに示す。 As described above, in this embodiment, an inverted output (1, 0, −1) is obtained for a ternary input (−1, 0, 1), thereby realizing a ternary one input inverter. is made of.
Here, in Non-Patent Document 1 described above, a resistor is used to realize ternary operation. However, since only the FET is used in this embodiment, the degree of circuit integration is increased and the operation speed is also improved. it can.
Next, in this embodiment, the result of operation simulation when the horizontal axis is the input voltage and the vertical axis is the output voltage is shown in FIG. 3-B, the operation when the horizontal axis is the input voltage and the vertical axis is the current value. The result of the simulation is shown in FIG.

ここから理解できるように、本実施例では、出力電圧が０Ｖとなる入力電圧の範囲が狭いことが分かる。また、出力電圧が０Ｖとなるときの電流値が大きい（約５０μＡ）ことが分かる。これらの点を改良した、他の実施例については後に説明を加える。
なお、ｍ個の単位回路を接続した、前記発明１に対応する回路図を図４に示す。ここで、401、403および405が正極性の電源端子に、407、409および411が負極性の電源端子に、相当する。 As can be understood from this, in this embodiment, it is understood that the range of the input voltage where the output voltage is 0 V is narrow. It can also be seen that the current value when the output voltage is 0 V is large (about 50 μA). Other embodiments in which these points are improved will be described later.
FIG. 4 shows a circuit diagram corresponding to the invention 1 in which m unit circuits are connected. Here, 401, 403, and 405 correspond to positive power terminals, and 407, 409, and 411 correspond to negative power terminals.

次に、本実施例を拡張して、多入力の３値インバータを実現した実施例２を、図５を用いて説明する。
本実施例では、上述の実施例１で用いた回路（単位回路）を３個（501、503、505）使用している。この３個の単位回路の出力を共通の出力端子（507）に接続し、各単位回路の入力（それぞれ、509、511、513）にそれぞれＶin１，Ｖin２，Ｖin３なる電圧を加える。
このように構成すると、上述の実施例１の回路動作から理解できるように、表３のOut１のような論理動作が実現できる。 Next, a second embodiment in which this embodiment is expanded to realize a multi-input three-value inverter will be described with reference to FIG.
In this embodiment, three circuits (unit circuits) (501, 503, 505) used in the first embodiment are used. The outputs of the three unit circuits are connected to a common output terminal (507), and voltages Vin1, Vin2, and Vin3 are applied to the inputs (509, 511, and 513, respectively) of each unit circuit.
With this configuration, as can be understood from the circuit operation of the first embodiment, a logical operation such as Out1 in Table 3 can be realized.

表３実施例２における入出力関係

Table 3 Input / output relationships in Example 2

この表で、Out１は入力部のみの出力値、Out２は入力部＋出力部（インバータ型）の出力部である。
この場合の利点・問題点も上述の実施例１と同様である。
なお、２値のＡＮＤゲートとＯＲゲートをこのゲートで実現できる。ただし、本ゲートの出力(表3のOut2)“−１”を“0”と同等とみなす必要がある。以下にその場合の真理値表を表４に、実現回路を図６に示す。この場合、２値ＮＯＴゲートを追加使用する。Ｘ1を制御信号としてＸ1=−１の時はＡＮＤとＮＡＮＤの出力を、制御信号を０とした時はＯＲとＮＯＲを出力する回路となっている。
なお、図６中で、出力部（正規化回路）とは図３−Ａ、図７−Ｂ、図１０−Ａのいずれかである。

表４２値のAND（NAND）およびOR(NOR)回路実現における入出力関係

In this table, Out1 is an output value of only the input unit, and Out2 is an output unit of the input unit + output unit (inverter type).
Advantages and problems in this case are the same as those in the first embodiment.
A binary AND gate and an OR gate can be realized by this gate. However, the output of this gate (Out2 in Table 3) “−1” needs to be regarded as equivalent to “0”. The truth table in that case is shown in Table 4, and the realization circuit is shown in FIG. In this case, a binary NOT gate is additionally used. When X1 is a control signal and X1 = -1, the output of AND and NAND is output. When the control signal is set to 0, OR and NOR are output.
In FIG. 6, the output unit (normalization circuit) is any one of FIG. 3-A, FIG. 7-B, and FIG. 10-A.

Table 4 Input / output relations in the realization of binary AND (NAND) and OR (NOR) circuits

このように、本発明の３値３入力の実施例を用いれば、３入力のうちの第１入力を制御ラインとして利用することによって、第２入力と第３入力が２値（０，１）のときのＡＮＤ、ＯＲ、ＮＡＮＤ、ＮＯＲ、の２値出力を出力可能な回路が、容易に実現可能となる。
本発明は、このような点でもメリットを持つ。 As described above, according to the ternary three-input embodiment of the present invention, the second input and the third input are binary (0, 1) by using the first input of the three inputs as a control line. In this case, a circuit that can output a binary output of AND, OR, NAND, and NOR can be easily realized.
The present invention also has an advantage in this respect.

次に「出力電圧が０Ｖとなる入力電圧の範囲が狭い」という実施例１および２の問題点を解決することを目的とした実施例３を、図７−Ａ、図７−Ｂ、図７−Ｃ及び図８を用いて説明する。
図７−Ａ（ＦＥＴの替わりに抵抗を用いた回路）のような回路によれば、挿入抵抗によって入力電圧と出力電圧の関係が、図７−Ｃに示すように緩やかとなり、その結果の出力電圧が０Ｖとなるポイントが実施例１に比して広がる。この抵抗をＦＥＴに置換したのが、図７−Ｂである。抵抗の替わりにＦＥＴを用いることで、回路規模が小さくでき、動作速度も向上する。 Next, Example 3 aimed at solving the problem of Examples 1 and 2 that “the input voltage range where the output voltage is 0 V is narrow” is shown in FIGS. 7-A, 7 -B, 7. This will be described with reference to -C and FIG.
According to a circuit such as FIG. 7-A (a circuit using a resistor instead of an FET), the relationship between the input voltage and the output voltage becomes gentle as shown in FIG. The point at which the voltage becomes 0 V is wider than that in the first embodiment. FIG. 7B shows that this resistor is replaced with an FET. By using FETs instead of resistors, the circuit scale can be reduced and the operation speed can be improved.

本実施例の回路を３個用いた、３値３入力インバータ回路を実施例４として図８に示す。論理動作は上記表３のOut１と同様である。
なお、ｍ個の単位回路を接続した、前記発明２に対応する回路図を図９に示す。ここで、901、903および905が正極性の電源端子に、907、909および911が負極性の電源端子に、相当する。 A ternary three-input inverter circuit using three circuits of this embodiment is shown in FIG. The logical operation is the same as Out1 in Table 3 above.
FIG. 9 shows a circuit diagram corresponding to Invention 2 in which m unit circuits are connected. Here, 901, 903, and 905 correspond to positive power terminals, and 907, 909, and 911 correspond to negative power terminals.

次に、「出力電圧が０Ｖとなるときの電流値が大きい」という問題点の解決を目指した回路が、次に図１０−Ａ、１０−Ｂ、１０−Ｃを用いて説明する実施例５である。
本実施例によれば、カレントミラー回路を用いることによって、論理回路部分に流れる電流値を強制的に制御することによって、出力電圧が０Ｖとなるときの電流値を小さくすることが可能である。 Next, a circuit that aims to solve the problem that “the current value when the output voltage becomes 0 V is large” will be described with reference to FIGS. 10-A, 10-B, and 10-C. It is.
According to this embodiment, by using the current mirror circuit, the current value when the output voltage becomes 0 V can be reduced by forcibly controlling the current value flowing through the logic circuit portion.

本実施例において、横軸を入力電圧、縦軸を出力電圧、とした場合の動作シミュレーションの結果を図１０−Ｂに、横軸を入力電圧、縦軸を電流値とした場合の動作シミュレーションの結果を図１０−Ｃに示す。
ここから理解できるように、本実施例では、実施例１における図３−Ｂ及び図３−Ｃと比較して、出力電圧が０Ｖとなる入力電圧の範囲が広く、出力電圧が０Ｖとなるときの電流値が小さい（約5.0μＡ）ことが分かる。 In this embodiment, the result of the operation simulation when the horizontal axis is the input voltage and the vertical axis is the output voltage is shown in FIG. 10-B, and the operation simulation when the horizontal axis is the input voltage and the vertical axis is the current value. The results are shown in Fig. 10-C.
As can be understood from this, in this embodiment, the input voltage range in which the output voltage is 0 V is wider and the output voltage is 0 V, as compared with FIGS. It can be seen that the current value is small (about 5.0 μA).

本実施例の回路を３個用いた、３値３入力インバータ回路を実施例６として図１１に示す。論理動作は上記表３のOut１と同様である。
なお、ｍ個の単位回路を接続した、前記発明３に対応する回路図を図１２に示す。ここで、1201、1203、1205、1207、および1209が正極性の電源端子に、1211、1213、1215、1217、および1219が負極性の電源端子に、相当する。 FIG. 11 shows a ternary three-input inverter circuit using three circuits of this embodiment as a sixth embodiment. The logical operation is the same as Out1 in Table 3 above.
FIG. 12 shows a circuit diagram corresponding to Invention 3 in which m unit circuits are connected. Here, 1201, 1203, 1205, 1207, and 1209 correspond to positive power supply terminals, and 1211, 1213, 1215, 1217, and 1219 correspond to negative power supply terminals.

＜出力正規化回路＞
次に、上述のような入力演算部の後段に接続して、入力演算部の出力の「ずれ」を補正する、出力正規化回路について説明する。
基本的に、出力正規化回路は上述の「入力演算部」と同一である。
即ち、上述の実施例１（図３−Ａ）、実施例２（図５）、実施例３（図７−Ｂ）、実施例４（図８）、実施例５（図１０−Ａ）、実施例６（図１１）の各回路の出力端子に、上述の実施例１（図３−Ａ）、実施例３（図７−Ｂ）、実施例５（図１０−Ａ）のいずれかを（出力正規化回路として）接続することによって、入力演算部の特性の「ずれ」が補正される。 <Output normalization circuit>
Next, an output normalization circuit that is connected to the subsequent stage of the input calculation unit as described above and corrects the “deviation” of the output of the input calculation unit will be described.
Basically, the output normalization circuit is the same as the “input operation unit” described above.
That is, Example 1 (FIG. 3-A), Example 2 (FIG. 5), Example 3 (FIG. 7-B), Example 4 (FIG. 8), Example 5 (FIG. 10-A), The output terminal of each circuit of the sixth embodiment (FIG. 11) is connected to any one of the first embodiment (FIG. 3-A), the third embodiment (FIG. 7-B), or the fifth embodiment (FIG. 10-A). By connecting (as an output normalization circuit), the “deviation” of the characteristics of the input arithmetic unit is corrected.

実施例１（単なるインバータ）を「正規化」回路として使用するメリットを、説明する。
一般論として、論理回路を複数個接続していく場合、各論理回路の出力が理想的な値（３ｖ，０ｖ，−３ｖ）であるとは限らず、ＦＥＴのばらつきや複数配線することによるインピーダンスの低下などにより、論理回路の出力が理想的な値（３ｖ，０ｖ，−３ｖ）でなくなる事がある。また、大きく値がずれた場合には誤動作を生じさせる。特に、本特許の回路においては電圧信号によるワイヤードＯＲを用いている。このまま次の複数の論理回路に接続すると更にワイヤードＯＲが発生し、論理回路としての働きが失われてしまう。これらを避けるため（ワイヤードＯＲ回路を終了させるため）インバータを入れている。本来なら、バッファー回路を使いたいところであるが、バッファー回路にするとＦＥＴの数が一般にインバータの場合の倍の数となり、集積回路化に有利でない。また、単に信号のインバータとして動作させる機能も持たすことができこの方が有利である。 Advantages of using the first embodiment (simple inverter) as a “normalization” circuit will be described.
In general, when a plurality of logic circuits are connected, the output of each logic circuit is not necessarily an ideal value (3v, 0v, -3v). The output of the logic circuit may not be an ideal value (3v, 0v, -3v) due to a decrease in the output. In addition, if the value is greatly deviated, a malfunction occurs. In particular, the circuit of this patent uses a wired OR based on a voltage signal. If it is connected to the next plurality of logic circuits as it is, a wired OR is further generated and the function as the logic circuit is lost. In order to avoid these (in order to terminate the wired OR circuit), an inverter is included. Originally, it would be desirable to use a buffer circuit. However, if the buffer circuit is used, the number of FETs is generally twice that of an inverter, which is not advantageous for integration. In addition, it is possible to provide a function of simply operating as an inverter of a signal, which is advantageous.

オリジナルの回路の入力部の特性は、例えば図３−Ｂのようになる。この場合、入力０ｖ近辺に対して、０ｖを出力する範囲が非常に狭くなる。これを広くする為に出力正規化回路をつける。これによって、出力が０Ｖから多少ずれても、それを補正して０Ｖを出力することが可能となる。
「ずれ」が補正される理由を、図１３および１４を用いて説明する。
今仮に、多値インバータ回路の入出力電圧伝達特性が「特性１」（図１３）のようなものであったと仮定する。このとき、入力電圧０ｖに対し出力電圧は０ｖとなり「ずれ」は生じない（1301）。しかし、入力部のＦＥＴのばらつきなどによって入力電圧が0ｖから１ｖに「ずれ」が生じているとする（1303）。この場合には出力は−１ｖとなり、次々と「ずれ」が増大する可能性がある。これを避けるため、図７−Ｂや図１０−Ａの回路を、シリーズに出力に接続することを考える。これらの回路の入出力電圧伝達特性が理想的で「特性２」（図１４）であったと仮定する。 The characteristic of the input part of the original circuit is, for example, as shown in FIG. In this case, the range for outputting 0 v is very narrow with respect to the vicinity of the input 0 v. In order to widen this, an output normalization circuit is attached. As a result, even if the output is slightly deviated from 0V, it can be corrected to output 0V.
The reason why the “deviation” is corrected will be described with reference to FIGS.
Assume that the input / output voltage transfer characteristic of the multi-value inverter circuit is like "Characteristic 1" (FIG. 13). At this time, the output voltage becomes 0 v with respect to the input voltage 0 v, and no “deviation” occurs (1301). However, it is assumed that the input voltage has a “deviation” from 0v to 1v due to variations in the FETs of the input section (1303). In this case, the output becomes −1v, and “shift” may increase one after another. To avoid this, consider connecting the circuit of FIG. 7-B or FIG. 10-A to the output in series. Assume that the input / output voltage transfer characteristics of these circuits are ideal and are "Characteristic 2" (FIG. 14).

この回路の入力が前と同様に１ｖであったとすると、「特性２」（図１４）の電圧伝達特性より出力は０ｖとなり正規化(補正)される。「特性２」のような理想的な場合には
−３ｖ＜入力＜ −1.5ｖならば出力＝＋3ｖ
−1.5ｖ＜入力＜ +1.5ｖならば出力＝ 0ｖ
＋1.5ｖ＜入力＜ +3ｖならば出力＝−3ｖ
（式３）
となり、0ｖ近辺でのノイズマージンは±1.5ｖすなわち3ｖの幅となる。
このように、上記実施例１（図３−Ａ）、実施例３（図７-Ｂ）、実施例５（図１０−Ａ）が正規化回路として採用できる。 Assuming that the input of this circuit is 1v as before, the output is 0v and normalized (corrected) from the voltage transfer characteristic of “Characteristic 2” (FIG. 14). In an ideal case such as “Characteristic 2”, if −3v <input <−1.5v, output = + 3v
If -1.5v <input <+ 1.5v, output = 0v
If + 1.5v <input <+ 3v then output = -3v
(Formula 3)
Thus, the noise margin in the vicinity of 0v is ± 1.5v, that is, a width of 3v.
As described above, the first embodiment (FIG. 3-A), the third embodiment (FIG. 7-B), and the fifth embodiment (FIG. 10-A) can be employed as the normalization circuit.

ここで、実施例１（図３−Ａ）を正規化回路として採用した場合には、０Ｖ出力に対応する入力レンジが狭いこと、及び消費電力が大きい、という問題が存在し、実施例３（図７-Ｂ）を正規化回路として採用した場合には、入力レンジが拡大されるが、電流が大きいという問題が存在し、実施例５（図１０−Ａ）正規化回路として採用した場合には、入力レンジが拡大でき、かつ、電流を制御できる、という特徴をそれぞれ持つ点は、上記入力演算回路の場合と同様である。
なお、入力演算部の出力に正規化回路を接続すると、インバータの２重接続となって、全体としての回路動作はバッファとなる。 Here, when Example 1 (FIG. 3-A) is adopted as a normalization circuit, there are problems that the input range corresponding to 0 V output is narrow and power consumption is large. When FIG. 7-B) is adopted as a normalization circuit, the input range is expanded, but there is a problem that the current is large, and when the normalization circuit is employed in Example 5 (FIG. 10-A). Are the same as those in the case of the above input arithmetic circuit in that the input range can be expanded and the current can be controlled.
When a normalization circuit is connected to the output of the input arithmetic unit, a double connection of inverters is provided, and the circuit operation as a whole becomes a buffer.

ここで、ｍ個の単位回路を備える第１の出力端子に接続された、前記発明７に対応する正規化回路図を図１５に、前記発明８に対応する正規化回路図を図１６に、前記発明９に対応する正規化回路図を図１７に示す。 Here, FIG. 15 shows a normalization circuit diagram corresponding to the invention 7 and FIG. 16 shows a normalization circuit diagram corresponding to the invention 8, which are connected to a first output terminal having m unit circuits. A normalization circuit diagram corresponding to the ninth aspect is shown in FIG.

次に、実施例７として、実施例１，３，５以外の出力正規化回路について説明する。
図１８−Ａ〜Ｃを参照頂きたい。
図１８−Ａで、Ｐ型ＦＥＴ1801とＮ型ＦＥＴ1802からなるインバータ（第1のインバータ）による動作特性は、図１８−Ｂの右側の線で示され、Ｐ型ＦＥＴ1803とＮ型ＦＥＴ1804からなるインバータ（第２のインバータ）による動作特性は、図１８−Ｂの左側の線で示される。 Next, as Embodiment 7, output normalization circuits other than Embodiments 1, 3, and 5 will be described.
Please refer to FIGS.
In FIG. 18-A, the operating characteristics of the inverter (first inverter) composed of P-type FET 1801 and N-type FET 1802 are indicated by the right line in FIG. 18-B, and the inverter composed of P-type FET 1803 and N-type FET 1804 ( The operating characteristics of the second inverter) are indicated by the left line in FIG.

これらの特性を単純に加算すれば、図１８−Ｃに示す特性が得られるが、本実施例では、両特性の加算のために出力段にＰ型ＦＥＴ1807及びＮ型ＦＥＴ1808からなるインバータ（第３のインバータ）を用い、この第3のインバータのＰ型ＦＥＴ1807を上記第1のインバータで駆動し、Ｎ型ＦＥＴ1808を上記第２のインバータで駆動している。
ただ、このように接続すると、インバータの２重接続となり、全体としての論理動作はバッファとなってしまうので、全体としてもインバータとして動作させるために、インバータ1805及び1806を両者の間に接続している。 If these characteristics are simply added, the characteristics shown in FIG. 18-C can be obtained. In this embodiment, an inverter (the third type consisting of P-type FET 1807 and N-type FET 1808 in the output stage) is added to add both characteristics. The third inverter P-type FET 1807 is driven by the first inverter, and the N-type FET 1808 is driven by the second inverter.
However, this connection results in a double connection of inverters, and the logical operation as a whole becomes a buffer. Therefore, in order to operate as an inverter as a whole, inverters 1805 and 1806 are connected between them. Yes.

以上のように構成すると、その入出力電圧伝達特性は図１８−Ｃのようになり、理想的な論理閾値調整が可能となる。
即ち、入力演算回路の入出力電圧伝達特性が多少ずれていても、その「ずれ」が図１８−Ｃの階段部分の範囲内にあれば、出力は正しく出力されるのである。つまり、入力演算部と組合せることによって、全体としての入力レンジが大きく拡大できるし、その結果、出力レベルのフラット化も図れる。 With the above configuration, the input / output voltage transfer characteristics are as shown in FIG. 18-C, and ideal logic threshold adjustment is possible.
That is, even if the input / output voltage transfer characteristics of the input arithmetic circuit are slightly deviated, if the “deviation” is within the range of the staircase portion of FIG. 18-C, the output is correctly output. That is, by combining with the input calculation unit, the overall input range can be greatly expanded, and as a result, the output level can be flattened.

但し、図１５、図１６、図１７、と比較すれば分かるように、回路規模は大きくなる。また、消費電流も大きくなる。
消費電流が大きくなる理由は、以下のとおりである。
つまり、入力０Ｖのとき、出力０Ｖを得るため、Ｐ型ＦＥＴ1807とＮ型ＦＥＴ1808は共にＯＮとなり、−3Ｖと+3Ｖの合成によって０ｖを出力している。すなわち、Ｐ型ＦＥＴ、Ｎ型ＦＥＴ共にＯＮとなることにより、＋電極からＰ型ＦＥＴ1807（ＯＮ状態）を経由して、Ｎ型ＦＥＴ1808（ＯＮ状態）を通り−電極へ大きな電流が流れる。 However, as can be seen from comparison with FIGS. 15, 16, and 17, the circuit scale increases. In addition, current consumption increases.
The reason why the current consumption increases is as follows.
In other words, when the input is 0V, the P-type FET 1807 and the N-type FET 1808 are both turned ON to obtain 0V, and 0V is output by the combination of −3V and + 3V. That is, when both the P-type FET and the N-type FET are turned on, a large current flows from the + electrode through the P-type FET 1807 (ON state) through the N-type FET 1808 (ON state) to the negative electrode.

図１８−Ａで、Ｐ型ＦＥＴ1801とＮ型ＦＥＴ1802からなるインバータ（第1のインバータ）による動作特性は、図１８−Ｂの左側の線で示され、Ｐ型ＦＥＴ1803とＮ型ＦＥＴ1804からなるインバータ（第２のインバータ）による動作特性は、図１８−Ｂの右側の線で示される。
参考として、実施例４（図８）の３値３入力の回路の出力に、実施例７（図１８−Ａ）を出力正規化回路として接続した場合の回路図を図１９−Ａに、その回路動作のシミュレーション結果を図１９−Ｂに示す。上記表３のOut２の論理動作が実現できることが確認できる。
なお、ｍ個の単位回路を備える第１の出力端子に接続された、前記発明１０に対応する正規化回路図を図２０に示す。 In FIG. 18A, the operating characteristics of the inverter (first inverter) composed of the P-type FET 1801 and the N-type FET 1802 are indicated by the left line in FIG. 18-B, and the inverter composed of the P-type FET 1803 and the N-type FET 1804 ( The operating characteristics of the second inverter) are indicated by the right line in FIG.
As a reference, FIG. 19A shows a circuit diagram in the case where Example 7 (FIG. 18-A) is connected as an output normalization circuit to the output of the ternary three-input circuit of Example 4 (FIG. 8). A simulation result of the circuit operation is shown in FIG. It can be confirmed that the logic operation of Out2 in Table 3 can be realized.
FIG. 20 shows a normalization circuit diagram corresponding to the tenth aspect of the invention connected to a first output terminal having m unit circuits.

ここで、前記発明１０は図２１のようにモデル化できる。この回路の動作を入出力関係で示した図が図２２−Ａおよび図２２−Ｂである。さらに、この入出力関係をFETの動作状態をもとに示したのが表５−１および表５−２である。 The invention 10 can be modeled as shown in FIG. Figures 22-A and 22-B show the operation of this circuit in terms of input / output. Further, Table 5-1 and Table 5-2 show this input / output relationship based on the operation state of the FET.

図２２−Ａに示した特性は、「前記第１のインバータの論理閾値電圧値が前記正極性の電源電圧値と前記負極性の電源電圧値の中間地より小さく、前記第２のインバータの論理閾値電圧値が前記正極性の電源電圧値と前期負極性の電源電圧値の中間値より大きい」場合の図であり、この場合の動作を示したのが表５−１である。 The characteristic shown in FIG. 22-A is “the logic threshold voltage value of the first inverter is smaller than the intermediate point between the positive power supply voltage value and the negative power supply voltage value, and the logic of the second inverter is The threshold voltage value is greater than the intermediate value between the positive power supply voltage value and the previous negative power supply voltage value. The operation in this case is shown in Table 5-1.

一方、図２２−Ｂに示した特性は、「前記第１のインバータの論理閾値電圧値が前記正極性の電源電圧値と前記負極性の電源電圧値の中間地より大きく、前記第２のインバータの論理閾値電圧値が前記正極性の電源電圧値と前期負極性の電源電圧値の中間値より小さい」場合の図であり、この場合の動作を示したのが表５−２である。
このように、したがって、どちらの表現でも同じ機能を達成する。 On the other hand, the characteristic shown in FIG. 22B is that the logic threshold voltage value of the first inverter is larger than the intermediate point between the positive power supply voltage value and the negative power supply voltage value, and the second inverter The logic threshold voltage value is less than the intermediate value between the positive power supply voltage value and the negative power supply voltage value. The operation in this case is shown in Table 5-2.
Thus, both representations accomplish the same function.

ただし、論理演算の機能としては同じであるが、消費電力の点において大きな違いがある。すなわち、領域βにおいて、下記表５−２に示してあるような論理閾値電圧の場合はＡ、ＢのＦＥＴ共にＯＦＦとなり、電流が流れない。しかし、下記表５−１の場合はＡ、ＢのＦＥＴ共にＯＮとなり電流が流れ、消費電流増加につながる。 However, although the functions of the logical operation are the same, there are significant differences in terms of power consumption. That is, in the region β, in the case of the logical threshold voltage as shown in the following Table 5-2, both the A and B FETs are turned off and no current flows. However, in the case of Table 5-1 below, both the A and B FETs are turned on and current flows, leading to an increase in current consumption.

表５−１動作を示した表（その１）

ただし、L：Low、H：High、M：Middle（０ｖ）を表す。

Table 5-1 Table showing operation (Part 1)

However, L: Low, H: High, M: Middle (0v) are represented.

表５−２動作を示した表（その２）

ただし、L：Low、H：High、M：Middle（０ｖ）を表す。 Table 5-2 Operation table (2)

However, L: Low, H: High, M: Middle (0v) are represented.

更に、ｍ個の単位回路を備える第１の出力端子に接続された、前記発明１１に対応する正規化回路図を図２３に示す。ここで、第（２ｍ＋５）のＮ型ＦＥＴおよび第（２ｍ＋６）のＮ型ＦＥＴからなる回路は、回路中の、第（２ｍ＋４）のＰ型ＦＥＴおよび第（２ｍ＋４）のＮ型ＦＥＴが共にＯＦＦとなったとき、第２の出力端子が電圧的に「浮いた」状態になるのを防ぎ、回路動作を安定化させる目的を持つ。また、これ以外の時にはこれらのＦＥＴ（第（２ｍ＋５）のＮ型ＦＥＴと第（２ｍ＋６）のＮ型ＦＥＴ）は無くても良いので第（２ｍ＋４）の接点および第（２ｍ＋５）の接点からの信号によっていずれか一方あるいは共にＯＦＦとし第2の出力端子から切り離すことによってここへ流れる電流を遮断している。
また、ｍ個の単位回路を備える第１の出力端子に接続された、前記発明１２に対応する正規化回路図を図２４に示す。 Further, FIG. 23 shows a normalization circuit diagram corresponding to the eleventh aspect of the present invention, which is connected to a first output terminal having m unit circuits. Here, in the circuit composed of the (2m + 5) th N-type FET and the (2m + 6) th N-type FET, both the (2m + 4) th P-type FET and the (2m + 4) th N-type FET are OFF. In this case, the second output terminal is prevented from being in a “floating” state in terms of voltage, and has the purpose of stabilizing the circuit operation. At other times, these FETs ((2m + 5) N-type FET and (2m + 6) N-type FET) may be omitted, so that signals from the (2m + 4) contact and the (2m + 5) contact are provided. Thus, either or both of them are turned OFF and disconnected from the second output terminal to cut off the current flowing therethrough.
FIG. 24 shows a normalization circuit diagram corresponding to the invention 12 connected to a first output terminal including m unit circuits.

＜バッファタイプの演算回路＞ <Buffer type arithmetic circuit>

次に、実施例８として、インバータではなく、バッファタイプの入力演算部を示す。
図２５−Ａを参照頂きたい。本実施例では、Ｐ型ＦＥＴ2501とＮ型ＦＥＴ2502からなる第１のインバータ（2510）と、Ｐ型ＦＥＴ2503とＮ型ＦＥＴ2504からなる第２のインバータ（2520）の論理閾値を調整してある。（なお、Ｎ型ＦＥＴ2507およびＮ型ＦＥＴ2508からなる回路は、Ｐ型ＦＥＴ2505とＮ型ＦＥＴ2506が共にＯＦＦとなったとき、出力端子2516が電気的に「浮いた」状態になるのを防ぎ、Ｎ型ＦＥＴ2507およびＮ型ＦＥＴ2508は共にＯＮとなり、出力端子2516をゼロ電位に接地し、出力電圧を安定化させる目的をもつ。また、これ以外の時にはこれらのＦＥＴ（2507、2508）は無くても良いので接点2512および2518からの信号によっていずれか一方あるいは共にＯＦＦとし出力端子2516から切り離すことによってここへ流れる電流を遮断している。 Next, as an eighth embodiment, not a inverter but a buffer type input calculation unit is shown.
Please refer to FIG. 25-A. In this embodiment, the logic threshold values of the first inverter (2510) composed of the P-type FET 2501 and the N-type FET 2502 and the second inverter (2520) composed of the P-type FET 2503 and the N-type FET 2504 are adjusted. (Note that the circuit composed of the N-type FET 2507 and the N-type FET 2508 prevents the output terminal 2516 from becoming electrically “floating” when both the P-type FET 2505 and the N-type FET 2506 are turned off. Both FET2507 and N-type FET2508 are turned on, with the purpose of stabilizing the output voltage by grounding the output terminal 2516 to zero potential, and at other times these FETs (2507, 2508) may be omitted. Either one or both of them are turned off by a signal from the contacts 2512 and 2518 and disconnected from the output terminal 2516 to cut off the current flowing therethrough.

入力電圧＝０Ｖのとき（図２５−Ｂ）に、第１のインバータのＰ型ＦＥＴ2501はＯＮ（導通状態）、Ｎ型ＦＥＴ2502はＯＦＦ（非導通状態）となり出力電圧＝３Ｖ、となる。一方、第２のインバータのＰ型ＦＥＴ2503はＯＦＦ（非導通状態）、Ｎ型ＦＥＴ2504はＯＮ（導通状態）となり、各部の電圧は同図に示すようになり、その結果、出力電圧＝０Ｖとなるように調整されている。 When the input voltage = 0V (FIG. 25B), the P-type FET 2501 of the first inverter is ON (conductive state), the N-type FET 2502 is OFF (non-conductive state), and the output voltage is 3V. On the other hand, the P-type FET 2503 of the second inverter is OFF (non-conducting state), the N-type FET 2504 is ON (conducting state), and the voltage of each part is as shown in the figure, and as a result, the output voltage = 0V. Have been adjusted so that.

入力電圧＝−３Ｖのとき（図２５−Ｃ）は、第１のインバータのＰ型ＦＥＴ2501はＯＮ、Ｎ型ＦＥＴ2502はＯＦＦとなり、出力電圧＝３Ｖ、となる。一方、第２のインバータのＰ型ＦＥＴ2503はＯＮ、Ｎ型ＦＥＴ2504はＯＦＦとなり、各部の電圧は同図に示すようになり、その結果、出力電圧＝−３Ｖである。 When the input voltage is −3 V (FIG. 25C), the P-type FET 2501 of the first inverter is ON, the N-type FET 2502 is OFF, and the output voltage is 3 V. On the other hand, the P-type FET 2503 of the second inverter is turned on and the N-type FET 2504 is turned off, and the voltages of the respective parts are as shown in the figure. As a result, the output voltage is −3V.

また、入力電圧＝３Ｖのとき（図２５−Ｄ）は、第１のインバータのＰ型ＦＥＴ2501はＯＦＦ、Ｎ型ＦＥＴ2502はＯＮとなり、出力電圧＝−３Ｖ、となる。一方、第２のインバータのＰ型ＦＥＴ2503はＯＦＦ、Ｎ型ＦＥＴ2504はＯＮとなり、各部の電圧は同図に示すようになり、その結果、出力電圧＝３Ｖである。 When the input voltage is 3 V (FIG. 25D), the P-type FET 2501 of the first inverter is OFF, the N-type FET 2502 is ON, and the output voltage is −3 V. On the other hand, the P-type FET 2503 of the second inverter is turned off and the N-type FET 2504 is turned on, and the voltages of the respective parts are as shown in the figure. As a result, the output voltage is 3V.

このように構成すると、入出力電圧伝達特性は図２５−Ｅのようになる（シミュレーション結果）。入力レンジが広いことが分かる。 With this configuration, the input / output voltage transfer characteristics are as shown in FIG. 25-E (simulation results). You can see that the input range is wide.

また、実施例１（図３−Ａ）や実施例３（図７−Ｂ）による正規化回路の場合に、入力電圧＝０Ｖのときに、インバータに電流が流れてしまうのとは対照的に、本実施例８（図２５−Ａ）では入力電圧＝０Ｖのときにも、第１のインバータ（2510）及び第２のインバータ（2520）は、それぞれ内部のＰ型ＦＥＴおよびＮ型ＦＥＴが完全にＯＦＦ（非導通）、または、ＯＮ（導通）となるため、電流値が小さくなる。電流が流れるのは図２５−Ｆ、Ｇのように入力電圧が−３Ｖと０Ｖとの間、及び０Ｖと３Ｖとの間を変化する際のみである。 Further, in the case of the normalization circuit according to the first embodiment (FIG. 3-A) or the third embodiment (FIG. 7-B), in contrast to the current flowing through the inverter when the input voltage = 0V. In the eighth embodiment (FIG. 25-A), even when the input voltage is 0 V, the first inverter (2510) and the second inverter (2520) are completely composed of the internal P-type FET and the N-type FET, respectively. Since the current value is OFF (non-conducting) or ON (conducting), the current value is small. The current flows only when the input voltage changes between -3V and 0V and between 0V and 3V as shown in FIGS.

ここで、図２５−Ａ乃至図２５−ＤにおけるＦＥＴ2507及び2508は、回路動作を安定化するために用いられるものであり、節点2512が＋３Ｖで2514が−３Ｖのときに、共にオン状態となって、出力端子2516をゼロ電位に接地し、それ以外の場合には、いずれか一方、または両方のＦＥＴが、オフ状態となって、出力端子2516を接地電位から開放するものである。 Here, the FETs 2507 and 2508 in FIGS. 25-A to 25-D are used to stabilize the circuit operation, and both are turned on when the node 2512 is + 3V and 2514 is −3V. Thus, the output terminal 2516 is grounded to zero potential, and in other cases, one or both FETs are turned off to release the output terminal 2516 from the ground potential.

この実施例８は、実施例１〜６までの回路を入力演算回路とし、その出力に接続して正規化回路とすることも可能であるし、これ自体独立して、正規化回路不用の入力演算回路とすることも可能である。 In the eighth embodiment, the circuits of the first to sixth embodiments can be used as an input arithmetic circuit, and can be connected to the output to be a normalization circuit. An arithmetic circuit can also be used.

また、実施例８の回路（図２５−Ａ）のうち、Ｎ型ＦＥＴ（2507、2508）を除いた回路（（ａ）部分）の出力を３個ワイヤド・オア接続した回路を図２６−Ａの（ｂ）に、当該回路の動作特性のシミュレーション結果を図２６−Ｂに示す。図２６−Ｂから、上述の表２に示した、３値３入力の場合の論理動作が実現することが確認できる。（図２６−Ａの右下の、ＦＥＴを上下方向に直列接続した回路は、図２６−Ａの右側の３つの回路の出力段のＰ型ＦＥＴおよびＮ型ＦＥＴが共にＯＦＦとなるとき、回路中の出力の節点が電圧的に「浮いた」状態になるのを防ぎ、回路動作を安定化させる目的を持つ。 Further, in the circuit of the eighth embodiment (FIG. 25A), a circuit in which three outputs (part (a)) excluding the N-type FETs (2507, 2508) are wired or connected is shown in FIG. FIG. 26B shows the simulation result of the operating characteristics of the circuit. From FIG. 26-B, it can be confirmed that the logical operation in the case of ternary three-input shown in Table 2 above is realized. (The circuit in the lower right of FIG. 26-A, in which the FETs are connected in series in the vertical direction, is the circuit when both the P-type FET and N-type FET of the output stage of the three circuits on the right side of FIG. The purpose is to prevent the output node from becoming "floating" in terms of voltage and to stabilize the circuit operation.

なお、ｍ個の単位回路を備える第１の出力端子に接続された、前記発明１４に対応する正規化回路図を図２７に示す。同図は、基本となる回路（（ａ）部分）を（ｂ）のように表現し、その（ｂ）の回路を（ｃ）に示すように複数個用意し、それらの３個ずつの出力をそれぞれ、（ｃ）のように接続したものである。（同図（ｃ）部分右下の、ＦＥＴを上下方向に直列接続した回路も、回路中の節点が電圧的に「浮いた」状態になるのを防ぎ、回路動作を安定化させる目的を持つ。） FIG. 27 shows a normalization circuit diagram corresponding to the fourteenth aspect of the present invention, which is connected to a first output terminal having m unit circuits. In this figure, the basic circuit (part (a)) is expressed as shown in (b), and a plurality of the circuits shown in (b) are prepared as shown in (c). Are respectively connected as shown in (c). (The circuit in the lower right part of the figure (c), in which FETs are connected in series in the vertical direction, also has the purpose of preventing the nodes in the circuit from becoming “floating” in terms of voltage and stabilizing the circuit operation. .)

前記発明１４の記載の最終部分において、「（１）前記第（５ｊ−４）のインバータの論理閾値電圧値が前記正極性の電源電圧値と前記負極性の電源電圧値の中間値より小さく、前記第（５ｊ−３）のインバータの論理閾値電圧値が前記正極性の電源電圧値と前記負極性の電源電圧値の中間値より大きい、または、（２）前記第（５ｊ−４）のインバータの論理閾値電圧値が前記正極性の電源電圧値と前記負極性の電源電圧値の中間値より大きく、前記第（５ｊ−３）のインバータの論理閾値電圧値が前記正極性の電源電圧値と前記負極性の電源電圧値の中間値より小さい」との記載が存在するが、このように、論理閾値を変更しても同じ動作となる理由を述べる。 In the final part of the description of the invention 14, the logic threshold voltage value of (1) the (5j-4) th inverter is smaller than an intermediate value between the positive power supply voltage value and the negative power supply voltage value, The logic threshold voltage value of the (5j-3) th inverter is greater than the intermediate value between the positive power supply voltage value and the negative power supply voltage value, or (2) the (5j-4) th inverter. Is greater than an intermediate value between the positive power supply voltage value and the negative power supply voltage value, and the logical threshold voltage value of the (5j-3) th inverter is the positive power supply voltage value. Although there is a description that it is smaller than the intermediate value of the negative power supply voltage value, the reason why the same operation is achieved even if the logic threshold is changed will be described.

ここで、前記発明１４は図２８のようにモデル化できる。この回路の動作を入出力関係で示した図が図２９−Ａおよび図２９−Ｂである。さらに、この入出力関係をＦＥＴの動作状態をもとに示したのが表６−１および表６−２である。 The invention 14 can be modeled as shown in FIG. Figures 29-A and 29-B show the operation of this circuit in terms of input / output. Further, Table 6-1 and Table 6-2 show this input / output relationship based on the operating state of the FET.

図２９−Ａに示した特性は、「（１）前記第（５ｊ−４）のインバータ（図中の曲線１）の論理閾値電圧値が前記正極性の電源電圧値と前記負極性の電源電圧値の中間値より小さく、前記第（５ｊ−３）のインバータ（図中の曲線２）の論理閾値電圧値が前記正極性の電源電圧値と前記負極性の電源電圧値の中間値より大きい」場合の図であり、この場合の動作を示したのが表６−１である。 The characteristics shown in FIG. 29-A are: “(1) The logic threshold voltage value of the (5j-4) th inverter (curve 1 in the figure) is the positive power supply voltage value and the negative power supply voltage. The logical threshold voltage value of the (5j-3) th inverter (curve 2 in the figure) is larger than the intermediate value of the positive polarity power supply voltage value and the negative polarity power supply voltage value. Table 6-1 shows the operation in this case.

一方、図２９−Ｂに示した特性は、「（２）前記第（５ｊ−４）のインバータ（図中の曲線１）の論理閾値電圧値が前記正極性の電源電圧値と前記負極性の電源電圧値の中間値より大きく、前記第（５ｊ−３）のインバータ（図中の曲線２）の論理閾値電圧値が前記正極性の電源電圧値と前記負極性の電源電圧値の中間値より小さい」場合の図であり、この場合の動作を示したのが表６−２である。
このように、どちらの表現でも同じ機能を達成する。 On the other hand, the characteristics shown in FIG. 29-B are: (2) The logical threshold voltage value of the (5j-4) th inverter (curve 1 in the figure) is the positive power supply voltage value and the negative polarity. The logic threshold voltage value of the (5j-3) th inverter (curve 2 in the figure) is greater than the intermediate value of the power supply voltage value, and the intermediate value between the positive power supply voltage value and the negative power supply voltage value. FIG. 6-2 shows the operation in this case.
Thus, both expressions achieve the same function.

ただし、論理演算の機能としては同じであるが、消費電力の点において大きな違いがある。すなわち、領域βにおいて、下記表６−２に示してあるような論理閾値電圧の場合はＡ、ＢのＦＥＴ共にＯＦＦとなり、電流が流れない。しかし、下記表６−１の場合はＡ、ＢのＦＥＴ共にＯＮとなり電流が流れ、消費電流増加につながる。 However, although the functions of the logical operation are the same, there are significant differences in terms of power consumption. That is, in the region β, in the case of the logical threshold voltage as shown in Table 6-2 below, both the A and B FETs are turned off and no current flows. However, in the case of Table 6-1 below, both the A and B FETs are turned on and current flows, leading to an increase in current consumption.

表６−１動作を示した表（その１）

ただし、L：Low、H：High、M：Middle（０ｖ）を表す。 Table 6-1 Table showing operation (Part 1)

However, L: Low, H: High, M: Middle (0v) are represented.

表６−２動作を示した表（その２）

ただし、L：Low、H：High、M：Middle（０ｖ）を表す。 Table 6-2 Table showing operation (Part 2)

However, L: Low, H: High, M: Middle (0v) are represented.

＜３値４入力の回路構成及び真理値表＞
以上、３値１入力、及び３値３入力の場合の実施例について説明してきたが、本発明に係る多値論理回路の入力数は３個に限らない。
図４、図８、図１１、において、入力を４個に増やせば３値４入力回路が実現でき、その出力に図１５、図１６、図１７、図１８−Ａ、等の正規化回路を接続すれば、その多値論理動作はより安定する。図２５−Ａの回路を４個用意して、それらの出力を共通の出力端子に接続し、その出力に図１８−Ａの正規化回路を接続してもよい。
さて、このようにして実現された３値４入力論理回路の真理値表を示したのが、以下の表７である。 <Third and four input circuit configuration and truth table>
Although the embodiments in the case of ternary 1 input and ternary 3 input have been described above, the number of inputs of the multilevel logic circuit according to the present invention is not limited to 3.
4, 8, and 11, a ternary four-input circuit can be realized by increasing the number of inputs to four, and a normalization circuit such as FIG. 15, FIG. 16, FIG. 17, or FIG. When connected, the multi-level logic operation becomes more stable. It is also possible to prepare four circuits of FIG. 25-A, connect their outputs to a common output terminal, and connect the normalization circuit of FIG. 18-A to the output.
Table 7 below shows a truth table of the ternary 4-input logic circuit realized in this way.

表７３値４入力論理回路の真理値表

Table 7 Truth table of 3-value 4-input logic circuit

上記表７において、Ｘ１＝Ｘ２＝−１のとき、Ｘ３とＸ４の間に、次の真理値関係をもたらす。
表８

In Table 7, when X1 = X2 = −1, the following truth value relationship is brought about between X3 and X4.
Table 8

同様に、Ｘ１＝−１、Ｘ２＝０のとき、Ｘ３とＸ４の間に、次の真理値関係をもたらす。
表９

Similarly, when X1 = −1 and X2 = 0, the following truth value relation is brought about between X3 and X4.
Table 9

以下同様に、Ｘ１とＸ２を制御信号として捉えると、回路のハードウェア自体は固定したまま、制御信号を変化させることによって、当該回路の論理動作を変更することが可能となる。
本発明における各実施例における３値多入力論理回路は、以上のような効果を持つものである。 Similarly, when X1 and X2 are regarded as control signals, the logic operation of the circuit can be changed by changing the control signal while fixing the hardware of the circuit itself.
The ternary multi-input logic circuit in each embodiment of the present invention has the above effects.

なお、このようなインバータ回路の出力をｍ個ワイヤドＯＲした、３値ｍ入力の回路の入出力関係を一般式で表現すると以下のようになる。

ｍ入力の場合の一般式は、
で表現できる。 It should be noted that the input / output relationship of a ternary m-input circuit in which m outputs of such inverter circuits are wired OR is expressed as follows.

The general formula for m inputs is
Can be expressed as

＜その他の多値論理回路の例＞
以下、上記の各実施例以外の他の論理回路（インバータタイプの演算回路）の例を示す。
なお、これらの出力に、上記実施例１（図３−Ａ）、実施例３（図７−Ｂ）、実施例５（図１０−Ａ）、および、実施例７（図１８−Ａ）のような、正規化回路を接続することによっても、やはり、その動作が安定化する。 <Examples of other multi-value logic circuits>
Hereinafter, examples of other logic circuits (inverter type arithmetic circuits) other than the above-described embodiments will be described.
In addition, the output of Example 1 (FIG. 3-A), Example 3 (FIG. 7-B), Example 5 (FIG. 10-A), and Example 7 (FIG. 18-A) is included in these outputs. By connecting the normalization circuit as described above, the operation is also stabilized.

本実施例における回路図を図３０−Ａに示す。
この回路は上述の実施例１（図３−Ａ）のそれと類似するが、実施例１において上段のＰ型ＦＥＴの入力と、下段のＮ型ＦＥＴの入力が共通に接続（301）され、同じ入力信号が加えられているのに対し、本実施例においては、上段のＰ型ＦＥＴ（3005）にＸ１という入力、下段のＮ型ＦＥＴ（3007）にはＸ２という入力が別個に加えられている点が異なる。 A circuit diagram in this embodiment is shown in FIG.
This circuit is similar to that of the above-described first embodiment (FIG. 3A). However, in the first embodiment, the input of the upper P-type FET and the input of the lower N-type FET are commonly connected (301) and the same. In contrast to the input signal being applied, in this embodiment, an input X1 is separately applied to the upper P-type FET (3005), and an input X2 is separately applied to the lower N-type FET (3007). The point is different.

本実施例の回路の出力特性の測定結果を図３０−Ｂに示す。
なお、グラフ上から入力Ｘ１、Ｘ２を示し、一番下のグラフが出力のグラフである。また、以後の各実施例における、回路動作のシミュレーションは、以下のような緒元を持つシミュレータを使用した。 The measurement result of the output characteristics of the circuit of this example is shown in FIG.
The inputs X1 and X2 are shown on the graph, and the bottom graph is the output graph. Further, in the following embodiments, circuit simulators used simulators having the following specifications.

表１０シミュレータの緒元

Table 10 Origin of simulator

また、Ｘ１とＸ２との間の真理値表を以下の表１１に示す。

表１１実施例９におけるＸ１とＸ２との間の真理値表

The truth table between X1 and X2 is shown in Table 11 below.

Table 11 Truth table between X1 and X2 in Example 9

本実施例において、回路の入力端子Ｘ２を０Ｖに接地し、入力端子Ｘ１のみにおいて入力電圧を変化させると（図３０−Ｃ参照）、以下の表１２のような動作を行う。

表１２実施例９においてＸ２端子を接地した場合の入出力関係

In this embodiment, when the input terminal X2 of the circuit is grounded to 0 V and the input voltage is changed only at the input terminal X1 (see FIG. 30C), the operation shown in Table 12 below is performed.

Table 12 Input / output relationship when X2 terminal is grounded in Example 9

このように、Ｘ２端子を接地すれば、実施例１とは異なる回路構成で、３値１入力のインバータが達成される。
同様に、Ｘ１端子を接地すれば、実施例１とは異なる回路構成で、３値１入力のインバータが達成される。
なお、本実施例９の図３０−Ａ、３０−Ｃ、にそれぞれ対応する、前記発明４、１６に対応する回路図を、図３０−Ｄ、図３０−Ｅ、に示す。 Thus, if the X2 terminal is grounded, a three-value one-input inverter is achieved with a circuit configuration different from that of the first embodiment.
Similarly, if the X1 terminal is grounded, a three-value one-input inverter is achieved with a circuit configuration different from that of the first embodiment.
In addition, the circuit diagram corresponding to the said invention 4 and 16 corresponding to FIG. 30-A of this Example 9 and 30-C, respectively is shown to FIG. 30-D and FIG. 30-E.

本実施例における回路図を図３１−Ａ及び図３１−Ｂに示す。
これらの回路で使用されるＦＥＴのスレッシュホールド電圧及び各パラメータは以下のとおりである。 A circuit diagram in this embodiment is shown in FIGS. 31-A and 31-B.
The threshold voltage and parameters of FETs used in these circuits are as follows.

表１３ＦＥＴのスレッシュホールド電圧

Table 13 FET threshold voltage

表１４ＦＥＴの各パラメータ

図３１−Ａの回路による回路動作のシミュレーション結果を、図３１−Ｃに示す。
また、図３１−Ａの回路によって達成される真理値表は以下の表１５の通りである。

Table 14 FET parameters

A simulation result of the circuit operation by the circuit of FIG. 31-A is shown in FIG. 31-C.
The truth table achieved by the circuit of FIG. 31-A is as shown in Table 15 below.

表１５実施例１０の図２３−Ａの回路におけるＸ１とＸ２との間の真理値表

Table 15 Truth table between X1 and X2 in the circuit of FIG. 23-A in Example 10

また、図３１−Ｂの回路によれば、３値ｍ入力が可能となり、
一般式は、

で表現できる。
なお、ｍ個の単位回路を備える、前記発明５に対応する回路図を、図３１−Ｄに示す。 Further, according to the circuit of FIG. 31-B, ternary m input is possible,
The general formula is

Can be expressed as
A circuit diagram corresponding to the invention 5 including m unit circuits is shown in FIG. 31-D.

本実施例における回路図を図３２−Ａ及び図３２−Ｂに示す。
これらの回路で使用されるＦＥＴのスレッシュホールド電圧及び各パラメータは以下のとおりである。 A circuit diagram in this embodiment is shown in FIGS. 32-A and 32-B.
The threshold voltage and parameters of FETs used in these circuits are as follows.

表１６ＦＥＴのスレッシュホールド電圧

Table 16 FET threshold voltage

表１７ＦＥＴの各パラメータ

Table 17 FET parameters

図３２−Ａの回路による回路動作のシミュレーション結果を、図３２−Ｃに示す。
また、図３２−Ａの回路によって達成される真理値表は以下の表１８の通りである。 A simulation result of the circuit operation by the circuit of FIG. 32-A is shown in FIG. 32-C.
The truth table achieved by the circuit of FIG. 32-A is as shown in Table 18 below.

表１８実施例１１の図２４−Ａの回路におけるＸ１とＸ２との間の真理値表

Table 18 Truth table between X1 and X2 in the circuit of FIG.

また、図３２−Ｂの回路によれば、３値ｍ入力が可能となり、
一般式は、

で表現できる。
なお、ｍ個の単位回路を備える、前記発明６に対応する回路図を、図３２−Ｄに示す。 In addition, according to the circuit of FIG.
The general formula is

Can be expressed as
A circuit diagram corresponding to the invention 6 including m unit circuits is shown in FIG.

従来の多値論理回路の例。An example of a conventional multi-value logic circuit. Ｎ型ＦＥＴの電圧電流特性。Voltage-current characteristics of N-type FET. 本発明の第１の実施例。1 shows a first embodiment of the present invention. 本発明の第１の実施例における動作シミュレーション結果（入力電圧−出力電圧）。The operation | movement simulation result (input voltage-output voltage) in 1st Example of this invention. 本発明の第１の実施例における動作シミュレーション結果（入力電圧−電流値）。The operation simulation result (input voltage-current value) in the 1st example of the present invention. 発明１に対応する回路。A circuit corresponding to the first aspect. 本発明の第２の実施例。2 shows a second embodiment of the present invention. ２値ＡＮＤ、ＯＲ、ＮＡＮＤ、ＮＯＲ、回路の実現例。Realization example of binary AND, OR, NAND, NOR, circuit. 挿入抵抗を用いた本発明の第３の実施例。Third embodiment of the present invention using an insertion resistor. 挿入抵抗をＦＥＴに置換した本発明の第３の実施例。3 shows a third embodiment of the present invention in which an insertion resistor is replaced with an FET. 本発明の第３の実施例における動作シミュレーション結果（入力電圧−出力電圧）。The operation simulation result (input voltage-output voltage) in the 3rd example of the present invention. 本発明の第４の実施例。4 shows a fourth embodiment of the present invention. 発明２に対応する回路。A circuit corresponding to the second aspect of the present invention. 本発明の第５の実施例。5 shows a fifth embodiment of the present invention. 本発明の第５の実施例における動作シミュレーション結果（入力電圧−出力電圧）。The operation | movement simulation result (input voltage-output voltage) in the 5th Example of this invention. 本発明の第５の実施例における動作シミュレーション結果（入力電圧−電流値）。The operation simulation result (input voltage-current value) in the 5th example of the present invention. 本発明の第６の実施例。6 shows a sixth embodiment of the present invention. 発明３に対応する回路。A circuit corresponding to invention 3. 「出力正規化回路」によって「ずれ」が補正される理由の説明図（仮想入出力伝達特性１）。Explanatory drawing of the reason why "deviation" is corrected by "output normalization circuit" (virtual input / output transfer characteristic 1). 「出力正規化回路」によって「ずれ」が補正される理由の説明図（仮想入出力伝達特性２）。Explanatory drawing of the reason why "deviation" is corrected by "output normalization circuit" (virtual input / output transfer characteristic 2). 発明７に対応する正規化回路。A normalization circuit corresponding to the seventh aspect of the present invention. 発明８に対応する正規化回路。A normalization circuit corresponding to the eighth aspect of the present invention. 発明９に対応する正規化回路。A normalization circuit corresponding to the ninth aspect of the present invention. 本発明の第７の実施例。7 shows a seventh embodiment of the present invention. 本発明の第７の実施例における、第１のインバータおよび第２のインバータの動作特性（入力電圧−出力電圧）。The operating characteristic (input voltage-output voltage) of the 1st inverter and the 2nd inverter in the 7th example of the present invention. 本発明の第７の実施例における、入出力電圧伝達特性（入力電圧−出力電圧）。Input / output voltage transfer characteristics (input voltage-output voltage) in the seventh embodiment of the present invention. 実施例４（図８）の３値３入力の回路の出力に、実施例７（図１８−Ａ）を出力正規化回路として接続した場合の回路図。The circuit diagram at the time of connecting Example 7 (FIG. 18-A) as an output normalization circuit to the output of the circuit of 3 values 3 inputs of Example 4 (FIG. 8). 図１９−Ａの回路の動作シミュレーション結果。The operation | movement simulation result of the circuit of FIG. 19-A. 発明１０に対応する正規化回路図。FIG. 11 is a normalization circuit diagram corresponding to the tenth aspect of the present invention. 発明１０をモデル化した回路。The circuit which modeled invention 10. 発明１０をモデル化した回路の入出力特性１。The input / output characteristics 1 of the circuit modeling the invention 10. 発明１０をモデル化した回路の入出力特性２。The input / output characteristics 2 of the circuit modeling the invention 10. 発明１１に対応する正規化回路図。The normalization circuit diagram corresponding to the eleventh aspect. 発明１２に対応する正規化回路図。The normalization circuit diagram corresponding to the invention 12. FIG. 本発明の第８の実施例（バッファタイプの入力演算部）。8 shows an eighth embodiment of the present invention (buffer type input operation unit). 入力電圧＝０Ｖのときの本発明の第８の実施例の動作説明。Operation of the eighth embodiment of the present invention when the input voltage = 0V. 入力電圧＝−３Ｖのときの本発明の第８の実施例の動作説明。Explanation of the operation of the eighth embodiment of the present invention when the input voltage = -3V. 入力電圧＝３Ｖのときの本発明の第８の実施例の動作説明。The operation of the eighth embodiment of the present invention when the input voltage is 3V. 本発明の第８の実施例の入出力電圧伝達特性（入力電圧−出力電圧）。The input / output voltage transfer characteristic (input voltage-output voltage) of the eighth embodiment of the present invention. 本発明の第８の実施例の動作シミュレーション結果入力電圧−電流値）。Operation simulation result input voltage-current value of the eighth embodiment of the present invention). 本発明の第８の実施例の動作シミュレーション結果入力電圧−電流値）。Operation simulation result input voltage-current value of the eighth embodiment of the present invention). 実施例８の回路（図２５−Ａ）のうち、Ｎ型ＦＥＴ（2507、2508）を除いた回路（（ａ）部分）の出力を３個ワイヤド・オア接続した回路（（ｂ）部分）。Of the circuit of Example 8 (FIG. 25-A), a circuit ((b) part) in which three outputs of the circuit (part (a)) excluding the N-type FETs (2507, 2508) are wired or connected. 図２６−Ａの回路の動作特性のシミュレーション結果。The simulation result of the operating characteristic of the circuit of FIG. 26-A. 発明１４に対応する正規化回路。A normalization circuit corresponding to the fourteenth aspect of the present invention. 発明１４をモデル化した回路。The circuit which modeled invention 14. 発明１２をモデル化した回路の入出力関係１。The input / output relationship 1 of the circuit modeling the invention 12. 発明１２をモデル化した回路の入出力関係２。The input / output relationship 2 of the circuit modeling the invention 12. 本発明の第９の実施例。Ninth embodiment of the present invention. 実施例９の回路の出力特性のシミュレーション結果。10 is a simulation result of output characteristics of the circuit of Example 9. 実施例９において、回路の入力端子Ｘ２を０Ｖに接地し、入力端子Ｘ１のみにおいて入力電圧を変化させた場合の回路図。In Example 9, the circuit diagram at the time of grounding the input terminal X2 of a circuit to 0V and changing an input voltage only in the input terminal X1. 発明４に対応する回路図。The circuit diagram corresponding to the invention 4. FIG. 発明１６に対応する回路図。FIG. 17 is a circuit diagram corresponding to the sixteenth aspect of the present invention. 本発明の第１０の実施例（その１）。The 10th example of the present invention (the 1). 本発明の第１０の実施例（その２）。10th Example (the 2) of this invention. 図３１−Ａの回路による回路動作のシミュレーション結果。The simulation result of the circuit operation | movement by the circuit of FIG. 31-A. 発明５に対応する回路図。FIG. 9 is a circuit diagram corresponding to the fifth aspect of the invention. 本発明の第１１の実施例（その１）。11th Embodiment of the present invention (No. 1) 本発明の第１１の実施例（その２）。11th Embodiment of the present invention (No. 2) 図３２−Ａの回路による回路動作のシミュレーション結果。The simulation result of the circuit operation | movement by the circuit of FIG. 32-A. 発明６に対応する回路図。The circuit diagram corresponding to the invention 6. FIG.

Explanation of symbols

401、403、405、901、903、905、1201、1203、1205、1207、1209 正極性の電源端子
407、409、411、907、909、911、1211、1213、1215、1217、1219 負極性の電源端子 401, 403, 405, 901, 903, 905, 1201, 1203, 1205, 1207, 1209 Positive power supply terminal
407, 409, 411, 907, 909, 911, 1211, 1213, 1215, 1217, 1219 Negative polarity power supply terminal

Claims

The gate electrode is connected to the jth input terminal (0 <j, j is an integer), the source electrode is connected to the positive power supply terminal, and the drain electrode is connected to the (2j−1) th node ( 2j-1) P-type FET;
A 2j P-type FET having a source electrode connected to the (2j-1) th node and a drain electrode connected to the first output terminal;
A (2j-1) th N-type FET having a drain electrode connected to the first output terminal and a source electrode connected to the 2j node;
A 2j N-type FET having a gate electrode connected to the jth input terminal, a drain electrode connected to the 2j node, and a source electrode connected to the negative power supply terminal
Have
The channel resistance value of the conductive state of the (2j-1) th P-type FET and the channel resistance value of the conductive state of the second j-type FET are substantially equal,
The channel resistance value of the conductive state of the 2j P-type FET and the channel resistance value of the conductive state of the (2j-1) -th N-type FET are substantially equal.
M unit circuits with j = 1 to m (0 <m, where m is an integer),
The gate of the 2nd j (for all j of 0 <j <m + 1) is connected to the (2m + 1) th node, and the gate of the (2j−1) th N-type FET is the (2m + 2) th gate. Connected to the node,
A (2m + 1) th P-type FET having a gate electrode and a drain electrode connected to the (2m + 1) th node and a source electrode connected to a positive power supply terminal;
A (2m + 1) -th N-type FET having a gate electrode and a drain electrode connected to the (2m + 2) -th node and a source electrode connected to a negative power supply terminal;
Further comprising
A constant current is caused to flow from the (2m + 1) -th node toward the negative power source by a constant current source,
A constant current is caused to flow from the positive power supply terminal toward the (2m + 2) th node by a constant current source,
The channel resistance value of the conduction state of the (2m + 1) th P-type FET and the channel resistance value of the conduction state of the (2m + 1) th N-type FET are substantially equal.
Multi-valued logic circuit.

A jth N-type gate electrode connected to the jth input terminal (0 <j, j is an integer), a drain electrode connected to the first output terminal, and a source electrode connected to the negative power supply terminal With m FETs from j = 1 to m (0 <m, where m is an integer),
Furthermore,
A P-type FET having a ground electrode connected to the gate electrode, a positive power supply terminal connected to the source electrode, and a first output terminal connected to the drain electrode;
The channel resistance value of the j-th N-type FET (0 <j <m) in the conductive state and the channel resistance value of the P-type FET in the conductive state are substantially the same.
Multi-valued logic circuit.

A jth P-type having a gate electrode connected to a jth input terminal (0 <j, j is an integer), a source electrode connected to a positive power supply terminal, and a drain electrode connected to a first output terminal. With m FETs from j = 1 to m (0 <m, where m is an integer),
Furthermore,
An N-type FET having a ground electrode connected to the gate electrode, a first output terminal connected to the drain electrode, and a negative power supply terminal connected to the source electrode;
The channel resistance value of the j-th P-type FET (0 <j <m, where m is an integer) and the channel resistance value of the N-type FET in the conduction state are substantially the same.
Multi-valued logic circuit.

A multi-valued logic circuit according to any one of claims 1 to 3 ,
Furthermore,
A (2m + 2) th P-type FET having a gate electrode connected to the first output terminal, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the (2m + 3) th node;
A (2m + 3) th P-type FET having a gate electrode connected to the (2m + 4) th node, a source electrode connected to the (2m + 3) th node, and a drain electrode connected to the second output terminal;
A (2m + 2) th N-type FET having a gate electrode connected to the (2m + 5) node, a drain electrode connected to the second output terminal, and a source electrode connected to the (2m + 6) node;
A (2m + 3) N-type FET having a gate electrode connected to the first output terminal, a drain electrode connected to the (2m + 6) node, and a source electrode connected to the negative power supply terminal;
A (2m + 4) th P-type FET having a gate electrode and a drain electrode connected to the (2m + 4) th node, and a source electrode connected to a positive power supply terminal;
A (2m + 4) -th N-type FET having a gate electrode and a drain electrode connected to the (2m + 5) -th node and a source electrode connected to a negative-polarity power supply terminal;
With
A constant current is caused to flow from the (2m + 4) node to the negative power source by a constant current source,
A constant current is caused to flow from the positive power supply terminal toward the (2m + 5) th node by a constant current source,
The channel resistance value of the conduction state of the (2m + 2) th P-type FET and the channel resistance value of the conduction state of the (2m + 3) th N-type FET are substantially equal,
The channel resistance value of the conduction state of the (2m + 3) th P-type FET and the channel resistance value of the conduction state of the (2m + 2) th N-type FET are substantially equal,
The channel resistance value of the conduction state of the (2m + 4) th P-type FET and the channel resistance value of the conduction state of the (2m + 4) th N-type FET are substantially equal.
Multi-valued logic circuit.

A multi-valued logic circuit according to any one of claims 1 to 3 ,
Furthermore,
A (2m + 2) th P-type FET having a gate electrode connected to the first output terminal, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the (2m + 3) th node;
A (2m + 2) N-type FET having a gate electrode connected to the first output terminal, a drain electrode connected to the (2m + 3) node, and a source electrode connected to the negative power supply terminal;
A first inverter comprising:
A first inverter that outputs negative and positive voltages to the (2m + 3) node, respectively, with respect to positive and negative voltages applied to the first output terminal;
A (2m + 3) th P-type FET having a gate electrode connected to the first output terminal, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the (2m + 5) node;
A (2m + 3) N-type FET having a gate electrode connected to the first output terminal, a drain electrode connected to the (2m + 5) node, and a source electrode connected to the negative power supply terminal;
A second inverter comprising:
A second inverter that outputs negative and positive voltages to the (2m + 5) node, respectively, with respect to positive and negative voltages applied to the first output terminal;
A third inverter having an input terminal connected to the (2m + 3) node and an output terminal connected to the (2m + 4) node;
A fourth inverter having an input terminal connected to the (2m + 5) node and an output terminal connected to the (2m + 6) node;
A (2m + 4) P-type FET having a gate electrode connected to the (2m + 4) node, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the second output terminal;
A (2m + 4) N-type FET having a gate electrode connected to the (2m + 6) node, a drain electrode connected to the second output terminal, and a source electrode connected to a negative power supply terminal;
Have
Furthermore,
(1) The logical threshold voltage value of the first inverter is smaller than an intermediate value between the positive power supply voltage value and the negative power supply voltage value, and the logical threshold voltage value of the second inverter is the positive polarity. Greater than the intermediate value between the power supply voltage value and the negative power supply voltage value,
Or
(2) A logical threshold voltage value of the first inverter is greater than an intermediate value between the positive power supply voltage value and the negative power supply voltage value, and a logical threshold voltage value of the second inverter is the positive polarity. Less than the intermediate value between the power supply voltage value and the negative power supply voltage value,
The logical threshold voltage values of the third inverter and the fourth inverter are both approximately intermediate values of the positive power supply voltage value and the negative power supply voltage value,
The channel resistance value of the conductive state of the (2m + 4) th P-type FET and the channel resistance value of the conductive state of the (2m + 4) th N-type FET are substantially equal.
Multi-valued logic circuit.

A multi-valued logic circuit according to any one of claims 1 to 3 ,
Furthermore,
A (2m + 2) th P-type FET having a gate electrode connected to the first output terminal, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the (2m + 3) th node;
A (2m + 2) N-type FET having a gate electrode connected to the first output terminal, a drain electrode connected to the (2m + 3) node, and a source electrode connected to the negative power supply terminal;
A first inverter that outputs negative and positive voltages to the (2m + 3) node with respect to positive and negative voltages applied to the first output terminal, respectively,
A (2m + 3) th P-type FET having a gate electrode connected to the first output terminal, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the (2m + 5) node;
A (2m + 3) N-type FET having a gate electrode connected to the first output terminal, a drain electrode connected to the (2m + 5) node, and a source electrode connected to the negative power supply terminal;
A second inverter that outputs negative and positive voltages to the (2m + 5) node for the positive and negative voltages applied to the first output terminal, respectively,
A third inverter whose input is connected to the (2m + 3) node and whose output is connected to the (2m + 4) node;
A fourth inverter whose input is connected to the (2m + 5) th node and whose output is connected to the (2m + 6) th node;
A (2m + 4) P-type FET having a gate electrode connected to the (2m + 4) node, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the second output terminal;
A (2m + 4) N-type FET having a gate electrode connected to a (2m + 6) node, a drain electrode connected to a second output terminal, and a source electrode connected to a negative power supply terminal;
A (2m + 5) th N-type FET having a gate electrode connected to the (2m + 5) th node, a drain electrode connected to the second output terminal, and a source electrode connected to the (2m + 7) th node;
A (2m + 6) th N-type FET having a gate electrode connected to the (2m + 4) th node, a drain electrode connected to the (2m + 7) th node, and a source electrode connected to a ground electrode of zero potential;
Have
Furthermore,
(1) The logical threshold voltage value of the first inverter is smaller than an intermediate value between the positive power supply voltage value and the negative power supply voltage value, and the logical threshold voltage value of the second inverter is the positive polarity. It is larger than the intermediate value between the power supply voltage value and the negative power supply voltage value,
Or
(2) A logical threshold voltage value of the first inverter is greater than an intermediate value between the positive power supply voltage value and the negative power supply voltage value, and a logical threshold voltage value of the second inverter is the positive polarity. Less than the intermediate value between the power supply voltage value and the negative power supply voltage value,
The logical threshold voltage values of the third inverter and the fourth inverter are both approximately intermediate values of the positive power supply voltage value and the negative power supply voltage value,
The channel resistance value of the conduction state of the (2m + 4) th P-type FET and the channel resistance value of the conduction state of the (2m + 4) th N-type FET are substantially equal.
The channel resistance value of the conductive state of the (2m + 5) N-type FET and the channel resistance value of the conductive state of the (2m + 6) N-type FET are substantially equal.
Multi-valued logic circuit.

A multi-valued logic circuit according to any one of claims 1 to 3 ,
Furthermore,
First control means having an input connected to the first output terminal and an output connected to a (2m + 4) th node;
Second control means having an input connected to the first output terminal and an output connected to the (2m + 6) th node;
The gate electrode is connected to the (2m + 4) node, the source electrode is connected to the positive power supply terminal, the drain electrode is connected to the second output terminal, the (2m + 4) P-type FET,
A (2m + 4) N-type FET having a gate electrode connected to the (2m + 6) node, a drain electrode connected to the second output terminal, and a source electrode connected to a negative power supply terminal;
With
The channel resistance value of the conduction state of the (2m + 4) th P-type FET and the channel resistance value of the conduction state of the (2m + 4) th N-type FET are substantially equal.
In the first control means, the potential of the first input terminal is Vss to Vss + {(Vdd−Vss) / N} (where Vss is the voltage value of the negative power supply terminal, and Vdd is A voltage value for turning on the (2m + 4) -th P-type FET when the voltage value is between the positive-polarity power supply terminal and N is a real number of 2 or more; otherwise, A voltage to turn off the (2m + 4) th P-type FET is output;
When the potential of the first input terminal is between Vdd − {(Vdd−Vss) / P} and Vdd (where P is a real number of 2 or more), the second control means A voltage for turning on the (2m + 4) N-type FET is output; otherwise, a voltage for turning off the (2m + 4) N-type FET is output.
Multi-valued logic circuit.

The voltage for turning on the (2m + 4) th P-type FET is a potential between Vdd− (Vdd−Vss) / 3 and Vdd, and the voltage for turning off the (2m + 4) th P-type FET is Vss. To Vdd− (Vdd−Vss) / 3,
The voltage for turning on the (2m + 4) N-type FET is a potential between Vss and Vss + (Vdd−Vss) / 3, and the voltage for turning off the (2m + 4) N-type FET is Vss + (Vdd− Vss) / 3 to Vdd.
The multi-value logic circuit according to claim 7.

The gate electrode is connected to the jth input terminal (0 <j, j is an integer), the source electrode is connected to the positive power supply terminal, and the drain electrode is connected to the (5j-4) th node ( 5j-4) P-type FET;
A (5j-4) th N-type FET having a gate electrode connected to the jth input terminal, a drain electrode connected to the (5j-4) th node, and a source electrode connected to the negative power supply terminal; ,
The (5j-4) th inverter is configured to output negative and positive voltages to the (5j-4) th node with respect to the positive and negative voltages applied to the jth input terminal, respectively. A (5j-4) th inverter;
A (5j-3) th P-type FET having a gate electrode connected to the jth input terminal, a source electrode connected to the positive power supply terminal, and a drain electrode connected to the (5j-3) th node; ,
A (5j-3) th N-type FET having a gate electrode connected to the jth input terminal, a drain electrode connected to the (5j-3) th node, and a source electrode connected to the negative power supply terminal; ,
The (5j-3) th inverter is configured to output negative and positive voltages to the (5j-3) th node with respect to the positive and negative voltages applied to the jth input terminal, respectively. A (5j-3) th inverter;
A (5j-2) th P-type FET having a gate electrode connected to the (5j-4) th node, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the first output terminal; ,
A (5j-2) -th N-type FET having a gate electrode connected to the (5j-3) -th node, a drain electrode connected to the first output terminal, and a source electrode connected to the negative power supply terminal; ,
The (5j-1) th inverter comprising:
A (5j-2) th inverter having an input terminal connected to the (5j-3) th node and an output terminal connected to the (5j-2) th node;
The gate electrode is connected to the (5j-2) th node, the drain electrode is connected to the (5j-1) th node, and the source electrode is connected to the (5j) th node. N-type FET,
A 5jth N-type FET having a gate electrode connected to the (5j-4) th node, a drain electrode connected to the (5j) th node, and a source electrode connected to the (5j + 1) th node;
Including m unit circuits from j = 1 to m (0 <m, where m is an integer),
A fourth node is connected to the first output terminal;
The (5m + 1) th node is grounded to zero potential,
The channel resistance value of the conductive state of the (5j-2) th P-type FET is substantially equal to the channel resistance value of the conductive state of the (5j-2) th N-type FET,
The channel resistance value of the conductive state of the (5j-1) th N-type FET and the channel resistance value of the conductive state of the fifth j-type FET are substantially equal,
Furthermore,
(1) A logic threshold voltage value of the (5j-4) th inverter is smaller than an intermediate value between the positive power supply voltage value and the negative power supply voltage value, and the logic of the (5j-3) th inverter. A threshold voltage value is greater than an intermediate value between the positive power supply voltage value and the negative power supply voltage value;
Or
(2) The logic threshold voltage value of the (5j-4) th inverter is larger than the intermediate value between the positive power supply voltage value and the negative power supply voltage value, and the logic of the (5j-3) th inverter. A threshold voltage value is smaller than an intermediate value between the positive power supply voltage value and the negative power supply voltage value,
The logic threshold voltage values of the (5j-2) th inverter and the (5j-1) th inverter are both substantially intermediate values of the positive power supply voltage value and the negative power supply voltage value. ,
Multi-valued logic circuit.

The gate electrode is connected to the jth input terminal (0 <j, j is an integer), the source electrode is connected to the positive power supply terminal, and the drain electrode is connected to the (5j-4) th node ( 5j-4) P-type FET;
A (5j-4) th N-type FET having a gate electrode connected to the jth input terminal, a drain electrode connected to the (5j-4) th node, and a source electrode connected to the negative power supply terminal; ,
The (5j-4) th inverter is configured to output negative and positive voltages to the (5j-4) th node with respect to the positive and negative voltages applied to the jth input terminal, respectively. A (5j-4) th inverter;
A (5j-3) th P-type FET having a gate electrode connected to the jth input terminal, a source electrode connected to the positive power supply terminal, and a drain electrode connected to the (5j-3) th node; ,
A (5j-3) th N-type FET having a gate electrode connected to the jth input terminal, a drain electrode connected to the (5j-3) th node, and a source electrode connected to the negative power supply terminal; ,
The (5j-3) th inverter is configured to output negative and positive voltages to the (5j-3) th node with respect to the positive and negative voltages applied to the jth input terminal, respectively. A (5j-3) th inverter;
The gate electrode is connected to the (5j-4) th node, the source electrode is connected to the positive power supply terminal, the drain electrode is connected to the first output terminal, and the (5j-2) th P-type FET ,
The gate electrode is connected to the (5j-3) node, the drain electrode is connected to the first output terminal, the source electrode is connected to the negative power supply terminal, and the (5j-2) N-type FET ,
A (5j-2) th inverter having an input terminal connected to the (5j-3) th node and an output terminal connected to the (5j-2) th node;
Have
The channel resistance of the conductive state of the (5j-2) th P-type FET and the channel resistance of the conductive state of the (5j-2) th N-type FET are substantially the same,
Furthermore,
(1) A logic threshold voltage value of the (5j-4) th inverter is smaller than an intermediate value between the positive power supply voltage value and the negative power supply voltage value, and the logic of the (5j-3) th inverter. A threshold voltage value is greater than an intermediate value between the positive power supply voltage value and the negative power supply voltage value;
Or
(2) The logic threshold voltage value of the (5j-4) th inverter is larger than the intermediate value between the positive power supply voltage value and the negative power supply voltage value, and the logic of the (5j-3) th inverter. A threshold voltage value is smaller than an intermediate value between the positive power supply voltage value and the negative power supply voltage value;
M unit units from j = 1 to m (0 <m, m is an integer),
Furthermore,
Short-circuit opening means connected between the first output terminal and the zero-potential ground terminal, the short-circuit opening means for all j from j = 1 to m, the (5j-4) -th node The first output terminal and the zero-potential ground terminal are short-circuited when the potential of the first and the (5j-2) -th node are all zero potential, otherwise the first output terminal And short-circuit opening means to open the ground terminal of zero potential,
With
Multi-valued logic circuit.

A P-type FET having a gate electrode connected to the first input terminal, a source electrode connected to a positive power supply terminal, and a drain electrode connected to the first output terminal;
An N-type FET having a gate electrode connected to a ground electrode, a drain electrode connected to a first output terminal, and a source electrode connected to a negative power supply terminal;
Have
The channel resistance value of the conductive state of the P-type FET and the channel resistance value of the conductive state of the N-type FET are substantially the same.
Multi-valued logic circuit.

A P-type FET having a gate electrode connected to a ground electrode, a source electrode connected to a positive power supply terminal, and a drain electrode connected to a first output terminal;
An N-type FET having a gate electrode connected to the first input terminal, a drain electrode connected to the first output terminal, and a source electrode connected to a negative power supply terminal;
Have
The channel resistance value of the conductive state of the P-type FET and the channel resistance value of the conductive state of the N-type FET are substantially the same.
Multi-valued logic circuit.