JP2005065084A - D/a conversion circuit and semiconductor integrated circuit using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a D/A conversion circuit capable of reducing glitch. <P>SOLUTION: The D/A conversion circuit is equipped with current cells C<SB>1</SB>to C<SB>n</SB>which output a predetermined current according to digital signals and resistors R1, R2, and outputs potential of a connection point between the current cells C<SB>1</SB>to C<SB>n</SB>and the resistors R1, R2. Each of the current cells C<SB>1</SB>to C<SB>n</SB>is equipped with a differential signal output circuit 11, a constant current output circuit 12, resistors R3, R4 connected with the constant current output circuit 12, respectively, a transistor QP1 of which the source to drain path is connected between the resistors R3 and R1 and to the gate of which one of differential signals is supplied, and a transistor QP2 of which the source to drain path is connected between the resistors R4 and R2 and to the gate of which the other of the differential signals is supplied. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a D / A conversion circuit that outputs a potential corresponding to a digital signal, and more particularly to a current addition type D / A conversion circuit. Furthermore, the present invention relates to a semiconductor integrated circuit using such a D / A conversion circuit.

A conventional current addition type D / A conversion circuit will be described with reference to FIGS.
As shown in FIG. 6, the D / A conversion circuit 30 includes current cells F _{n to} F ₁ and resistors R8 and R9. Each of the current cells F _{n to} F ₁ includes a differential signal output circuit 31, a constant current output circuit 32, and a switch circuit 33.
The current cells F _{n to} F ₁ are supplied with n-bit digital signals G _{n to} G ₁ , and the current cells F _{n to} F ₁ are either first or second depending on the n-bit digital signals G _{n to} G ₁ . A predetermined current is output from each of the two output terminals to the resistor R8 or R9.

The resistor R8 is connected between the first output terminal of the switch circuit 33 in the current cells F _{n to} F ₁ and a predetermined first power supply potential (here, the ground potential V _SS ). outputs a potential which is represented by the product of the first sum and the resistance value of the current supplied from the output terminal of F _n to F ₁ in the switch circuit 33 as a first output signal (analog signal).
Similarly, the resistor R9 is connected between the second output terminal of the switch circuit 33 in the current cells F _{n to} F ₁ and a predetermined first power supply potential (here, the ground potential V _SS ). A potential represented by the product of the sum of the currents supplied from the second output terminals of the switch circuit 33 in the current cells F _{n to} F ₁ and the resistance value is output as a second output signal (analog signal). .

FIG. 7 is a diagram showing an internal circuit configuration of the current cell F _n . As shown in FIG. 7, the differential signal output circuit 31 in the current cell F _n includes a D-type flip-flop FF3, and the digital signal G _n is supplied to the flip-flop FF3. The non-inverted output signal of the flip-flop FF3 is supplied to the first inverter INV5, and the inverted output signal of the flip-flop FF3 is supplied to the second inverter INV6. The inverters INV5 and INV6 are supplied with power from a predetermined first power supply potential (here, ground potential V _SS ) and a predetermined second power supply potential (here, V _DD2 ). A signal having a level corresponding to the potential difference between the power supply potential (here, ground potential V _SS ) and the second power supply potential (here, V _DD2 ), which is a non-inverted output signal and an inverted output signal of the flip-flop FF3. The inverted signals are supplied to the switch circuit 33 as a pair of differential signals.

The constant current output circuit 32 includes a P-channel transistor QP8, the source of the transistor QP8 is connected to a predetermined third power supply potential (here, V _DD ), and the gate is a predetermined bias potential. Connected to V _BIAS . The transistor QP8 supplies a current corresponding to the bias potential V _BIAS to the switch circuit 33.

The switch circuit 33 includes P-channel transistors QP9 and QP10.
The sources of the transistors QP9 and QP10 are connected to the drain of the transistor QP8 in the constant current output circuit 32.
The drain of the transistor QP9 is connected to the resistor R8 (see FIG. 6), and the output signal of the inverter INV6 in the differential signal output circuit 31 is supplied to the gate.
The drain of the transistor QP10 is connected to the resistor R9 (see FIG. 6), and the output signal of the inverter INV5 in the differential signal output circuit 31 is supplied to the gate.

In the current cell F _n shown in FIG. 7, since the potential at the connection point (node N2) between the drain of the transistor QP8 and the sources of the transistors QP9 and QP10 is not constant, the current supplied to the resistors R8 and R9 is irregularly As a result, a glitch has occurred in the output signal of the D / A conversion circuit 30. The following two points can be considered as the cause that the potential of the node N2 is not constant.

(1) The differential signal generated by the differential signal output circuit 31 changes linearly. When such a linearly changing differential signal is supplied to the gates of the transistors QP9 and QP10, the drain currents of the transistors QP9 and QP10 change irregularly without changing linearly. As a result, a glitch occurs in the output signal of the D / A conversion circuit 30. Figure 8 is applied between the transistors QP9, QP10 gate-source to vary the drain current I _d of the drain current I _d (QP9) and the transistor QP10 transistors QP9 in the switch circuit 33 (QP10), respectively linearly is a diagram showing a should do gate-source voltage V _gs (QP9) and V _gs (QP10).
As shown in FIG. 8, the drain current I _d of the drain current I _d (QP9) and the transistor QP10 of the transistor QP9 the (QP10) in order to linearly changed respectively, the gate-source voltage V _gs (QP9) and It is necessary to vary V _gs (QP10) in a curved manner.
However, it is not easy to generate a differential signal that changes in a curve as shown in FIG.

  (2) The charge charged in the parasitic capacitance of the transistor QP8 is discharged and flows as a current to the node N2, thereby causing a glitch in the output signal of the D / A conversion circuit 30.

D / A conversion circuits that reduce glitches caused by the above-described causes have been proposed (see, for example, Non-Patent Documents 1 and 2).
According to Non-Patent Document 1, a voltage approximating the gate-source voltage shown in FIG. 8 is supplied between the gate and the source of the transistor in the switch circuit by delaying the rising edge of the linearly changing signal. / A conversion circuit is listed.
However, the D / A converter circuit described in Non-Patent Document 1 supplies a voltage approximating an ideal gate-source voltage between the gate and source of a transistor using a linearly changing signal. Therefore, the glitch is reduced to some extent. Moreover, the magnitude of the glitch changes due to the individual difference of the inverter.

Non-Patent Document 2 discloses a D / A that supplies a voltage that approximates the ideal gate-source voltage shown in FIG. 8 between the gate and source of a transistor in the switch circuit using a differential amplifier circuit. A conversion circuit is listed.
However, the D / A converter circuit described in Non-Patent Document 2 supplies a voltage approximating the gate-source voltage shown in FIG. 8 between the gate and source of the transistor using a linearly changing signal. It is only a matter of reducing glitches to some extent. Further, the D / A conversion circuit described in Non-Patent Document 2 causes an increase in power consumption by using a differential amplifier circuit.

H. Khono, et al, "A 350-MS / s 3.3-V 8-bit CMOS D / A Converter Using a Delayed Driving Sheme", Proc. Of CICC, 1995. L. Sumanen, et al, "A 10-bit High-Speed Low-Power CMOS D / A Converter in 0.2mm2", Proc. Of ICECS, 1998

が成立する。ここで、Ｖ_giはトランジスタＱＰ９、ＱＰ１０のスイッチングのために必要且つ理想的なゲート〜ソース間電圧であり、Ｖ_tはトランジスタＱＰ９、ＱＰ１０のスレッショルド電圧であり、Ｉ_dはトランジスタＱＰ９、ＱＰ１０のドレイン電流であり、μはトランジスタＱＰ９、ＱＰ１０の正孔易動度であり、Ｃｏｘは、トランジスタＱＰ９、ＱＰ１０の単位面積当たりのゲート容量であり、ＷはトランジスタＱＰ９、ＱＰ１０のゲート幅であり、ＬはトランジスタＱＰ９、ＱＰ１０のゲート長である。
トランジスタＱＰ９、ＱＰ１０のゲート〜ソース間に現実に印加されるゲート〜ソース間電圧Ｖ_goは、インバータＩＮＶ５、ＩＮＶ６の電源電圧（Ｖ_DD2−Ｖ_SS）によって定まる。 By the way, in the saturation region of the transistors QP9 and QP10 shown in FIG.

Is established. Here, V _gi is a gate-source voltage necessary and ideal for switching of the transistors QP9 and QP10, V _t is a threshold voltage of the transistors QP9 and QP10, and I _d is a drain of the transistors QP9 and QP10. Μ is the hole mobility of the transistors QP9 and QP10, Cox is the gate capacitance per unit area of the transistors QP9 and QP10, W is the gate width of the transistors QP9 and QP10, and L is This is the gate length of the transistors QP9 and QP10.
The gate-source voltage V _go actually applied between the gates and sources of the transistors QP9 and QP10 is determined by the power supply voltage (V _DD2 −V _SS ) of the inverters INV5 and INV6.

Ideally, it is desirable to set V _go = V _gi , but it is not easy to set the power supply voltage (V _DD2 −V _SS ) of the inverters INV5 and INV6 to a desired voltage, so V _go > V _gi or In general, V _go >> V _gi .
When V _go >> V _gi , the potential of the node N2 (see FIG. 7) fluctuates and a glitch occurs. Therefore, in order to make V _gi as close as possible to V _go , it is conceivable to reduce W (gate width) / L (gate length).

  In order to reduce W (gate width) / L (gate length), either or both of (a) reducing W (gate width) and (b) increasing L (gate length) are necessary. is there. However, W (gate width) cannot be set to a predetermined value or less because of limitations of design rules and manufacturing processes. On the other hand, when L (gate length) is increased, the gate capacitances of the transistors QP9 and QP10, which are proportional to the product of W (gate width) and L (gate length), increase, and charges are charged and discharged in the gate capacitance. Therefore, the fluctuation of the potential of the node N2 (see FIG. 7) becomes large, and a glitch is generated.

  Therefore, in view of the above points, an object of the present invention is to provide a D / A conversion circuit capable of reducing glitches. Furthermore, an object of the present invention is to provide a semiconductor integrated circuit including such a D / A conversion circuit.

  In order to solve the above problems, a D / A conversion circuit according to a first aspect of the present invention includes a plurality of circuits that output predetermined currents according to a plurality of bits of a digital signal, a plurality of circuits, and a predetermined circuit, respectively. And a first resistive load circuit connected between the first potential and a first resistive load circuit that outputs a potential at a connection point between the plurality of circuits and the first resistive load circuit as an output signal. A differential signal output circuit for outputting a pair of differential signals corresponding to one bit of the plurality of bits of the digital signal, and one end of the second circuit having a predetermined second A constant current output circuit connected to a potential; second and third resistive load circuits having one end connected to the other end of the constant current output circuit; and a source-drain path being a second resistive load circuit Connected between the first resistive load circuit and the gate with a pair of differences A first transistor to which one of the signals is supplied, a source connected to the third resistive load circuit, and a second to which the other signal of the pair of differential signals is supplied to the gate A transistor.

  A D / A conversion circuit according to a second aspect of the present invention includes a plurality of circuits that respectively output a predetermined current according to a plurality of bits of a digital signal, a plurality of circuits, and a predetermined first potential. A D / A converter circuit that outputs a potential at a connection point between the plurality of circuits and the first resistive load circuit as an output signal. Each of the plurality of circuits is connected to a differential signal output circuit that outputs a pair of differential signals corresponding to one bit of the plurality of bits of the digital signal, and one end is connected to a predetermined second potential. First and second constant current output circuits, and a second resistance having one end connected to the other end of the first constant current output circuit and the other end connected to the other end of the second constant current output circuit The load circuit and the source-drain path are the other end of the first constant current output circuit and the second resistor A first transistor connected between one end of the load circuit and the first resistive load circuit and having one of a pair of differential signals supplied to the gate, and a source serving as a second constant current output And a second transistor connected to the other end of the circuit and the other end of the second resistive load circuit, and having the gate supplied with the other signal of the pair of differential signals.

  Furthermore, a semiconductor integrated circuit according to the present invention includes the D / A conversion circuit.

  According to the present invention, glitches can be reduced. Thereby, it is possible to improve the S / N ratio.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, about the same component, it has shown with the same reference number.

FIG. 1 is a diagram showing an outline of a D / A conversion circuit according to the first embodiment of the present invention. As shown in FIG. 1, the D / A conversion circuit 10 includes n (n is a natural number) current cells C _{n to} C ₁ and resistors R1 and R2. Each of the current cells C _{n to} C ₁ includes a differential signal output circuit 11, a constant current output circuit 12, and a switch circuit 13.
The current cell C _n -C ₁ is supplied the digital signal D _n to D ₁ of n bits, the current cell C _n -C _1, in accordance with the digital signal D _n to D _1, the first or second output A predetermined current is output from the terminal to the resistor R1 or R2.

The resistor R1 is connected between the first output terminal of the switch circuit 13 in the current cells C _{n to} C ₁ and a predetermined first power supply potential (here, the ground potential V _SS ). A potential represented by the product of the sum of currents supplied from the first output terminal of the switch circuit 13 in C _{n to} C ₁ and the resistance value is output as a first output signal (analog signal).
Similarly, the resistor R2 is connected between the second output terminal of the switch circuit 13 in the current cells C _{n to} C ₁ and a predetermined first power supply potential (here, the ground potential V _SS ). The potential represented by the product of the sum of the current supplied from the second output terminal of the switch circuit 13 in the current cells C _{n to} C ₁ and the resistance value is output as a second output signal (analog signal). .
In this embodiment, two resistors R1 and R2 are provided to output the first and second output signals. However, only one of the resistors R1 and R2 is provided and one output signal is output. It may be output.

FIG. 2 is a diagram showing an internal circuit configuration of the current cell C _n . As shown in FIG. 2, the differential signal output circuit 11 in the current cell C _n includes a D-type flip-flop FF1, and a digital signal D _n is supplied to the flip-flop FF1. The non-inverted output signal of the flip-flop FF1 is supplied to the first inverter INV1, and the inverted output signal of the flip-flop FF1 is supplied to the second inverter INV2. The inverters INV1 and INV2 are supplied with power from a predetermined first power supply potential (here, ground potential V _SS ) and a predetermined second power supply potential (here, V _DD2 ). A signal having a level corresponding to the potential difference between the power supply potential (here, ground potential V _SS ) and the second power supply potential (here, V _DD2 ), which is a non-inverted output signal and an inverted output signal of the flip-flop FF1 The inverted signals are supplied to the switch circuit 13 as a pair of differential signals.

The constant current output circuit 12 includes a P-channel transistor QP3, the source of the transistor QP3 is connected to a predetermined third power supply potential (here, V _DD ), and the gate is a predetermined bias potential. Connected to V _BIAS . The transistor QP3 supplies a current corresponding to the bias potential V _BIAS to the switch circuit 13.

The switch circuit 13 includes resistors R3 and R4 and P-channel transistors QP1 and QP2. One ends of the resistors R3 and R4 are connected to the drain of the transistor QP3 in the constant current output circuit 12.
The source of the transistor QP1 is connected to the other end of the resistor R3, the drain is connected to the resistor R1 (see FIG. 1), and the output signal of the inverter INV2 in the differential signal output circuit 11 is connected to the gate. Entered.
The source of the transistor QP2 is connected to the other end of the resistor R4, the drain is connected to the resistor R2 (see FIG. 1), and the output signal of the inverter INV1 in the differential signal output circuit 11 is connected to the gate. Entered.
The current cells C _{n−1 to} C ₁ have the same configuration as the current cell C _n shown in FIG.

で表すことができる。ここで、Ｒは、抵抗Ｒ３、Ｒ４（図２参照）の抵抗値である。（２）式において、右辺第３項（Ｒ・Ｉ_d）を除くと、（１）式と等しくなる。Ｒの値を変化させることは、他のパラメータを変化させることに比べて、設計ルールやプロセス製造の限界による制約を受けにくい。トランジスタＱＰ１、ＱＰ２のゲート〜ソース間に現実に印加されるゲート〜ソース間電圧Ｖ_goと理想的なゲート〜ソース間電圧Ｖ_giとの関係はＶ_go＝Ｖ_giとなることが望ましいので、Ｖ_go≒Ｖ_giとなるようにＲの値を調整し、Ｖ_gsの特性を従来技術図８の曲線から、図３では直線に近いラインに改善させた。
このような直線的に変化する差動信号は、図２に示すように、フリップフロップＦＦ１及びインバータＩＮＶ１、ＩＮＶ２を用いて生成可能であり、他の回路構成を用いても容易に生成可能である。 FIG. 3 shows a case where the drain current I _d (QP1) of the transistor QP1 and the drain current I _d (QP2) of the transistor QP2 in the switch circuit 13 are linearly changed between the gates and sources of the transistors QP1 and QP2, respectively. It is the figure showing the gate-source voltage _Vgs (QP1) and _Vgs (QP2) which should be performed.
As shown in FIG. 3, in order to linearly change the drain current I _d (QP1) of the transistor QP1 and the drain current I _d (QP2) of the transistor QP2, respectively, the gate-source voltage V _gs (QP1) and V _gs (QP2) may be changed substantially linearly. That is, the pair of differential signals output from the differential signal output circuit 11 may be changed linearly.
Here, the gate-source voltage V _gi necessary and ideal for switching of the transistors QP1 and QP2 is:

It can be expressed as Here, R is the resistance value of the resistors R3 and R4 (see FIG. 2). In the formula (2), if the third term (R · I _d ) on the right side is excluded, it becomes equal to the formula (1). Changing the value of R is less subject to restrictions due to design rules and process manufacturing limits than changing other parameters. Since the relationship between the gate-source voltage V _go actually applied between the gate and source of the transistors QP1 and QP2 and the ideal gate-source voltage V _gi is preferably V _go = V _gi , V to adjust the value of R so that _go ≒ V _gi, the characteristics of V _gs from the curve of the prior art Figure 8, was improved in the line close to a straight line in FIG. 3.
Such a linearly changing differential signal can be generated using the flip-flop FF1 and inverters INV1 and INV2, as shown in FIG. 2, and can be easily generated using other circuit configurations. .

Thus, since the currents output from the current cells C _{n to} C ₁ change linearly, the currents flowing through the resistors R1 and R2 (see FIG. 1) also change linearly, and the D / A conversion circuit It is possible to reduce glitches of the ten output signals.
Further, when the charge charged in the parasitic capacitance of the transistor QP3 is discharged and flows as a current to the connection point (node N1) between the drain of the transistor QP3 and the resistors R3 and R4, the nodes N1 are connected by the resistors R3 and R4. Of the output signal of the D / A conversion circuit 10 can be reduced.
Furthermore, the degree of freedom in designing the gate width and gate length of the transistors QP1 and QP2 can be increased.

  In the present embodiment, the switch circuit 13 includes the resistors R3 and R4, but includes other resistive loads (for example, an analog switch that is always on) instead of the resistors R3 and R4. It is also good to do.

Next, a second embodiment of the present invention will be described.
FIG. 4 is a diagram showing an outline of a D / A conversion circuit according to the second embodiment of the present invention. As shown in FIG. 4, the D / A conversion circuit 20 includes n (n is a natural number) current cells E _{n to} E ₁ and resistors R5 and R6. Each of the current cells E _{n to} E ₁ includes a differential signal output circuit 21, constant current output circuits 22 and 23, and a switch circuit 24.
The current cell E _n to E ₁ is supplied the digital signal D _n to D ₁ of n bits, the current cell E _n to E ₁ in response to the digital signal D _n to D _1, the first or second output A predetermined current is output from the terminal to the resistor R5 or R6, respectively.

The resistor R5 is connected between the first output terminal of the switch circuit 24 in the current cells E _{n to} E ₁ and a predetermined first power supply potential (here, the ground potential V _SS ). A potential represented by the product of the sum of the currents supplied from the first output terminals of the switch circuit 24 in E _{n to} E ₁ and the resistance value is output as a first output signal (analog signal).
Similarly, the resistor R6 is connected between the second output terminal of the switch circuit 24 in the current cells E _{n to} E ₁ and a predetermined first power supply potential (here, the ground potential V _SS ). A potential represented by the product of the sum of currents supplied from the second output terminals of the switch circuit 24 in the current cells E _{n to} E ₁ and the resistance value is output as a second output signal (analog signal). .
In the present embodiment, two resistors R5 and R6 are provided to output the first and second output signals. However, only one of the resistors R5 and R6 is provided and one output signal is output. It may be output.

Figure 5 is a diagram showing a circuit configuration inside the current cell E _n. As shown in FIG. 5, the differential signal output circuit 21 in the current cell E _n is provided with a D-type flip-flop FF2, to the flip-flop FF2, the digital signal D _n is supplied. The non-inverted output signal of the flip-flop FF2 is supplied to the first inverter INV3, and the inverted output signal of the flip-flop FF2 is supplied to the second inverter INV4. The inverters INV3 and INV4 are supplied with electric power from a predetermined first power supply potential (here, the ground potential V _SS ) and a predetermined second power supply potential (here, V _DD2 ). A signal having a level corresponding to the potential difference between the power supply potential (here, the ground potential V _SS ) and the second power supply potential (here, V _DD2 ), the non-inverted output signal and the inverted output signal of the flip-flop FF2 The inverted signals are supplied to the switch circuit 24 as a pair of differential signals.

The constant current output circuit 22 includes a P-channel transistor QP4, the source of the transistor QP4 is connected to a predetermined third power supply potential (here, V _DD ), and the gate is a predetermined bias potential. Connected to V _BIAS . The transistor QP4 supplies a current corresponding to the bias potential V _BIAS to the switch circuit 24.
Similarly, the constant current output circuit 23 includes a P-channel transistor QP5, the source of the transistor QP5 is connected to a predetermined third power supply potential (here, V _DD ), and the gate is a predetermined _Is connected to the bias potential V _BIAS . The transistor QP5 supplies a current corresponding to the bias potential V _BIAS to the switch circuit 24.

The switch circuit 24 includes a resistor R7 and P-channel transistors QP6 and QP7. Both ends of the resistor R7 are connected to the drain of the transistor QP4 in the constant current output circuit 22 and the drain of the transistor QP5 in the constant current output circuit 23, respectively.
The source of the transistor QP6 is connected to the drain of the transistor QP4 in the constant current output circuit 22 and one end of the resistor R7, the drain is connected to the resistor R5 (see FIG. 4), and the gate has a differential signal. An output signal of the inverter INV4 in the output circuit 21 is input.
The source of the transistor QP7 is connected to the drain of the transistor QP5 in the constant current output circuit 23 and the other end of the resistor R7, and the drain is connected to the resistor R6 (see FIG. 4). The output signal of the inverter INV3 in the signal output circuit 21 is input.
The current cell E _n-1 to E ₁ have the same construction as the current cell E _n shown in FIG.

Similar to the current previously described cell C _n (see FIG. 2), in order to linearly vary respectively the drain current of the drain current and the transistor QP7 transistors QP6 in current cell E _n shown in FIG. 5, the transistor What is necessary is just to change the gate-source voltage of QP6 and QP7 substantially linearly. That is, the pair of differential signals output from the differential signal output circuit 21 may be changed linearly. Such a linearly changing differential signal can be generated using the flip-flop FF2 and inverters INV3 and INV4 as shown in FIG. 5, and can also be generated using other circuit configurations.

As described above, since the currents output from the current cells E _{n to} E ₁ change linearly, the currents flowing through the resistors R5 and R6 (see FIG. 4) also change linearly. It is possible to reduce glitches of the 20 output signals.

  The present invention can be used in a current addition type D / A conversion circuit. Furthermore, the present invention can be used in a semiconductor integrated circuit using such a D / A conversion circuit.

1 is a diagram illustrating an outline of a D / A conversion circuit according to a first embodiment of the present invention. It is a diagram showing a circuit configuration inside the current cell C _n in FIG. The figure of the gate-source voltage and drain current of transistors QP1 and QP2. It is a figure which shows the outline | summary of the D / A converter circuit which concerns on the 2nd Embodiment of this invention. It is a diagram showing a circuit configuration inside the current cell E _n in FIG. It is a figure which shows the outline | summary of the conventional D / A conversion circuit. It is a diagram showing a circuit configuration inside the current cell F _n in FIG. The figure of the gate-source voltage and drain current of transistors QP9 and QP10.

Explanation of symbols

10, 20, 30 D / A conversion circuit, 11, 21, 31 a differential signal output circuit, 12,22,23,32 constant current output circuit, 13,24,33 switch circuit, C _n ~C _1, E _n ~E _1, F _n ~F ₁ current cell, FF1 to FF3 flip-flop, INV1～INV6 inverter, R1 to R9 resistors, QP1～QP10 transistor

Claims (3)

A plurality of circuits each outputting a predetermined current according to a plurality of bits of the digital signal; and a first resistive load circuit connected between the plurality of circuits and a predetermined first potential. A D / A conversion circuit for outputting, as an output signal, a potential at a connection point between the plurality of circuits and the first resistive load circuit,
Each of the plurality of circuits is
A differential signal output circuit for outputting a pair of differential signals according to one bit of the plurality of bits of the digital signal;
A constant current output circuit having one end connected to a predetermined second potential;
Second and third resistive load circuits each having one end connected to the other end of the constant current output circuit;
A source-drain path is connected between the second resistive load circuit and the first resistive load circuit, and a gate is supplied with one of the pair of differential signals. A transistor,
A D / A conversion circuit comprising: a second transistor having a source connected to the third resistive load circuit and a gate supplied with the other signal of the pair of differential signals. A plurality of circuits each outputting a predetermined current according to a plurality of bits of the digital signal; and a first resistive load circuit connected between the plurality of circuits and a predetermined first potential. A D / A conversion circuit for outputting, as an output signal, a potential at a connection point between the plurality of circuits and the first resistive load circuit,
Each of the plurality of circuits is
A differential signal output circuit for outputting a pair of differential signals according to one bit of the plurality of bits of the digital signal;
First and second constant current output circuits each having one end connected to a predetermined second potential;
A second resistive load circuit having one end connected to the other end of the first constant current output circuit and the other end connected to the other end of the second constant current output circuit;
A source-drain path is connected between the other end of the first constant current output circuit, one end of the second resistive load circuit, and the first resistive load circuit, and the pair of differentials at the gate A first transistor to which one of the signals is supplied;
A source is connected to the other end of the second constant current output circuit and the other end of the second resistive load circuit, and a gate is supplied with the other signal of the pair of differential signals. A D / A conversion circuit including a transistor. A semiconductor integrated circuit comprising the D / A conversion circuit according to claim 1.

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