JP5414060B2 - MOS transistor circuit with level converter circuit - Google Patents

Description

  The present invention relates to an improved technique of a level converter circuit using an insulated gate field effect transistor. In particular, in a CMOS circuit, when the low logic signal amplitude from the low power supply voltage circuit is smaller than the logic threshold voltage of the high power supply voltage circuit, the low logic signal amplitude signal is converted to the high logic signal amplitude signal of the high power supply voltage circuit. It relates to a level converter (LC) circuit capable of static operation. The static operation is a logic signal that does not change in time at the output node when an input logic signal that does not change in time is applied to the input node in a logic circuit using MOS transistors. , An operation of outputting a logic signal as a result of applying the logic action of the logic circuit to the input logic signal.

First, terms and symbols used in this specification are defined. FIG. 3 shows a circuit diagram of a CMOS inverter and a symbol representing it.
MP in FIG. 3 is a P-type insulated gate field effect transistor (PMOST),
MN is an N-type insulated gate field effect transistor (NMOST).
IN is the input node,
OUT indicates the output node.
VDD is the potential of the high potential side power line,
VSS is a potential of the low potential side power supply line.
VDD-VSS is referred to as a power supply voltage.
Note that VSS <VDD. The power supply line is indicated by the same symbol as the symbol indicating the potential. For example, the power supply line VDD represents a power supply line whose potential is VDD.
Further, a circuit having a large difference between VDD and VSS, that is, a power supply voltage value is called a high power supply voltage circuit, and a circuit having a small power supply voltage value is called a low power supply voltage circuit.

FIG. 4 schematically shows an input / output characteristic curve (see Non-Patent Document 1) of a general CMOS inverter as shown in FIG. The horizontal axis in FIG. 4 is the input voltage VIN (voltage applied to the node IN), and the vertical axis is the output voltage VOUT (voltage observed at the output node OUT).
The transition region (TR) is an input voltage range that is in the middle of changing when the output voltage changes from VDD to VSS or vice versa, and is usually defined as follows. That is, this input / output characteristic curve usually has two input voltage values at which the slope of the tangent (represented by a straight line) is −1. Of these input voltage values, the lower one of the input voltage values is designated as the transition region lower limit ( TRL), the higher input voltage is the transition region upper limit (TRH), and the input voltage range sandwiched between these voltages is the transition region (TR).

An input voltage whose output voltage is equal to (VDD + VSS) / 2 is referred to as a logical threshold voltage (VTL) of the inverter. VTL is located in TR. VTL is preferably an average value of VDD and VSS.
Further, the difference between VDD and VSS is referred to as a logic amplitude (LS). In general, in order for the CMOS inverter to operate reliably, the input voltage must be changed so as to cross this transition region. Note that VDD of the input voltage VIN on the horizontal axis represents the same voltage value as the output voltage VDD.

In a logic integrated circuit using an insulated gate field effect transistor (MOST), it is desired to reduce power consumption without deteriorating the operation speed.
As one of the methods for that purpose, the power supply voltage of the partial circuit whose operation speed may be slow may be made smaller than the power supply voltage of the other part that must operate at high speed. In this case, a logic signal with a low logic signal amplitude from a low power supply voltage circuit with a small power supply voltage is used to drive a high power supply voltage circuit with a large power supply voltage operating with a signal with a high logic signal amplitude without logical error. There must be.

  However, FIG. 5 is a circuit diagram in which a CMOS inverter that operates at a low power supply voltage is directly connected to a CMOS inverter that operates at a high power supply voltage in a conventional circuit in which the low-potential side power supply voltage is shared with GND. As shown in FIG. 5, the output of the CMOS inverter (LPS_INVERTER) connected to the common low-potential side power supply line GND (ground, potential is 0 V) and operating at the low power supply voltage (VDDL) is connected to the high power supply voltage (VDDH). If it is directly connected to the input of the CMOS inverter (HPS_INVERTER) that is operating at Here, 0 <VDDL <VDDH. An output signal from a logic circuit operating at a low power supply voltage can be a logic signal from a logic circuit other than a gate circuit or an inverter in general. However, since an inverter is usually used as a buffer circuit, a CMOS inverter The output signal from will be described.

FIG. 6 is a schematic diagram showing the input / output characteristics of HPS_INVERTER in FIG. FIG. 6 corresponds to the characteristics of FIG.
The origin is GND (when this symbol indicates a potential, it means 0V). When the input voltage VIN is increased from 0V, when the input voltage VIN exceeds the logical threshold voltage (VTLH) of HPS_INVERTER, the output voltage is changed from the high level (VDDH) to the low level (GND = 0V) of the logical signal. Transition.
Conversely, when the input voltage VIN is decreased from the high level, when the input voltage VIN becomes lower than the logical threshold voltage VTLH of HPS_INVERTER, the output voltage transitions from the low level of the logic signal to the high level.

  LSH (logic amplitude on the high power supply voltage circuit side) is a logic signal amplitude of HPS_INVERTER, and TRH indicates a transition region of HPS_INVERTER. The lower limit value of TRH is indicated by TRHL, and the upper limit value is indicated by TRHH. The width of TRH, that is, the difference between TRHH and TRHL, is the threshold voltage Vthn of NMOST (MN) and the threshold voltage Vthp (<0) of PMOST (MP) used for the inverter, and the respective current driving forces (specifically, It is evaluated by the magnitude of the absolute value of each drain current when a gate voltage having the same absolute value and a drain voltage having the same absolute value are applied, and the larger the value, the greater the current driving force). Dependent. Also, the width of TRH tends to decrease when both Vthn and | Vthp |

FIG. 6 also shows an input / output characteristic curve of LPS_INVERTER. The characteristic curve schematically shows the potential change seen at the output node N1, that is, the input node of HPS_INVERTER, when the input potential changes from VDDL to GND. VTLL indicates the logical threshold voltage of LPS_INVERTER.
Note that VTLL, VDDL, and VDDH of the input voltage VIN on the horizontal axis in FIG. 6 represent the same voltage values as the output voltages VTLL, VDDL, and VDDH.
Generally, for reliable operation of the inverter, it is necessary to make the input voltage lower than the lower limit value TRHL of TRH or higher than the upper limit value TRHH.

  However, in the case of FIG. 6, the input of HPS_INVERTER is the potential of the node N1, and the high level value is the high level of the output of LPS_INVERTER with the low logic signal amplitude, VDDL. If the amplitude (equal to LSL) is smaller than TRHL, it is natural that TRH cannot be exceeded as shown in FIG. 6, and the output of HPS_INVERTER is not inverted to low level. That is, when VDDL is significantly smaller than VDDH, the circuit of FIG. 5 may not operate correctly.

Therefore, a level converter (LC) circuit shown in FIG. 7 is required between LPS_INVERTER and HPS_INVERTER as a circuit for performing signal level conversion during this period.
FIG. 7 is a circuit configuration diagram in which a level converter (LC) circuit is interposed between LPS_INVERTER and HPS_INVERTER.
That is, the LC circuit is a circuit in which a signal having a low logic signal amplitude is applied to the input node, but a logic signal having a high logic signal amplitude is output to the output node. Of course, it is required to satisfy a required operating speed, to consume less power, and to use a smaller number of elements.

A conventional LC circuit is shown, for example, in Non-Patent Document 2 below, and has a circuit configuration shown in FIG.
In FIG. 8, MP1 and MP2 are PMOSTs, and MN1 and MN2 are NMOSTs. Q and QB are output nodes, which are complementary to each other, and in a steady state, a positive feedback circuit is configured with MP1 and MP2 to ensure that one of them is at the high level of the high power supply voltage circuit, that is, VDDH. ing. This also makes it possible to reduce the steady current very much. An inverter symbol in gray (meaning that the Δ symbol is not white) is an inverter (LPS_INVERTER) used in the low power supply voltage circuit, and the output high level is VDDL. The high level of the input of the LC circuit, the node LC_IN, is VDDL, and the low level is GND (0 V). That is, it is driven at the logic level of the low power supply voltage circuit, and therefore MN1 and MN2 and LPS_INVERTER are also driven at the same logic level.

It has been pointed out in the following Reference 3 etc. that the conventional LC has a problem in operation when VDDL is equal to or lower than the threshold voltage of MN1.
That is, in a steady state, when LC_IN is at a low level (0 V), the node Q is at a low level, and the node QB is at a high level, LC_IN is set to a high level (VDDL) and Q is changed from a low level to a high level. In this case, MN1 operates at the subthreshold, whereas MP1 operates at the superthreshold because the gate potential is 0V at the Q potential, so that the current driving capability of MN1. The current driving power of MP1 is much larger than that of MP1, and the potential of node QB cannot be lowered until MP2 becomes conductive. Therefore, Q remains at a high level and the LC purpose cannot be achieved.

An LC circuit shown in FIG. 9 in which the above drawbacks are improved is proposed in Reference 3.
The difference from FIG.
(1) A MOS diode formed by MP3 of PMOST is inserted between MP1 of PMOST and MN1 of NMOST. Similarly, a MOS diode formed by MP4 of PMOST is inserted between MP2 of PMOST and MN2 of NMOST. Being
(2) The output node Q is provided at the connection point between MP2 and MP4, and its complementary output node QB is provided at the connection point between MP1 and MP3.
(3) The gate of MP1 is connected to node N3, which is the connection point between MP4 and MN2, and the gate of MP2 is connected to node N2, which is the connection point between MP3 and MN1,
(4) Output node QB is connected to GND through MN3 of NMOST, and its gate is connected to LC_IN. Similarly, output node Q is connected to GND through MN4 of NMOST, and its gate is inverted LC_INB (LPS_INVERTER of LC_IN). Output).

  The functions of the MOS diodes MP3 and MP4 are to weaken the current driving power of the MP1 and MP2, respectively, so that the potential of the node N2 or N3 is also conducted by the MN1 or MN2 operating at the subthreshold. This LC circuit is characterized in that it can be reduced to a state. The functions of MN3 and MN4 are to prevent the low level of QB or Q from rising from the GND level (0V) by the voltage drop due to the diode consisting of MP3 or MP4 in the steady state, and to avoid adversely affecting the next stage. It is to discharge to the GND level surely.

However, when Q is at a low level and QB is at a high level in a steady state, if a high level (VDDL) is input to LC_IN to invert the state, MP2 is surely turned on and Q is at a high level (VDDH). However, MPB becomes non-conductive eventually, but the potential of QB is discharged by MN1 and MN3 operating at the subthreshold, so that QB becomes low level than the time when Q becomes high level. It is a disadvantage that the time is longer.
Each of the conventional LC circuits has a drawback that a large number of transistors are used. In FIG. 8, there are 6 (because LPS_INVERTER for generating LC_INB is also necessary), and 10 in FIG. 9 (since LPS_INVERTER for generating LC_INB is also necessary). For this reason, in order to finely design the performance of the circuit, it is disadvantageous to use it for a small partial circuit whose logic level is to be locally changed because the increase in the element area becomes remarkable.

Japanese Patent No. 3543117 U.S. Pat. No. 7,610,555

`` Modern VLSI Design (A Systems Approach) '', author Wayne (Hendrix) Wolf, PTR Prentice Hall Englewood Cliffs, New Jersey 07632, see pages 101 and fig 3-15 K. Usami and M. Horowitz: “Clustered Voltage Scaling Technique for Low-Power Design”, Proc. Of the 1995 International symposium on Low Power Design, pp.3-7. H. Shao and C-Y. Tsui: “A Robust Voltage Adaptive and Low Energy Consumption Level Converter for Sub-threshold Logic”, ESSCIRC’07 pp.312-315.

  An object of the present invention is to provide a MOS transistor circuit having a static operation level converter circuit that eliminates the above-mentioned operational disadvantages and uses a small number of transistors.

In order to achieve the above object, the present invention employs a configuration comprising the following invention specific items.
Configuration 1: A MOS transistor circuit having a level converter circuit is connected to a high potential side power line and a low potential side power line of a high power supply voltage circuit and operates as a level converter circuit, and an input node The first logic signal having the logic amplitude of the low power supply voltage circuit is supplied, the output node is connected to the input node of the first CMOS inverter, and the high power supply line and the low potential power supply line of the low power supply voltage circuit are connected. The second CMOC inverter operating and the input node connected to the output node of the first CMOS inverter, connected to the high potential side power line and the low potential side power line of the high power supply voltage circuit, and operated. And a third CMOC inverter that outputs a second logic signal having a logic amplitude of the high power supply voltage circuit at the node, and the potential of the high potential side power line of the low power supply voltage circuit and the low potential The potential of the power supply line is sandwiched between the potential of the high potential side power supply line and the potential of the low potential side power supply line of the high power supply voltage circuit, and within the voltage change range of the output logic signal of the second CMOS inverter The potential of the high potential side power supply line and the potential of the low potential side power supply line of the high power supply voltage circuit are set so that the transition region of the first CMOS inverter is included in the first CMOS inverter. And the third CMOS inverter is driven by the output logic signal of the first CMOS inverter .

Configuration 2: In Configuration 1, the threshold voltage of the NMOST used in the first CMOS inverter is obtained by subtracting the potential of the low-potential side power supply line of the high power supply voltage circuit from the potential of the low-potential side power supply line of the low power supply voltage circuit. The absolute value of the threshold voltage of the PMOST used for the first CMOS inverter is subtracted from the potential of the high power supply line of the high power supply voltage circuit from the potential of the high power supply line of the low power supply voltage circuit. It was larger than the value .
Configuration 3: In Configuration 1 or Configuration 2, the threshold voltage of the NMOST used for the first CMOS inverter is changed from the potential of the high-potential side power line of the low power supply voltage circuit to the potential of the low potential side power line of the high power supply voltage circuit. And the absolute value of the threshold voltage of the PMOST used in the first CMOS inverter is set to the value of the low-potential side power line of the low power-supply voltage circuit from the potential of the high-potential-side power line of the high-power-supply voltage circuit. The value was smaller than the value obtained by subtracting the potential .
Configuration 4: In any of compositions 1 through 3, the logic threshold voltage of the first CMOS inverter, the high-potential side power supply line of the low power supply voltage circuit of the sum of the potential of the low potential side power supply line The potential of the high potential side power supply line and the potential of the low potential side power supply line of the high power supply voltage circuit were set so as to be equal to the average value.

  In each configuration of the means for solving the above problems, the LC circuit is one first CMOS inverter on the high power supply voltage circuit side, so the number of transistors is as small as two, and the device area is reduced as compared with the conventional example. And power consumption can be reduced. Even if it is used for a local partial circuit, the increase rate of the element area and the increase rate of the power consumption can be made smaller than before.

FIG. 3 is a circuit configuration diagram in which a level converter (LC) circuit is interposed between LPS_INVERTER and HPS_INVERTER of the present invention. It is explanatory drawing of the principle of operation of the circuit structure of this invention of FIG. A circuit diagram of the CMOS inverter and its circuit symbol are shown. The definition of the term in the input-output characteristic curve of a CMOS inverter is shown. FIG. 6 is a circuit diagram in which a CMOS inverter that operates at a low power supply voltage is directly connected to a CMOS inverter that operates at a high power supply voltage in a conventional circuit in which a low-potential-side power supply voltage is shared with GND. FIG. 6 is a schematic diagram of input / output characteristics of HPS_INVERTER in FIG. 5. FIG. 6 is a circuit configuration diagram in which a level converter (LC) circuit is interposed between LPS_INVERTER and HPS_INVERTER. This is a circuit configuration of a conventional LC circuit. 9 is a circuit configuration of a conventional LC circuit improved from the example of FIG.

  An embodiment of a MOS transistor circuit provided with a level converter circuit of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit configuration diagram in which a level converter (LC) circuit is interposed between LPS_INVERTER and HPS_INVERTER according to the present invention.
In FIG.
A CMOS inverter LPS_INVERTER on the low power supply voltage circuit side that is connected to the high potential power supply line VDDL and the low potential power supply line VSSL to operate (indicated by a symbol painted on gray (meaning that the symbol inside is not white)) In the output node N1,
Connect the input node of the high power supply voltage circuit side CMOS inverter HPS_INVERTER_1 (meaning the white symbol is inside of the triangle) connected to the high potential power supply line VDDH and the low potential power supply line VSSH, and use this as the LC circuit Use
If necessary, an input node of another CMOS inverter HPS_INVERTER_2 on the high power supply voltage circuit side is connected to the output node OUT so that the inverted output of the node OUT can be taken out from the output node OUTB.

A logic signal from the low power supply voltage circuit side is input to the input node IN of LPS_INVERTER. Here, the operation of HPS_INVERTER_1 of the LC circuit is set so as to satisfy the following condition 1 when the transition region lower limit value is TRHL and the upper limit value is TRHH.
Condition 1:

  That is, while maintaining the logic amplitude on the low power supply voltage circuit side and the high power supply voltage circuit side, the logic signal on the low power supply voltage circuit side, specifically, the CMOS inverter on the high power supply voltage circuit side within the change range of the output logic signal of LPS_INVERTER The operation of LPS_INVERTER and HPS_INVERTER_1 is defined by setting VSSL, VDDL, VSSH, and VDDH together with the element parameters of each MOS transistor so that the transition region is included. In practice, one of the power supply voltages is often defined, but in that case, the other is set so as to satisfy the condition 1.

  However, there is no solution that satisfies the above condition 1 if TRH = TRHH−TRHL> LSL, but the absolute value | Vthp | of the negative threshold voltage Vthp of the NMOST and the negative threshold voltage Vthp of the PMOST is respectively calculated. By increasing it, TRH <LSL can be established. Note that there is also a transition region in LPS_INVERTER, which is designed to be sufficiently smaller than LSL so as not to hinder the operation, such as preventing the leakage current in the steady state from becoming excessively large. . If necessary, TRH can be made smaller than the transition region width of LPS_INVERTER.

As a special case, when the logical threshold value of LPS_INVERTER is set to VTLL and the logical threshold value of HPS_INVERTER_1 is set to VTLH, the element parameters and power supply voltage of each MOS transistor are set so that the above condition 1 is satisfied and VTLH = VTLL. it can. In practice, however, VTLL and VTTLH may not necessarily coincide with each other due to variations in the manufacturing process of the elements. However, if the difference is within a range that does not deviate from the operation principle described later, it can be considered that they coincide. Absent.
In order to evenly distribute the noise margin to the high level side and the low level side, it is desirable to set VTLH = (VDDH + VSSH) / 2 and VTLL = (VDDL + VSSL) / 2. Furthermore, it is desirable that the logical threshold voltage of HPS_INVERTER_2 also matches the logical threshold voltage of HPS_INVERTER_1 used in the LC circuit. The power supply voltage of the circuit on the high power supply voltage side is the same as that used for HPS_INVERTER_1 and HPS_INVERTER_2 unless the level is further converted.

  The operation principle of the present invention will be described with reference to FIG. FIG. 2 schematically shows an input / output characteristic curve (solid line) of HPS_INVERTER_1 and an input / output characteristic curve (dotted line) of LPS_INVERTER. The horizontal axis represents the input voltage (VIN) of HPS_INVERTER_1, and the vertical axis represents the output voltage (VOUT). Note that VSSL, VDDL, and VDDH of the input voltage VIN on the horizontal axis in FIG. 2 represent the same voltage values as the output voltages VSSL, VDDL, and VDDH.

LPS_INVERTER is drawn by reversing the input voltage axis and the output voltage axis so that the output voltage becomes the input voltage of HPS_INVERTER_1. As a special case, the case where VTLH = VTLL is shown. The input voltage VIN of HPS_INVERTER_1 is changed within the change range of the output logic signal voltage of LPS_INVERTER. That is, VSSL ≦ VIN ≦ VDDL. The change range of the output logic signal voltage of LPS_INVERTER includes the transition region TRH of HPS_INVERTER_1. Therefore, when VIN = VSSL, the output voltage VOUT of HPS_INVERTER_1 is not exactly equal to the high level VDDH, but becomes a value close to VDDH that can be regarded as a high level when viewed as a logic signal, and when VIN = VDDL, VOUT is strictly not equal to the low level VSSH but ing a value close to be regarded as a low level VSSH when viewed as a logic signal. Therefore, an output that can be regarded as the high logic signal amplitude LSH at the input of the low logic signal amplitude LSL can be obtained. This is because the above description assumes the following case.

  In FIG. 2, when Vthn <VSSL or | Vthp | <VDDH−VDDL, for example, when VIN = VSSL, the PMOST is sufficiently turned on, but the NMOST is not yet turned off and is in a steady state. The leakage current increases, and when VIN = VDDL, the NMOST is sufficiently turned on, but the PMOST is not yet turned off, and there is a concern that the leakage current in the steady state is also increased. Even in this case, it can be set to a potential that can be regarded as a sufficiently high level or a potential that can be regarded as a sufficiently low level. However, in order to reliably solve this, Vthn and | Vthp | It is good to satisfy.

Condition 2:
In this way, when one of the MOST and PMOST of the HPS_INVERTER_1N is reliably turned on by the logic signal from the LPS_INVERTER, the other can be turned off, and the leakage current can be reduced. Although the operation speed of HPS_INVERTER_1 is slow, it is only necessary to reduce the load to about one inverter, and since this can be done, there is no disadvantage.

further,
Condition 3:
If the above condition is added, since both the NMOST and the PMOST operate at the super threshold value in the ON state, it is possible to suppress a decrease in the operation speed.

Emphasis on operating speed, Dare condition 4:
It is also possible. Note that the input signal level of HPS_INVERTER_2 subsequent to HPS_INVERTER_1 has already been converted, so that it is not limited to the above, and a normal CMOS inverter that operates at a high power supply voltage may be used.

Even if VTLL and VTLL don't match,
Condition 5:
If the condition is satisfied, level conversion is possible.
In practice, one of the power supply voltages will often be fixed. For example, it is assumed that VSSL and VDDL on the low power supply voltage circuit side are determined. In this case, VTHL of HPS_INVERTER_1 should be determined when VDDH and VSSH are set.

Condition 6:
VDDH and VSSH may be adjusted so that. When VSSH and VDDH on the high power supply voltage circuit side are determined, VTLH is known.

Condition 7:
To VSSL and VDDL.
The LC circuit described above is not limited to the bulk type MOST, but is formed of, for example, crystalline silicon on an insulating layer on a substrate as disclosed in Patent Documents 1 and 2, and a current flows in parallel to the substrate. The present invention can also be applied to fin-type double insulated gate gate field effect transistors (two gate electrodes are integrally formed with a channel sandwiched therebetween and others are electrically separated from each other). .

MP, MP1, MP2, MP3: P-type MOS transistors MN, MN1, MN2, MN3, MN4: N-type MOS transistors VDD, VDDL, VDDH: High-potential side power supply voltages VSS, VSSL, VSSH: Low-potential side power supply voltages GND: Ground VTL, VTLL, VTLH: CMOS inverter logic threshold voltages LS, LSL, LSH: CMOS inverter logic signal amplitude TR, TRH: CMOS inverter transition region TRHL, TRHH: Transition region boundary values IN, OUT , OUTB, N1, N2, N3, Q, QB, LC_IN, LC_INB: Node
VIN: CMOS inverter input voltage VOUT: CMOS inverter output voltage LPS_INVERTER: Low power supply voltage side circuit CMOS inverter HPS_INVERTER: High power supply voltage side circuit CMOS inverter LC: Level conversion circuit

Claims (4)

A first CMOS inverter connected to the high potential side power supply line and the low potential side power supply line of the high power supply voltage circuit and operating as a level converter circuit;
The first logic signal having the logic amplitude of the low power supply voltage circuit is supplied to the input node, the output node is connected to the input node of the first CMOS inverter, and the low potential power supply line of the low power supply voltage circuit and the low potential A second CMOC inverter connected to the side power supply line and operating;
An input node is connected to an output node of the first CMOS inverter, operates by being connected to a high potential side power line and a low potential side power line of the high power voltage circuit, and the logic of the high power voltage circuit is connected to an output node. A third CMOC inverter for outputting a second logic signal of amplitude;
The potential of the high potential side power line and the potential of the low potential side power line of the low power supply voltage circuit are the potential of the potential of the high potential side power line and the potential of the low potential side power line of the high power supply voltage circuit. The potential of the high-potential-side power supply line of the high-power-supply voltage circuit so that the transition region of the first CMOS inverter is included in the voltage change range of the output logic signal of the second CMOS inverter. And the potential of the low potential side power supply line are set, the first CMOS inverter is driven by the output logic signal of the second CMOS inverter, and the third CMOS inverter is driven by the output logic of the first CMOS inverter. A MOS transistor circuit having a level converter circuit characterized by being configured to be driven by a signal . The threshold voltage of the NMOST used for the first CMOS inverter is set larger than a value obtained by subtracting the potential of the low potential side power line of the high power supply voltage circuit from the potential of the low potential side power line of the low power supply voltage circuit. The absolute value of the threshold voltage of the PMOST used for the first CMOS inverter is obtained by subtracting the potential of the high potential side power line of the low power source voltage circuit from the potential of the high potential side power source line of the high power source voltage circuit. 2. A MOS transistor circuit comprising a level converter circuit according to claim 1, wherein the MOS transistor circuit is larger than the value . The threshold voltage of the NMOST used for the first CMOS inverter is set to be smaller than a value obtained by subtracting the potential of the low potential side power line of the high power supply voltage circuit from the potential of the high potential side power line of the low power supply voltage circuit. The absolute value of the threshold voltage of the PMOST used for the first CMOS inverter is obtained by subtracting the potential of the low potential side power line of the low power source voltage circuit from the potential of the high potential side power line of the high power source voltage circuit. MOS transistor circuit having a level converter circuit according to claim 1 or 2, characterized in that the smaller than the value. The high power supply voltage is set so that a logic threshold voltage of the first CMOS inverter is equal to an average value of the sum of the potential of the high potential power supply line and the potential of the low potential power supply line of the low power supply voltage circuit. MOS transistor having a level converter circuit according to any one of claims 1 to 3, characterized in that the potential of the high potential side power supply line potential and the low potential side power supply line of the voltage circuit is set circuit.