JP5139568B2 - Multi-value buffer means - Google Patents

Description

The first invention is in that to numbers used (or meaning or content) are three or triplicate above defined potential and the potential (or each voltage) and its respective numerical values to its use corresponding one-to-one The present invention relates to a multi-value buffer means in a mode (or voltage mode) . This multi-value buffer means can be multi-value storage means , multi-value (or multi-adic) memory cell, multi-value (or multi-adic) memory, (external) multi-value (or multi-adic) information storage means or multi-stable It can be used as a circuit configuration means .
Further, this multi-value buffer means can be used as a multi-value (or multi-adic) logic circuit, a multi-value (or multi-adic) arithmetic circuit, a multi-value computer (or a multi-adic computer, particularly 4, 8, "10", 16 32, 64, “100”, 128-base computer, etc.), various multi-value modulation communication means such as in-vehicle, wireless or wired, multi-value recording means or multi-value (or multi-adic) control means it can be.
The second invention relates to a multi-value buffer means having the same functions and effects as those of the first invention, a smaller number of parts than the first invention, and a simple configuration.

The problems of the multi-value buffer means shown in FIGS. 10 and 11 considered by the inventor prior to the first invention will be described. In these “multi-value buffer means of L (≧ 3) value in FIG. 10 and ternary multi-value buffer means in FIG. 11” , most or one of each pull means (= each pull-up means and each pull-down means). As a result of incorporating a “diode means such as a diode with forward voltage (or forward voltage)” in the section, there are the following two problems , and the first invention can solve these two problems .
(A) the forward voltage of each output voltage to the ON voltage of the respective pull means is increased, the difference between the respective output voltages, a result of the difference is small, "the noise immunity is reduced, the next stage circuitry There is easily affected by the noise, the input potential, it becomes easy to determine the mistake such as an input numerical value corresponding to the input voltage ". →→ Reference: Non-Patent Documents 1-6 listed later.
(B) therefore their respective pull means by the presence of the forward voltage can not be reduced firmly pull than its forward voltage becomes like the original source potential (or power supply voltage) around an open condition to be output is the means to pull That is, since the output impedance becomes large, “ the output signal is likely to be subjected to noise, and the next-stage circuit amplifies the noise and has other adverse effects”.

Here, the multi-value buffer means of FIG. 10 having the L value buffer function will be described. All the MOS FETs are normally-off type, and the potentials of the power supply line V ₀ to the power supply line V _L−1 , that is, the potential v ₀ to the potential v _L−1 are sequentially increased. Is connected to the power supply line V _{0 ~} power supply line V _L-1 between the & 2 power line "binary buffer means connected 2-stage binary inverter means" one by one, a total of (L -1) pieces there .
Connected to each line of the power supply lines _{V 1} ~ power supply line _{V L-2} "series circuit of a diode and NMOS-FET" and "PMOS-FET and the series circuit of the diode" is oneway on-off control switching both Means, and can be kept off with respect to the reverse voltage even during on-drive.
The diodes DU ₁ to DU _L-2 and DL _{2 to} DL _L-1 are connected so that a power supply short circuit does not occur when the ( L- 1) binary buffer means cooperate to perform L value buffer operation. Has been. Normally, the potential v _{0 is changed} to the numerical value “0”, the potential v _{1 is changed} to the numerical value “1”, the potential v _{2 is changed} to the numerical value “2”, and similarly, the potentials are sequentially changed to the potential v _L−1. The potential v _L−1 is made to correspond to the numerical value “ L −1”. Of course, other uses are possible.

To describe concretely operation, the potential _{v 0} is input to the input terminal Tin, the transistor _{QL 1 ~QL L-1} when the output terminal Tout is output potential _{v 0} but is on, diode _DL 2 through DL _L-1 prevents power shorting transistor _QL 2 _{~QL L-1} and the transistor QL _1.
The potential _{v L-1} is input to the input terminal Tin, although the transistor _{QU 1 ~QU L-1} when the output terminal Tout is output potential _{v L-1} is ON, the diode _DU 1 _{~DU L-2} There prevents power shorting transistor _{QU L-1} and the transistor _QU 1 _{~QU L-2.}
Furthermore, the potential _{v 1} is input to the input terminal Tin, the transistor QU ₁ and _QL 2 _{~QL L-1} when the output terminal Tout is output potentials _{v 1} is on, the diode _DL 3 _{~DL L-1} is A power supply short circuit between the transistors QL _{3 to} QL _L-1 and the transistor QL ₂ is prevented.
Moreover, at this time, the parallel circuit of “the series circuit of the transistor QU ₁ and the diode DU ₁ ” and “the series circuit of the diode DL ₂ and the transistor QL ₂ ” is substantially bi-directional pull means, that is, “pull-up or pull- "Means to go down".
Similarly, when the potentials v ₂ to v _L−2 are sequentially input to the input terminal Tin, and the output terminal Tout sequentially outputs the potentials v ₂ to v _L−2. A similar parallel circuit substantially constitutes a bidirectional pulling means.
Note that the multi-value buffer means of FIG. 11 is the case where L = 3 in the multi-value buffer means of FIG.

From here , two problems, such as the multi-value buffer means of FIG. 10, are explained in full detail. While the the higher e.g. transistors _QU 1, QL ₂ is an upper limit of the potential of preparative-out output terminal T out of the on the forward voltage of the diode DL ₂ (sentence) extra multilevel buffer means 10, the transistors _QU 2, since QL ₃ is the lower limit of the potential of preparative-out output terminal T out of the on is the forward voltage of the diode DU ₂ (sentence) extra low, the difference between the potential v ₂ output and the potential v ₁ output, the difference becomes smaller End up. The same applies to other potential outputs.
As a result, for most of the pull means is built-in "diode means with a forward voltage", "the noise immunity is reduced, the next stage circuitry is susceptible to noise Runode, the input potential becomes easy determination is inaccurate such as an input value corresponding to the input voltage ". (First issue)

In general, the normal forward voltage of a signal diode is about 0.6 volts, and as can be seen from the voltage-current characteristics of the diode, the forward current is very small so that the forward voltage is close to zero volts. Must be a value. For this reason, when each “pull means with built-in diode means” pulls up or down something, it can pull firmly even if it tries to pull at a forward voltage of almost zero volts. It ca n't be done , it only pulls very weakly.
In other words, the pull means cannot pull firmly within a voltage range smaller than the normal forward voltage, so that the pull means is in an open state near the original power supply potential (or power supply voltage) to be output. Become. That is, the output impedance becomes large. As a result, “ the output signal is likely to be subjected to noise, and the next-stage circuit amplifies the noise and has other adverse effects”. (Second problem)

Patent No. 2853041 (multi-value storage means, application of the present inventor) JP 2004-88763 (same as above) Japanese Patent Application No. 2004-303564 (same as above)

“Introduction to Transistor Circuit Lecture 5: Digital Circuits”, p. 46-p. 47 “4.6 Notes on using logic circuits [1] Logic voltage level and noise margin”. Supervision: Yoshifumi Amemiya and Nori Koshiba. Authors: Kensuke Shimizu and Masahiro Masakazu. Issued on May 20, 1981 by Ohm Co., Ltd. “Digital Digital Circuits Understandable”, p. 76-p. 80 [[1] logic level to [2] noise margin]. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 126-p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. “Pulse Digital Circuit”, p. 125-p. 130 “5. Basic characteristics of circuit 5.1 Amplitude characteristics of pulse digital circuit ”. Author: Akira Kawamata. Published by Nikkan Kogyo Shimbun on February 15, 1995. “Pulse and digital circuit”, p. 128 “Threshold Level” and p. 129 “Logical Level”. Edit: Masao Yoneyama. Author: Shigeyuki Ohara, Sumio Yoshikawa, Toshio Shinozaki, Shiro Takahashi. Published by Tokai University Press on April 5, 2001. “Practical Introduction Series: How to Use CMOS Circuit [1]”, “Element Threshold Voltage” on page 44 and “Circuit Threshold Voltage” on page 50. Author: Yasoji Suzuki. Published on October 15, 1997 by the Industrial Research Committee.

■■ Problems to be solved by the first invention ■■
Each multi-value buffer means of FIGS. 10 and 11 has the following two problems.


★ a) for each pull means is a built-in "diode means with a forward voltage", "Sono noise margin is reduced, Runode Sono next-stage circuit is susceptible to the influence of noise, the input voltage, the input voltage would Tsu an easy determination is a mistake such as an input value corresponding to ". (First issue)
* B) Because the pull means becomes open near the original power supply potential (or power supply voltage) to be output, that is, the output impedance becomes large. noise rides easily a Runode, the next-stage circuit will adversely affect the other amplifies the noise "on. (Second problem)

Accordingly, the first invention aims to provide multi-value buffer means having the following characteristics. (Object of the first invention)


★ a) from each pull means does not have a built-in "diode means with a forward voltage," "that noise margin is increased, Runode Sono next-stage circuit is hardly affected by noise, the input numerical values of the determination is that a difficult mistake ".
* B) Moreover, since each pull means does not include a diode means, the pull means does not become an open state near the original power supply potential (or power supply voltage) to be output, that is, its output impedance. since does not increase, "the output signal to noise is hardly ride Runode, the next-stage circuit does not easily affect the other is reduced to amplify the noise."

■■ Problems to be solved by the second invention ■■
In any field, “the same function and the same effect are desired, but a small number of parts, a simple structure, and a low production cost are desired”. The same applies to the first invention. ( Task )
Therefore, the second invention is to provide a "same functionality as the multi-level buffer means in the first invention, while having the same effect, small-parts, simple structure, the multi-level buffer means which can be realized at low-production cost" It is an object. (Object of the second invention)

■■ Means for the first invention to solve the problem ■■
That is, the first invention,
When L represents a predetermined plurality of 3 or 3 or more,
Having a first potential supply means to an Lth potential supply means for supplying L potentials that increase in potential in numerical order from the first potential to the Lth potential;
A "first binary inverter means, in" Nomaryi off, and on-off controllable output pull-up switching means, in Nomaryi off, the on-off controllable output pull-down switching means One binary buffer means having a second binary inverter means connected to a subsequent stage of the first binary inverter means , one by one, between the two potential supply means adjacent to each other by number. Provided for each,
In each of the binary buffer means except the uppermost binary buffer means, instead of the output pull-up switching means, “the output pull-up switching means” and “normally off, the on drive voltage polarity is plus, 2 at both can replace the role of the "main electrode or the main terminals" is put together I by the direction of the applied voltage between the two "main electrode or main terminals", the next higher first Using a series circuit of "first on / off control switching means using the output signal of the value inverter means as a drive signal"
In each of the binary buffer means except the lowest binary buffer means, the output pull down switching means and the output pull down switching means are normally off and the on drive voltage polarity is minus, that both can be interchanged "main electrode or the main terminals" role of each other I by the direction of the applied voltage between the two "main electrode or the main terminals", one lower of said first 2 A series circuit of "second on / off control switching means using the output signal of the value inverter means as a drive signal"
"Inlet means from which signals are input" of each of the first binary inverter means are connected together to form one inlet means;
Each of the second binary inverter means is a multi-value buffer means in which “exit means from which signals are output” are connected together to form one exit means .
However, in each of the former (L-2) series circuits, the two switching means are both of the four-terminal insulated gate type, or each of the latter (L-2) series circuits. In the case where the two switching means are both of the four-terminal insulated gate type, L is 4 or 4 or more.

Thereby, in the first potential supply means - the first L potential supplying means, the binary buffer means between each of the two potential supply means comprising a between neighboring in number are provided one by one, a total of ( L -1) pieces of the binary buffer means is. As described above (paragraph number [0012]), each of the binary buffer means that are in a vertical relationship with each other is not short-circuited with the power supply means between the potential supply means . A first on / off control switching means for reverse blocking is connected in series to form a series circuit for output pull-up, and a second on-off for reverse blocking is also connected to each specific output pull-down switching means. Control switching means are connected in series one by one to form an output pull-down series circuit.
In addition, a parallel circuit of “the output pull-up series circuit and the output pull-down series circuit” is connected to each of the second to ( L- 1) potential supply means. Each parallel circuit substantially functions as a bidirectional pulling means. As a result, ( L- 1) pieces of the binary buffer means cooperate to function as a multi-value buffer means.
At that time, the outlet means thereof all binary buffer means: in (eg. Output terminals, etc.) each binary buffer means excluding the binary buffer means uppermost as no problem even if connected to its When the output pull-up switching means is on and a reverse voltage is applied to the “series circuit of the output pull-up switching means and the first on / off control switching means”, the first on / off control is performed. The switching means is driven off to prevent its reverse voltage, while its output pull-up switching means is on and when the forward voltage is applied to the series circuit, the first on / off control switching means Are also driven on, and the series circuit performs an output pull-up operation.
Then, also hinder its output pull-down switching means in each binary buffer means excluding the least significant of said binary buffer means as there is no is on, the "output pull-down switching means and the second on When the reverse voltage is applied to the "series circuit of off- control switching means", the second on-off control switching means is driven off to block the reverse voltage, while its output pull-down switching means When ON is applied and a forward voltage is applied to the series circuit, the second on / off control switching means is also driven on, and the series circuit performs an output pull-down operation.

Incidentally, the first potential at Honda value buffer means is input to said inlet means, when said outlet means you outputs the first potential, "connected output pull-down to the first potential supply means "Switching means" is ON, " Output pull-up switching means connected to the L-th potential supply means " and each "Parallel circuit of the output pull-up series circuit and the output pull-down series circuit" Is off.
Further, said first L potential in Honda value buffer means is input to said inlet means, wherein when the outlet means you output the first L potential, "the first L potential is connected to the supply means output pull-up The “ switching means ” is on, and the “ output pull-down switching means connected to the first potential supply means ” and the above parallel circuits are off.
Further, "one of the second potential-that the (L -1) potential, certain potential" in Honda value buffer means is input to said inlet means, when said outlet means you output the potential, the potential “All the output pull-down switching means above that potential and above that potential” and “all the output pull-up switching means below that potential and below that potential” are turned on. However, even if these are on the drive, the "each said output pull-up with respect to reverse voltage by the action of as described above and the first on-off control the switching means each second on-off control the switching means Since the series circuit for output and each of the output pull-down series circuits are turned off, only the parallel circuit of the potential is turned on bidirectionally and functions as bidirectional pulling means, so that a power supply short circuit does not occur.

In the multi-value buffer means described in paragraph [0012], each of the output pull-up / switching means, each of the output pull-down switching means, each of the first on / off control switching means, or In some cases, each of the second on / off control switching means is “a three-terminal FET whose back gate and source are connected and whose drain is connected to the outlet means side”.
→→ Corresponds to the multi-value buffer means according to claim 2.

(2) In the multi-value buffer means described in paragraph [0012], “each of the first on / off control switching means or each of the output pull down down switching means is a four-terminal N-channel FET and its back gate When the back gate is connected to the first potential supply means or the “potential supply means having a lower potential than this” so that neither the source PN junction nor the back gate / drain PN junction is conducted ”or“ each The output pull-up switching means or each of the second on / off control switching means is a four-terminal P-channel FET so that neither the back gate-source PN junction nor the back gate-drain PN junction is conductive. In the case where the back gate is connected to the L-th potential supply means or "potential supply means having a higher potential" That.
→→ Corresponds to the multi-value buffer means according to claim 3.

In the multi-value buffer means described in paragraph [0012], each switching means is “a“ bipolar transistor having one end of a base current limiting means connected to its base ”. In some cases, the transistor means has an end as its control terminal.
→→ Corresponds to the multi-value buffer means according to claim 4.

■■ Means for the second invention to solve the problem ■■
That is, the second invention is
In each of the potential supply means of the second potential supply means to the ( L- 1) th potential supply means, the “series circuit for output pull-up and the output pull-down series connected to the potential supply means” both series circuit "function as bidirectional pull means, if the two functions are mapped twice, of pre SL series circuit that will be connected by two to each of its potential supplying unit, detached one by one or the other The multi-value buffer means described in paragraph number [0012], paragraph number [0015], paragraph number [0016] or paragraph number [0017] .
→→ Corresponds to the multi-value buffer means according to claim 5.

In the above-mentioned (= mentioned paragraph [00 12-00 17]) multilevel buffer means in the first invention, "the potential supply in each potential supplying means of said second voltage-the third (L -1) potential Both the series circuit for output pull-up connected to the means and the series circuit for output pull-down function as bidirectional switching means, that is, bidirectional pull means, and these functions are prominent. because the second invention is "out of the previous SL series circuit that will be connected by two to each of its potential supplying means, the multilevel buffer means configured removed one by one or the other."

■■ Effect of the first invention ■■
As a result, the multi-value buffer means of the first invention has the following effects.



★ a) from each pull means does not have a built-in "diode means with a forward voltage", "the noise immunity is increased, Runode the next-stage circuit is hardly affected by noise, the input numerical values It ’s hard to make a mistake ” .
* B) Moreover, since each pull means does not include a diode means, the pull means does not become an open state near the original power supply potential (or power supply voltage) to be output, that is, its output impedance. since is not increased, "because each pull means can be firmly pulled, hardly take the noise output signal, the next-stage circuit does not easily affect the other is reduced to amplify the noise."

Incidentally, ~ the second potential supply means multilevel buffer means in the first invention the (L -1) potential supplying unit and its outlet means (eg. Output terminal or the like) substantially interactivity between each of it means that the pull means is configured, for example, can an external data line is connected to the outlet means, even if the potential of the external data lines but intends intends Takakaro but Hikukaro than the potential of the outlet means, the The external data line is pulled up or down depending on the output potential .

■■ Effect of the second invention ■■
As a result, the multilevel buffer means of the second invention, since only the just detached "configuration means the feature is mapped twice" in the multi-level buffer means in the first invention, the second invention, and functions of the first invention while it has the effect, it is possible to realize a small number of components than the first invention, a simple structure and low have manufacturing cost.

It is a circuit diagram showing one embodiment of the first invention. It is a circuit diagram showing one embodiment of the first invention . It is a circuit diagram showing one embodiment of the first invention. It is a circuit diagram showing one embodiment of the first invention. It is a circuit diagram showing one embodiment of the first invention. It is a circuit diagram showing one embodiment of the first invention. It is a circuit diagram showing one embodiment of the first invention. It is a circuit diagram showing one embodiment of the first invention. It is a circuit diagram which shows one Example of 2nd invention. FIG. 7 is a circuit diagram showing an example of the multi-value buffer means of the present inventor used for explaining the effect of the present invention instead of the conventional circuit. FIG. 7 is a circuit diagram showing an example of the multi-value buffer means of the present inventor used for explaining the effect of the present invention instead of the conventional circuit.

In order to explain each invention in more detail, this will be described with reference to the accompanying drawings. Note that represents the potential of the power supply line _{V 0} at a potential _{v 0} represents the potential of the power source line _{V 1} at a potential _{v 1,} the potential of each potential similarly after the power supply line _{V 2} to the power supply line _{V 9 v 2} ~ potential v is represented by _9. Further, the potential increases in order from the potential v ₀ to the potential v ₉ .

The embodiment 1 shown in FIG. 1 is a 10-value multi-value buffer means, and the above-mentioned L is 10, and the conductors having the same reference numerals with respect to the symbols s 0 to s 5 are in a conductive state. All the MOS FETs are normally off type, ie, enhancement mode FETs, and one binary CMOS buffer means is connected between each power supply line, and there are nine in total. 1 correspond to the constituent means in claim 1 as follows.
★ a) The potential v ₀ to the potential v ₉ are sequentially applied to the first potential to the Lth potential in the same paragraph.
* B) The power supply line V ₀ to the power supply line V ₉ are sequentially supplied to the first potential supply means to the Lth potential supply means in the same paragraph.
★ c) input terminal T in is the inlet mouth means in according paragraph.
* D) The output terminal Tout is the outlet means described in the same paragraph.
★ e ) Nine binary CMOS buffer means connected one by one between each power supply line V ₀ to power supply line V _{9 to} the binary buffer means described in the same paragraph.
* F ) Each of the transistors 1c to 9c is connected to the output pull-up switching means described in the same paragraph.
* G ) Transistors 1d to 9d are respectively connected to the output pull-down switching means described in the same paragraph.
* H ) The transistors 1e to 8e are respectively connected to the first on / off control switching means described in the same paragraph.
I ) Each of the transistors 2f to 9f is used for each of the second on / off control switching means described in the same paragraph.
★ j ) Each series circuit of transistors “1c, 1e”, “2c, 2e”,..., “8c, 8e” is replaced with each series circuit for output pull-up described in the same paragraph.
* K ) Each series circuit of transistors “2f, 2d”, “3f, 3d”..., “9f, 9d” is replaced with each series circuit for output pull-down described in the same paragraph.

As does not occur supply short circuit be combined into output output one terminal T out by connecting the terminal of the full binary CMOS buffer means, transistor 1c~8c "the opposite direction reverse its voltage during each on-period Each of the reverse blocking transistors 1e to 8e that is off when a voltage is applied blocks the reverse voltage during the ON period of each of the transistors 2d to 9d, and “the reverse blocking transistor 2f that is off when the reverse voltage is applied”. ~ 9f each "will block.
For example the potential _{v 1} is input to the input terminal Tin, when the transistor output terminal Tout is you output potential _{v 1} "2a~9a, 2d~9d, 1c, 1b" is on, the transistor "2C～9c, 2B- Since 9b, 1a, 1d "is off, the transistors" 1e-8e, 2f "are on and the transistors" 3f-9f "are off.
As a result, these transistors do not short-circuit the power supply lines. That is, a power supply short circuit does not occur. When the output voltage _{v 1,} is ON transistor "2f, 2d, 1c, 1e 'is conduction between the power supply line _{V 1} and output terminal T out bidirectionally, these transistors bidirectional pull means ( Pull-up or pull-down means) and essentially constitute a bi-directional pull means. Such bidirectional pull means is configured in the same manner not only when inputting / outputting the potential v ₁ but also when inputting / outputting each potential of the potentials v _{2 to} v ₈ .

In addition,
For example, the potential v _{0 is used in correspondence} with the numerical value “0”, the potential v ₁ is the numerical value “1”, the potential v ₂ is the numerical value “2”,..., And the potential v ₉ is the numerical value “9”. . Of course, it is possible to use each power supply potential in correspondence with an arbitrary code, meaning, or content. For example, numerical values “−2” to “7” or characters “a” to “j” may be used instead of the numerical values “0” to “9”. The usage of other embodiments is the same.
Also,

If the on-drive voltage polarity is the same as each FET, instead of each FET, “normally-off control electrode insulation type switching means in which the roles of both main electrodes can be interchanged depending on the direction of the applied voltage” one by one Can be used.
Further , each of the back gates of the transistors 1a to 9a is connected to its source or “a power supply line having a higher potential than that source”, and each of the back gates of the transistors 1b to 9b is connected to its source or “a power supply line having a lower potential than that source”. Etc. ".
On the other hand, the back gate of each of the transistors 2f to 9f is connected to the source, but the power line V ₉ (or the power line) so that the back gate-source PN junction and the back gate-drain PN junction are not conductive. it may be connected to the high power line, etc. "of potential than V _9.
Similarly, the back gates of the transistors 1e to 8e are connected to the sources thereof, but the power supply line V ₀ (or the power supply) is used so that the back gate / source PN junction and the back gate / drain PN junction do not conduct. it may be connected from the line V ₀ to a low supply line, etc. "of potential.
By the way, the reverse blocking transistors “1e to 8e, 2f to 9f” have their drain and source roles interchanged depending on the applied voltage direction between their drains and sources. May be actively used as a built-in diode. This also applies to each embodiment using a MOS • FET described later.

Between the power supply line V ₂ · power supply line V ₁ in the embodiment of FIG. 1 "(not shown.) Power and binary buffer means" Remove both power supply line is directly connected to the power supply line V ₂ and the power supply line V ₁ , A gate of the transistor 1e is connected to both drains of the transistors 3a and 3b, and an embodiment of a nine-value multi-value buffer means in which the gate of the transistor 3f is connected to both drains of the transistors 1a and 1b is possible. Further, the “power supply (not shown) and binary buffer means ” between the power supply line V ₃ and the power supply line V ₂ are removed, and the power supply lines V _{1 to} V ₃ are directly connected to share the three power supply lines. An embodiment of an eight-valued multi-value buffer means in which the gate is connected to both drains of the transistors 4a and 4b and the gate of the transistor 4f is connected to both drains of the transistors 1a and 1b is possible.
Similarly, 7-value to 3-value multi-value buffer means can be made in the order of "Removal of power supply and binary buffer means , common use of power supply lines, and reconnection of gates" in order. become. These things the same in each of the other embodiments described later, can be configured different embodiment of the multi-level number (e.g., if .10 value that the L value of the L 10. after this called.). (Derived Example)

Example 2 3 is a multi-level buffer means 4 values that have changed 4 value buffer means 10 value buffer means in the embodiment 1 in FIG. 1.

In the fourth embodiment shown in FIG. 3 , the upper and lower connections of the transistors “1e and 1c, 2e and 2c..., 8e and 8c” and the transistors “2d and 2f, 3d and 3f. .., 9d and 9f "are 10-value multi-value buffer means in which the upper and lower connections are interchanged.
In this case, the transistors 1c~8c or respective back gates connected to its source, or, the back gate-source PN junction and its back gate-drain PN junction power supply line V ₉ so as not to conduct _(or power to connect the line V ₉ to the high power line, such as "the potential.
Similarly, the back gate of each of the transistors 2d to 9d is also connected to the source thereof, or the power line V ₀ (or the power line) so that the back gate-source PN junction and the back gate-drain PN junction are not conductive. to connect from V ₀ to a low supply line such as "the potential.
On the other hand, the back gates of the transistors 1e to 8e are connected to their sources, but may be reconnected to “a power supply line lower than their source potential”.
The back gates of the transistors 2f to 9f are connected to their sources, but may be reconnected to “a power supply line higher than their source potential”.
Note that wire together with the same reference numerals with respect to reference numerals t 0 t5 in FIG. 3 is in the connected state.

In the fifth embodiment shown in FIG. 4 , the ten-value buffer means is changed from the ten-value buffer means in the first embodiment shown in FIG. 1, and a PNP transistor with a base current limiting means is used instead of each P-type MOS.FET. NPN transistors with base current limiting means are used in place of the type MOS • FETs, and the roles of the collector and the emitter of the transistors 11e to 13e and the transistors 12f to 14f are set in accordance with the direction of the applied voltage between the collector and the emitter. This is a five-value multi-value buffer means using something that can be replaced.
Since the input resistance of the potential (or voltage) discriminating means of the next stage circuit connected to the output terminal Tout is large, each on-driving transistor is overdriven and is in a supersaturated state, and the on-voltage is in the normal order of the diode. Small compared to voltage. The same applies to Examples 5 to 6 described later.

The sixth embodiment shown in FIG. 5 uses a PNP transistor with base current limiting means instead of each P-type MOS.FET in the third embodiment of FIG. 2 , and has base current limiting means instead of each N-type MOS.FET. Using an NPN transistor, each of the transistors 11e to 12e and transistors 12f to 13f has a quaternary value using the collector and emitter whose roles can be interchanged depending on the direction of the applied voltage between the collector and the emitter. Multi-value buffer means.

In the seventh embodiment shown in FIG. 6 , the ten-value buffer means is changed from the ten-value buffer means to the five-value buffer means in the fourth embodiment shown in FIG. 3 , and a PNP transistor with a base current limiting means is used instead of each P-type MOS FET. NPN transistors with base current limiting means are used in place of the type MOS • FETs, and the roles of the collector and the emitter of the transistors 11e to 13e and the transistors 12f to 14f are set in accordance with the direction of the applied voltage between the collector and the emitter. This is a five-value multi-value buffer means using something that can be replaced.

FIG Example 8 shown in 7 (not shown.) All "Power between the input terminal T in and an output terminal power supply line _{V 8} · power supply line _{V 1} leaving Tout in the embodiment of FIG. 3 and circuit configuration Remove the parts ", directly connected to the power supply line V ₈ and the power supply line V ₁ in common both supply line, connects the gate of transistor 1e transistors 9a, both the drain of 9b, the gate transistors 1a of the transistor 9f, 1b These are ternary multi-value buffer means connected to both drains.
That is, it is the power supply line _{V 9} · power supply line _{V 8} between binary buffer means, the power supply line _{V 1} · power supply line _{V 0} between binary buffer means, and was equal to connect the output terminal Tout and the input terminal T in 3 Value buffer means.
Other binary buffer means likewise its uppermost in each example, the least significant binary buffer means, and, like that directly connects the two binary buffer means leaving only the output terminal Tout and the input terminal T in the vertical Thus, a ternary buffer means can be configured. (Derived Example)

Example 9 shown in FIG. 8, (not shown.) All "power between input terminal T to leave in the output terminal Tout power supply line V ₈ · power supply line V ₁ in the embodiment of FIG. 1 with the circuit Remove the Assembly ", directly connected to the power supply line V ₈ and the power supply line V ₁ in common both supply line, connects the gate of transistor 1e transistors 9a, both the drain of 9b, the gate transistors 1a of the transistor 9f, A ternary multi-value buffer means connected to both drains 1b.

Example 1 0 shown in FIG. 9 (second invention), the transistor "1c~8c, 1e~8e" in the embodiment of FIG. 1 Remove a 6 value was changed to 6 value buffer means 10 value buffer means multi Value buffer means. In the embodiment of FIG. 1, both the series circuit of the transistors 1c and 1e and the series circuit of the transistors 2f and 2d function as bidirectional pulling means, and have only one function. Therefore, one of them can be removed.
Similarly, “series circuit of transistors 2c and 2e and series circuit of transistors 3f and 3d”, “series circuit of transistors 3c and 3e and series circuit of transistors 4f and 4d”,..., “Series circuit of transistors 8c and 8e The same can be said for each of the "series circuit of transistors 9f and 9d", and one of the series circuits can be removed one by one.
Similarly, in each of the first to tenth embodiments of the first invention, either one of the same two series circuits can be removed one by one, and this embodiment can be removed from the multi-value buffer means of the second invention. This is an example (derived example).
* Contrast: A multi-value AND circuit (paragraph number 0032) disclosed in Japanese Patent Application Laid-Open No. 2004-32702 with one input terminal.

A supplementary explanation will be given at the end. For convenience of explanation, an input terminal, an output terminal (claim 1 Input mouth means in described, corresponds to the outlet means.) And he called, but does not actually exist as a terminal, it is often like a mere conductor and electrode. This is the same as what is called a base terminal, a base electrode, and a base lead wire of a transistor, for example.
For example , a series circuit of PMOS and NMOS is more advantageous in terms of on-voltage than a series circuit of MOS.FET and diode. Because it requires there always consider the voltage drop of the forward voltage of the I diode, since in its series circuit requires only the sum of both the on-resistance is the need, by reducing the respective on-resistance.

In particular, "the number of parts is small, with a simple configuration, the second shot Akira manufacturing cost is low," it has a high industrial applicability

Claims (5)

When L represents a predetermined plurality of 3 or 3 or more,
Having a first potential supply means to an Lth potential supply means for supplying L potentials that increase in potential in numerical order from the first potential to the Lth potential;
A "first binary inverter means, in" Nomaryi off, and on-off controllable output pull-up switching means, in Nomaryi off, the on-off controllable output pull-down switching means One binary buffer means having a second binary inverter means connected to a subsequent stage of the first binary inverter means , one by one, between the two potential supply means adjacent to each other by number. Provided for each,
In each of the binary buffer means except the uppermost binary buffer means, instead of the output pull-up switching means, “the output pull-up switching means” and “normally off, the on drive voltage polarity is plus, 2 at both can replace the role of the "main electrode or the main terminals" is put together I by the direction of the applied voltage between the two "main electrode or main terminals", the next higher first Using a series circuit of "first on / off control switching means using the output signal of the value inverter means as a drive signal"
In each of the binary buffer means except the lowest binary buffer means, the output pull down switching means and the output pull down switching means are normally off and the on drive voltage polarity is minus its both can interchanged "main electrode or the main terminals" role of each other I by the direction of the applied voltage between at both "main electrode or main terminals", one lower of said first 2 A series circuit of "second on / off control switching means using the output signal of the value inverter means as a drive signal"
"Inlet means from which signals are input" of each of the first binary inverter means are connected together to form one inlet means;
Multi-value buffer means characterized in that "exit means from which signals are output therefrom" of each of the second binary inverter means are connected together to form one exit means.
However, in each of the former (L-2) series circuits, the two switching means are each a four-terminal insulated gate type, or in the latter (L-2) series circuits. When both of the two switching means are of the 4-terminal insulated gate type, L is 4 or 4 or more. Each output pull-up switching means, each output pull-down switching means, each first on / off control switching means, or each second on-off control switching means 2. The multi-value buffer means according to claim 1, wherein the back-gate and the source are connected, and the drain thereof is a three-terminal FET connected to the outlet means side . “The first on / off control switching means or the output pull down switching means is a four-terminal N-channel FET, and its back gate-source PN junction is also its back gate-drain PN junction. The back gate is connected to the first potential supply means or “potential supply means having a lower potential than that” or “the output pull-up switching means or the second on / The off-control switching means is a four-terminal P-channel FET, and the back gate is connected to the L-th potential supply means so that neither the back gate-source PN junction nor the back gate-drain PN junction is conducted. 2. The multi-value buffer means according to claim 1, wherein the multi-value buffer means is connected to a high potential supply means. Each of the switching means is “a bipolar transistor in which one end of a base current limiting means is connected to the base thereof, but the other end of the base current limiting means is a transistor means having a control terminal”. The multi-value buffer means according to claim 1. In each of the potential supply means of the second potential supply means to the ( L- 1) th potential supply means, the “series circuit for output pull-up and the output pull-down series connected to the potential supply means” both series circuit "function as bidirectional pull means, if the two functions are mapped twice, of pre SL series circuit that will be connected by two to each of its potential supplying unit, detached one by one or the other 5. The multi-value buffer means according to claim 1, 2, 3 or 4.

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