JP5048315B2 - Logic circuit and its application circuit - Google Patents

Description

  The present invention relates to a logic circuit. In particular, the present invention relates to a logic circuit having transistors of the same type and a circuit to which the logic circuit is applied.

FIG. 1 shows a conventional logic circuit 10 having transistors of the same type only. FIG. 2 shows an equivalent circuit of the logic circuit 10. The logic circuit 10 includes a first p-type metal oxide semiconductor transistor 12, a second p-type metal oxide semiconductor transistor 14 in series with the first p-type metal oxide semiconductor transistor 12, a first p-type metal oxide semiconductor transistor 12, and a first p-type metal oxide semiconductor transistor 12. An output capacitor 16 connected to the 2p-type metal oxide semiconductor transistor 14 is provided. The logic circuit 10 is a negative circuit.
The operation of the logic circuit 10 will be described with reference to FIG. FIG. 3 shows an oscillogram of the logic circuit 10. When the input voltage Vin at the input terminal IN of the logic circuit 10 is low (logic low), the output voltage Vout at the output terminal OUT of the logic circuit 10 is VDD * R2 / (R1 + R2). Here, R1 is the on-resistance (operation impedance) of the first p-type metal oxide semiconductor transistor 12, and R2 is the on-resistance of the second p-type metal oxide semiconductor transistor 14. As shown in the equivalent circuit, a voltage divider is formed by the first p-type metal oxide semiconductor transistor 12 and the second p-type metal oxide semiconductor transistor 14. On the other hand, when the input voltage Vin is a high voltage (logic high) HIGH, the output voltage Vout is Vth. Here, Vth is a threshold voltage of the second p-type metal oxide semiconductor transistor 14.

The logic circuit 10 is equivalent to a voltage dividing circuit. Therefore, in order to reach the output voltage Vout to VDD (ideal high level) when the input voltage Vin becomes the low voltage LOW, the on-resistance R1 of the first p-type metal oxide semiconductor transistor 12 is the second p-type. The metal oxide semiconductor transistor 14 needs to be designed to be much smaller than the on-resistance R2. In this case, the aspect ratio (W / L) ₁ of the first p-type metal oxide semiconductor transistor 12 is made much larger than the aspect ratio (W / L) ₂ of the _second p-type metal oxide semiconductor transistor 14. There is a need. If such a design is performed, the size of the logic circuit 10 becomes very large.
Further, when the input voltage Vin becomes the high voltage HIGH, the output voltage Vout of the logic circuit 10 becomes Vt. This is greater than zero (ideal low level). With such an output voltage Vout, other logic circuits connected to the logic circuit 10 may not be operated correctly.
Further, when the input voltage Vin is the low voltage LOW, a direct current flows between the first p-type metal oxide semiconductor transistor 12 and the second p-type metal oxide semiconductor transistor 14 of the logic circuit 10. As a result, the electric energy is consumed by the logic circuit 10 while the input voltage Vin is the logic low voltage LOW.

FIG. 4 shows a circuit diagram of a conventional logic circuit 20. FIG. 5 is an equivalent circuit diagram of the logic circuit 20 when the input voltage Vin at the input terminal IN of the logic circuit 20 is the low voltage LOW. FIG. 6 shows an equivalent circuit diagram of the logic circuit 20 when the input voltage Vin at the input terminal IN of the logic circuit 20 is the high voltage HIGH. FIG. 7 shows an oscillogram of the logic circuit 20. The logic circuit 20 is a negative circuit.
The logic circuit 20 further includes a third p-type metal oxide semiconductor transistor 22 and a coupling capacitor 26 in addition to the first p-type metal oxide semiconductor transistor 12, the second p-type metal oxide semiconductor transistor 14, and the output capacitor 16. ing. This solves the problem of the logic circuit 10 that an ideal low level cannot be output even when the input voltage Vin is the high voltage HIGH.

  As shown in FIG. 5, when the input voltage Vin of the logic circuit 20 is the low voltage LOW, the output voltage Vout is VDD * R2 / (R1 + R2) as in the logic circuit 10. In this case, the voltage at the first end 24 of the coupling capacitor 26 is also VDD * R2 / (R1 + R2), and the voltage at the second end 28 of the coupling capacitor 26 is Vth. When the input voltage Vin is switched from the low voltage LOW to the high voltage HIGH, the first p-type metal oxide semiconductor transistor 12 is turned off. On the other hand, since the second p-type metal oxide semiconductor transistor 14 is energized, the voltage at the first end 24 of the coupling capacitor 26 is lower than Vth. However, the potential difference between the first end 24 and the second end 28 of the coupling capacitor 26 is still maintained at VDD * R2 / (R1 + R2) −Vth. As a result, as shown in FIGS. 6 and 7, the voltage Vx at the second end 28 of the coupling capacitor 26 decreases to Vth−VDD * R2 / (R1 + R2). Thus, the logic circuit 20 can output the ideal low-level output voltage Vout when the input voltage Vin is the high voltage HIGH.

However, in order to output an ideal high-level output voltage Vout, the logic circuit 20 also has the aspect ratio (W / L) ₁ of the first p-type metal oxide semiconductor transistor 12 set to the second p-type metal oxide film. It is necessary to make it much larger than the aspect ratio (W / L) _{2 of the} semiconductor transistor 14. Also, the logic circuit 20 has a problem caused by the energization of a direct current as in the logic circuit 10.
In the conventional logic circuit having only the same type of transistor, the above-described problem exists in the NAND circuit (NAND) and the NOR circuit (NOR) other than the NOT circuit (for example, the logic circuits 10 and 20).

FIG. 8 shows a circuit diagram of a conventional NAND circuit 30 having transistors of the same type only. FIG. 9 shows an oscillogram of the NAND circuit 30. The NAND circuit 30 includes a fourth p-type metal oxide semiconductor transistor 32, a fifth p-type metal oxide semiconductor transistor 34 in series with the fourth p-type metal oxide semiconductor transistor 32, and a fifth p-type metal oxide semiconductor transistor 34. And an output voltage capacitor 38 connected to the fifth p-type metal oxide semiconductor transistor 34 and the sixth p-type metal oxide semiconductor transistor 36 in series.
Similarly, in the NAND circuit 30, there is a problem that the size is too large (the aspect ratio (W / L) ₄ of the _fourth p-type metal oxide semiconductor transistor 32 and the aspect ratio of the fifth p-type metal oxide semiconductor transistor 34 ( W / L) ₅ is required to be much larger than the aspect ratio (W / L) ₆ of the _sixth p-type metal oxide semiconductor transistor 36), and the input voltage Vin is the high voltage HIGH. In the case where the output voltage Vout does not become an ideal low voltage (as shown in FIG. 9, when the input voltage Vin is a high voltage HIGH, the output voltage Vout is equal to the threshold voltage of the VSS + fifth p-type metal oxide semiconductor transistor 34). There is a problem that a large amount of electrical energy is consumed by energizing a direct current (because it becomes equal to the voltage Vth5).

  The main object of the present invention is to reduce energy consumption in a logic circuit having only transistors of the same type and a circuit using the same.

The present invention provides a logic circuit having transistors of the same type only. The logic circuit includes a first logic unit in which a power supply terminal is connected to a first voltage source and a voltage signal is input to an input terminal, and a power supply terminal is connected to a first voltage source and an input terminal is a first logic unit. a second logic unit being connected to the input end of the unit, an input terminal connected to the output terminal of the first logic unit, the power supply terminal is connected to the second voltage source, an output terminal of the first logic unit A step-up / step-down unit that raises / lowers the voltage at the power source, a resistance unit having an input end connected to the output end of the step-up / down unit and an output end connected to the output end of the second logic unit, and a first power supply end 1 is connected to the power supply terminal of the logic unit, the second power supply terminal is connected to the second voltage source, the input terminal is connected to the input terminal of the first logic unit, and the control terminal is connected to the output terminal of the resistance unit. Connected and full amplitude And a full amplitude signal generator for generating a logic signal.

Another logic circuit having transistors of the same type embodied by the present invention includes a first logic unit having a power supply terminal connected to the first voltage source and a voltage signal input to the input terminal, and a power supply terminal A second logic unit connected to the output terminal of the first logic unit and having an input terminal connected to the input terminal of the first logic unit; and an input terminal connected to the output terminal of the first logic unit; power terminal is connected to the second voltage source, a buck-boost unit for elevating the voltage at the output of the first logic unit, the output terminal with the input terminal connected to an output terminal of the step-up and step-down unit second logic The resistance unit connected to the output terminal of the unit, the first power supply terminal is connected to the power supply terminal of the first logic unit, the second power supply terminal is connected to the second voltage source, and the input terminal is the first logic terminal Uni Is connected to the bets input terminal, the control terminal is connected to the output end of the resistor unit, and a full amplitude signal generator for generating a full swing logic signal.

The present invention can also be embodied in a buffer circuit. The buffer circuit includes a first negation circuit in which a voltage signal is input to the input terminal, and a second negation circuit in which the input terminal is connected to the output terminal of the first negation circuit.
The first negative circuit includes a first transistor, a second transistor, a first step-up / step-down unit, a first resistance unit, and a first full amplitude signal generator. The source of the first transistor is connected to the first voltage source, and a voltage signal is input to the gate. The second transistor has a source connected to the first voltage source and a gate connected to the gate of the first transistor. The first step-up / step-down unit has an input end connected to the drain of the first transistor and a power supply end connected to the second voltage source, and raises or lowers the voltage at the drain of the first transistor. The first resistance unit has an input terminal connected to the output terminal of the step-up / step-down unit and an output terminal connected to the drain of the second transistor. The first full amplitude signal generator has a first power supply terminal connected to the source of the first transistor, a second power supply terminal connected to the second voltage source, and an input terminal connected to the gate of the first transistor. And the control end is connected to the output end of the resistor unit to generate the first full amplitude logic signal.

  The second negation circuit includes a third transistor, a fourth transistor, a second step-up / step-down unit, a second resistance unit, and a second full amplitude signal generator. The third transistor has its source connected to the first voltage source and its gate connected to the output terminal of the first full amplitude signal generator of the first inverter, and inputs the first full amplitude logic signal. To do. The fourth transistor has a source connected to the drain of the third transistor and a gate connected to the gate of the third transistor. The second step-up / step-down unit has an input end connected to the drain of the third transistor and a power supply end connected to the second voltage source to raise and lower the voltage at the drain of the third transistor. The second resistance unit has an input terminal connected to the output terminal of the step-up / step-down unit and an output terminal connected to the drain of the fourth transistor. The second full amplitude signal generator has a first power supply terminal connected to the source of the third transistor, a second power supply terminal connected to the second voltage source, and an input terminal connected to the gate of the third transistor. And the control end is connected to the output end of the resistor unit to generate a second full amplitude logic signal.

(First embodiment)
FIG. 10 shows a logic circuit 50 according to the first embodiment. In the logic circuit 50, all transistors are of the same type. The logic circuit 50 includes a first logic unit 52, a second logic unit 54, a step-up / step-down unit (boost element) 56, a resistance unit 58, and a full amplitude buffer generator (full swing buffer) 60.

  The power supply terminal 62 of the first logic unit 52 is connected to the first voltage source VDD. A signal is input to the input 64 of the first logic unit 52. That is, the first input signal IN1 is input. The first logic unit 52 and the second logic unit 54 have the same type of transistor. Specifically, in the first embodiment, the first logic unit 52 includes a first p-type metal oxide semiconductor transistor 68. The source 70 is connected to the first power source VDD, and the gate 72 receives the first input signal IN1. The second logical unit 54 is the same as the first logical unit 52. That is, the second logic unit 54 also includes the second p-type metal oxide semiconductor transistor 76. The power supply terminal 84 of the second logic unit 54 is connected to the output terminal 66 of the first logic unit 52. In other words, it is connected to the drain 74 of the first p-type metal oxide semiconductor transistor 68. The input terminal 86 of the second logic unit 54 is connected to the input terminal 64 of the first logic unit 52. That is, it is connected to the gate 72 of the first p-type metal oxide semiconductor transistor 68. Similarly, the source 78 of the second p-type metal oxide semiconductor transistor 76 is connected to the drain 74 of the first p-type metal oxide semiconductor transistor 68. The gate 80 of the second p-type metal oxide semiconductor transistor 76 is connected to the gate 72 of the first p-type metal oxide semiconductor transistor 68.

  The input end 90 of the step-up / step-down unit 56 is connected to the output end 66 of the first logic unit 52, and the power supply end 92 is connected to the second power supply end VSS. The step-up / down unit 56 is provided to change the voltage at the output end 66 of the first logic unit 52. The transistors included in the step-up / down unit 56 are of the same type as the transistors included in the first logic unit 52. Specifically, in the first embodiment, the step-up / step-down unit 56 includes a fifth p-type metal oxide semiconductor transistor 96, a sixth p-type metal oxide semiconductor transistor 98, and a step-up / down capacitor 100. The source 102 of the fifth p-type metal oxide semiconductor transistor 96 is connected to the output terminal 66 of the first logic unit 52. In other words, it is connected to the drain 74 of the first p-type metal oxide semiconductor transistor 68. The first end 114 of the buck-boost capacitor 100 is connected to the source 102 of the fifth p-type metal oxide semiconductor transistor 96, and the second end 116 of the buck-boost capacitor 100 is the gate 104 of the fifth p-type metal oxide semiconductor transistor 96. It is connected to the. The source 108 of the sixth p-type metal oxide semiconductor transistor 98 is connected to the second end 116 of the buck-boost capacitor 100. The gate 110 of the sixth p-type metal oxide semiconductor transistor 98 is connected to the second power supply terminal VSS. The drain 112 of the sixth p-type metal oxide semiconductor transistor 98 is connected to the gate 110 of the sixth p-type metal oxide semiconductor transistor 98.

  The input end 118 of the resistance unit 58 is connected to the output end 94 of the step-up / step-down unit 56. The output terminal 120 of the resistance unit 58 is connected to the output terminal 88 of the second logic unit 54. The transistor included in the resistance unit 58 is the same type as the transistor included in the first logic unit 52. Specifically, in the first embodiment, the resistance unit 58 includes a fourth p-type metal oxide semiconductor transistor 122. The source 124 of the fourth p-type metal oxide semiconductor transistor 122 is connected to the output terminal 94 of the step-up / step-down unit 56. That is, it is connected to the gate 104 of the fifth p-type metal oxide semiconductor transistor 96. The gate 126 of the fourth p-type metal oxide semiconductor transistor 122 is connected to the source 124 of the fourth p-type metal oxide semiconductor transistor 122. The drain 128 of the fourth p-type metal oxide semiconductor transistor 122 is connected to the output end 88 of the second logic unit 54. That is, it is connected to the drain 82 of the second p-type metal oxide semiconductor transistor 76.

  The first power supply terminal 130 of the full amplitude signal generator 60 is connected to the first voltage source VDD. In other words, the first power supply terminal 130 of the full amplitude signal generator 60 is connected to the power supply terminal 62 of the first logic unit 52. The second power supply terminal 132 of the full amplitude signal generator 60 is connected to the second voltage source VSS. In other words, the second power supply end 132 of the full amplitude signal generator 60 is connected to the power supply end 92 of the step-up / step-down unit 56. The input 134 of the full amplitude signal generator 60 is connected to the input 64 of the first logic unit 52. The control terminal 136 of the full amplitude signal generator 60 is connected to the output terminal 120 of the resistance unit 58. A full amplitude signal generator 60 is provided to generate a full logic swing signal.

  The transistors included in the full amplitude signal generator 60 are also the same type as the transistors included in the first logic unit 52. Specifically, in the first embodiment, the full amplitude signal generator 60 includes a seventh p-type metal oxide semiconductor transistor 138 and a third p-type metal oxide semiconductor in series with the seventh p-type metal oxide semiconductor transistor 138. A transistor 146 is included. The gate 150 of the third p-type metal oxide semiconductor transistor 146 is connected to the output terminal 120 of the resistance unit 58. That is, it is connected to the drain 128 of the fourth p-type metal oxide semiconductor transistor 122. The drain 152 of the third p-type metal oxide semiconductor transistor 146 is connected to the second voltage source VSS. In other words, the drain 152 of the fourth p-type metal oxide semiconductor transistor 146 is connected to the drain 112 of the sixth p-type metal oxide semiconductor transistor 98 of the step-up / step-down unit 56.

  The source 140 of the seventh p-type metal oxide semiconductor transistor 138 is connected to the first voltage source VDD. In other words, the source 140 of the seventh p-type metal oxide semiconductor transistor 138 is connected to the source 70 of the first p-type metal oxide semiconductor transistor 68. The gate 142 of the seventh p-type metal oxide semiconductor transistor 138 is connected to the input end 86 of the second logic unit 54. That is, it is connected to the gate 80 of the second p-type metal oxide film semiconductor 76. The drain 144 of the seventh p-type metal oxide semiconductor transistor 138 is connected to the source 148 of the third p-type metal oxide semiconductor transistor 146. The seventh p-type metal oxide semiconductor transistor 138 can be regarded as the third logic unit 154 similarly to the first logic unit 52 (or the second logic unit 54). The power supply terminal 156 of the third logic unit 154 is connected to the first voltage source VDD. The input terminal 158 of the third logic unit 154 is connected to the input terminal 64 of the first logic unit 52 and receives the first input signal IN1. The output terminal 160 of the third logic unit 154 is connected to the source 148 of the third p-type metal oxide semiconductor transistor 146. The full amplitude logic signal generated from the full amplitude buffer 60 is output from the output terminal 160.

  An operation process of the logic circuit 50 will be described with reference to FIG. FIG. 11 shows an oscillogram of the logic circuit 50. When the first input signal IN1 at the input terminal 64 of the logic circuit 50 is at a low voltage LOW, the first, second, and seventh p-type metal oxide semiconductor transistors 68, 76, and 138 are all energized. In addition, the sixth, fifth, and fourth p-type metal oxide semiconductor transistors 98, 96, and 122 are all energized. Therefore, the first voltage V1 at the output end 66 of the first logic unit 52, the second voltage V2 at the output end 88 of the second logic unit 54, and the third voltage V3 at the second end 116 of the buck-boost capacitor 100 are: Each is as shown in the first portion 1 of FIG. These are all lower than VDD. However, the third p-type metal oxide semiconductor transistor 146 is not energized, and the second voltage V2 at the gate 150 of the third p-type metal oxide semiconductor transistor 146 approaches the high voltage HIGH. The output voltage OUT at the output terminal 160 is substantially equal to VDD.

  On the other hand, when the first input signal IN1 is switched from the low voltage LOW to the high voltage HIGH, all of the first, second, and seventh p-type metal oxide semiconductor transistors 68, 76, and 138 are not in the energized state. The sixth, fifth, and fourth p-type metal oxide semiconductor transistors 98, 96, and 122 are directly energized. Therefore, the third voltage V3 at the second end 116 of the buck-boost capacitor 100 rapidly decreases as shown in the second portion of FIG. As a result, the third p-type metal oxide semiconductor transistor 146 can be sufficiently energized, and an ideal low-level output voltage OUT can be output from the output terminal 160 of the logic circuit 50.

  Briefly, in the logic circuit 50, when the voltage of the signal input to the input terminal 64 of the first logic unit 52 is equal to the high voltage HIGH, the voltage of the full amplitude logic signal output from the output terminal 160 is the low voltage LOW. Is equal to On the other hand, when the voltage of the signal input to the input terminal 64 of the first logic unit 52 is equal to the low voltage LOW, the voltage of the full amplitude logic signal output from the output terminal 160 is equal to the high voltage HIGH.

  In the first embodiment, the primary logic unit 52, the second logic unit 54, the step-up / step-down unit 56, and the resistance unit 58 are mainly responsible for the third p-type metal oxide semiconductor transistor 146 of the third logic unit 154. The third object is to provide a third voltage V3 that can be sufficiently energized as shown in the second part of FIG. The important role of actually driving other logic circuits connected to the downstream side of the logic circuit 50 is left to the third logic circuit 154. Accordingly, the sizes of the first logic unit 52, the second logic unit 54, the step-up / step-down unit 56, and the resistance unit 58 can be made extremely small. Accordingly, since the first logic unit 52, the second logic unit 54, the step-up / step-down unit 56, and the resistance unit 58 are all small in size and high in resistance, the first logic unit 52, the second logic unit 54, and the like. As a result, the direct current flowing through the step-up / step-down unit 56 and the resistance unit 58 is reduced, and the logic circuit 50 consumes a small amount of electrical energy.

  In the first embodiment, all the transistors included in the logic circuit 50 are p-type metal oxide semiconductor transistors. However, in the logic circuit having only the same type of transistor of this embodiment, all the transistors can be n-type metal oxide semiconductor transistors.

(Second embodiment)
FIG. 12 shows a circuit diagram of the logic circuit 250 of the second embodiment. In the logic circuit 250, all transistors are of the same type. The logic circuit 250 includes a first logic unit 52, a second logic unit 54, a step-up / step-down unit 56, a resistance unit 258, and a full amplitude signal generator 60. As in the first embodiment, the input end 218 of the resistance unit 258 is connected to the output end 94 of the step-up / step-down unit 56, and the output end 220 of the resistance unit 258 is connected to the output end 88 of the second logic unit 54. It is connected.

In the logic circuit 50 of the first embodiment, the power supply terminal 84 of the second logic unit 54 is connected to the output terminal 66 of the first logic unit 52, whereas in the logic circuit 250 of the second embodiment, the second logic The power supply terminal 84 of the unit 54 is connected to the first voltage source VDD. When the first input voltage IN1 is the low voltage LOW, the voltage at the output 66 of the first logic unit 52 is equal to VDD. Therefore, the power supply terminal 84 of the second logic unit 54 is not necessarily connected to the output terminal 66 of the first logic unit 52, and may be directly connected to the first voltage source VDD.
In the logic circuit 50 of the first embodiment, the fourth p-type metal oxide semiconductor transistor 122 of the resistor unit 58 is simply used as a resistor. Accordingly, in the logic circuit 250 of the second embodiment, the resistor unit 258 is not provided with the fourth p-type metal oxide semiconductor transistor 58, but is replaced with the resistor element 222. A first end 224 of the resistance element 222 is connected to the output end 94 of the step-up / step-down unit 56, and a second end 228 of the resistance element 222 is connected to the output end 88 of the second logic unit 54.
The operation of the logic circuit 250 illustrated in FIG. 12 is similar to the operation of the logic circuit 50 illustrated in FIG. Therefore, redundant explanation is avoided. It should be noted that the resistance value of the resistance element 222 needs to be extremely large in order to make the direct current flowing in the logic circuit 250 extremely small.

(Third embodiment)
FIG. 13 shows a circuit diagram of the logic circuit 350 of the third embodiment. In the logic circuit 350, all transistors are the same type. The logic circuit 350 includes a fourth logic unit 352, a fifth logic unit 354, a buck-boost unit 56, a resistance unit 258, and a full amplitude signal generator 360. The connection method among the fourth logic unit 352, the fifth logic unit 354, the step-up / step-down unit 56, the resistance unit 258, and the full amplitude signal generator 360 in the logic circuit 350 is the same as that of the first logic unit 52 in the logic circuit 50. 2 The connection method among the logic unit 54, the step-up / step-down unit 56, the resistance unit 58, and the full amplitude signal generator 60 is substantially the same. Therefore, the description is omitted here.

  In the logic circuit 50 of the first embodiment, the first logic unit 52 includes only the first p-type metal oxide semiconductor transistor 68. On the other hand, in the logic circuit 350 of the third embodiment, the fourth logic unit 352 includes an eleventh p-type metal in series with the first p-type metal oxide semiconductor transistor 68 in addition to the first p-type metal oxide semiconductor transistor 68. An oxide film semiconductor transistor 368 is further provided. The source 370 of the eleventh p-type metal oxide semiconductor transistor 368 is connected to the drain 74 of the first p-type metal oxide semiconductor transistor 68. The second input signal IN2 is input to the gate 372 of the eleventh p-type metal oxide semiconductor transistor 368. The drain 374 of the eleventh p-type metal oxide semiconductor transistor 368 is connected to the input end 90 of the step-up / step-down unit 56. The fourth logic unit 352 is equivalent to a negative theoretical product circuit (NAND).

In the logic circuit 350, the fifth logic unit 354 and the sixth logic unit 454 of the full amplitude signal generator 360 need to be the same as the fourth logic unit 352. Accordingly, the fifth logic unit 354 further includes a twelfth p-type metal oxide semiconductor transistor 376 in series with the second p-type metal oxide semiconductor transistor 76 in addition to the second p-type metal oxide semiconductor transistor 76. The sixth logic unit 454 further includes a seventeenth p-type metal oxide semiconductor transistor 438 in series with the seventh p-type metal oxide semiconductor transistor 138 in addition to the seventh p-type metal oxide semiconductor transistor 138. Here, the gate 380 of the twelfth p-type metal oxide semiconductor transistor 376 and the gate 442 of the seventeenth p-type metal oxide semiconductor transistor 438 are both connected to the gate 372 of the eleventh p-type metal oxide semiconductor transistor 368. In addition, the second input signal IN2 is input.
FIG. 14 shows an oscillogram of the logic circuit 350. The fourth logic unit 352, the fifth logic unit 354, and the sixth logic unit 454 of the full amplitude signal generator 360 are equivalent to a negative theoretical product circuit. Therefore, the high voltage HIGH is output from the output terminal 160 of the logic circuit 350 only when both the first input signal IN1 and the second input signal IN2 are at the low voltage LOW.

(Fourth embodiment)
FIG. 15 shows a circuit diagram of the logic circuit 550 of the fourth embodiment. In the logic circuit 550, all transistors are the same type. The logic circuit 550 includes a seventh logic unit 552, an eighth logic unit 554, a step-up / step-down unit 56, a resistance unit 258, and a full amplitude signal generator 560. The connection method among the seventh logic unit 552, the eighth logic unit 554, the step-up / step-down unit 56, the resistance unit 258, and the full amplitude signal generator 560 in the logic circuit 550 of the fourth embodiment is the same as the logic of the first embodiment. The connection method among the first logic unit 52, the second logic unit 54, the step-up / step-down unit 56, the resistance unit 58, and the full amplitude signal generator 60 in the circuit 50 is substantially the same. Therefore, the description is omitted here.

  In the logic circuit 50 of the first embodiment, the first logic unit 52 includes only the first p-type metal oxide semiconductor transistor 68. On the other hand, in the logic circuit 550 of the fourth embodiment, the seventh logic unit 552 includes a 14th p-type metal parallel to the first p-type metal oxide semiconductor transistor 68 in addition to the first p-type metal oxide semiconductor transistor 68. An oxide film semiconductor transistor 568 is further provided. The source 570 of the fourteenth p-type metal oxide semiconductor transistor 568 is connected to the source 70 of the first p-type metal oxide semiconductor transistor 68. The second input signal IN2 is input to the gate 572 of the fourteenth p-type metal oxide semiconductor transistor 568. The drain 574 of the fourteenth p-type metal oxide semiconductor transistor 568 is connected to the input end 90 of the buck-boost unit 56. The seventh logic unit 552 is equivalent to a NOR circuit (NOR).

  In the logic circuit 550, the eighth logic unit 554 and the ninth logic unit 654 of the full amplitude signal generator 560 need to be the same as the seventh logic unit 552. Accordingly, the eighth logic unit 554 further includes a fifteenth p-type metal oxide semiconductor transistor 576 in parallel with the second p-type metal oxide semiconductor transistor 76 in addition to the second p-type metal oxide semiconductor transistor 76. The sixth logic unit 654 further includes a sixteenth p-type metal oxide semiconductor transistor 638 in parallel with the seventh p-type metal oxide semiconductor transistor 138 in addition to the seventh p-type metal oxide semiconductor transistor 138. The gate 580 of the fifteenth p-type metal oxide semiconductor transistor 576 and the gate 642 of the sixteenth p-type metal oxide semiconductor transistor 638 are both connected to the gate 572 of the fourteenth p-type metal oxide semiconductor transistor 568, and The second input signal IN2 is input.

  FIG. 16 shows an oscillogram of the logic circuit 550. The seventh logic unit 552, the eighth logic unit 554, and the ninth logic unit 654 of the full amplitude signal generator 560 are equivalent to a NOR circuit. Accordingly, the high voltage HIGH is output from the output terminal 160 of the logic circuit 550 only when at least one of the first input signal IN1 and the second input signal IN2 is the low voltage LOW.

(5th Example)
FIG. 17 shows a circuit diagram of a logic circuit 750 of the fifth embodiment. The logic circuit 750 further includes a step-up / step-down unit 756 in addition to the first logic unit 52, the second logic unit 54, and the full amplitude signal generator 60.
In the first to fourth embodiments described above, each of the resistance units 58 (same as the resistance unit 258) is provided outside the step-up / step-down unit 56. However, as in the fifth embodiment, the resistor units 58 and 258 can be provided in the step-up / step-down unit 56 in the logic circuit of each embodiment.
In the fifth embodiment of the present invention, the step-up / step-down unit 756 includes a resistor unit 58 (or, in addition to the fifth p-type metal oxide semiconductor transistor 96, the sixth p-type metal oxide semiconductor transistor 98, and the step-up / down capacitor 100). A resistance unit 258). Input end 118 of the resistor units 58, like the other embodiments, is connected to the source 108 of the 6p-type metal oxide semiconductor transistor 98. However, instead of connecting the gate 104 of the fifth p-type metal oxide semiconductor transistor 95 to the source 108 of the sixth p-type metal oxide semiconductor transistor 98 as in the other embodiments (see FIG. 10), a resistance unit is used. 58 output terminals 120 are connected. The output end 96 of the step-up / step-down unit 756 is directly connected to the control end 136 of the full amplitude signal generator 60 instead of being connected to the input end 118 of the resistance unit 58 as in the other embodiments (see FIG. 10). Has been.
The course of operation of the logic circuit 750 in the fifth embodiment is substantially the same as the course of operation of the logic circuit 50 in the first embodiment. Therefore, the description is omitted here.

The logic circuits of the above-described embodiments can be applied to various actual circuits. For example, FIG. 18 shows a circuit diagram of a buffer circuit 850 in which a large number of logic circuits 50 are connected in series. The buffer circuit 850 can exhibit a considerable level and driving capability by changing the number of the logic circuits 50 and the size of the full amplitude signal generator 60 in the logic circuit 50. As a matter of course, the logic circuit of each embodiment can be applied to a latch circuit and a shift register.
In each of the embodiments described above, each of the logic circuits 50 (250, 350, 550, 750) includes the full amplitude signal generator 60 (360, 560). Here, the full amplitude signal generator 60 can be changed to various other types of buffer circuits. For example, a buffer circuit 850 can be used as shown in FIG.

  Compared to the prior art, the logic circuit of the present embodiment having only the same type of transistor includes a first logic unit, a second logic unit, a step-up / step-down unit, a resistance unit, and a full amplitude signal generator. ing. In the logic circuit of this embodiment, the first logic unit, the second logic unit, the step-up / step-down unit, and the resistance unit enable sufficient energization to the transistors of the third logic unit in the full amplitude signal generator. The main role is to provide voltage. The important role of driving other logic circuits connected to the downstream side of the logic circuit is substantially entrusted to the third logic unit. Accordingly, the sizes of the first logic unit, the second logic unit, the step-up / step-down unit, and the resistance unit can be made extremely small. As a result, the first logic unit, the second logic unit, the step-up / step-down unit, and the resistance unit are small in size and have a high resistance. Extremely small. In the logic circuit, only a small amount of electrical energy is consumed. Furthermore, by providing a full amplitude signal generator, the logic circuit can output a full amplitude logic signal with sufficient amplitude.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology illustrated in this specification or the drawings achieves a plurality of objects at the same time, and achieving one of the objects itself has technical utility.

FIG. 6 is a circuit diagram of a conventional logic circuit having only the same type of transistor. FIG. 2 is an equivalent circuit diagram of the logic circuit shown in FIG. 1. The oscillogram of the logic circuit shown in FIG. The circuit diagram of the other conventional logic circuit. FIG. 5 is an equivalent circuit diagram of the logic circuit shown in FIG. 4 (when the input signal is at a low voltage). FIG. 5 is an equivalent circuit diagram of the logic circuit shown in FIG. 4 (when the input signal is at a high voltage). The oscillogram of the logic circuit shown in FIG. The circuit diagram of the negative theoretical product circuit where all the conventional transistors are only the same type. The oscillogram of the negative theoretical product circuit shown in FIG. The circuit diagram of the logic circuit of the 1st example. FIG. 11 is an oscillogram of the logic circuit shown in FIG. 10. FIG. The circuit diagram of the logic circuit of 2nd Example. The circuit diagram of the logic circuit of 3rd Example. The oscillogram of the logic circuit shown in FIG. The circuit diagram of the logic circuit of 4th Example. The oscillogram of the logic circuit shown in FIG. The circuit diagram of the logic circuit of 5th Example. FIG. 11 is a circuit diagram of a buffer circuit including a plurality of logic circuits shown in FIG. 10. FIG. 19 is a circuit diagram of a logic circuit having the buffer circuit shown in FIG. 18.

Explanation of symbols

10, 20, 50, 250, 350, 550, 750: logic circuit 12, 68: first p-type metal oxide semiconductor transistor 14, 76: second p-type metal oxide semiconductor transistor 16: output capacitor 22, 146: third p Type metal oxide semiconductor transistor 26: coupling capacitor 32, 122: fourth p type metal oxide semiconductor transistor 34, 96: fifth p type metal oxide semiconductor transistor 36, 98: sixth p type metal oxide semiconductor transistor 52, 54 154, 352, 454, 552, 554, 654: logic unit 56, 756: buck-boost unit 58, 258: resistance unit 60, 360, 560: full amplitude signal generator 368: eleventh p-type metal oxide semiconductor transistor 376 : 12th p-type metal oxide semiconductor transistor 438: 17p-type metal oxide semiconductor transistor 568: the 14p-type metal oxide semiconductor transistor 576: the 15p-type metal oxide semiconductor transistor 638: the 16p-type metal oxide semiconductor transistor

Claims (27)

A first logic unit having a power supply terminal connected to the first voltage source and a voltage signal input to the input terminal;
A second logic unit having a power supply terminal connected to the first voltage source and an input terminal connected to the input terminal of the first logic unit;
An input terminal power end with is connected to the output terminal of the first logic unit is connected to the second voltage source, a buck-boost unit for elevating the voltage at the output terminal of the first logic unit,
A resistance unit having an input end connected to the output end of the buck-boost unit and an output end connected to the output end of the second logic unit;
The first power supply terminal is connected to the power supply terminal of the first logic unit, the second power supply terminal is connected to the second voltage source, the input terminal is connected to the input terminal of the first logic unit, and the control terminal is A full amplitude signal generator connected to the output of the resistor unit for generating a full amplitude logic signal;
A logic circuit comprising:   The first logic unit, the second logic unit, the step-up / step-down unit, the resistor unit, and the full amplitude signal generator are configured using transistors of the same type. Item 2. The logic circuit according to Item 1. The full amplitude signal generator has a third logic unit and a third transistor;
The third logic unit has a power supply terminal connected to the power supply terminal of the first logic unit, an input terminal connected to the input terminal of the first logic unit, and outputs the full amplitude logic signal from the output terminal. And
The third transistor has a gate connected to the output terminal of the resistor unit, a source connected to the output terminal of the third logic unit, and a drain connected to the second voltage source. The logic circuit according to claim 1 or 2.   When the voltage of the voltage signal input to the input terminal of the first logic unit is equal to the voltage of the first voltage source, the voltage of the full amplitude logic signal is equal to the voltage of the second voltage source. The logic circuit according to claim 1.   When the voltage of the voltage signal input to the input terminal of the first logic unit is equal to the voltage of the second voltage source, the voltage of the full amplitude logic signal is equal to the voltage of the first voltage source. The logic circuit according to claim 1. The first logic unit includes a first metal oxide semiconductor transistor;
The first metal oxide semiconductor transistor has a source connected to the first voltage source, a gate to which the voltage signal is input, and a drain connected to the input terminal of the step-up / step-down unit. The logic circuit according to claim 1. The voltage signal has a first voltage signal and a second voltage signal;
The first voltage signal is input to a gate of the first metal oxide semiconductor transistor;
The first logic unit further includes a second metal oxide semiconductor transistor,
The second metal oxide semiconductor transistor has a source connected to the first voltage source, a gate to which the second voltage signal is input, and a drain connected to the input terminal of the buck-boost unit. The logic circuit according to claim 6. The voltage signal has a first voltage signal and a second voltage signal;
The first logic unit includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor;
The first metal oxide semiconductor transistor has a source connected to the first voltage source, a gate to which the first voltage signal is input,
The second metal oxide semiconductor transistor has a source connected to the first metal oxide semiconductor transistor, a gate to which the second voltage signal is input, and a drain connected to the input terminal of the buck-boost unit. The logic circuit according to any one of claims 1 to 5, wherein the logic circuit is provided. The resistance unit includes a resistance element,
The resistance element has a first end connected to an output end of the buck-boost unit and a second end connected to an output end of the second logic unit. The logic circuit according to any one of the above. The resistance unit includes a fourth transistor,
The fourth transistor has a source connected to the output terminal of the buck-boost unit, a gate connected to the source of the fourth transistor itself, and a drain connected to the output terminal of the second logic unit. The logic circuit according to claim 1, wherein the logic circuit is provided. A first logic unit having a power supply terminal connected to the first voltage source and a voltage signal input to the input terminal;
Together with the power supply terminal is connected to the output terminal of the first logical unit, a second logical unit whose input terminal is connected to the input terminal of the first logic unit,
An input terminal power end with is connected to the output terminal of the first logic unit is connected to the second voltage source, a buck-boost unit for elevating the voltage at the output terminal of the first logic unit,
A resistance unit having an input end connected to the output end of the buck-boost unit and an output end connected to the output end of the second logic unit;
The first power supply terminal is connected to the power supply terminal of the first logic unit, the second power supply terminal is connected to the second voltage source, the input terminal is connected to the input terminal of the first logic unit, and the control terminal is A full amplitude signal generator connected to the output of the resistor unit for generating a full amplitude logic signal;
A logic circuit comprising:   The first logic unit, the second logic unit, the step-up / step-down unit, the resistor unit, and the full amplitude signal generator are configured using transistors of the same type. Item 12. The logic circuit according to Item 11. The full amplitude signal generator comprises a third logic unit and a third transistor;
The third logic unit has a power supply terminal connected to the power supply terminal of the first logic unit, an input terminal connected to the input terminal of the first logic unit, and outputs the full amplitude logic signal from the output terminal. And
The third transistor has a gate connected to the output terminal of the resistor unit, a source connected to the output terminal of the third logic unit, and a drain connected to the second voltage source. The logic circuit according to claim 11 or 12.   When the voltage of the voltage signal input to the input terminal of the first logic unit is equal to the voltage of the first voltage source, the voltage of the full amplitude logic signal is equal to the voltage of the second voltage source. The logic circuit according to claim 11.   When the voltage of the voltage signal input to the input terminal of the first logic unit is equal to the voltage of the second voltage source, the voltage of the full amplitude logic signal is equal to the voltage of the first voltage source. The logic circuit according to claim 11. The first logic unit includes a first metal oxide semiconductor transistor;
The first metal oxide semiconductor transistor has a source connected to the first voltage source, a gate to which the voltage signal is input, and a drain connected to the input terminal of the step-up / step-down unit. The logic circuit according to claim 11. The voltage signal has a first voltage signal and a second voltage signal;
The first voltage signal is input to a gate of the first metal oxide semiconductor transistor;
The first logic unit further includes a second metal oxide semiconductor transistor,
The second metal oxide semiconductor transistor has a source connected to the first voltage source, a gate to which the second voltage signal is input, and a drain connected to the input terminal of the buck-boost unit. The logic circuit according to claim 16. The voltage signal has a first voltage signal and a second voltage signal;
The first logic unit includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor;
The first metal oxide semiconductor transistor has a source connected to the first voltage source, a gate to which the first voltage signal is input,
The source of the second metal oxide semiconductor transistor is connected to the first metal oxide semiconductor transistor, the second voltage signal is input to the gate, and the drain is connected to the input terminal of the buck-boost unit. The logic circuit according to claim 11, wherein the logic circuit is provided. The resistance unit includes a resistance element,
19. The resistance element has a first end connected to an output end of the step-up / step-down unit and a second end connected to an output end of the second logic unit. The logic circuit according to any one of the above. The resistance unit includes a fourth transistor,
The fourth transistor has a source connected to the output terminal of the buck-boost unit, a gate connected to the source of the fourth transistor itself, and a drain connected to the output terminal of the second logic unit. The logic circuit according to claim 11, wherein the logic circuit is provided. A first logic unit having a power supply terminal connected to the first voltage source and a voltage signal input to the input terminal;
Together with the power supply end connected to the first voltage source, a second logical unit whose input terminal is connected to the input terminal of the first logic unit,
A fifth transistor having its source connected to the output of the first logic unit and its drain connected to a second voltage source ;
A buck-boost capacitor having a first end connected to the source of the fifth transistor and a second end connected to the gate of the fifth transistor;
A sixth transistor having its source connected to the second end of the buck-boost capacitor, its gate connected to a second voltage source, and its drain connected to its own gate;
A fourth transistor having its source connected to the second end of the buck-boost capacitor, its gate connected to its source, and its drain connected to the output of the second logic unit;
Together with the power supply terminal is connected to a power supply terminal of the first logic unit, and a third logic unit input end connected to an input terminal of the first logic unit,
A third transistor having its source connected to the output of the third logic unit, its gate connected to the drain of the fourth transistor, and its drain connected to the second voltage source ;
A logic circuit comprising: The first logic unit, the second logic unit, the fifth transistor, the sixth transistor, the fourth transistor, the third logic unit, and the third transistor are transistors of the same type. The logic circuit according to claim 21, wherein the logic circuit is configured by using. A first logic unit having a power supply terminal connected to the first voltage source and a voltage signal input to the input terminal;
A power terminal connected to the output terminal of the first logic unit and the monitor, and a second logical unit whose input terminal is connected to the input terminal of the first logic unit,
A fifth transistor having its source connected to the output of the first logic unit and its drain connected to a second voltage source ;
A buck-boost capacitor having a first end connected to the source of the fifth transistor and a second end connected to the gate of the fifth transistor;
A sixth transistor having its source connected to the second end of the buck-boost capacitor, its gate connected to a second voltage source, and its drain connected to its own gate;
A fourth transistor having its source connected to the second end of the buck-boost capacitor, its gate connected to its source, and its drain connected to the output of the second logic unit;
A third logic unit having a power supply terminal connected to the power supply terminal of the first logic unit and an input terminal connected to the input terminal of the first logic unit;
A third transistor having its source connected to the output of the third logic unit, its gate connected to the drain of the fourth transistor, and its drain connected to the second voltage source ;
A logic circuit comprising: The first logic unit, the second logic unit, the fifth transistor, the sixth transistor, the fourth transistor, the third logic unit, and the third transistor are transistors of the same type. The logic circuit according to claim 23, wherein the logic circuit is configured by using. A first negation circuit in which a voltage signal is input to the input end, and a second negation circuit in which the input end is connected to the output end of the first negation circuit ,
The first negation circuit is
A first transistor having a source connected to the first voltage source and a gate receiving a voltage signal;
A second transistor having its source connected to the first voltage source and its gate connected to the gate of the first transistor;
A first step-up / step-down unit that has an input end connected to the drain of the first transistor and a power supply end connected to the second voltage source, and raises or lowers the voltage at the drain of the first transistor;
A first resistance unit having an input terminal connected to the output terminal of the buck-boost unit and an output terminal connected to the drain of the second transistor;
The first power supply terminal is connected to the source of the first transistor, the second power supply terminal is connected to the second voltage source, the input terminal is connected to the gate of the first transistor, and the control terminal is the first resistance unit. A first full-amplitude signal generator for generating a first full-amplitude logic signal,
The second negation circuit is
A third transistor having a source connected to the first voltage source and a gate connected to the output terminal of the first full amplitude signal generator of the first negative circuit; ,
A fourth transistor whose source is connected to the drain of the third transistor and whose gate is connected to the gate of the third transistor;
A second step-up / step-down unit that has an input end connected to the drain of the third transistor and a power supply end connected to the second voltage source, and raises or lowers the voltage at the drain of the third transistor;
A second resistance unit having an input end connected to the output end of the second step-up / step-down unit and an output end connected to the drain of the fourth transistor;
The first power supply terminal is connected to the source of the third transistor, the second power supply terminal is connected to the second voltage source, the input terminal is connected to the gate of the third transistor, and the control terminal is the second resistance unit. And a second full-amplitude signal generator for generating a second full-amplitude logic signal.   The second transistor, the first buck-boost unit, the first resistor unit, the first full amplitude signal generator, the third transistor, the fourth transistor, and the second buck-boost unit 26. The buffer circuit according to claim 25, wherein the second resistance unit and the transistor included in the second full amplitude signal generator are of the same type as the first transistor. A first logic unit having a power supply terminal connected to the first voltage source and a voltage signal input to the input terminal;
A second logic unit having a power supply terminal connected to the first voltage source and an input terminal connected to the input terminal of the first logic unit;
A step-up / step-down unit having an input terminal connected to an output terminal of the first logic unit and a power supply terminal connected to a second voltage source, and raising and lowering a voltage at the output terminal of the first logic unit;
A resistance unit having an input end connected to the output end of the buck-boost unit and an output end connected to the output end of the second logic unit;
The first power supply terminal is connected to the power supply terminal of the first logic unit, the second power supply terminal is connected to the second voltage source, the input terminal is connected to the input terminal of the first logic unit, and the control terminal is A full amplitude signal generator connected to the output of the resistor unit to generate a full amplitude logic signal;
A logic circuit.

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