JP3867842B2 - Capacitor charging method and apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor charging method and apparatus for detecting a load capacitor voltage with high accuracy and stability, and periodically charging the load capacitor to a set voltage.
[0002]
[Prior art]
The capacitor charger is used to repeatedly charge a capacitor at the first stage of a drive pulse power source of a drive pulse laser such as a copper vapor laser or an excimer laser, that is, a load capacitor. In particular, excimer lasers often require highly accurate charging of load capacitors.
[0003]
The conventional capacitor charger is configured by connecting a rectifier circuit Re to the output of the inverter unit IV as shown in FIG. That is, the capacitor charger controls the power output from the DC voltage source DC, converts the DC supplied from the DC voltage source DC into AC (square wave AC voltage) by the inverter unit IV, and is boosted by the transformer H. The alternating current is rectified by the rectifier circuit Re, and the load capacitor Cd is charged by the rectified current.
[0004]
And the control part 100 divides | segments the charge voltage value of the load capacitor Cd into the measurement voltage which is proportional to the charge voltage value by the voltage divider M1, and controls the charge to the load capacitor Cd to be charged. And a set voltage indicating a target value of the charging voltage of the load capacitor Cd. That is, the control unit 100 determines whether or not the measured voltage from the voltage divider M1 exceeds the set voltage set inside, and if it exceeds, stops the inverter unit IV at that time. The charging of the load capacitor Cd is stopped.
[0005]
[Problems to be solved by the invention]
However, since the conventional capacitor charger uses an analog control method, it continuously detects the output voltage. In such analog control, noise countermeasures are required in the control unit so that the noise generated by the high frequency switching operation does not affect the detected output voltage value. A sufficiently large filter is used on the input side of the detection circuit as a countermeasure against noise in detection. As a result, the detected voltage value is detected later than the actual output voltage value, and high-accuracy charging cannot be performed.
Therefore, in view of the above problems, the present invention provides a capacitor charging method and apparatus capable of obtaining a highly accurate and stable load voltage detection value and obtaining a high-speed and highly accurate output voltage. Is an issue.
[0006]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, claim 1 of the present invention detects an output voltage of a converter circuit having an inverter operated by a drive pulse of a constant frequency, and uses the detected output voltage to set the load capacitor to a set voltage. In the capacitor charging method in which the output voltage is charged up to, the detected value of the output voltage within the drive pulse width after the drive pulse is input to the inverter and no current flows through the load capacitor is used as the output voltage detected value. A capacitor charging method is provided.
[0007]
In order to solve the above-mentioned problem, the present invention provides a main capacitor charger having a first inverter that is operated with a drive pulse having a constant frequency and one or more main capacitor chargers connected in parallel to the main capacitor. A sub-charger for fine adjustment having a second inverter that is operated with a driving pulse having a constant frequency higher than that of the charger is connected in parallel, and the charging voltage set at a steep slope by operating the main capacitor charger. After increasing the charging voltage of the load capacitor until just before, the operation of the main capacitor charger is stopped, and only the sub capacitor charger for fine adjustment with small output power is operated to set the load capacitor with a gentle gradient. In the capacitor charging method of charging to a voltage, the drive pulse is within the drive pulse width after being input to the inverter, and the drive pulse is The detected value of the output voltage in the period in which no current flows through the load capacitor to provide a capacitor charging method according to the output voltage detection value.
[0008]
In order to solve the above-mentioned problem, according to a third aspect of the present invention, a plurality of output voltages are detected within the drive pulse width after the drive pulse is input to the inverter and a current does not flow through the load capacitor. 3. The capacitor charging method according to claim 1, wherein an average value of detection values of the plurality of output voltages is calculated, and the calculated average value is used as the output voltage detection value. To do.
[0009]
In order to solve the above-mentioned problem, according to a fourth aspect of the present invention, the output voltage is detected four or more times within the drive pulse width after the drive pulse is input to the inverter and during which no current flows through the load capacitor. The detected values are compared, the maximum and minimum detected values are excluded from the comparison results, and the average value of the remaining detected values excluding the maximum and minimum detected values is calculated. 4. The capacitor charging method according to claim 1, wherein the capacitor is calculated and the calculated average value is set as the output voltage detection value.
[0010]
In order to solve the above-described problem, according to a fifth aspect of the present invention, the second inverter is operated with a driving pulse having a constant frequency that is an integer multiple higher than the first inverter, and the first and second inverters are operated. The capacitor charging method according to any one of claims 2 to 4, wherein the capacitor is operated so that drive pulses of the inverter are synchronized.
[0011]
In order to solve the above-mentioned problem, according to a sixth aspect of the present invention, when a plurality of the main capacitor chargers are connected in parallel, the second inverter is a constant that is an integer multiple higher than the first inverter. 6. The method according to claim 2, wherein the first and second inverters are operated so as to be synchronized with each other, and the first inverter is operated in phase or in phase. A capacitor charging method according to claim 1 is provided.
[0012]
In order to solve the above-mentioned problems, a seventh aspect of the present invention provides a detection circuit for detecting an output voltage of a converter circuit having an inverter that is operated with a drive pulse having a constant frequency, and detection of an output voltage obtained by the detection circuit. Among the values, the detected value of the output voltage within the drive pulse width after the drive pulse is input to the inverter and when no current flows through the load capacitor is extracted and compared with a reference value, and the drive pulse And a control circuit for generating the capacitor.
[0013]
In order to solve the above-mentioned problems, the present invention provides a main capacitor charger having a first inverter that is operated with a drive pulse having a constant frequency and one or more main capacitor chargers connected in parallel to the main capacitor. A sub-charger for fine adjustment having a second inverter that is operated with a driving pulse having a constant frequency higher than that of the charger is connected in parallel, and the charging voltage set at a steep slope by operating the main capacitor charger. After increasing the charging voltage of the load capacitor until just before, the operation of the main capacitor charger is stopped, and only the sub capacitor charger for fine adjustment with small output power is operated to set the load capacitor with a gentle gradient. In a capacitor charging device that charges to a voltage, a detection circuit that detects an output voltage, and a detection value of an output voltage obtained by the detection circuit Control that generates a drive pulse by extracting a detected value of an output voltage within a drive pulse width after the drive pulse is input to the inverter and during which no current flows through the load capacitor, and comparing it with a reference value And a capacitor charging device.
[0014]
In order to solve the above-mentioned problems, a ninth aspect of the present invention provides a detection circuit for detecting an output voltage, and the detected value of the output voltage obtained by the detection circuit after the drive pulse is input to the inverter. A plurality of the detected values are taken out within a drive pulse width and a current does not flow through the load capacitor, and an average value of the plurality of detected values is calculated, and the calculated average value is output as an output voltage. The capacitor charging device according to claim 7 or 8, further comprising: a control circuit that generates the drive pulse by comparing the detected value with a reference value.
[0015]
In order to solve the above-described problem, a tenth aspect of the present invention provides a detection circuit for detecting an output voltage, and of the detected value of the output voltage obtained by the detection circuit, after the drive pulse is input to the inverter. The output voltage is taken out four or more times within the drive pulse width and the current does not flow to the load capacitor, and the detected values are compared. From the comparison result, the maximum and minimum detected values are detected. The average value of the remaining detection values excluding these maximum and minimum detection values is calculated, and the calculated average value is set as a detection value of the output voltage, which is compared with the detection value and a reference value. A capacitor charging device according to claim 7, further comprising a control circuit that generates a driving pulse.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
The capacitor charging of the present invention is performed by repeatedly switching the switching element at a high frequency at a frequency determined by the resonance frequency of the resonance inductance and the resonance capacitor in the converter, and controlling the switching drive pulse width according to the output voltage to be increased. Thus, the amount of power supply is adjusted, and the load capacitor is charged to the target voltage value at high speed. The drive pulse width of the switching element that adjusts the power supply amount is determined by the detected value of the output voltage, and the width is controlled.
[0017]
The detected value of the output voltage is the value of the output voltage detected during a period in which a current does not flow through the load capacitor after a certain drive pulse is input to the inverter, that is, a period in which the output voltage does not increase. The detected value is set as the output voltage detected value. Based on the detected output voltage detection value, the switching element after the next half cycle is turned on to supply power, and whether or not to increase the output voltage value is determined. Further, the switching element is turned on. In this case, control is performed to determine an on-time for controlling the amount of power supply.
[0018]
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of a capacitor charger including a converter circuit composed of a resonant inverter and a rectifier circuit and a control circuit for the converter circuit. The resonant inverter includes an inverter part IV, a resonant inductor Lr, a transformer H, a resonant capacitor Cd, and the like. In this figure, the inverter part IV is a drive pulse width modulation type composed of switching elements S1 to S4 such as FET (field effect transistor), IGBT (insulated gate bipolar transistor) and the like. The DC voltage output from the rectified DC voltage source DC is converted into a square wave AC voltage (hereinafter referred to as AC voltage).
[0019]
When the inverter unit IV generates an alternating voltage, the inverter unit IV controls the drive voltage train that is input so that the combination of the switching elements S3 and S2 and the combination of the switching elements S1 and S4 are alternately turned on. To AC voltage. On the primary side of the step-up transformer H, one terminal is connected via the resonant inductor LR, and the other terminal is directly connected to the inverter unit IV. Further, on the secondary side of the transformer H, a resonance capacitor Cr is inserted between terminals, and is connected to the rectifier circuit Re. The resonance capacitor Cr may be connected to the primary side. The rectifier circuit Re is composed of rectifier diodes D1 to D4, and full-wave rectifies the boosted AC voltage output from the transformer H and outputs it as a DC charging current to the load capacitor Cd.
[0020]
Next, the control circuit 1 will be described. The output voltage is detected by the detection circuit 3 through the voltage divider 2 that divides the output voltage at a predetermined ratio. Since the voltage divider 2 and the detection circuit 3 are ordinary ones, description thereof is omitted. However, it is preferable that a filter circuit including a capacitance serving as a delay element is not connected to the input and output sides of the detection circuit 3. The detected value of the output voltage detected by the detection circuit 3 is converted into a digital value by an analog / digital converter (A / D) 4. The digitized detection voltage is sequentially taken into a register (not shown) in the FPGA (Field Programmable Gate Array) 6 at a time interval sufficiently shorter than the switching period of the inverter. Then, based on a pulse (reference drive pulse) that serves as a reference for the drive signal of the switching element generated by the CPU (Central Processing Unit) 5, a drive pulse is input to the resonant inverter only for a specific period. Since the current does not flow to the load capacitor Cd within the drive pulse width after that, the detected value of the output voltage stored in the register in the FPGA 6 is read as a signal from the CPU 5 during a period when the output voltage does not rise, It is stored in the RAM 5a in the CPU 5.
[0021]
Further, the CPU 5 performs arithmetic processing for predictive control based on the reference drive pulse and the value stored in the RAM 5a, and generates a pulse signal for determining the ON time of the switching element. Are distributed as signals for the switching elements S1 and S4 or the switching elements S2 and S3 and sent to the drive circuit 7. In the drive circuit 7, a driving voltage is generated based on this signal and applied to the switching element of the inverter to perform a switching operation. Here, a CPLD (complex programmable logic device) or the like may be used in addition to the FPGA 6. Further, the above processing may be performed only by the CPU 5 without using the FPGA 6 or the CPLD.
[0022]
Next, the circuit operation in the switching half cycle of this capacitor charging apparatus will be described with reference to FIGS. In FIG. 2, the horizontal axis indicates time. In the upper stage, the vertical axis indicates the drive pulses of the switching elements S1 and S4 and the drive pulses of the switching elements S2 and S3, and in the middle stage, the currents of the resonance capacitor and the load capacitor. The lower part shows the output voltage. FIG. 3 shows the flow of current in each region when the circuit operation in the switching half cycle of the capacitor charger is divided into three operation regions.
[0023]
The period a in FIG. 2 is a period until the secondary rectifier diodes D1 and D4 start to conduct when the switching elements S1 and S4 are in the on state, as shown in FIG. This is a case where the voltage of the capacitor Cr is lower than the voltage of the load capacitor Cd. During this period, a current flows only through the resonance capacitor Cr and no current flows through the load capacitor Cd, so that the output voltage, that is, the voltage of the load capacitor Cd is constant. In the present invention, in the state where the driving pulses are applied to the switching elements S1 and S4 or S3 and S2, the period during which the output voltage is constant is set as the output voltage detection period a, and the detection value detected in the output voltage detection period a One or more of these are used as output voltage detection values.
[0024]
When the resonant capacitor Cr is charged until it substantially matches the voltage of the load capacitor Cd, the secondary side rectifier diodes D1 and D4 begin to conduct as shown in FIG. 3B (in FIG. 2). At time t2), a current flows through the load capacitor Cd. Therefore, in the output voltage rise period b in FIG. 2, the output voltage rises by charging the load capacitor Cd. This continues while the switching elements S1 and S4 are in the on state.
[0025]
After the switching elements S1 and S4 are turned off, energy is recovered on the input side through the internal diodes of the switching elements S3 and S2, as shown in FIG. 3 (c). Also during this period, since the rectifier diodes D1 and D4 on the secondary side become conductive, a current flows through the load capacitor Cd, and the output voltage rises (period c in FIG. 2). As can be seen from the above description, the detection of the output voltage is performed within the period from time t1 to time t2 (output voltage detection period a) in FIG. The output voltage can be detected accurately and stably without providing a filter circuit. Furthermore, as shown in the lowermost stage of FIG. 2, after the switching element turning on time t1 that avoids a sufficient fixed period that is considered not to be affected by the instantaneous noise generation when the switching element is turned on. Similarly, in order to sufficiently avoid the occurrence of instantaneous noise due to the conduction of the secondary side rectifier diode from the time point ts, in order to avoid this influence, the time before the time point t2 when the secondary side rectifier diode is conducted is avoided. Preferably, it is performed during the time tf.
[0026]
Next, the detection of the output voltage and the control method using the detected value will be specifically described. The CPU 5 preliminarily reads the detected value of the output voltage stored in a register (not shown) of the FPGA 6 when the output voltage detection period a is reached after the above-described reference drive pulse is turned on, that is, generated. Set up. The read detection value of the output voltage is stored in the RAM 5a in the CPU 5. As shown in the output voltage waveform in the lower part of FIG. 2, it is assumed that the output voltage detection value detected in the output voltage detection period a in a certain drive pulse is Vn. At this time, the output voltage ΔVn which has been detected in the output voltage detection period half a cycle before the output voltage detection value Vn and increased in the meantime from the output voltage values Vn−1 and Vn stored in the register of the CPU 5 = Vn-Vn-1 is calculated. Using this result, it is assumed that the voltage value ΔVn + 1 that rises in the next half cycle is the same as ΔVn, and the next output voltage value Vn + 1 = Vn + ΔVn is predicted.
[0027]
Next, Vn + 1 is compared with the target output voltage Vf. When the predicted next output voltage Vn + 1 is smaller than the target output voltage Vf (Vn + 1 <Vf), the operation is performed with a predetermined substantially constant pulse width. When the predicted next output voltage Vn + 1 becomes larger than the target output voltage Vf (Vn + 1> Vf), it is necessary to control the pulse width for the first time. First, ΔV = Vf−Vn + 1 is calculated to obtain a voltage value to be increased to the target voltage. Here, the calculation of the ON time of the switching element necessary for increasing the voltage of ΔV is obtained by using the value stored in advance by the CPU 5 by determining the relationship between the ON time of the switching element and the output voltage increase. And do it.
[0028]
Here, when the on-time of the switching element is changed, the output voltage rise in a half cycle of one switching cycle is 2 after the output voltage rise period b due to the switching element being turned on and after the switching element is turned off. This is due to the conduction period of the secondary rectifier diode (period c in FIG. 2). The relationship between the ON time of the switching element and the output voltage rise is such that the output voltage rising in a half cycle with respect to the ON time of the switching element has a one-to-one relationship. In particular, the time ta during which the voltage does not increase from the time when the drive pulse is turned on is stored in the ROM 5 of the CPU 5. Further, when the ON time of the switching element and the voltage increase are in a proportional relationship, ΔV / Δt is stored in the CPU 5. In the calculation, the on-time tx of the switching element in the output voltage rise period b is obtained using the stored relationship, and then the time ta is added to the result, and the on-time ton of the switching element = Find ta + tx. From the on-time ton of the obtained switching element, the pulse width of the last half cycle is controlled.
[0029]
Since the detection of the output voltage is constant during the output voltage detection period a, it is only necessary to detect the output voltage once during this period. However, in order to further improve the accuracy of the detection value, the FPGA 6 uses a plurality of detection values. Is calculated, and the output voltage detection values averaged sequentially are stored in a register (not shown) of the FPGA 6. Similarly to the above-described method, the averaged detection value may be taken into the CPU 5 during the output voltage detection period a as an output detection value and stored in a register (not shown) of the CPU 5. Further, in order to further improve the accuracy of output voltage detection by removing detection values that may be affected by noise, a plurality of, for example, four or more detection values are used in the above-described FPGA 6, and the detection values of these detection values are used. When performing the calculation process for obtaining the average value, the four or more detection values are compared with each other, and the average value of the remaining two or more detection values is obtained except for the detection values that are the maximum value and the minimum value. The averaged detection value may be used as the output voltage detection value.
[0030]
Here, the detected output voltage values Vn and Vn-1 are digitized values. Actually, the voltage value ΔVn that rises with the charging amount of the switching half cycle of the switching element becomes smaller gradually as the charging voltage of the capacitor Cd rises. That is, in the increased voltage value ΔVn, n is a natural number, and the increased voltage values ΔV1, ΔV2, ΔV3, ΔV4,... Gradually decrease the voltage charged with the same set pulse width. However, the difference in voltage increase in one half cycle decreases as the output voltage value increases, and the adjacent voltage increases are almost equal immediately before the target voltage Vf.
[0031]
Here, after the output voltage is lower than the target voltage Vf and becomes the voltage V1 charged to such an extent that the difference in charge amount in the switching half cycle of the switching element becomes small, a certain switching element half The switching element ON time is predicted by predicting the output voltage Vn + 1 after the next half cycle, assuming that the voltage component ΔVn rising in the cycle and the voltage component ΔVn + 1 rising in the next switching device half cycle are substantially the same. To control.
[0032]
When the ON time of the switching element is changed, the output voltage rise in one switching half cycle changes as the input voltage changes. However, if the target output voltage system can be charged sufficiently high, it is not necessary to consider fluctuations in the input voltage in order to omit the means for detecting the output voltage. When taking into account fluctuations in the input voltage, the capacitor charger is provided with a detection circuit for detecting the input voltage. The CPU in the control circuit stores a one-to-one relationship with the output voltage that rises in a half cycle with respect to the ON time of the switching element according to the input voltage, and the detected value of the detected input voltage. Based on the above, the above-described pulse width is controlled.
[0033]
The target voltage value Vf is a final set voltage that is set in the CPU in the control circuit and is the target of the charging voltage value V1 for the load capacitor Cd. Note that the maximum width of the drive pulse is such that the switching elements S1 and S2 or S3 and S4 are simultaneously turned on by the adjacent drive pulses in the on / off operation of the switching elements S1 to S4, and the short circuit is not caused. It is determined as the pulse width of the maximum duty cycle possible within the range in which the capacitor charger can be operated normally at the switching frequency. When there is a margin for the charging time, the drive pulse having a drive pulse width set smaller than the maximum drive pulse width may be used, or the drive pulse width of several previous pulses may be adjusted or the number of drive pulses may be adjusted. Here, in the initial stage of charging, charging may be started with a soft driving pulse having a constant driving pulse width smaller than the constant driving pulse width or a gradually increasing driving pulse width.
[0034]
In the embodiment described above, an example in which a load capacitor is charged with a single capacitor charger has been described. However, as shown in FIG. Small sub-capacitor chargers S are connected in parallel, and the charging power by the driving pulse immediately before the final driving pulse from the first charging is the main capacitor charger M or the main capacitor charger M and the sub-capacitor charger S. The charging power may be supplied from the sub-capacitor charger M at least by the final drive pulse. In this case, the output voltages of the main capacitor charger M and the sub capacitor charger S are substantially equal, and the power supply amount is several to several tens of times that of the main capacitor charger M with respect to the sub capacitor charger S. The frequency of the driving pulse is preferably several times to several tens of times that of the sub capacitor charger S relative to the main capacitor charger M, and the driving pulses are preferably synchronized with each other.
[0035]
The main capacitor charger M and the sub capacitor charger S have the same configuration as that shown in FIG. 1. The inverter units IV1 and IV2 correspond to the inverter unit IV shown in FIG. 1, and the rectifier circuits Re1 and Re2 are shown in FIG. Corresponding to one rectifier circuit Re, the resonance circuits K1 and K2 are the same as the circuit constituted by the transformer H, the resonance inductor Lr, and the resonance capacitor Cr. The control circuit 1 includes control circuits for the inverter units IV1 and IV2, and each control circuit is formed of a circuit similar to that shown in FIG.
[0036]
FIG. 5 shows the output voltage of the capacitor charger composed of the main capacitor charger M and the sub capacitor charger S. Up to a certain voltage V1 lower than the target voltage, the main capacitor charger M and the sub capacitor charger S are operated, the charge voltage of the load capacitor is increased at a steep slope, the operation of the main converter circuit is stopped, and the output power Only the small fine adjustment converter circuit is operated to charge the load capacitor to the target voltage with a gentle slope.
[0037]
The main capacitor charger M and the sub capacitor charger S may have the same circuit configuration. For example, the main capacitor charger M supplies 99% or more of the required charging power, and the sub capacitor If the charger S is 1% or less, the sub-capacitor charger S has a small power loss even if it does not have a resonant circuit configuration. Therefore, a general driving pulse width control type high-frequency inverter unit that is not a resonant type is used. The circuit configuration may be the same.
[0038]
Further, when a plurality of main capacitor chargers M are connected in parallel in the embodiment shown in FIG. 4, the inverter of the sub capacitor charger S has a constant frequency that is an integer multiple higher than the inverter of the main capacitor charger M. It is preferable that the drive pulses of the inverters are operated so that the drive pulses of these inverters are synchronized, and that the inverter of the main capacitor charger M is operated in phase or in phase.
[0039]
As mentioned above, although one embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. Are also included in the present invention.
[0040]
In the above description, the drive pulse width is described as the maximum allowable drive pulse width or the set drive pulse width. However, the drive pulse width depends on the setting of the charging time for charging the load capacitor to the target voltage value. Of course, it is necessary to charge within the set charging time, but if it is faster than the set charging time, there will be a problem that the charging voltage will drop due to discharge. It is preferable to determine the drive pulse width of the drive pulse so that the charging is completed slightly before the set charging time.
[0041]
【The invention's effect】
The present invention has the characteristics as described above, and obtains a stable and accurate load voltage value by performing detection of the capacitor charger that charges to the target voltage during a certain period in which the load voltage does not increase. Thus, it is possible to improve the charging accuracy of the capacitor.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a capacitor charger according to a first embodiment of the present invention.
FIG. 2 shows the relationship between driving pulses for switching elements S1 and S4, switching element S2 and S3, and the current flowing in the resonance capacitor current and load capacitor current of the parallel resonant converter, and the load capacitor. It is a figure which shows the relationship with output voltage.
FIG. 3 is an explanatory diagram showing an operation from a region a to a region c when a half cycle of the parallel resonant converter is divided into three regions.
FIG. 4 is a diagram showing a configuration of a capacitor charger according to a second embodiment of the present invention.
FIG. 5 is a diagram illustrating an operation waveform of an output voltage of the capacitor charger according to the second embodiment of the present invention.
FIG. 6 is a conceptual diagram showing a configuration of a conventional parallel resonant converter.
[Explanation of symbols]
1-Control circuit 2-Voltage divider
3-Detection circuit for output voltage detection 4-Analog-digital converter
5-CPU 6-FPGA (Field Programmer
Bull Gate Array)
IV-Inverter part Re-rectifier circuit
H-transformer Cd-load capacitor

Claims (10)

In a capacitor charging method of detecting an output voltage of a converter circuit having an inverter that is operated with a drive pulse of a constant frequency, and charging the load capacitor to a set voltage using this output voltage detection value,
Capacitor charging method characterized in that a detected value of an output voltage within a period of a drive pulse width from when the drive pulse is input to the inverter and no current flows through the load capacitor is the output voltage detected value. . One or a plurality of main capacitor chargers having a first inverter that is operated with a drive pulse having a constant frequency are connected in parallel and a first capacitor that is operated with a drive pulse having a constant frequency higher than that of the main capacitor charger. After connecting the sub-capacitor charger for fine adjustment having two inverters in parallel and operating the main capacitor charger, the charging voltage of the load capacitor is increased up to just before the set charging voltage with a steep slope, In the capacitor charging method, which stops the operation of the main capacitor charger, operates only the sub capacitor charger for fine adjustment with small output power, and charges the load capacitor to the set voltage with a gentle slope.
Capacitor charging method characterized in that a detected value of an output voltage within a period of a drive pulse width from when the drive pulse is input to the inverter and no current flows through the load capacitor is the output voltage detected value. . A plurality of output voltages are detected within the drive pulse width after the drive pulse is input to the inverter and no current flows through the load capacitor, and an average value of the detected values of the plurality of output voltages is calculated. 3. The capacitor charging method according to claim 1, wherein the calculated average value is used as the output voltage detection value. The output voltage is detected at least four times within the drive pulse width after the drive pulse is input to the inverter and no current flows through the load capacitor, the detected values are compared, and the detection result is compared with the detection result. Among the values, the maximum and minimum detection values are excluded, the average value of the remaining detection values excluding the maximum and minimum detection values is calculated, and the calculated average value is calculated as the output voltage detection value. 4. The capacitor charging method according to claim 1, wherein the capacitor charging method is performed. The second inverter is operated with a driving pulse having a constant frequency that is an integer multiple higher than that of the first inverter, and the driving pulses of the first and second inverters are synchronized with each other. The capacitor charging method according to any one of claims 2 to 4. When a plurality of main capacitor chargers are connected in parallel, the second inverter is operated with a driving pulse having a constant frequency that is an integer multiple higher than the first inverter, and the first and first 6. The capacitor charging method according to claim 2, wherein the drive pulses of the two inverters are operated in synchronism, and further, the first inverter is operated in the same phase or different phase. A detection circuit that detects an output voltage of a converter circuit having an inverter that is operated with a drive pulse of a constant frequency, and a detected value of the output voltage obtained by the detection circuit after the drive pulse is input to the inverter A capacitor having a drive pulse width and a control circuit for extracting the detected value of the output voltage during a period when no current flows through the load capacitor and generating the drive pulse by comparing it with a reference value Charging device. One or a plurality of main capacitor chargers having a first inverter that is operated with a drive pulse having a constant frequency are connected in parallel and a first capacitor that is operated with a drive pulse having a constant frequency higher than that of the main capacitor charger. After connecting the sub-capacitor charger for fine adjustment having two inverters in parallel and operating the main capacitor charger, the charging voltage of the load capacitor is increased up to just before the set charging voltage with a steep slope, In the capacitor charger that stops the operation of the main capacitor charger and operates only the sub capacitor charger for fine adjustment with small output power and charges the load capacitor to the set voltage with a gentle slope.
Of the detection circuit for detecting the output voltage and the detected value of the output voltage obtained by the detection circuit, a current flows through the load capacitor within the drive pulse width after the drive pulse is input to the inverter. A capacitor charging device comprising: a control circuit that takes out a detected value of an output voltage during a non-period and compares it with a reference value to generate the drive pulse. Of the detection circuit for detecting the output voltage and the detected value of the output voltage obtained by the detection circuit, a current flows through the load capacitor within the drive pulse width after the drive pulse is input to the inverter. Means for taking out a plurality of the detected values in a non-period and calculating an average value of the plurality of detected values, and setting the calculated average value as a detected value of the output voltage and comparing the detected value with a reference value; The capacitor charging apparatus according to claim 7, further comprising a control circuit that generates the driving pulse. Among the detection circuit for detecting the output voltage and the detected value of the output voltage obtained by the detection circuit, the current does not flow to the load capacitor within the drive pulse width after the drive pulse is input to the inverter. Take out the output voltage four times or more in the period, compare these detection values, exclude the maximum and minimum detection values from the comparison results, and exclude the maximum and minimum detection values And a control circuit that generates the drive pulse by comparing the detected value with a reference value. The capacitor | condenser charging device in any one of Claim 7 thru | or 9.

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