JP2003153532A - Capacitor charging method and capacitor charging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an output voltage detection value which is not delayed, is stable, and has high precision and to improve the precision of charging a capacitor, accordingly. SOLUTION: In a capacitor charging method where an output voltage of a converter circuit, having an inverter made to operate by making the pulses driven with a certain frequency, and a load capacitor is charged to have a set voltage by using the detected output voltage, the detected value of the output voltage in a period, after the driving pulse is inputted to the inverter, within the width of the drive pulse, and while a current is not being applied to the load capacitor, is used as the detected value of the output voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor charging method and apparatus for performing highly accurate and stable detection of a voltage of a load capacitor and periodically charging the load capacitor to a set voltage.

[0002]

2. Description of the Related Art A capacitor charger is used to charge a capacitor at the first stage of a driving pulse power source of a driving pulse laser such as a copper vapor laser or an excimer laser, that is, a load capacitor repeatedly at high speed. In particular, excimer lasers often require highly accurate charging of load capacitors.

A conventional capacitor charger is configured by connecting a rectifier circuit Re to the output of an inverter unit IV as shown in FIG. That is, the capacitor charger is
Direct current voltage source D is controlled by controlling the power output from direct current voltage source DC.
The direct current supplied from C is converted into alternating current (square wave alternating voltage) by the inverter unit IV, the alternating current boosted by the transformer H is rectified by the rectifier circuit Re, and the load capacitor Cd is charged by this rectified current. .

Then, the control unit 100 controls the charging of the load capacitor Cd to be charged by the load capacitor Cd.
By dividing the charging voltage value of d by the voltage divider M1 into a measurement voltage having a proportional relationship with the charging voltage value, and comparing the measured voltage with the set voltage indicating the target value of the charging voltage of the load capacitor Cd. Have control. That is, the control unit 100
Determines whether or not the measured voltage from the voltage divider M1 exceeds the set voltage set inside, and if it exceeds, stops the inverter unit IV at that time and transfers it to the load capacitor Cd. Stop charging.

[0005]

However, since the conventional capacitor charger uses the analog control method, it continuously detects the output voltage. In such analog control, it is necessary for the control unit to take measures against noise so that the detected output voltage value is not affected by noise generated by the high frequency switching operation. A filter of sufficient size is used on the input side of the detection circuit as a measure against noise in detection. As a result, the detected voltage value is detected later than the actual output voltage value, and highly accurate charging cannot be performed. In view of the above problems, the present invention provides a capacitor charging method and a device thereof that can obtain a highly accurate and stable load voltage detection value and can obtain a high-speed and highly accurate output voltage. Is an issue.

[0006]

In order to solve the above-mentioned problems, the first aspect of the present invention is to detect the output voltage of a converter circuit having an inverter operated with a drive pulse of a constant frequency, and to detect the output voltage. In a capacitor charging method for charging the load capacitor to a set voltage by using, the detection of the output voltage in a period within the drive pulse width after the drive pulse is input to the inverter and during which no current flows in the load capacitor. Provided is a method of charging a capacitor, the value of which is the detected value of the output voltage.

In order to solve the above-mentioned problem, the second aspect of the present invention is that one or a plurality of main capacitor chargers having a first inverter operated with a drive pulse of a constant frequency are connected in parallel. By connecting in parallel with a sub-capacitor charger for fine adjustment, which has a second inverter operated by a drive pulse having a constant frequency higher than that of the main capacitor charger, a steep slope is obtained by operating the main capacitor charger. After raising the charging voltage of the load capacitor to just before the set charging voltage, stop the operation of the main capacitor charger and operate only the secondary capacitor charger for fine adjustment with small output power to load with a gentle gradient. In a capacitor charging method for charging a capacitor to a set voltage, within the driving pulse width after the driving pulse is input to the inverter. There is also provided a capacitor charging method, wherein the detected value of the output voltage during the period when no current flows in the load capacitor is the detected value of the output voltage.

In order to solve the above-mentioned problems, the third aspect of the present invention is to provide a plurality of outputs within a period within the drive pulse width after the drive pulse is input to the inverter and during which no current flows in the load capacitor. The capacitor charging according to claim 1 or 2, wherein a voltage is detected, an average value of detection values of the plurality of output voltages is calculated, and the calculated average value is used as the output voltage detection value. Provide a way.

In order to solve the above-mentioned problems, the fourth aspect of the present invention is that the output voltage is set to 4 when the drive pulse is within the drive pulse width after the drive pulse is input to the inverter and no current flows in the load capacitor. Detected more than once, comparing these detection values, out of the detection values from the comparison result, the maximum and minimum detection values are excluded, and the remaining detection values excluding these maximum and minimum detection values The capacitor charging method according to claim 1, wherein an average value is calculated, and the calculated average value is used as the output voltage detection value.

According to a fifth aspect of the present invention for solving the above-mentioned problems, the second inverter is operated with a drive pulse having a constant frequency which is an integral multiple higher than that of the first inverter, and The capacitor charging method according to claim 2, wherein the driving pulse of the second inverter is operated so as to be synchronized.

According to a sixth aspect of the present invention for solving the above-mentioned problems, when a plurality of the main capacitor chargers are connected in parallel, the second inverter is an integer greater than the first inverter. 3. A drive pulse of a constant frequency that is twice as high as the drive pulse, a drive pulse of the first and second inverters are operated in synchronization with each other, and the first inverter is operated in the same phase or in a different phase. 5. A method for charging a capacitor according to any one of 5 above is provided.

In order to solve the above-mentioned problems, a seventh aspect of the present invention provides a detection circuit for detecting an output voltage of a converter circuit having an inverter operated with a drive pulse having a constant frequency, and an output obtained by the detection circuit. Of the detected voltage values, the detected value of the output voltage during the period when the drive pulse is input to the inverter and within the drive pulse width and when no current flows in the load capacitor is extracted and compared with a reference value. A capacitor charging device comprising: a control circuit for generating the drive pulse.

In order to solve the above-mentioned problems, the eighth aspect of the present invention is that one or a plurality of main capacitor chargers having a first inverter operated with a drive pulse of a constant frequency are connected in parallel. By connecting in parallel with a sub-capacitor charger for fine adjustment, which has a second inverter operated by a drive pulse having a constant frequency higher than that of the main capacitor charger, a steep slope is obtained by operating the main capacitor charger. After raising the charging voltage of the load capacitor to just before the set charging voltage, stop the operation of the main capacitor charger and operate only the secondary capacitor charger for fine adjustment with small output power to load with a gentle gradient. In a capacitor charging device that charges a capacitor to a set voltage, a detection circuit that detects an output voltage and an output voltage obtained by the detection circuit Of the detected values, the detected value of the output voltage in a period within the drive pulse width after the drive pulse is input to the inverter and no current flows in the load capacitor is extracted and compared with a reference value to drive the drive. A capacitor charging device comprising: a control circuit for generating a pulse.

In order to solve the above-mentioned problems, a ninth aspect of the present invention provides a detection circuit for detecting an output voltage, and the drive pulse among the detection values of the output voltage obtained by the detection circuit is input to the inverter. And a means for calculating an average value of the plurality of detection values during a period in which a current does not flow in the load capacitor within the drive pulse width after the operation, and the calculated average value. 9. The capacitor charging device according to claim 7, further comprising: a control circuit that generates the drive pulse by comparing the detected value with an output voltage as a detection value and a reference value. To do.

According to a tenth aspect of the present invention to solve the above-mentioned problems, a detection circuit for detecting an output voltage, and among the detection values of the output voltage obtained by the detection circuit, the drive pulse is input to an inverter. After that, the output voltage is taken out four or more times during the period when the current does not flow in the load capacitor within the drive pulse width, these detection values are compared, and from the comparison result, the maximum and minimum of the detection values are detected. The detected value is excluded, the average value of the remaining detected values excluding these maximum and minimum detected values is calculated, and the calculated average value is used as the detected value of the output voltage, and the detected value and the reference value are compared. 10. A capacitor charging device according to any one of claims 7 to 9, further comprising a control circuit for generating the drive pulse.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION In the capacitor charging of the present invention, it is desired to repeatedly switch a switching element at a high frequency at a frequency determined by the resonance frequency of the resonance inductance in the converter and the resonance capacitor to increase the drive pulse width of this switching. The amount of power supplied is adjusted by controlling according to the output voltage, and the load capacitor is charged to the target voltage value at high speed. The drive pulse width of the switching element for adjusting the power supply amount is determined by the detected value of the output voltage, and the width is controlled.

The detected value of the output voltage is detected in a period within a drive pulse width after a certain drive pulse is input to the inverter and during which no current flows in the load capacitor, that is, during a period in which the output voltage does not rise. The detected value of the output voltage is used as the detected output voltage. Based on the detected output voltage detection value, the switching element after the next half cycle is turned on to supply electric power to determine whether or not to increase the output voltage value, and further turn on the switching element. In that case, control is performed to determine the on-time for controlling the amount of power supply.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of a capacitor charger including a converter circuit including a resonant inverter and a rectifier circuit and a control circuit thereof. The resonant inverter includes an inverter unit IV, a resonant inductor Lr, a transformer H, a resonant capacitor Cd, and the like. In this figure, an inverter unit IV is of a drive pulse width modulation type composed of switching elements S1 to S4 such as FETs (field effect transistors) and IGBTs (insulated gate bipolar transistors), and is a commercial AC voltage. The DC voltage output from the rectified DC voltage source DC is converted into a square wave AC voltage (hereinafter referred to as AC voltage).

When generating an AC voltage, the inverter unit IV controls the drive pulse train that is input so as to alternately turn on the combination of the switching elements S3 and S2 and the combination of the switching elements S1 and S4. , Converts DC voltage to AC voltage. On the primary side of the step-up transformer H, one terminal is connected to the inverter section IV via the resonance inductor LR and the other terminal is directly connected to the inverter section IV. In the transformer H, the resonance capacitor Cr is inserted between the terminals on the secondary side,
It is connected to the rectifier circuit Re. The resonance capacitor Cr may be connected to the primary side. Rectifier circuit Re
Is composed of rectifying diodes D1 to D4, performs full-wave rectification on the boosted AC voltage output from the transformer H, and outputs it to the load capacitor Cd as a DC charging current.

Next, the control circuit 1 will be described. It is detected by the detection circuit 3 through the voltage divider 2 that divides the output voltage at a predetermined ratio. Since the voltage divider 2 and the detection circuit 3 are ordinary ones, a description thereof will be omitted. However, it is preferable that the input and output sides of the detection circuit 3 are not connected to a filter circuit including a capacitance serving as a delay element. The detected value of the output voltage detected by the detection circuit 3 is converted into a digital value by the analog-digital converter (A / D) 4. The digitized detection voltage is sequentially captured in a register (not shown) in an FPGA (field programmable gate array) 6 at a time interval sufficiently shorter than the switching cycle of the inverter. And CPU
(Central processing unit) 5, based on a pulse (reference drive pulse) serving as a reference of a drive signal of a switching element, that is, after a certain drive pulse is input to the resonant inverter, Since the current does not flow in the load capacitor Cd within the drive pulse width, the detected value of the output voltage stored in the register in the FPGA 6 is read by the signal from the CPU 5 during the period in which the output voltage does not rise, and the value in the CPU 5 is read. It is stored in the RAM 5a.

The CPU 5 also performs arithmetic processing for predictive control based on the reference drive pulse and the value stored in the RAM 5a, and generates a pulse signal that determines the ON time of the switching element. By
It is distributed as a signal for the switching elements S1 and S4 of the inverter or a signal for the switching elements S2 and S3 and sent to the drive circuit 7. In the drive circuit 7, a driving voltage is generated based on this signal and applied to the switching element of the inverter to perform the switching operation. Here, CPLD (Complex Programmable Logic Device) or the like may be used in addition to the FPGA 6. Further, the above processing may be performed only by the CPU 5 without using the FPGA 6 or the CPLD.

Next, the circuit operation in the switching half cycle of this capacitor charging device will be described with reference to FIGS. 2 and 3. In FIG. 2, the horizontal axis represents time, the vertical axis in the upper stage shows the drive pulses of the switching elements S1 and S4 and the drive pulses of the switching elements S2 and S3, and the middle stage shows the current of the resonance capacitor and the load capacitor. , The lower part shows the output voltage. FIG. 3 shows the current flow in each region when the circuit operation in the switching half cycle of the capacitor charger is divided into three operating regions.

As shown in FIG. 3A, a period a in FIG. 2 is a period until the secondary side rectifying diodes D1 and D4 start to conduct when the switching elements S1 and S4 are in an ON state, That is, this is the case where the voltage of the resonance capacitor Cr is lower than the voltage of the load capacitor Cd. During this period, a current flows only in the resonance capacitor Cr and a current does not flow in the load capacitor Cd, so that the output voltage, that is, the voltage of the load capacitor Cd becomes constant. In the present invention, the switching elements S1 and S4 or S
In the state where the drive pulse is applied to S3 and S2, the period in which the output voltage is constant is defined as the output voltage detection period a, and one or more of the detection values detected in the output voltage detection period a are defined as the output voltage detection value. To use.

Then, when the resonance capacitor Cr is charged to substantially match the voltage of the load capacitor Cd, as shown in FIG. 3B, the rectifying diodes D1 and D on the secondary side are charged.
Since 4 starts to conduct (time t2 in FIG. 2), it is a period in which a current flows through the load capacitor Cd. For this reason,
During the output voltage rise period b of 1, the output voltage rises because the load capacitor Cd is also charged. This continues while switching elements S1 and S4 are in the on state.

After the switching elements S1 and S4 are turned off, energy is recovered to the input side through the internal diodes of the switching elements S3 and S2 as shown in FIG. 3 (c). In this period as well, since the rectifying diodes D1 and D4 on the secondary side become conductive, a current flows through the load capacitor Cd, and the output voltage rises (period c in FIG. 2). As can be seen from the above description, the detection of the output voltage is performed during the period in which the output voltage is constant, at times t1 to t in FIG.
Since it is performed within 2 (output voltage detection period a), the output voltage can be accurately and stably detected without providing a filter circuit as a delay element in the preceding stage of the detection circuit. further,
As shown at the bottom of FIG. 2, the ts after the time t1 at which the switching element is turned on avoids a sufficient fixed period considered not to be affected by the instantaneous generation of noise when the switching element is turned on. From the time point, similarly, in order to sufficiently avoid the occurrence of instantaneous noise due to the conduction of the secondary side rectification diode, a time point before the time point t2 when the secondary side rectification diode is conducted so as to avoid this influence. t
It is preferable to carry out during f.

Next, the detection of the output voltage and the control method using the detected value will be specifically described. CPU5
When the output voltage detection period a comes after the reference drive pulse described above is turned on, that is, is generated, the FPG
The CPU 5 is set in advance so that the detected value of the output voltage stored in the register (not shown) of A6 can be read. The read output voltage detection value is stored in the RAM 5a in the CPU 5. As shown in the output voltage waveform in the lower part of FIG. 2, it is assumed that the output voltage detection value detected in the output voltage detection period a at a certain drive pulse is Vn. At this time, from the output voltage values Vn-1 and Vn detected in the output voltage detection period half cycle before the output voltage detection value Vn and stored in the register of the CPU 5, the output voltage ΔVn increased during this period. = Vn-Vn-1 is calculated. Using this result, the voltage value ΔVn + 1 rising in the next half cycle is ΔV
Assuming the same as n, the next output voltage value Vn + 1 = Vn +
Predict to be ΔVn.

Next, Vn + 1 is compared with the target output voltage Vf. When the predicted next output voltage Vn + 1 is smaller than the target output voltage Vf (Vn + 1 <Vf), the operation is performed with a predetermined substantially constant pulse width. When the predicted next output voltage Vn + 1 becomes larger than the target output voltage Vf (Vn + 1> Vf), it is necessary to control the pulse width for the first time. First, ΔV = Vf−Vn + 1 is calculated,
Find the voltage value to increase to the target voltage. Where Δ
The CPU 5 calculates the on-time of the switching element required to increase the voltage V by using the value stored in advance to obtain the relationship between the on-time of the switching element and the increase in the output voltage. .

Here, when the ON time of the switching element is changed, the output voltage increase amount in a half cycle of one switching cycle is the output voltage increase period b due to the ON state of the switching element and the OFF state of the switching element. This is due to the subsequent conduction period of the secondary side rectifying diode (period c in FIG. 2). Regarding the relationship between the ON time of the switching element and the increase of the output voltage, the output voltage rising in a half cycle with respect to the ON time of the switching element has a one-to-one relationship. In particular, the time ta during which the voltage does not rise after the drive pulse is turned on is stored in the ROM 5 of the CPU 5. Further, when the ON time of the switching element and the voltage increase amount have a proportional relationship, ΔV / Δt is stored in the CPU 5. In the calculation, this stored relationship is used to obtain the on-time tx of the switching element during the output voltage rise period b, and then the time ta is added to this result to obtain the on-time ton = of the switching element. ta + tx
Ask for. ON time ton of the obtained switching element
To control the pulse width of the last half cycle.

The output voltage is detected in the output voltage detection period a
Since the output voltage is constant, it is necessary to detect the output voltage only once during this period. However, in order to further improve the accuracy of the detected value, the FPGA 6 performs arithmetic processing to obtain the average value of the plurality of detected values, Output averaged output voltage detection value is F
It is stored in a register (not shown) of the PGA 6. Similar to the method described above, the averaged detection value is taken into the CPU 5 as the output detection value during the output voltage detection period a, and the CPU 5
May be stored in a register (not shown). Further, in order to further improve the accuracy of the output voltage detection by eliminating the detection value that may be affected by noise, a plurality of detection values, for example, four or more detection values are used in the FPGA 6 described above,
When performing the arithmetic processing for obtaining the average value of the detected values, 4
The two or more detection values are compared with each other, the detection values that are the maximum value and the minimum value are respectively excluded, the average value of the remaining two or more detection values is obtained, and the averaged detection value is detected as the output voltage. It may be a value.

Here, the detected output voltage values Vn, V
n-1 is a digitized value. In reality, the voltage value ΔVn that increases with the amount of charge in the switching half cycle of the switching element gradually decreases as the charging voltage of the capacitor Cd increases. That is, the rising voltage value Δ
In Vn, n is a natural number and the rising voltage value ΔV1,
For ΔV2, ΔV3, ΔV4, ..., The voltage charged with the same set pulse width gradually decreases. However, the difference in the voltage increase in one half cycle becomes smaller as the output voltage value increases, and the voltage increases adjacent to each other are almost equal to each other just before the target voltage Vf.

Here, after the output voltage reaches the voltage V 1 which is lower than the target voltage Vf and is charged to such an extent that the difference in the charge amount in the switching half cycle of the switching element becomes small, Assuming that the voltage component ΔV n rising in the half cycle of the switching element and the voltage component ΔVn + 1 rising in the next half cycle of the switching element are almost the same, the output voltage Vn + 1 after the next half cycle is predicted and the switching element Control the on-time of the.

When the ON time of the switching element is changed, the output voltage increase in one switching half cycle also changes when the input voltage changes. However, if the target output voltage can be charged with a sufficiently high accuracy, in order to omit the means for detecting the output voltage,
It is not necessary to consider the fluctuation of the input voltage. When considering the fluctuation of the input voltage, the capacitor charger is provided with a detection circuit for detecting the input voltage. Further, in the CPU in the control circuit, the output voltage which rises in a half cycle with respect to the ON time of the switching element according to the input voltage is 1: 1.
Is stored and the above-mentioned pulse width is controlled based on the detected value of the detected input voltage.

Further, the target voltage value Vf is a final set voltage which is set in the CPU in the control circuit and is a target of the charging voltage value V1 for the load capacitor Cd. It should be noted that the maximum width of this drive pulse is such that, in the ON / OFF operation of the switching elements S1 to S4, the switching elements S1 and S2 or S3 and S4 are not turned on at the same time by the adjacent drive pulses and short-circuited. It is calculated as the pulse width of the maximum duty cycle possible within the range where the capacitor charger can be operated normally at the switching frequency. When the charging time has a margin, a drive pulse having a drive pulse width set to be smaller than the maximum drive pulse width may be used, or the drive pulse width several times before may be adjusted or the number of drive pulses may be adjusted. Here, at the initial stage of charging, charging may be started with a soft start drive pulse having a constant drive pulse width smaller than the constant drive pulse width or a drive pulse width that gradually increases.

In the above-described embodiment, the example in which the load capacitor is charged by the single capacitor charger has been described, but as compared with the main capacitor charger M having a large output capacity as shown in FIG. The secondary capacitor charger S having a small output capacity is connected in parallel, and the charging power by the driving pulse immediately before the final driving pulse from the first charging is the main capacitor charger M, or the main capacitor charger M and the secondary capacitor charger. S and S, and at least charging power by the final drive pulse may be supplied from the secondary capacitor charger M. In this case, the output voltages of the main capacitor charger M and the slave capacitor charger S are substantially equal to each other, and the amount of electric power supplied by the main capacitor charger M is several to several tens of times that of the slave capacitor charger S. Therefore, it is preferable that the frequency of the driving pulse is several times to several tens of times that of the sub capacitor charger S as compared with the main capacitor charger M, and the driving pulses are synchronized with each other.

The main capacitor charger M and the sub-capacitor charger S have the same configuration as that of FIG. 1, and each inverter section IV1, IV2 corresponds to the inverter section IV of FIG. 1, and the rectifier circuit Re1, Re2 is the rectifier circuit Re of FIG.
Corresponding to the above, the resonance circuits K1 and K2 are the same as the circuit including the transformer H, the resonance inductor Lr, and the resonance capacitor Cr. Then, the control circuit 1 uses the inverter unit IV.
1 and IV2 respectively, and each control circuit is composed of the same circuit as shown in FIG.

The output voltage of the capacitor charger including the main capacitor charger M and the slave capacitor charger S is shown in FIG. Up to a certain voltage V1 lower than the target voltage, the main capacitor charger M and the sub capacitor charger S are operated,
After the charging voltage of the load capacitor is increased steeply, the operation of the main converter circuit is stopped and only the fine adjustment converter circuit with a small output power is operated to charge the load capacitor to the target voltage with a gentle gradient.

Further, the main capacitor charger M and the slave capacitor charger S may have the same circuit configuration,
For example, if the main capacitor charger M supplies 99% or more of the required charging power and the sub-capacitor charger S is 1% or less, the sub-capacitor charger S does not have to be a resonance type circuit configuration. Since the power loss is small, a circuit configuration using a general drive pulse width control type high frequency inverter unit that is not a resonance type may be used.

Further, when a plurality of main capacitor chargers M are connected in parallel in the embodiment shown in FIG. 4, the inverter of the sub capacitor charger S is replaced by the main capacitor charger M.
It is preferable that the inverters of the main capacitor charger M are operated in the same phase or in different phases while operating with drive pulses having a constant frequency that is an integer multiple higher than that of the above inverters. .

Although one embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and design changes and the like within a range not departing from the gist of the present invention. Even so, it is included in the present invention.

Further, in the above description, the width of the drive pulse is explained as the maximum drive pulse width allowed or the set drive pulse width. However, the width of the drive pulse sets the charging time for charging the load capacitor to the target voltage value. It is of course necessary to charge the battery within the set charging time, but if the charging time is faster than the set charging time, the charging voltage will drop due to discharging, so the goal is It is preferable to determine the driving pulse width of the driving pulse so that the charging up to the voltage value ends just before the set charging time.

[0041]

EFFECTS OF THE INVENTION The present invention has the characteristics as described above, and by performing detection of a capacitor charger that charges to a target voltage during a certain period during which the load voltage does not rise,
It is possible to obtain a stable and highly accurate load voltage value, which can improve the charging accuracy of the capacitor.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a capacitor charger according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a drive pulse of switching elements S1 and S4, a drive pulse of switching elements S2 and S3 of a parallel resonant converter, a current flowing through a resonance capacitor current and a load capacitor current, and a load capacitor. It is a figure which shows the relationship with the output voltage of.

FIG. 3 is an explanatory diagram showing an operation from a region a to a region c when a half cycle of the parallel resonant converter is divided into three regions.

FIG. 4 is a diagram showing a configuration of a capacitor charger according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an operation waveform of an output voltage of the capacitor charger according to the second embodiment of the present invention.

FIG. 6 is a conceptual diagram showing a configuration of a conventional parallel resonance type converter.

[Explanation of symbols]

1-Control Circuit 2-Voltage Divider 3-Detection Circuit for Output Voltage Detection 4-Analog Digital Converter 5-CPU 6-FPGA (Field Programmable Gate Array) IV-Inverter Re-Rectifier Circuit H-Transformer Cd-load capacitor

Claims (10)

[Claims] 1. A capacitor charging method for detecting an output voltage of a converter circuit having an inverter that operates with a drive pulse having a constant frequency, and using the detected output voltage value to charge the load capacitor to a set voltage. A capacitor charging method, wherein a detected value of an output voltage in a period within a drive pulse width of a pulse after the pulse is input to the inverter and a current does not flow to the load capacitor is the output voltage detected value. 2. One or a plurality of main capacitor chargers having a first inverter operated in parallel with a drive pulse of a constant frequency, which are connected in parallel, and a constant frequency drive higher than the main capacitor charger. The secondary capacitor charger for fine adjustment, which has a second inverter operated by pulse, is connected in parallel, and the main capacitor charger is operated to steeply increase the charging voltage of the load capacitor until just before the set charging voltage. After that, the operation of the main capacitor charger is stopped, and only the sub-capacitor charger for fine adjustment of small output power is operated to charge the load capacitor to a set voltage with a gradual gradient. No current flows in the load capacitor within the drive pulse width after the drive pulse is input to the inverter. Capacitor charging method, characterized by said output voltage detection value detected value of the output voltage between. 3. A plurality of output voltages are detected during a period within a drive pulse width of the inverter after the drive pulse is input to the inverter and a current does not flow in the load capacitor,
The capacitor charging method according to claim 1 or 2, wherein an average value of detection values of the plurality of output voltages is calculated, and the calculated average value is used as the output voltage detection value. 4. The output voltage is detected four times or more during a period within the drive pulse width after the drive pulse is input to the inverter and no current flows through the load capacitor, and the detected values are compared, Of the detection values from the comparison result, the maximum and minimum detection values are excluded, the average value of the remaining detection values excluding these maximum and minimum detection values is calculated, and the calculated average value is 4. The capacitor charging method according to claim 1, wherein the output voltage detection value is used. 5. The second inverter is operated with a drive pulse having a constant frequency that is an integral multiple higher than that of the first inverter, and the drive pulses of the first and second inverters are synchronized with each other. The method of charging a capacitor according to claim 2, wherein 6. When a plurality of the main capacitor chargers are connected in parallel, the second inverter is operated with a drive pulse having a constant frequency that is an integral multiple higher than that of the first inverter, 6. The capacitor according to claim 2, wherein the driving pulses of the first and second inverters are operated so as to be synchronized with each other, and the first inverter is operated in the same phase or in the different phase. How to charge. 7. A detection circuit for detecting an output voltage of a converter circuit having an inverter operated by a drive pulse having a constant frequency, and the drive pulse among the detection values of the output voltage obtained by the detection circuit is the inverter. A control circuit for generating a drive pulse by extracting a detected value of an output voltage during a period in which a current does not flow in the load capacitor within a drive pulse width after being input to the load capacitor and comparing the detected value with a reference value. Capacitor charging device characterized by. 8. One or a plurality of main capacitor chargers having a first inverter operated in parallel with a drive pulse of a constant frequency are connected in parallel, and a drive of a constant frequency higher than the main capacitor charger. The secondary capacitor charger for fine adjustment, which has a second inverter operated by pulse, is connected in parallel, and the main capacitor charger is operated to steeply increase the charging voltage of the load capacitor until just before the set charging voltage. After that, the operation of the main capacitor charger is stopped, and only the sub-capacitor charger for fine adjustment with small output power is operated to charge the load capacitor to the set voltage with a gentle gradient. A detection circuit for detecting a voltage, and among the detection values of the output voltage obtained by the detection circuit, the drive pulse is A control circuit for generating a drive pulse by extracting a detected value of an output voltage during a period in which a current does not flow in the load capacitor within a drive pulse width after being input to the load capacitor and comparing the detected value with a reference value. Capacitor charging device characterized by. 9. A detection circuit for detecting an output voltage, and among the detection values of the output voltage obtained by the detection circuit, the load within the drive pulse width after the drive pulse is input to the inverter. A means for taking out a plurality of the detection values during a period in which no current flows in the capacitor and calculating an average value of the plurality of detection values, the calculated average value is used as a detection value of the output voltage, and the detection value and the reference value 9. The capacitor charging device according to claim 7, further comprising a control circuit that generates the drive pulse in comparison with a value. 10. A detection circuit for detecting an output voltage, and among the detection values of the output voltage obtained by the detection circuit, the load capacitor within the drive pulse width after the drive pulse is input to the inverter. The output voltage is extracted four times or more during the period when no current flows in the device, the detected values are compared, the maximum and minimum detected values among the detected values are excluded from the comparison result, and the maximum and minimum detected values are detected. A control circuit that calculates the average value of the remaining detection values excluding the values, sets the calculated average value as the detection value of the output voltage, and compares the detection value with a reference value to generate the drive pulse. The capacitor charging device according to any one of claims 7 to 9, characterized in that.