JP3865335B2 - High frequency power amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high frequency power amplifying device for a digital wireless communication device, and more particularly to a TDMA type digital wireless device that performs negative feedback control to compensate for nonlinear distortion of a transmitting high frequency power amplifier.
[0002]
[Prior art]
In recent mobile phones, PHS, and the like, TDMA digital radio communication technology is used for effective use of frequencies. In such digital radio communication devices, linear modulation schemes such as QPSK and 16QAM are used. It is increasing. On the other hand, a high-frequency power amplifying device for a wireless communication device is desired to have a linear amplification factor that amplifies and outputs a change in the input level as it is, but the actual high-frequency power amplifying device has a nonlinear distortion. is doing.
In many digital wireless communication devices, non-linear distortion in the amplification characteristics of the above-described high-frequency power amplifying device is restored while demodulating part of the output with a negative feedback circuit. The difference in the output of the amplifying device is compensated. An example of such a negative feedback amplifier is a Cartesian loop negative feedback amplifier.
Hereinafter, an example of the configuration of a conventional Cartesian loop type negative feedback amplification device will be described with reference to FIG.
Input baseband signals I and Q are input to the terminals 15 and 16. I and Q are values of two axes orthogonal to each other on a virtual plane for projecting a digital value in a linear modulation method onto a baseband phase change, and the phase of an input baseband signal is a combined angle of I and Q. Correspondingly, the amplitude of the input baseband signal is represented by values of I and Q.
The subtractor 1 and the subtracter 2 subtract the feedback baseband signals I ′ and Q ′ demodulated from the amplified antenna output signal and returned by negative feedback from the input baseband signals I and Q, and the result Output difference signals Ix and Qx.
The quadrature modulator 3 performs quadrature modulation with the difference signals Ix and Qx to which a carrier wave signal having an angular frequency ωc generated by a transmitter 7 described later is input, and outputs a quadrature modulated wave S for antenna transmission. The orthogonal modulation wave S is expressed by the following formula.
S = Ixcos ωct + Qxsin ωct
The power amplifier 4 amplifies the quadrature modulated wave S input from the quadrature modulator 3 and outputs it as a transmission signal SA.
[0003]
The antenna 5 radiates a transmission wave of the digital radio communication apparatus or receives a reception wave. In the case of FIG. 10, the antenna 5 radiates a transmission signal SA.
The attenuator 6 attenuates the transmission signal SA amplified by the power amplifier 4 to the level of the circuit before amplification in the negative feedback circuit and outputs the feedback signal SB.
The transmitter 7 is for generating a carrier wave signal having an angular frequency ωc for wireless transmission / reception.
The phase shifter 8 can output a demodulation carrier signal obtained by shifting the phase of the carrier signal generated by the transmitter 7 by an arbitrary angular frequency.
The orthogonal demodulator 9 orthogonally demodulates the input feedback signal SB with the demodulation carrier signal, and outputs feedback baseband signals I ′ and Q ′.
The feedback baseband signals I ′ and Q ′ are input to the subtractor 1 and the subtractor 2 as negative feedback signals as described above, and a difference signal between the input baseband signals I and Q is output. By controlling the amplification degree of the power amplifier 4 so as to decrease, the nonlinear distortion of the power amplifier 4 can be compensated.
By the way, in a high frequency amplifier of a digital wireless communication apparatus that performs such negative feedback, transmission is generally performed depending on the length of the negative feedback loop of the negative feedback circuit, the frequency characteristics and temperature characteristics of the power amplifier 4, the load variation of the antenna 5, and the like. The feedback signal SB is delayed compared to the signal SA, and the phases of the two carriers are different. Therefore, if the phase shift amount of the phase shifter 8 is a fixed value, a difference in carrier phase occurs between the input baseband signal SA and the feedback baseband signal SB when the delay amount changes due to the above-described reason. The compensation characteristic of the distortion of the feedback amplifier is deteriorated.
[0004]
FIG. 11 is a diagram exemplarily showing in the IQ virtual plane that the feedback signal SB is delayed compared to the transmission signal SA and the phases of the two carriers are different from each other for the sake of explanation.
FIG. 11 shows a case where the feedback baseband signal SB has a phase difference Δθ due to the delay of the input baseband signal SA on the IQ virtual plane. The input baseband signal SA and the feedback baseband signal SB are shown as combined vectors of the input baseband signals I and Q and the feedback baseband signals I ′ and Q ′ along the I axis and the Q axis, respectively. The composite vector SB is shown with a phase delay of SA by the phase difference Δθ. As described above, when the feedback baseband signal SB is delayed with respect to the input baseband signal SA on the IQ virtual plane and a phase difference occurs in the combined vector, the distortion compensation characteristics of the negative feedback amplifier deteriorate.
Returning to FIG. 10, if the phase shifter 8 has a fixed value, the distortion compensation characteristic of the negative feedback amplifier is deteriorated as described above, so that the phase shifter 8 can be changed in accordance with the change in the delay amount. In addition, in the conventional Cartesian loop negative feedback amplifier, the phase difference between the input baseband signal SA and the feedback baseband signal SB is detected, and the phase of the carrier wave of the transmitter 7 is shifted by the phase difference 8 by the phase difference. Are input to the quadrature demodulator 9.
First, the input baseband signals I and Q are converted into digital signals by the A / D converters 11 and 12, and the feedback baseband signals I 'and Q' are converted into digital signals by the A / D converters 13 and 14. And the phase difference between the two signals is calculated according to the following equation.
Δθ = tan −1 (Q ′ / I ′) − tan −1 (Q / I)
The phase control circuit 10 outputs a control signal that causes the phase shifter 8 to shift the phase of the carrier wave of the transmitter 7 by the phase difference Δθ based on the calculated phase difference Δθ. As a result, the input baseband signal and the feedback base The phase difference of the band signal is reduced, and finally the deterioration of the distortion compensation characteristic of the negative feedback amplifier is reduced.
[0005]
[Problems to be solved by the invention]
However, in the high frequency power amplifier of the conventional digital wireless communication apparatus, four A / D converters are required to obtain the phase difference between the input baseband signal and the feedback baseband signal, and the timing of each converter is required. Needed to match exactly. Further, a combined vector of the input baseband signal SA and the feedback baseband signal SB is calculated from the input baseband signals I and Q of the four A / D converters and the input signals of the feedback baseband signals I ′ and Q ′. Since the phase difference Δθ of the combined vector is calculated, the amount of calculation is large and the circuit scale of the arithmetic element is increased, resulting in an increase in cost.
The present invention has been made in view of the above-described background, and it is an object of the present invention to provide a small-sized and inexpensive high-frequency power amplifier without deterioration in performance by using a phase control circuit with a simple configuration.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, a high frequency of a digital wireless communication apparatus having a negative feedback circuit of a transmission circuit and a phase means for matching the phase of a carrier wave signal used for demodulating the feedback signal with the feedback signal. In the power amplifier, the binarization means for binarizing depending on whether or not the feedback signal exceeds a predetermined value, the output signal of the binarization means, and the signal indicating the rising timing of the burst signal, the level of the input signal and the feedback signal. Phase control means for estimating the phase difference and outputting a control signal for the phase means is provided, and at the rising edge of the burst signal of the transmission circuit, the input baseband signal and the feedback baseband signal are sampled to obtain I of the IQ virtual plane. The point of intersection in the axis or Q axis is detected, and the phase difference between the input baseband signal and the feedback baseband signal is determined according to the order of the detected intersection. Estimated to have decided phase control amount of the phaser.
That is, the invention of claim 1 makes a transmission carrier signal generated from a signal generating means a modulated signal modulated by an input signal, amplifies the modulated signal and transmits it as an output signal, and a transmission circuit for the output signal. A negative feedback circuit of the transmission circuit for branching a part as a feedback signal, demodulating the feedback signal and the carrier wave signal to obtain a demodulated feedback signal, and obtaining a compensation input signal from a difference between the input signal and the demodulated feedback signal; In a high-frequency power amplifier of a digital radio communication apparatus having phase means for matching the phase of the carrier wave signal used for the demodulated feedback signal to the feedback signal, binarization is performed depending on whether or not the feedback signal exceeds a predetermined value The phase difference between the input signal and the feedback signal is estimated from the binarizing means that performs the processing, and the output signal of the binarizing means and the signal that indicates the rising timing of the burst signal. Characterized in that it comprises a phase control means for outputting a control signal of the phase section.
According to a second aspect of the present invention, the phase control means outputs an AND means for outputting a logical product of the sampling clock signal of the binarization means and the output signal of the binarization means, and an output signal of the AND means. Counting means for counting and resetting up to a signal indicating the rising timing of the burst signal, computing means for obtaining the difference between the output of the counting means and the clock signal expected from the phase of the input signal, and the computation result of the computing means Conversion means for converting into a phase control amount in the phase means.
The invention of claim 3 is characterized in that the predetermined value in the binarizing means is a value in which Q in the IQ virtual plane is 0 (I axis) or I is 0 (Q axis).
The invention of claim 4 is characterized in that the signal indicating the rising timing of the burst signal is the number of clock signals during a period when the I or Q signal rises in the IQ virtual plane.
According to a fifth aspect of the present invention, the phase control means calculates a phase difference between the input signal and the feedback signal at a timing at which the signal intersects the I axis or the Q axis at least when the feedback signal rises in an IQ virtual plane. It is characterized by detecting the difference.
According to a sixth aspect of the present invention, the timing at which the signal crosses the I axis or the Q axis in the phase control means is detected by changing the signal I or Q from positive to negative or vice versa. It is characterized by doing.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
The high-frequency power amplifier of the digital wireless communication apparatus of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, the same functions as those in FIG. 10 of the prior art are given the same numbers. Specifically, terminals 15 and 16 of the transmission system and negative feedback system, subtractor 1 and subtractor 2, quadrature modulator 3, power amplifier 4, antenna 5, attenuator 6, transmitter 7, phase shifter 8, The quadrature demodulator 9 is the same as that shown in FIG.
The prior art FIG. 10 differs from FIG. 1 of the present invention in that, in FIG. 10 of the prior art, the signals input to the phase control circuit 10 are both I and Q of the input baseband signal and the feedback baseband signal. Both of I ′ and Q ′ are A / D converted by their own A / D converters, and the phase control circuit 10 detects the phase difference between the input baseband signal and the feedback baseband signal from the four signals. Thus, the phase control signal is sent to the phase shifter 8.
On the other hand, the signals input to the phase control circuit 18 of FIG. 1 of the present invention are the binary signal I′z detected by the zero-cross comparator 17 of the feedback baseband signal I ′, the burst rising timing signal TU, and The sample clock CLK estimates the phase difference between the input baseband signal and the feedback baseband signal from these signals and sends a phase control signal to the phase shifter 8. Although the binarized signal input to the phase control circuit 18 is the binarized signal I′z in this embodiment, at least one (or both) of the feedback baseband signal I ′ or Q ′ is used. The signal can be used as a binary signal detected by a zero cross comparator.
[0008]
The zero cross comparator 17 receives the I ′ signal (or Q ′ signal) of the feedback baseband signal SB demodulated by the quadrature demodulator 9 and crosses the I axis (or Q axis) of the IQ virtual plane. A point (zero-crossing) is detected, and a binary signal I′z (or Q′z) having a difference between positive and negative on the I axis (or Q axis) is output at the intersection.
The phase control circuit 18 receives the binarized signal I′z, a burst rise timing signal TU, which will be described later, and a sample clock CLK, and receives a phase difference at the rise of the input baseband signal SA and the feedback baseband signal SB. Δθ is estimated, and a phase control output to the phase shifter 8 is performed according to the phase difference. Here, detection of the phase difference at the time of rising of the input and feedback baseband signals in the IQ virtual plane, which is a basic concept of the present invention, will be described.
[0009]
FIG. 2 is a diagram showing a detection range of a phase difference at a point where either the input or feedback baseband signal on the IQ virtual plane crosses the Q axis at the time of rising (zero crossing).
The rising signal of the burst signal in the IQ virtual plane is represented as a rising signal LS1. Assuming that the rising signal LS1 is a signal at the rising time of the input baseband signal, the rising signal of the ideal feedback baseband signal has the same locus as the rising signal LS1 with a phase difference of 0 ° from the rising signal LS1. Is a signal. However, since the phase of the actual feedback baseband signal is delayed due to the frequency characteristics of the power amplifier described above, for example, it is expressed as a rising signal LS2 in FIG.
In other words, it can be said that the rising signal LS2 represents a feedback baseband signal when the phase difference is delayed by 90 ° when the rising signal LS1 is when the input baseband signal rises.
The phase when the input baseband signal rises and the phase when the feedback baseband signal rises can be detected on the positive side of the Q axis of the IQ virtual plane because both the input and feedback baseband signals rise when the Q axis rises. Therefore, if the rising time of both baseband signals is between the rising signal LS2 and the rising signal LS3 in FIG. 2, the phase difference can be detected. Become. In this case, the rising signal LS2 crosses the positive side of the Q axis is the locus of the rising signal immediately before the transmission power becomes constant from the rising time, and the rising signal LS3 is the rising side of the positive side of the Q axis. It represents the trajectory of the rising signal immediately before it does not cross.
By detecting the phase difference of the rising signal on the positive side and negative side of the Q axis of the IQ virtual plane and on the positive side and negative side of the I axis as described above, detection of the phase difference on almost the entire IQ virtual plane. Is possible.
[0010]
FIG. 3 is a diagram for explaining various cases in which the phase difference of the rising signal of the burst signal is detected.
FIG. 3A shows a case where a rising signal similar to that in FIG. 2 passes the positive side of the Q axis on the IQ virtual plane. In this case, the value of I (binarized signal I′z) changes from positive to negative. The phase difference is detected by detecting the timing of changing to.
FIG. 3B shows a case where the rising signal passes through the negative side of the Q axis of the IQ virtual plane, and in this case, the timing at which the value of I (binarized signal I′z) changes from negative to positive is detected. By doing so, the phase difference is detected.
FIG. 3C shows a case where the rising signal passes the negative side of the I axis of the IQ virtual plane, and in this case, the timing at which the value of Q (binarized signal Q′z) changes from positive to negative is detected. By doing so, the phase difference is detected.
FIG. 3D shows a case where the rising signal passes the positive side of the I axis of the IQ virtual plane, and in this case, the timing at which the value of Q (binarized signal Q′z) changes from negative to positive is detected. By doing so, the phase difference is detected.
[0011]
FIG. 4 is a diagram illustrating the rising timing of the burst signal of the input baseband signal during transmission.
FIG. 4A is a timing chart showing a timing signal in the rising period of the burst signal.
When the burst signal is output for the transmission period TXT, a rising period BL occurs when the burst signal rises. This rising period BL is detected by a rising signal generator described later to obtain a rising timing signal TU of the burst signal.
FIG. 4B is a diagram illustrating a signal locus of the rising period of the burst signal of the input baseband signal in the IQ virtual plane.
When the burst signal rises, the signal vector of the rise period continuously changes counterclockwise like IB1, IB2, IB3, and IB4, and stabilizes after the transmission period TXT in FIG. 4A rises. The rising period ends when the signal vector reaches the value of the dotted circle indicating the transmission power of the value.
[0012]
FIG. 5 is a diagram illustrating the trajectory of the signal vector during the rising period of the feedback baseband signal in the IQ virtual plane.
When the feedback baseband signal signal rises, the signal vector of the rising period continuously changes counterclockwise like FB1, FB2, FB3, FB4, and FB5, and a dotted line indicating a stable value after the rising is shown. The rising period ends when the signal vector reaches the value of the circle.
The phase difference between FIG. 4B and FIG. 5 is the phase difference Δθ to be obtained. In this application, the phase difference is obtained by estimating the difference in timing at which the signal vector crosses the Q axis.
FIG. 6 is a block diagram showing an embodiment of the phase control circuit 18 of FIG.
The AND circuit 21 receives the clock signal CLK for sampling and the binarized output signal I′z from the zero-cross comparator 17 and outputs a signal when the AND condition of both signals is satisfied.
The counter 22 is a counter for inputting the output signal of the AND circuit 21 and the timing signal TU of the rising edge of the burst signal shown in FIG. 4A, and after being reset by the timing signal TU, the output of the AND circuit 21 Count.
Since the output signal of the AND circuit 21 is a signal in which the clock signal CLK and the signal I′z are output under an AND condition, the number of clock pulses of the clock signal CLK while the signal I′z is positive is the counter 22. The output value K obtained as a result of counting is output.
The subtracter 23 receives the output value K of the counter 22 and the sampling clock pulse number D indicating the timing at which the phase trajectory of the rising signal vector of the input baseband signal obtained in advance intersects the Q axis. A value obtained by subtracting D is output.
The weighting circuit 24 estimates the phase difference between the input baseband signal and the feedback baseband signal from the output of the subtracter 23, performs weighting (× α) according to the phase difference, obtains the phase control amount P, The phase control amount P is output to the phase shifter 8.
In the phase control circuit 18, the output value K of the counter 22 indicates the timing until the signal vector of the feedback baseband signal crosses the Q axis after being reset by the burst signal of the input baseband signal. Can be obtained in advance from an IQ signal generator, which will be described later, so that the phase difference Δθ between the input baseband signal and the feedback baseband signal can be obtained.
[0013]
FIG. 7 is a timing chart showing changes in the values of the inputs of the phase control circuit 18 of FIG. 6 and the output K of the counter 22.
When the timing signal TU at the rising edge of the burst signal is turned on, the output signal I′z of the zero cross comparator 17 is also turned on and input to the AND circuit 21, and the sampling clock pulse starts to be counted by the counter 22.
When the feedback baseband signal crosses the Q axis and the value of I changes from positive to negative, the output signal I′z of the zero cross comparator 17 is turned off and the output of the AND circuit 21 is also lost, so that the counter 22 counts the clock pulse. The counter value K is canceled and the counter value K is output from the counter 22 to the subtracter 23.
When the burst signal rising timing signal TU is turned off, the counter value K of the counter 22 is reset, and the counter value becomes 0 until the next burst rising timing signal TU is turned on.
[0014]
FIG. 8 is a block diagram showing an embodiment of a device for generating a timing signal TU at the rising edge of a burst signal.
In the IQ signal generator 31, the transmission data signal TD of the digital wireless communication device, the sampling clock signal CLK, and the timing BT of the burst signal are input. Based on the input transmission data signal TD and the clock signal CLK, I, A Q signal is generated, and the timing of the burst to be transmitted at timing BT is determined.
The timing signal generator 32 receives the sampling clock signal CLK and the timing BT of the burst signal, is delayed by a time equivalent to the delay time in the IQ signal generator 31, and the I and Q signals of the burst signal in the IQ signal generator 31 The clock signal CLK that has been counted for the same time as the process of rising is output as the timing signal TU of the rising edge of the burst signal.
The delay element 41 delays the burst signal timing BT by the delay time τ of the IQ signal generator 31 and outputs it.
The delay element 42 delays the sampling clock signal CLK by the delay time τ of the IQ signal generator 31 and outputs it.
The counter 43 counts the clock signal CLK output from the delay element 42.
The flip-flop 44 is set by the input of the timing BT of the burst signal from the delay element 41 and starts to output the timing signal TU, and the I and Q signals of the burst signal in the IQ signal generator 31 from the counter 43 rise. When the clock signal CLK that has been counted for the same period of time is input, the output is reset and the output of the timing signal TU is stopped, and the output of the timing signal TU is continued until the timing BT of the burst signal from the delay element 41 is input again. Not performed.
[0015]
FIG. 9 is a timing chart of signals input to and output from an embodiment of the timing signal TU generator of FIG.
The sampling clock CLK is constantly input to the IQ signal generator 31 and the timing signal generator 32 as clock pulses, and the IQ signal generator 31 and the timing signal generator 32 have the same timing as the transmission data TD and the timing BT of the burst signal. Is input.
The I and Q signals from the IQ signal generator 31 are delayed by a delay time τ and output is started. At this time, a rising period of several pulses is generated by the clock CLK. For example, assuming that the rising period when the I and Q signals are generated from the IQ signal generator 31 is the number of clocks of 6 pulses (data 6 bits), the timing signal TU is also output for the period of the number of clocks of 6 pulses.
Therefore, the timing signal TU output from the timing signal generator 32 is output as a rising period of the I and Q signals delayed by the delay time τ.
By configuring as described above, conventionally, the I and Q signals of the input baseband signal and the feedback baseband signal from the output were A / D converted to perform a large amount of calculation to perform phase control. However, a simple configuration and a small amount of calculation can be performed.
In the present embodiment, the timing signal output from the timing signal generator 32 as the timing signal TU is used as the signal input to the phase control circuit 18, but the timing from the input baseband signals I and Q is the same as in the prior art. The present invention can also be implemented by obtaining a signal TU.
In this embodiment, the timing at which the positive side of the Q axis intersects with the feedback baseband signal on the IQ virtual plane is mainly described. However, on the IQ virtual plane, the negative side of the Q axis, the positive side of the I axis, Even on the negative side, the phase control amount P is calculated by estimating the phase difference between the input baseband and the feedback baseband by detecting the timing at which the baseband signals cross each axis using the same configuration and method as described above. Obtainable.
[0016]
【The invention's effect】
As described above, in the high frequency power amplifier according to the present invention, the phase control circuit can be simplified in configuration and the amount of calculation is reduced as compared with the conventional one without degrading the performance. A circuit can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an embodiment of the present invention.
FIG. 2 is a diagram showing a detection range of a phase difference at a point where a baseband signal of either input or feedback on the IQ virtual plane intersects with the Q axis at the time of rising (zero crossing).
FIGS. 3A to 3D are diagrams for explaining various cases in which the phase difference of the rising signal of the burst signal is detected.
4A is a timing chart showing a timing signal of a rising period of a burst signal, and FIG. 4B is a diagram showing a signal locus of a rising period of a burst signal of an input baseband signal in an IQ virtual plane.
FIG. 5 is a diagram illustrating a trajectory of a signal vector in a rising period of a feedback baseband signal in an IQ virtual plane.
6 is a block diagram illustrating an embodiment of the phase control circuit 18 of FIG.
7 is a timing chart showing changes in values of the respective inputs of the phase control circuit 18 of FIG. 6 and the output K of the counter 22. FIG.
FIG. 8 is a block diagram showing an embodiment of an apparatus for generating a timing signal TU at the rising edge of a burst signal.
9 is a timing chart of signals input to and output from an embodiment of the timing signal TU generator of FIG.
FIG. 10 is a block diagram illustrating an example of the configuration of a conventional Cartesian loop negative feedback amplifier.
FIG. 11 is a diagram illustrating a case where a phase difference Δθ is caused by delay of a feedback baseband signal SB with respect to an input baseband signal SA on an IQ virtual plane.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 2, 23 ... Subtractor, 3 ... Quadrature modulator, 4 ... Power amplifier, 5 ... Antenna, 6 ... Attenuator, 7 ... Oscillator, 8 ... Phase , 9 ... quadrature demodulator, 10, 18 ... phase control circuit, 11, 12, 13, 14 ... A / D converter, 15, 16 ... terminal, 17 ... binary , 21 ... AND circuit, 22, 43 ... counter, 24 ... weighting circuit, 31 ... IQ signal generator, 32 ... timing signal generator, 41, 42 ... Delay element, 44... Flip-flop

Claims (6)

A transmission carrier signal generated from the signal generation means is used as a modulation signal modulated by an input signal, and the modulation signal is amplified and transmitted as an output signal, and a part of the output signal is branched as a feedback signal. A negative feedback circuit of the transmission circuit that obtains a compensated input signal from a difference between the input signal and the demodulated feedback signal by demodulating with the feedback signal and the carrier signal, and the carrier used for the demodulated feedback signal In a high frequency power amplifier of a digital wireless communication device having phase means for matching the phase of a signal to the feedback signal,
Binarization means for binarizing according to whether the feedback signal exceeds a predetermined value;
Phase control means for estimating the phase difference between the input signal and the feedback signal from the output signal of the binarization means and the signal indicating the rise timing of the burst signal and outputting the control signal of the phase means A high frequency power amplifying device characterized by the above. The phase control means is
AND means for outputting a logical product of the sampling clock signal of the binarization means and the output signal of the binarization means;
Counting means for counting and resetting the output signal of the AND means up to a signal indicating the rising timing of the burst signal;
An arithmetic means for obtaining a difference between an output of the counting means and a clock signal expected from the phase of the input signal;
The high-frequency power amplifying apparatus according to claim 1, further comprising a conversion unit that converts a calculation result of the calculation unit into a phase control amount in the phase unit. 3. The high frequency power amplifying apparatus according to claim 1, wherein the predetermined value in the binarizing means is a value where Q in an IQ virtual plane is 0 (I axis) or I is 0 (Q axis). . A signal indicating the rising timing of the burst signal is
3. The high-frequency power amplifying apparatus according to claim 1, wherein the number of clock signals is a period during which an I or Q signal rises in an IQ virtual plane. The phase control means detects the phase difference between the input signal and the feedback signal by replacing it with a timing difference at which the signal intersects the I axis or the Q axis at least when the feedback signal rises in the IQ virtual plane. The high frequency power amplifier according to claim 1 or 2. The timing at which the signal in the phase control means crosses the I axis or the Q axis is detected by changing I or Q of the signal from positive to negative or vice versa. Item 6. A high-frequency power amplifier according to Item 5.

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