JP3860071B2 - Reconfigurable hardware and diagnostic method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to reconfigurable hardware having unit components that can be arranged in a two-dimensional array and exchange input / output signals between adjacent ones to realize an arbitrary logic circuit, and a diagnostic method thereof.
[0002]
[Prior art]
As an example of hardware capable of reconfiguring an arbitrary logic circuit, it includes a variable part PP (Plastic Part) and a built-in part BP (Built-in Part) that exchanges signals with the variable part PP. PCA (Plastic Cell Architecture) is under consideration (Reference: Akira Nagoya, Kiyoshi Oguri: "Outline of Plastic Cell Architecture (PCA) Technology", NTT R & D, Vol. 49, No. 9, pp. 513-517, Sep) .2000.)
[0003]
FIG. 15 shows the internal structure of the PCA chip 10. One PCA chip 10 has a configuration in which N × N (N: natural number) PCA cells 20 are arranged in an array, and each PCA cell 20 includes a variable part PP and a built-in part BP. . Each variable portion PP is two-dimensionally arranged in the PP layer, and input / output of adjacent variable portions PP are connected to each other to form a PP surface. The embedded part BP is two-dimensionally arranged on a BP layer different from the PP layer. In the PCA cell 20, a logic circuit (indicated by reference numerals R1 and R2 in FIG. 15) is formed on the PP surface (which may be single or plural, but using an arbitrary number of variable parts PP), and the path L1 and the built-in part An input / output signal (built-in part BP ← → variable part PP) is exchanged between the logic circuit and the outside via the BP. In addition, as shown in FIG. 16, one variable unit PP includes two M × M (M: natural number) basic cells BC (Basic Cell) having a four-way lookup table LUT (Look Up Table). The configuration is arranged in a dimensional array.
[0004]
Here, a reconfigurable hardware diagnostic method will be described. The target of diagnosis in the reconfigurable hardware extends to a system having a structure and characteristics of reconfigurable hardware such as a board or a device made up of a reconfigurable LSI chip as well as the PCA chip 10.
[0005]
In order to deal with a diagnosis target including such a system, a technique in which not only the chip but also a plurality of chips are arranged, that is, a condition that logically considers the condition of the chip boundary is necessary.
[0006]
Further, in the PCA cell 20 to be taken up, the embedded unit BP handles the exchange of signals (data signals, control signals, etc.) between the logic circuits configured in the variable unit PP, so that the embedded unit BP is diagnosed by input / output signals. it can. However, in the diagnosis of the other variable part PP, an arbitrary logic circuit can be realized by using a plurality of adjacent variable parts PP, so that an input / output signal between adjacent variable parts PP is taken into consideration. Need to handle. In the case of a two-dimensional array structure in which only the basic cells BC shown in FIG. 16 are arranged inside the variable part PP, the input / output signals of the basic cells BC located in the peripheral part of the variable part PP are transmitted between adjacent variable parts PP. Corresponds to the input / output signal between. Accordingly, in the PCA cell 20, comprehensive diagnosis of all the basic cells BC constituting the variable part PP is important.
[0007]
As a method for exhaustively diagnosing this basic cell BC, it has been known that there is a functional diagnosis method using a copy of a diagnostic circuit reconfigured on the PP surface of the PCA cell 20 (reference: Hideyuki Tsuboi). , Hideshi Kobayashi, Tsunemichi Shiozawa, Koichi Nagami, Akira Nagoya, “Examination of test method for autonomously reconfigurable hardware,” IEICE Technical Report, VLD2000-80, ICD2000-137, FTS2000-45, pp.65-70.Nov.2000).
[0008]
The diagram on the left side of FIG. 17 is a diagram showing a diagnostic method using circuit replication on the PP surface of the PCA cell 20. This PP surface has a boundary 10 </ b> A of a PCA chip 10 having N × N PCA cells 20. The boundary 10A of the PCA chip 10 is not connected to the adjacent variable part PP, but signals can be exchanged through the built-in part BP.
[0009]
The diagnostic circuit TST used for diagnosis is made up of blocks of the variable portion PP of 2 × 2 PCA cells 20, and in FIG. 17, the variable portion PP of 2 × 2 PCA cells 10 at the upper left corner of the PCA chip boundary 10A is programmed. Has been. The thin hatched portion TST1 of the diagnostic circuit TST is a diagnostic control unit TST1 that controls all operations of the diagnostic circuit TST, and the dark hatched portion TST2 is a diagnostic target circuit TST2. A black square portion in the diagnosis target circuit TST2 is a basic cell BC to be diagnosed. The diagnosis circuit TST performs diagnosis of the basic cell BC in one diagnosis target circuit TST2 (functional test of all lookup tables LUT that are constituent elements of the basic cell BC), and the same diagnosis circuit TST is adjacent to the right side. Duplicate The diagnosis result at this time is sent to the chip boundary 10A located at the right end and measured from an external terminal (not shown). The duplicated diagnostic circuit TST performs the same diagnosis and repeats self-replication to the right.
[0010]
The right side of FIG. 17 shows the diagnosis target circuit TST2. The diagnosis target circuit TST2 is composed of the variable part PP of one PCA cell 20. In the diagnosis target circuit TST2, the basic cell BC to be diagnosed is indicated by a black square. And the wiring which connects the input and output of the signal of all directions to this basic cell BC to diagnose is set by the other basic cell BC in the said PCA cell 20. FIG. An example of the wiring structure by the basic cell BC is shown in the center of FIG. Since the basic cell BC to be diagnosed shown in this example is not located in the periphery of the variable part PP, the diagnosis target circuit TST2B is contained in the variable part PP in one PCA cell.
[0011]
The diagnosis and duplication by the diagnosis circuit TST will be described in a little more detail. FIG. 18 is a diagram showing a typical scene of the diagnostic technique. The left side of FIG. 18 shows path setting and diagnosis execution, and the right side shows command issuance and duplication.
[0012]
First, in route setting, data is read from the diagnosis control unit TST1. A part of the data is a command string for setting a route in the built-in unit BP. When performing diagnosis, a path (message path) is connected from the diagnosis control unit TST1 to the diagnosis target circuit TST2, and an output path from the diagnosis target circuit TST2 to the external terminal is also set. Thereafter, diagnosis data and diagnosis results are transmitted via these routes, and diagnosis is executed.
[0013]
When the diagnosis execution at one place is completed, a replication command issuance and a replication operation start. The diagnosis control unit TST1 issues a command, and a duplicate command string is created on the built-in unit BP and buffered there. According to this replication command, the configuration information of the diagnostic circuit TST is read from the variable part PP, a path for replica data propagation is set, and the configuration information is written to the variable part PP at the adjacent position. In this way, duplication of the diagnostic circuit TST is realized.
[0014]
A flowchart on the left side of FIG. 19 in which the diagnostic circuit TST on the PCA cell 20 operates is shown. First, there is a step of programming the diagnostic circuit TST. Here, the diagnostic circuit TST is realized by inputting configuration information of the diagnostic circuit TST from the outside of the PCA cell 20 and writing it into the variable part PP. The writing position is, for example, the left end of the PCA chip. Further, after the writing of the configuration information of the diagnostic circuit TST is completed, an activation signal (such as Open) of the diagnostic circuit TST is also input from the outside.
[0015]
Secondly, there is a stage for performing path setting and diagnosis. When the activation signal is received, data is automatically read from the diagnosis control unit TST1 of the diagnosis circuit TST. With this data, a path necessary for diagnosis (between the diagnosis control unit TST1 and the diagnosis target circuit TST2 and between the diagnosis target circuit TST2 and the external terminal) is set, and the diagnosis data and the diagnosis result propagate along this path, and the diagnosis is performed. Executed. This diagnosis result is observed from an external terminal and collated with an expected value externally. The external terminal is set at the right end of the PCA chip 10.
[0016]
Third, there is a step of deleting the path. When a series of diagnostic data input to the diagnostic circuit TST is read from the diagnostic control unit TST1, the path is deleted. That is, when the diagnosis target circuit TST2 receives a peculiar input, a termination command (Clear) is output, and the termination command clears the path between the diagnosis target circuit TST2 and the external output. Note that the route between the diagnosis control unit TST1 and the diagnosis target circuit TST2 is not specifically deleted. This is because this route is set by a signal corresponding to activation of reading from the diagnosis control unit TST1, and this route is automatically deleted when reading of all data is completed.
[0017]
Fourth, there is a stage of performing replication. For duplication, a duplication command string of data immediately before completion of reading of data of the diagnosis control unit TST1 is used. This is once sent to the built-in unit BP and buffered on the built-in unit BP. The buffered copy command sequence instructs the diagnostic control unit TST1 that has finished sending the data sequence to read the configuration information of the diagnostic circuit TST and write it to the adjacent variable unit PP. The diagnostic circuit TST is duplicated by this series of procedures. Note that the adjacent variable part PP indicates, for example, the right neighbor of the copy source.
[0018]
Fifth, there is a step of starting the replicated diagnostic circuit TST. Following the duplicate command string buffered in the built-in unit BP in the previous duplicate, an activation command is added in the same manner. The duplicated diagnostic circuit TST is activated by this added command.
[0019]
In the flowchart on the left side of FIG. 19, the procedure from path setting and diagnosis execution to the start of the duplicate diagnosis circuit is repeated. This repeated branching condition is that the diagnostic circuit TST programmed at the left end of the PCA chip 10 repeats this procedure, and as shown on the right side of FIG. The condition is that the right end has been reached and this row direction has been completed.
[0020]
Then, each time the diagnosis in the row direction is completed, the diagnosis circuit TST is newly programmed from the outside, and the diagnosis and duplication by the diagnosis circuit TST are repeated as described above. When this diagnosis is repeated over the entire surface of the PCA chip 10, the diagnosis by this method is completed.
[0021]
In the diagnosis of the PCA chip 10 described above, the diagnosis circuit TST that is repeatedly used by duplication is important. A diagnosis circuit having a small size has a larger number of times of duplication in the PCA chip 10 than that of a large size, and enables efficient diagnosis.
[0022]
[Problems to be solved by the invention]
On the left side of FIG. 20, the basic cell BC to be diagnosed is located in the lower right corner of the variable portion PP, and in order to set the input / output wiring for diagnosis, the variable of 2 × 2 PCA cells 20 minutes is set as the diagnosis target circuit TST2. The example where the part PP is required is shown. Here, as shown on the right side of FIG. 20, in order to diagnose the basic cell BC at the lower right corner of the upper left variable portion PP among the 2 × 2 variable portions PP, the upper right variable portion PP and the lower left variable portion PP Wiring is set using the variable portion PP. As described above, the size of the diagnosis target circuit TST2 does not fit in the variable part PP of one PCA cell and extends over four PCA cells 20. In addition to this case, when the basic cell BC to be diagnosed is located in the peripheral part of the variable part PP, the wiring connecting the input signal and the output signal must be set in the variable part PP area of the adjacent PCA cell 20. I don't get it.
[0023]
As described above, the left side of FIG. 20 shows a state of duplication of the diagnostic circuit TST when the diagnostic target circuit TST2 does not fit in the variable part PP in one PCA cell. In this diagnostic circuit TST, the diagnostic control unit TST1 is composed of two vertical PCA cells 20, and the diagnostic target circuit TST2 is composed of 2 × 2 PCA cells 20 as described above. As a result, the diagnostic circuit TST is composed of 2 × 3 PCA cells 20.
[0024]
Here, when one PCA chip 10 is composed of N × N PCA cells 20, “N” is a multiple of 2 and all diagnostic circuits TST are 2 × 2 PCA cells 20. There is no limitation on duplication, and duplication can be performed “N / 2” times in the horizontal and vertical directions (right side in FIG. 19). However, when 2 × 3 PCA cells 20 are required as the diagnostic circuit TST, even if “N” is a multiple of 3, there is a limitation on replication.
[0025]
This is because the same diagnostic target circuit TST2 in one PCA cell 20 at an arbitrary position in the diagnostic circuit TST of 2 × 2 PCA cells 20 (in FIG. 17, the diagnostic target is located in the upper right position in the diagnostic circuit TST). Even if the circuit TST2 is provided), the diagnosis circuit TST can be duplicated under the same conditions to diagnose all the variable parts PP.
[0026]
However, in the diagnostic circuit TST of the 2 × 3 PCA cells 20, even if the same diagnostic target circuit TST2 of the 2 × 2 PCA cells 20 is rearranged on the left and right, the diagnostic circuit has three columns of PCA cells 20 The variable part PP for one column in the TST cannot be diagnosed. Further, it is impossible to diagnose the upper and lower variable portions PP of the diagnostic circuit TST for two rows.
[0027]
Therefore, it is necessary to provide an offset for one PCA cell in advance in the right or downward direction for duplication, or to use another different diagnosis target circuit.
[0028]
However, when duplication is performed with the offset of one PCA cell 20 set in advance to the right, the boundary 10A of the PCA chip 10 as shown on the lower side of the left side of FIG. In a place where there is no connection, the diagnosis target circuit TST2 cannot be reconfigured (cannot be duplicated). Therefore, the 2 × 3 PCA cell diagnostic circuit TST is subject to chip boundary limitations during replication.
[0029]
Due to this limitation, various types of (several types) of different sizes (multiple basic cells BC including the basic cells BC located in the periphery of the variable portion PP) can be used for diagnosis. In this case, there is a problem that a diagnosis circuit TST including a diagnosis target circuit TST2 is prepared and diagnoses are individually performed (which covers the basic cell BC in each variable part PP). .
[0030]
Here, the “issues” described so far will be summarized from the viewpoint of the variable portion PP arranged in a two-dimensional array. FIG. 21 shows connections between adjacent variable parts PP in the normal state. The variable units PP arranged in a two-dimensional array and capable of realizing an arbitrary logic circuit can exchange input / output signals with the adjacent variable units PP. In FIG. 21, when paying attention to a certain variable part (C-PP), there are variable parts (N-PP, S-PP, W-PP, E-PP) that are adjacent in the upper, lower, left, and right directions. , I / O signals can be exchanged between each of these and the C-PP.
[0031]
Therefore, as described above with reference to FIG. 15, the reconfigurable hardware has a different scale by connecting a number of variable parts PP as well as a single variable part PP as needed. A logic circuit can also be realized.
[0032]
However, when diagnosing a variable part PP having such characteristics, input / output signals between adjacent variable parts PP must be considered. For this reason, even in a conventional diagnostic method using a replica of a diagnostic circuit, it is not sufficient to use a diagnosis target circuit set in one variable part PP and diagnose each variable part PP over the entire surface. It cannot be said that the variable part PP is diagnosed.
[0033]
For example, in consideration of input / output signals between the variable parts PP adjacent in the vertical direction, a diagnosis is performed using a circuit to be diagnosed including C-PP and N-PP (or S-PP). Separately, a circuit to be diagnosed including C-PP and W-PP (or E-PP) is used in consideration of the input / output signals between the lateral directions. Furthermore, a diagnostic target circuit that simultaneously considers input / output signals between the variable parts PP adjacent in the vertical and horizontal directions is also necessary.
[0034]
The present invention has been made in view of the above points, and an object of the present invention is to provide a reconfigurable hardware that is provided with a diagnostic mechanism so as not to be restricted by the chip boundary. It is to provide a diagnostic method using
[0035]
[Means for Solving the Problems]
Claim 1 Take The invention has a unit component that is arranged in a two-dimensional array and can exchange an input / output signal between adjacent ones to realize an arbitrary logic circuit. That is, a diagnostic peripheral mechanism that turns back signals exchanged between adjacent unit components is provided. In reconfigurable hardware, The unit configuration section has a basic configuration section that is arranged in a two-dimensional array and can exchange an input / output signal between adjacent units to form an arbitrary basic logic circuit, and the diagnostic peripheral mechanism is included in the unit configuration section. Fold signals back and forth between two basic components located on the same side outside the array Reconfigurable hardware characterized by that.
[0036]
The invention according to claim 2 is the invention according to claim 1, The diagnostic peripheral mechanism includes switching means for switching between signals exchanged between adjacent unit components and the folded signal. Reconfigurable hardware characterized by that.
[0037]
The invention according to claim 3 is the invention according to claim 1 or 2, When the diagnostic peripheral mechanism is set at a connection position for exchanging control signals between the logic circuit of the unit component and the outside, the control signal is connected to the logic circuit at another position of the unit component Do Reconfigurable hardware characterized by that.
[0038]
The invention according to claim 4 is: In a method for diagnosing a reconfigurable hardware that has a unit configuration part that can be arranged in a two-dimensional array and exchange input / output signals between adjacent ones to realize an arbitrary logic circuit, at one end of the hardware Diagnose a block consisting of a plurality of the unit component parts positioned as a diagnostic circuit, and repeat the same diagnostic circuit next to the other end direction to perform the same diagnosis, When diagnosing a unit component, a diagnostic peripheral mechanism that turns back signals exchanged between adjacent unit components is used as a diagnostic signal wiring path It is characterized by Diagnostic method .
[0043]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1 shows the configuration of the variable portion PP of the PCA cell 20 having the diagnostic peripheral mechanism of the first embodiment. Here, a “diagnostic peripheral mechanism” is provided around each variable part PP of the N × N PCA cells 20 constituting the PCA chip 10, and the basic cell BC located in the peripheral part of the variable part PP is provided. Is connected to the output and input of the basic cell BC located on the same side of the variable part PP by the diagnostic peripheral mechanism, and the signal is turned back. The variable part PP is a kind of unit constituent part recited in the claims, and the basic cell BC is a kind of basic constituent part recited in the claims.
[0044]
The diagnostic peripheral mechanism X1 provided on the right side and the lower side around the variable part PP in FIG. 1 is connected to the output from the basic cell BC (the look-up table LUT therein) toward the adjacent variable part PP, The input from the variable part PP to the basic cell BC is connected to the same input and the same output of the adjacent basic cell BC. The right side and the lower side where the diagnostic peripheral mechanism X1 is provided are portions where signals are not exchanged with the built-in unit BP.
[0045]
The places where signals are exchanged with the built-in part BP are the left side and the upper side of the variable part PP. First, an input of a signal exchanged with the outside via the built-in unit BP, that is, a signal connection from the built-in unit BP to the variable unit PP is located on the left side of the variable unit PP. Further, the output of a signal exchanged with the outside via the built-in unit BP, that is, the position where the output signal from the variable unit PP to the built-in unit BP is connected corresponds to the upper side of the variable unit PP. A diagnostic peripheral mechanism X2 is provided on the left side, and a diagnostic peripheral mechanism X3 is provided on the upper side. These diagnostic peripheral mechanisms X2 and X3 are signals input from the built-in unit BP to the basic cell BC (built-in unit BP → variable unit PP) or signals output from the basic cell BC to the built-in unit BP (variable unit PP). It is necessary to consider both the respective signals of the built-in part BP) and the return signal (basic cell BC → basic cell BC).
[0046]
That is, in the diagnostic peripheral mechanism X2 on the left side, an input signal (embedded part BP → variable part PP, a, c in FIG. 1) and a return signal (b, FIG. 1) taken from the outside via the built-in part BP. The logical sum (o1, o2) with d) is taken and input to the basic cell BC located in the peripheral part of the variable part PP.
[0047]
Further, the diagnostic peripheral mechanism X3 on the upper side branches an output signal (variable part PP → embedded part BP) output to the outside via the built-in part BP. One of the branch signals is an output signal (variable part PP → embedding part BP), and the other of the branch signals is an input to a basic cell BC located in the peripheral part of the variable part PP. The connection between the built-in part BP-variable part PP and the adjacent variable part PP is described in Japanese Patent Application No. 2001-142728.
[0048]
FIG. 2 is a diagram showing an example in which the diagnostic peripheral mechanism X1 shown in FIG. 1 is used. The diagnostic circuit TST includes a diagnostic control unit TST1 and a diagnostic target circuit TST2, and the position of the basic cell BC to be diagnosed is the lower right corner of the variable unit PP of the diagnostic target circuit TST2. As shown on the right side of FIG. 2, the basic cell BC (black part) to be diagnosed is connected to the basic cell BC from the adjacent basic cell BC via the diagnostic peripheral mechanism X1, so in FIG. The diagnosis target circuit TST2 that required the variable part PP for 2 × 2 PCA cells as described is accommodated in the variable part PP of one PCA cell.
[0049]
In the diagnostic circuit TST composed of 2 × 2 variable parts PP shown above the left PP surface in FIG. 2, the diagnostic target circuit TST2 is arranged on the upper right side. In the lower diagnostic circuit TST, the diagnosis target circuit TST2 is set to the upper left side. When the PCA chip 10 has N × N variable parts PP and N is “a multiple of 2”, both diagnosis circuits TST perform diagnosis and replication from the left end of the PCA chip boundary 10A. Repeatedly, the right end of the PCA chip boundary 10A can be reached. In this way, the diagnostic circuit TST can be made to be a small constant size composed of 2 × 2 variable parts PP, so that when the diagnostic circuit TST for diagnosing all the variable parts PP is duplicated, there is an interval for duplicating the diagnostic circuit TST next to it. The disadvantage of expansion can be avoided, and there is no need to be restricted by the PCA chip boundary 10A.
[0050]
FIG. 3 shows an example similar to FIG. 2, but the position of the basic cell BC to be diagnosed by the diagnosis target circuit TST2 is different. The example of FIG. 3 uses the diagnostic peripheral mechanisms X2 and X3, and the position of the basic cell BC to be diagnosed is the input of a signal exchanged with the outside via the built-in unit BP (the built-in unit BP → This is a place where both the variable part PP) and the output (variable part PP → embedded part BP) exist. In this case, the input to the left side of the variable part PP of one PCA cell (the place corresponding to the built-in part BP → the variable part PP) uses an input that is logically ORed by the diagnostic peripheral mechanism X2. In addition, the signal output to the upper side of the PCA (location corresponding to the variable part PP → the embedded part BP) is once sent to the output signal, and the diagnosis is performed after the signal is branched by the diagnostic peripheral mechanism X3. It is led to the cell BC.
[0051]
In the example shown on the right side of FIG. 3, the diagnosis target circuit TST2 is accommodated in the variable part PP for one PCA cell. As in the case of FIG. 2, as shown on the left side of FIG. The interval of duplicating the diagnostic circuit TST to the adjacent area can be avoided, and the diagnosis of all the variable parts PP can be completed without being affected by the PCA chip boundary.
[0052]
[Specific examples of peripheral mechanisms for diagnosis]
The diagnostic peripheral mechanism is required to have three functions necessary for performing functional diagnosis of all the basic cells BC in the diagnosis target circuit TST2 of one PCA cell. The first is the input / output loopback function of the basic cell BC located around the PCA cell as described above. That is, this is a function for connecting the input / output of the peripheral basic cell BC in the same PCA cell at the time of diagnosis. However, in the pin assignment part that handles input / output signals with the built-in part BP, the signal from the built-in part BP to the variable part PP is ORed, and the signal from the variable part PP to the built-in part BP is branched. And go back.
[0053]
The second is a diagnostic mode function. Switching between the input / output loopback at the time of diagnosis and the input / output connection of the basic cell BC located around the PCA cell at the normal time is performed. The loopback is performed in the diagnostic mode, and the normal connection is switched to the normal mode.
[0054]
The third function is to switch control pin assignments at two locations. In addition to the pin assignment (PP_din, PP_dout) related to the input / output data signal between the embedded unit BP and the variable unit PP, the variable control unit PP of one PCA cell includes an input control signal from the embedded unit BP to the variable unit PP ( in_req, in_ack) and an output control signal (out_req, out_ack) from the variable part PP to the embedded part BP. There are also specially assigned signal pins that erase the path set in the built-in part BP. In the diagnosis of the basic cell BC in the part related to the input / output located at the pin assignment of the control signal, the control signal and the data signal cannot be mixed. Therefore, in the diagnosis mode, the control signal pin assignment is different. Must be replaced with a position. FIG. 4 assumes that these control signals are related to the upper left corner. When diagnosing the basic cell BC other than this position, the control signal is handled as it is without turning back the signal of the built-in part BP indicated by the broken line (the above-described diagnostic peripheral mechanism X1). When performing the diagnosis, the signal wrapping indicated by the broken line (diagnostic peripheral mechanism X1) is used, and at this time, the control signal is handled as a pin assignment at another position (not shown). In addition, about the diagnosis of the basic cell BC of the part relevant to this control signal, it abbreviate | omitted in FIGS. 1-3.
[0055]
As described above, basically, the basic circuit BC of the boundary of the PCA chip 10 is diagnosed by the diagnostic circuit TST having the diagnostic target circuit TST2 of various sizes as in the past by the signal folding function and the diagnostic mode function. The need to do is eliminated. Further, the same effect is exhibited by the control signal switching function for the basic cell BC to which the control signal is pinned. Only one diagnostic circuit TST having one PCA cell 20 as the diagnosis target circuit TST2 is prepared by the diagnostic peripheral mechanism having the above three functions, and the diagnosis circuit TST of the same size is duplicated for all the PCA cells. can do.
[0056]
Prior to specific description, the basic cell BC will be described again. The variable part PP has a structure in which only M × M basic cells BC are arranged in a plane, and the structure of each basic cell BC is a memory as a lookup table LUT with four inputs and one output as shown on the right side of FIG. It consists of 4 blocks. A 4-bit input signal to each lookup table LUT is common, and an output signal from an adjacent basic cell BC of N (upper), E (right), W (left), and S (lower) is input. To do. Each lookup table LUT outputs the contents of one of the 16 memory cells (SRAM) selected according to the 4-bit input signal as a 1-bit output signal.
[0057]
Each output signal is output after taking a logical product with a 1-bit input signal LUT_connect input from the built-in unit BP before being output outside the basic cell BC. That is, adjacent basic cells BC are logically connected to each other only when LUT_connect is “1”. As a result, it is possible to prevent inadvertent occurrence of ring oscillation that may occur depending on the contents of the lookup table LUT.
[0058]
Next, 16 SRAMs in the lookup table LUT will be described. The SRAM layer of the variable part PP is, for example, 2 ^Na The word memory and SRAM address lines are Na bits, and the data lines are Nd bits for both input and output. The address line (add) is divided into a row address (row_add) and a column address (col_add). For the row address, an exclusive signal is generated by the input decoder, and one row of the memory cells is selected. The column address is input to the selection circuit, and Nd is selected from one row of memory cells selected in the writing or reading direction by each 1-bit write_enable and read_enable signals, and Nd-bit data (Mdata_I, Mdata_O) is written or Read.
[0059]
Next, the external interface and peripheral circuits will be described. FIG. 5 shows input / output signals for one variable part PP. The external interface signals of the variable part PP are roughly classified into the following three types (i) to (iii). Details of (i) and (iii) are described in Japanese Patent Application No. 2001-142728.
[0060]
(i) Signals between adjacent variable parts PP: As described above, the basic cells BC in the variable part PP are connected to each other by 1-bit input and output signals in four directions. The input / output ports facing the outside of the basic cell BC located on the outermost side of the BC are directly connected to the corresponding input / output ports of the basic cell BC outside of another adjacent variable part PP. In other words, when viewed from the layer of the basic cell BC, it seems as if the network (Sea of LUTs) of the basic cell BC extends beyond the boundary of the variable part PP. These signals have input and output signals in the directions of N (upper), E (right), W (left), and S (lower) as described above for each variable part PP (N_PPO, N_PPI, E_PPO, E_PPI, W_PPO, W_PPI, S_PPO, S_PPI).
[0061]
(ii) Memory interface signal: This memory interface signal is an interface signal between the SRAM layer and the embedded portion BP described above for the SRAM. Note that the LUT_connect signal described in the basic cell BC is included here.
[0062]
(iii) Object interface signal between built-in part BP and variable part PP: After the functional circuit (object) is configured by the memory interface signal in the previous section (ii) using the lookup table LUT in the variable part PP, A signal group of an interface between the functional circuit and the built-in unit BP that controls the functional circuit corresponds to this. As shown in FIG. 5, the signal breakdown is as follows: data input and output signals (PP_din, PP_dout), and each of these asynchronous control signals (in_req, in_ack, out_req, out_ack) look in the variable part PP. A signal used for initializing asynchronous registers composed of a set of uptable LUTs is performed with a pair (reset_req, reset_ack) and an adjacent variable unit PP in the periphery of the variable unit PP, or a built-in unit BP It consists of a select signal (sel_BP) that selects whether or not to perform.
[0063]
As shown in FIG. 4, the connection on the variable part PP side of each object interface signal is branched as it is in the output direction from some of the signals between the adjacent variable parts PP described above, and the input direction. Selects whether the signal from the adjacent variable unit PP is input to the variable unit PP or the object interface signal is input to the variable unit PP using the sel_BP signal as a selection control signal.
[0064]
Next, the diagnostic peripheral mechanism added around the variable part PP will be described in detail. This diagnostic peripheral mechanism differs depending on each location and signal type (X1, X2, and X3 described above), and a circuit to be added and an operation speed to be satisfied by the circuit differ accordingly.
[0065]
First, the connection between the built-in part BP and the variable part PP will be described. The diagnostic peripheral mechanism required for the improvement using the conventional replication is basically provided in the outermost peripheral part of each variable part PP (for each PCA cell 20). This part is also a place where the built-in part BP and the variable part PP are connected. The connection of signals between the built-in part BP and the variable part PP has been described with reference to FIGS. 4 and 5, the classification / contents of signals to be connected and the means for connecting the object interface signals among the variable parts PP of the PCA cells that are actually adjacent to each other have been described. However, the points added by the diagnostic peripheral mechanism are not described at this point.
[0066]
Next, as shown in FIG. 5, there are various kinds of signals for connecting the built-in part BP and the variable part PP, but between the adjacent variable parts PP located in the peripheral part of each variable part PP. The connection signal between the built-in part BP and the variable part PP related to the diagnostic peripheral mechanism inserted into the object is limited to the object interface signal shown in FIG. More specifically, the diagnostic peripheral mechanism is added to the fan-out point shown in FIG. 6A and the selector SEL shown in FIG.
[0067]
Here, the peripheral mechanism for diagnosis in each case will be described. First, FIG. 7 shows a diagnostic peripheral mechanism X1 that handles only signal folding between adjacent basic cells BC in the same PCA cell. This diagnostic peripheral mechanism X1 can be seen in all of the right side and the lower side of the variable portion PP in FIGS. A specific circuit example of the diagnostic peripheral mechanism X1 is shown in FIG. Basically, two selectors SEL similar to those in FIG. 6B are used, and in normal use, signals are input / output to / from the basic cell BC of another adjacent PCA cell 20, and the diagnostic peripheral mechanism X1. When used as, the circuit of FIG. 7A is realized.
[0068]
Next, FIG. 8 shows a diagnostic peripheral mechanism X2 that receives an input signal from the built-in unit BP. This diagnostic peripheral mechanism X2 can be seen on the left side of the variable portion PP in FIGS. As shown in FIG. 8B, the diagnostic peripheral mechanism X2 includes a two-stage selector SEL and one 3-input OR circuit OR. The signals A2 and B2 in FIG. 8B are connected to A1 and B1 in FIG.
[0069]
Next, a diagnostic peripheral mechanism X3 that outputs a signal to the built-in unit BP is shown in FIG. This diagnostic peripheral mechanism X3 can be seen on the upper side of the variable portion PP in FIGS. In this diagnostic peripheral mechanism X3, four fan-outs (one for the built-in portion BP, one for each of the two basic cells BC on the same side, and the basic for the adjacent PCA cell for the output from the basic cell BC. It is necessary to take one to the cell BC. For this reason, an amplifier AMP for signal amplification is connected in addition to the selector SEL. Note that the signals A3 and A3 in FIG. 9B are connected to the signals A1 and B1 in FIG.
[0070]
Finally, the priority for speed propagation delay is described. In the connection described with reference to FIGS. 8 and 9, multi-stage signal connection and branching occur, but the propagation speed of the signal to be considered in this case is as follows. (1) Basic cell BC between adjacent PCA cells (2) The connection data signal with the built-in part BP, (3) The high-speed signal is ensured in the order of the connection signal with the other basic cell BC in the same PCA cell. Since (3) is an additional signal for diagnosis, the required degree of speed may be limited to a low level. This is shown in FIGS. 8 (c) and 9 (c).
[0071]
Here, the first embodiment will be summarized. FIG. 10 shows input / output signals between the variable parts PP that are turned back during diagnosis. The variable parts PP arranged in a two-dimensional array can normally be connected to adjacent variable parts PP and exchange input / output signals (FIG. 21). At the time of diagnosis, the input / output signal between the variable parts PP is turned back so that the input signal of a certain variable part PP becomes the output signal.
[0072]
That is, the C-PP can exchange input / output signals with the adjacent N-PP, S-PP, W-PP, and E-PP at the normal time. At the time of diagnosis, output signal lines from C-PP to N-PP, S-PP, W-PP, and E-PP are respectively connected from N-PP, S-PP, W-PP, and E-PP to C-PP. Switch to connect to the input signal line.
[0073]
As a result, input / output signals between the variable parts PP adjacent in the vertical direction are output signals from C-PP to N-PP and S-PP, and input signals from N-PP and S-PP to C-PP. Given. Similarly, as for the input / output signals between the horizontal directions, the output signals from C-PP to W-PP and E-PP become the input signals from W-PP and E-PP to C-PP. Moreover, the input / output signals folded in both the vertical and horizontal directions are considered simultaneously.
[0074]
Therefore, in the diagnostic method using a duplicate of the diagnostic circuit, the diagnosis target circuit set in one variable unit PP can be used to diagnose each PP over the entire surface, and it functions sufficiently as a complete PP diagnosis.
[0075]
[Second Embodiment]
FIG. 11 shows the diagnostic scan mechanism Y of the second embodiment. 11 shows the entire PP surface of the PCA chip 10. The PCA chip 10 has N × N PCA cells 20, and the variable part PP of one PCA cell 20 is M × N. It consists of M basic cells BC. The diagnostic scanning mechanism Y is provided on each of the left and right sides and the upper and lower sides of all PP surfaces including all the variable portions PP in the PCA chip 10.
[0076]
As shown on the left side of FIG. 11, the diagnostic scan mechanism Y includes a shift register Y1 that handles an input signal to the basic cell BC and a shift register Y2 that handles an output signal from the basic cell BC. The registers of the shift registers Y1 and Y2 are connected to the input and output of the basic cell BC located on the outermost periphery of all PP surfaces. The shift registers Y1 and Y2 can write / read data from / to the shift register by scanning with a scan path for diagnosis.
[0077]
FIG. 12 is a diagram showing a specific example of the diagnostic scanning mechanism Y. When diagnosing the basic cell BC, a diagnosis logic is set for a plurality of diagnosis target basic cells BC arranged in a diagonal direction on all PP surfaces of the PCA chip 10, and other basic cells BC are set. Set up, down, left, and right wiring paths (logic that the lookup table LUT has one input and one output). After setting all the PP surfaces in this way, the input data (diagnosis data) from the shift register Y1 of the diagnostic scan mechanism Y provided on the upper, lower, left and right sides of all the PP surfaces is used as a lookup table in the basic cell BC to be diagnosed. Input to the LUT, output (diagnosis result data) from the lookup table LUT is output to the shift register Y2, and diagnosis is performed.
[0078]
During this diagnosis, the PP surface is treated as a unit over the entire chip, and all adjacent basic cells BC are connected to each other for input / output. In other words, it is essential to switch the diagnostic mode different from the normal use, and while the diagnostic mode is set, scan input / output of diagnostic data and diagnostic execution control are performed.
[0079]
Next, the diagnostic procedure by this scan will be described. The whole procedure is shown in the diagnosis time chart of FIG. The method of diagnosing by arranging the diagnostic scanning mechanism Y can be broadly divided into PP surface setting change and diagnostic mode, and these are alternately repeated as many times as necessary.
[0080]
In changing the setting of the PP plane, memory writing (handling as a RAM) is performed to change the logic of the lookup table LUT in the diagnosis target basic cell BC and the position of the basic cell BC on all PP planes. As a result, the logic for diagnosis is set in the basic cells BC arranged in the diagonal direction as shown in the lower side of FIG. However, at first, there is also a meaning of initialization of the entire PP surface, and the diagnostic logical writing shown in FIG. 12 is performed on all the basic cells BC arranged in the diagonal direction of the PP surface, and all the remaining basic cells BC on the PP surface. Is set to the wiring path shown in FIG. After the diagnosis for each basic cell BC to which the diagnosis logic is written is sequentially performed by scanning, the diagnosis logic of each basic cell BC is changed and the diagnosis is sequentially performed in the same manner. Next, the logic for diagnosis is newly written in the same way for a plurality of basic cells BC arranged in different diagonal directions on the PP surface, and the wiring path shown in FIG. Set. This is repeated below.
[0081]
In the diagnostic mode, the diagnostic logic and scan input of the diagnostic data from the diagnostic scanning mechanism Y, the diagnostic execution control, and the diagnostic result to the diagnostic scanning mechanism Y are held while maintaining the PP surface on which the diagnostic logic and wiring path are set. Three processes of scan output are performed. This is repeated sequentially for each basic cell BC arranged in the diagonal direction. The scan input of the diagnostic data and the scan output of the diagnostic result are handled in the same way as a general boundary scan diagnosis. The diagnostic execution control applies the value obtained by scanning the diagnostic data by the diagnostic scanning mechanism Y to the logic constituted by the multi-stage connection of the lookup table LUT set on the PP surface, and the output result of the basic cell BC is obtained. Latching to the diagnostic scan output.
[0082]
As described above, according to the diagnostic scan mechanism Y of the second embodiment, by setting the PP surface once, each basic cell constituting one PP for each row and each column, that is, each basic cell constituting the entire PP surface. When both the number of rows and the number of columns of BC are the same, the basic cell BC of the number of columns (or the number of rows) can be diagnosed simultaneously by scanning, so that a large number of locations can be diagnosed.
[0083]
Here, the second embodiment will be summarized. FIG. 14 shows a diagnostic scanning mechanism Y provided on the PP surface. The diagnostic scanning mechanism Y is composed of a plurality of unit diagnostic scanning mechanisms Y3 corresponding to one variable part PP. Each variable part PP arranged in a two-dimensional array can realize an arbitrary logic circuit. Also, input / output signals can be exchanged with the adjacent variable section PP. Therefore, as shown in the upper left part of the PP surface in FIG. 14, a diagnostic scan mechanism Y that handles input / output signals for the outermost side is disposed on the entire PP surface.
[0084]
In order to explain the arrangement and connection of the diagnostic scanning mechanism more accurately, a matrix expression is applied to each variable part PP. The top row is PP (0, 0), PP (0, 1), PP (0, 2), PP (0, 3), ... PP (0, j), ... PP (0, n) from the upper left corner ), And the leftmost column is PP (0, 0), PP (1, 0), PP (2, 0), PP (3, 0), ... PP (i, 0), ... PP (n, 0). Here, N × N variable parts PP are used. However, the vertical and horizontal numbers may be different. Generally, the variable part PP at a certain position is PP (i, j), where i and j are n or less. It becomes an integer.
[0085]
In this way, the unit diagnosis scanning mechanism Y3 arranged on the outermost side of the PP plane can set and observe the input / output signal on the left side of PP (0, j). Similarly, input / output signals on the upper side of PP (i, 0), the right side of PP (n, j), and the lower side of PP (i, n) can be handled.
[0086]
Therefore, when diagnosing PP (i, j), the variable part corresponding to PP (h, k), h ≠ i, k ≠ j is set at the same time as the diagnosis target circuit is set in PP (i, j). All the PPs are set as logic circuits that allow the vertical and horizontal input / output signals to pass through. Then, input signals are set to the upper and lower sides of the “j” row, the left and right sides of the “i” column, and the diagnostic scan mechanism, and the output signals obtained from the same diagnostic scan mechanism are observed.
[0087]
This makes it possible to diagnose PP (i, j). In addition, this diagnosis can be performed simultaneously in parallel on the variable parts PP of different rows and columns.
[0088]
【The invention's effect】
According to the present invention, by using a diagnostic peripheral mechanism, the size of a diagnostic target circuit to be replicated even when a basic configuration unit such as a basic cell located in the periphery of a unit configuration unit such as a variable unit is a target of diagnosis. Can always be fixed to one basic component. For this reason, it is possible to duplicate the diagnostic circuit programmed once at the same interval (pitch) at the time of diagnosis as compared with the conventional technique, and the problem at the PCA chip boundary is also solved. As a result, since an area to be diagnosed is expanded in proportion to the number of basic components to be diagnosed, efficient diagnosis becomes possible. In addition, since all the basic components of the unit component can be handled in the same manner of duplication, preparation for this diagnosis can be facilitated.
[0089]
In addition, by using the diagnostic scanning mechanism, a plurality of basic components can be diagnosed at once, and problems at the PCA chip boundary are also eliminated.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a variable unit PP having a diagnostic peripheral mechanism according to a first embodiment.
FIG. 2 is an explanatory diagram for performing diagnosis using the diagnostic peripheral mechanism of the first embodiment.
FIG. 3 is another explanatory diagram for performing diagnosis using the diagnostic peripheral mechanism of the first embodiment.
FIG. 4 is a specific explanatory diagram of a variable portion PP having a diagnostic peripheral mechanism according to the first embodiment.
FIG. 5 is an explanatory diagram of input / output signals of a variable unit PP with respect to a built-in unit PP.
FIG. 6 is an explanatory diagram of the exchange of signals between the variable parts PP and the built-in part BP in the connection part between the adjacent variable parts PP.
FIG. 7 is an explanatory diagram of signal folding between basic cells BC in a variable part PP of a PCA cell.
FIG. 8 is an explanatory diagram of signal folding between basic cells BC in a variable unit PP that receives a signal from a built-in unit BP;
FIG. 9 is an explanatory diagram of signal folding between basic cells BC in a variable unit PP that outputs a signal to a built-in unit BP;
FIG. 10 is an explanatory diagram summarizing the diagnostic peripheral mechanism according to the first embodiment;
FIG. 11 is an explanatory diagram of all PP surfaces of a PCA chip having a diagnostic scan mechanism of a second embodiment.
FIG. 12 is an explanatory diagram of all PP surfaces of a PCA chip having a specific diagnostic scan mechanism according to the second embodiment;
FIG. 13 is a time chart of diagnosis by a diagnostic scan mechanism.
FIG. 14 is an explanatory diagram summarizing a diagnostic scan mechanism according to a second embodiment;
FIG. 15 is an explanatory diagram of the structure of a conventional PCA.
FIG. 16 is an explanatory diagram of the structure of a conventional PCA cell.
FIG. 17 is an explanatory diagram of conventional diagnosis.
FIG. 18 is an explanatory diagram of diagnosis by a conventional diagnosis circuit and duplication of the diagnosis circuit.
FIG. 19 is a flowchart of a conventional diagnosis procedure and an explanatory diagram of replication.
FIG. 20 is an explanatory diagram of problems caused by conventional diagnosis.
FIG. 21 is an explanatory diagram of connection between adjacent PPs in a normal state.
[Explanation of symbols]
10: PCA chip, 10A: Chip boundary
20: PCA cell
X1-X3: Peripheral mechanism for diagnosis
Y: scan mechanism for diagnosis, Y1, Y2: shift register, Y3: scan mechanism for unit diagnosis
PP: Variable part of PCA cell
BP: Built-in part of PCA cell
BC: Basic cell

Claims (4)

Disposed in a two-dimensional array Chi lifting the unit configuration section arbitrary logic circuit output signal is exchanged between each other can be realized adjacent, diagnostic peripheral mechanism folding the signals exchanged mutually between adjacent unit components In reconfigurable hardware with
The unit configuration section has a basic configuration section that is arranged in a two-dimensional array and can exchange an input / output signal between adjacent ones to form an arbitrary basic logic circuit.
The reconfigurable hardware characterized in that the diagnostic peripheral mechanism folds back signals between two basic components located on the same side outside the array in the unit component . The reconfigurable hardware of claim 1,
The diagnostic peripheral mechanism includes switching means for switching between signals exchanged between adjacent unit components and the folded signal.
Reconfigurable hardware characterized by that. The reconfigurable hardware according to claim 1 or 2,
When the diagnostic peripheral mechanism is set at a connection position for exchanging control signals between the logic circuit of the unit component and the outside, the control signal is connected to the logic circuit at another position of the unit component reconfigurable hardware, characterized by. In a method for diagnosing a reconfigurable hardware having a unit configuration unit that can be arranged in a two-dimensional array and exchange input / output signals between adjacent ones to realize an arbitrary logic circuit,
Diagnose a block consisting of a plurality of the unit components located at one end of the hardware as a diagnostic circuit,
Repeat the same diagnostic circuit next to the other end direction to make a similar diagnosis,
A diagnostic method characterized in that a diagnostic peripheral mechanism for turning back signals exchanged between adjacent unit constituent parts is used as a diagnostic signal wiring path when diagnosing the unit constituent part at the other end. .

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