JP3803053B2 - Test circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test circuit including a test target circuit and a test execution control unit that applies a test pattern to the test target circuit.
[0002]
[Prior art]
FIG. 19 is a diagram for explaining a test method for a reconfigurable circuit, which is a first conventional example.
[0003]
A reconfigurable circuit (for example, a field programmable gate array (FPGA)) originally realizes the desired circuit in various ways by programming the circuit desired by the user. Therefore, since a reconfigurable circuit does not have a specific function, when testing a reconfigurable circuit, conventionally, the reconfigurable circuit is programmed and tested each time it is tested. .
[0004]
In FIG. 19, in the first test, the first test target circuit TC11 is programmed, this programmed test target circuit TC11 is tested, and in the second test, the test target circuit TC12 is programmed, The programmed test target circuit TC12 is tested, and in the third and subsequent tests, the test target circuit TC13, the test target circuit TC14,..., And the test target circuit TC1n are programmed and tested in the same manner as described above. .
[0005]
FIG. 20 is a flowchart showing the operation of the first conventional test method when testing a reconfigurable circuit.
[0006]
First, the first logic circuit is programmed (S101), the programmed logic circuit is regarded as the first test target circuit, input data is given, tested (S102), and the output value is observed.
[0007]
The output value is compared with a value expected when the programmed circuit (test target circuit) is normal to check whether or not they match (S103), and both values match each other. If not, it is determined that a fault exists in the reconfigurable circuit (S104). On the other hand, if both values match each other (S103), it is determined that no fault exists.
[0008]
If the two values match each other (S103), the second logic circuit is programmed in the reconfigurable circuit (S101) and is regarded as the second test target circuit, and this is tested ( S102), the above programming, testing, and comparison are repeatedly executed (S101, S102, S103, S105). When all the aspects of the reconfigurable circuit have been tested (S105), all tests in one reconfigurable circuit are completed.
[0009]
FIG. 21 is an explanatory diagram of a BIST as a second conventional example.
[0010]
The BIST is a test circuit called a self-built-in test circuit (Built-in selftest), and an example in which this BIST (self-built-in test circuit) is applied to a memory is described in Japanese Patent Application Laid-Open No. 2000-30483. BIST circuit for large scale memory ”.
[0011]
The BIST as the second conventional example is a simpler test method than the test method for the reconfigurable circuit as the first conventional example.
[0012]
In a conventional BIST, a test target circuit having a specific function and a test control unit are usually built in advance in an LSI. The test control unit includes a test pattern generator and a comparator. The test pattern generator is a circuit that generates a test pattern, which is test input data in the test target circuit, and the comparator outputs data output from the test target circuit and when the test target circuit is normal. This circuit compares the expected value.
[0013]
When a start trigger is received from outside the BIST during the test, the test control unit starts operating, and at the end of the test, a result output indicating whether the test is OK is output from the comparator to the outside of the LSI. Is done.
[0014]
[Problems to be solved by the invention]
In the first conventional example, in order to test the first test target circuit TC11, an input path IP11 for passing the test pattern from the input terminal to the position of the test target circuit TC11 is prepared, and the test target circuit TC11 outputs the output terminal The output path OP11 carrying the output result must be prepared. In this case, the programming of the input path IP11 and the output path OP11 is handled together with the programming of the test target circuit TC11.
[0015]
When the test target circuit TC12 is programmed, the input path IP12 and the output path OP12 are programmed together, and the test target circuit TC13, the test target circuit TC14,..., And the test target circuit TC1n are each programmed. Is the same as above.
[0016]
That is, when each test target circuit is programmed, the input path and output path associated therewith are programmed.
[0017]
However, the first test target circuit TC11, the second test target circuit TC12, the third test target circuit TC13,..., The nth test target circuit TC1n are the same functional circuit. Even if the programming is performed as described above, the positions of the input / output paths and the input / output terminals in the test target circuits are different from each other if the arrangement positions of the programmed test target circuits are different on the reconfigurable circuit.
[0018]
Therefore, in the first conventional example, it is necessary to individually set different input / output paths (need to be programmed) for each test target circuit (each time the test target circuit is programmed as a logic circuit), and There is a problem that different input / output terminals need to be individually set (programmed).
[0019]
By the way, in the BIST as the second conventional example, it is assumed that the test target circuit is a specific functional circuit. That is, it is necessary to know (at the time of design) what kind of signal the test pattern signal input to the test target circuit is and what value the expected value is. In addition, it is necessary to prepare the input test pattern signal and its expected value before manufacturing the LSI.
[0020]
Therefore, there is a problem that it is difficult to simply apply the conventional BIST to a circuit that programs a logic circuit such as a reconfigurable circuit.
[0021]
Further, in the conventional BIST, there is a problem that a test control unit is provided in advance in the LSI, and even after the test is completed, the test control unit remains as it is and cannot be used for purposes other than the test control unit. That is, there is a problem that overhead occurs.
[0022]
In the present invention, even if the entire circuit to be tested is large, it can be handled by the same method, the preparation for the test is simple, the method of the test itself is simple, and further, the test object is tested from the input terminal. Providing a test circuit that does not require a test pattern to be input to the circuit through the input path, and in addition, does not require an output path to carry test result data to the output terminal by a program or the like every time the test is performed It is intended.
[0023]
[Means for Solving the Problems]
The present invention is a test circuit including a test target circuit and a test execution control unit that applies a test pattern to the test target circuit. The test execution control unit is a test circuit having means for copying the test circuit.
[0024]
The present invention is a test circuit in which the duplicated test execution control unit (replication source test execution control unit) has means for starting up the duplicated test execution control unit.
[0025]
Furthermore, the present invention is a test circuit having means for providing an output path for outputting test result data from the test target circuit to a predetermined output terminal.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
[First embodiment]
A test circuit TC1 according to an embodiment of the present invention is a circuit that tests a reconfigurable logic circuit. An example of the reconfigurable logic circuit is a PCA (Plastic Cell Architecture). Briefly described.
[0027]
PCA includes a variable part (PP: Plastic Part) for realizing an arbitrary function (object) and a built-in part (BP: Built-in Part) that performs communication between objects and the outside. It is configured.
[0028]
FIG. 1 is a diagram showing the structure of a PCA as an example of a reconfigurable logic circuit to be tested by a test circuit TC according to an embodiment of the present invention.
[0029]
As shown in FIG. 1, the PCA cell has a reconfigurable logic circuit structure, controls the communication path and the variable part (PP), and the PCA cell is arranged in a two-dimensional manner. It is.
[0030]
FIG. 2 is a diagram showing the relationship between objects and messages in PCA.
[0031]
As shown in FIG. 2, each built-in unit (BP) constitutes a mesh network and performs function setting of the variable unit (PP) and routing of messages between objects configured on the variable unit (PP). . Each variable part (PP) is also connected to the variable part (PP) of an adjacent cell, and an object of an arbitrary size can be formed across a plurality of cells.
[0032]
The variable part (PP) is configured by a 4-input 1-output LUT (Look-Up Table) coupling network. The LUT constitutes a basic cell in units of four. Each basic cell uses an output signal of 1 bit from each basic cell adjacent in all directions as an input signal.
[0033]
These 4-bit signals are input signals common to the four LUTs in the basic cell. The outputs of these LUTs become input signals of basic cells adjacent in all directions. As a result, a network of two-way adjacent coupling of basic cells can be constructed. In PCA, the variable part (PP) of each PCA cell is an array of 8 × 8 basic cells as shown in FIG. It is constituted by. That is, the variable part (PP) to be managed by one embedded part (BP) is 64 basic cells (= 256 LUTs), and this is the minimum unit of the object.
[0034]
Various logic circuits can be realized by writing data as a memory in the LUT on the variable section (PP).
[0035]
FIG. 3 is a diagram illustrating a logic circuit realized by writing data as a memory in the LUT on the variable unit (PP) in the above embodiment.
[0036]
Each basic cell not only realizes arbitrary combinational logic, but also realizes wiring elements that connect logic elements. In a predetermined basic cell, for example, in order to realize the connection from the W direction to the E direction, as shown in FIG. 3 (2), 16 memory cells of the ELUT among the four LUTs in the basic cell For the input from the W direction (W _in ) Should be written so that it is transparent. In addition, an asynchronous register or a Muller-C element can be realized by configuring feedback with LUTs in two adjacent basic cells.
[0037]
The outline of PCA technology, detailed structure (hardware), and realized circuits are described in “Akira Nagoya, et al., Special Issue 2“ Plastic Cell Architecture ”NTTR & D Vol. 49 No. 9 pp 513-545 Sep. 10th. .. 2000. ”, many are described.
[0038]
FIG. 4 is a diagram for explaining the operation of copying the second test circuit TC2 after testing the first test circuit TC1 of the test circuits TC according to the embodiment of the present invention.
[0039]
The test circuit TC is a general term for the first test circuit TC1, the second test circuit TC2,..., The nth test circuit TCn, and is on a reconfigurable circuit RCC (for example, PCA). It is provided and applied to a test circuit for testing the structure of the variable part (PP).
[0040]
The test circuit TC1 includes a test execution control unit 101 and a test target circuit 201, the test circuit TC2 includes a test execution control unit 102 and a test target circuit 202,..., And the test circuit TCn includes test execution. It has a control unit 10n and a test target circuit 20n.
[0041]
The test execution control unit 101 is a circuit that applies a predetermined test pattern to the test target circuit 201, and is a circuit having means for copying the test circuit TC2, as shown in FIG. That is, the test execution control unit 101 is a circuit having means for copying the test execution control unit 102 and the test target circuit 202.
[0042]
The test execution control unit 102 is a circuit that gives a predetermined test pattern to the test target circuit 202, and is a circuit that has means for copying the test circuit TC3. That is, the test execution control unit 102 is a circuit having means for copying the test execution control unit 103 and the test target circuit 203.
[0043]
Further, in the same manner as described above, the test execution control unit 10 (n-1) is a circuit that applies a predetermined test pattern to the test target circuit 20 (n-1), and includes means for copying the test circuit TCn. It is a circuit having. That is, the test execution control unit 10 (n-1) is a circuit having means for replicating the test target circuit 20n and the test execution control unit 10n.
[0044]
That is, the test execution control units 101, 102,..., 10 (n−1) are examples of means for copying the test execution control unit and the test target circuit.
[0045]
The test execution control unit 101 has a function of starting the duplicated test circuit TC2, and a function of providing an output path for outputting test result data from the test target circuit 202 to a predetermined output terminal. Have.
[0046]
The test execution control unit 102 has a function of starting the duplicated test circuit TC3, and a function of providing an output path for outputting test result data from the test target circuit 203 to a predetermined output terminal. Have.
[0047]
Thereafter, in the same manner as described above, the test execution control unit 10 (n-1) has a function of starting the duplicated test circuit TCn, and outputs an output path for outputting test result data. It has a function of providing a predetermined output terminal from the test target circuit 20n.
[0048]
That is, the test execution control units 101, 102,..., 10 (n-1) are the means by which the replicated test execution control unit (replication source test execution control unit) activates the replicated test execution control unit. It is an example.
[0049]
Further, the test execution control units 101, 102,..., 10 (n−1) are examples of means for providing an output path for outputting test result data from each test target circuit to a predetermined output terminal.
[0050]
Next, the operation of the above embodiment will be described.
[0051]
FIG. 5 is a flowchart showing the test operation in the above embodiment.
[0052]
First, among the test circuits TC, the first test circuit TC1 prepared first is programmed as a logic circuit (S1). In this programming, an input path and an output path are formed, and an output terminal of the reconfigurable circuit RCC is formed.
[0053]
When the first test circuit TC1 is activated, a trigger signal is input only once from the outside of the reconfigurable circuit RCC (S1), and the first test circuit TC1 is input by the input trigger signal. Is activated.
[0054]
Then, the test execution control unit 101 gives a test pattern to the test target circuit 201, and the test is executed (S2). The result of this test is carried to the output terminal of the reconfigurable circuit RCC via the output terminal and output path of the test target circuit 201 (S3). Then, the result of this test is compared with an expected value outside the reconfigurable circuit RCC to determine whether the test target circuit 201 is good or bad.
[0055]
Here, a part of the beginning of the expected value also serves as a part of an instruction command to the built-in unit (BP), and an output path for output data is formed by the instruction command to the built-in unit (BP). Is done. For example, if “8”, “9”, “a”, “b” are included in a part of the beginning of the above expected value, the built-in unit (BP) It is interpreted as a command for setting a path in “west”, “north”, “east”, and “south”. Table 1 on page 522 (42) of "NTT R & D Vol. 49 No. 9 2000" shows an example of the instruction set of the message between PCA built-in parts (BP). Other than the setting of is also described.
[0056]
Therefore, in the above embodiment, when forming an output path from the test circuit TC2 to the output terminal, it is not necessary to send an instruction for forming an output path from the outside of the reconfigurable circuit RCC each time.
[0057]
After the output path is realized, the test result of the test target circuit 201 for the test pattern is output to the output terminal.
[0058]
As described above, when the test for the first test circuit TC1 is completed (S4), the test execution control unit 101 copies the second test circuit TC2 next to the first test circuit TC1. (S5).
[0059]
When duplicating a test circuit after the second test circuit TC2, the same test circuit as the test circuit TC1 is duplicated and the same test is repeated until the test circuit is out of the range on the reconfigurable logic circuit RCC.
[0060]
Then, the test execution control unit 101 of the first test circuit TC1 applies an activation trigger to the test execution control unit 102 of the duplicated second test circuit TC2.
[0061]
As described above, in the above embodiment, it is not necessary to provide the test circuit TC2 with an input path for supplying a trigger from the external terminal of the reconfigurable circuit RCC.
[0062]
In the first conventional example (reconfigurable circuit test), it is necessary to provide an input path for inputting a test pattern from an external terminal to a circuit to be tested. Since a test pattern is given to the test target circuit from the test execution control unit, it is not necessary to input the test pattern from an external terminal, and therefore it is not necessary to provide an input path for inputting the test pattern.
[0063]
In the second conventional example (BIST), it is necessary to input a start trigger from an external terminal. However, in the first embodiment, the first test circuit TC1 inputs a trigger for start from the outside. Although it is necessary, the duplicated test circuits (second and subsequent test circuits) TC2, TC3,..., TCn receive an activation trigger from the test execution control unit of the duplicating test circuit, so that external terminals There is no need to input a start trigger.
[0064]
When the test execution control unit 102 receives the activation trigger, the test execution control unit 102 gives a test pattern to the test target circuit 202, and the test is executed via the logic circuit formed in the test target circuit 202 ( S2) The result of this test is output from the output terminal of the reconfigurable circuit RCC via the output path (S3).
[0065]
Thereafter, the test execution control unit 102 duplicates the third test circuit TC3 next to the second test circuit TC2 (S5), and the test execution control unit 102 of the second test circuit TC2 performs the test execution control unit. 103 is activated to test the test target circuit 203 (S2), and the result of this test is output from the output terminal of the reconfigurable circuit RCC via the output path (S3).
[0066]
Then, the above operation is repeated, and next to the (n-1) th test circuit TC (n-1), the test execution control unit 10 (n-1) duplicates the nth test circuit TCn (S5), The test execution control unit 10 (n-1) of the (n-1) th test circuit TC (n-1) applies a start trigger to the test execution control unit 10n to test the test target circuit 20n (S2). The result of the test is output from the output terminal of the reconfigurable circuit RCC via the output path (S3).
[0067]
In the above embodiment, as described above, it is necessary to provide an input path for trigger supply between the external terminal of the reconfigurable circuit RCC and each of the test circuits TC3, TC4,. Absent.
[0068]
When the test result is output from the output terminal of the reconfigurable circuit RCC via the output path (S3), the output test result is output outside the reconfigurable circuit RCC. , 20n is compared with the expected value to determine whether the test target circuits 201, 202,.
[0069]
FIG. 6 is a diagram showing a state in which the test circuit TC2 is duplicated next to the test circuit TC1 in the range on the reconfigurable logic circuit RCC (for example, on the PCA system) in the above embodiment.
[0070]
In FIG. 6, a logic circuit program corresponding to the first test circuit TC1 is input from the input terminal on the left side, and a start trigger for starting the test execution control unit 101 of the first test circuit TC1 is input. . As a result, the test result is output from the test target circuit 201 to the output terminal on the right side via the output path OP1.
[0071]
The test circuit TC2 is duplicated to the right of the test target circuit 201. The test target circuit 202 duplicated in the same manner outputs the result to the right side terminal through the output path OP2 of the same path as the output path OP1. In this case, the copy-source test execution control unit 101 sends a trigger to the copied test circuit TC2 to activate the test circuit TC2.
[0072]
Thereafter, similarly to the above, the duplication of the test circuit TC, the supply of the trigger, and the test execution are repeated until the right side of the reconfigurable circuit RCC (PCA system) is reached.
[0073]
In the above embodiment, the activation trigger is applied only to the first test circuit TC1, and the activation trigger is supplied from the previous test circuit for the second test circuit TC2 and thereafter. Therefore, it is not necessary to supply a start trigger from the reconfigurable circuit RCC to the second test circuit TC2 and thereafter.
[0074]
According to the above embodiment, the entire range of the reconfigurable logic circuit RCC (the entire PCA system) can be tested by repeatedly performing the test using the relatively small test circuit TC.
[0075]
It is much easier to prepare a small test circuit TC than to prepare a test circuit that tests the entire range of a very large reconfigurable logic circuit RCC (the entire PCA system) at once. That is, test circuit design, verification, test execution, etc. are much easier.
[0076]
By the way, in the first conventional method for testing a reconfigurable logic circuit, the test pattern is tested when the same test circuit is moved and tested within the range of the PCA system (reconfigurable logic circuit). The input path given to the target circuit and the output path for outputting the test result must be changed.
[0077]
However, in the above embodiment, the test execution control unit 102 that gives the test pattern to the test target circuit 202 is duplicated as the test circuit TC2 is duplicated, so that it is not necessary to provide a separate input path. In the above embodiment, an output path is automatically created for each test by devising a test pattern so as to give the meaning of an instruction for generating an output path according to the expected value.
[0078]
Next, a specific operation of the above embodiment will be described by taking a device simulation based on PCA as an example.
[0079]
First, for an overview of simulation based on PCA and explanation of drawings, refer to the document “Konishi et al.,“ Software that Supports PCA Realization ”, 16th Parthenon Study Group Collection, Vol 16, p4-12, Ome Sato Foundation. "Partenon Study Group, May 19, 2000".
[0080]
FIG. 7 is a diagram showing an initial circuit after programming the logic circuit (test circuit TC1) in the above embodiment.
[0081]
FIG. 8 is a diagram simply showing the same state as that shown in FIG.
[0082]
In the upper left corner of FIG. 7, the test circuit TC1 is programmed. The test execution control unit 101 and the test target circuit 201 constitute a test circuit TC1. In FIG. 7, one register and one gate are provided for each fine circuit wiring. However, the following description will be made using a state diagram during the simulation operation as an abstract simplified display as in the variable part (PP) after activation shown in FIG.
[0083]
FIG. 9 is a diagram showing a built-in part (BP) at the time of testing in the above embodiment.
[0084]
8 shows a state in which the output path extends from the first test circuit TC1, which is the same as the variable section (PP) after activation shown in FIG. 8, to the external terminal and sends data.
[0085]
It can also be seen that the test pattern stored in the test execution control unit 101 is given to the test target circuit 201. That is, in FIG. 9, the data of the thick horizontal bar drawn in the test execution control unit of the test circuit is read.
[0086]
FIG. 10 is a diagram showing a replication command output to the first test circuit TC1 in the above embodiment.
[0087]
When the test of the test circuit TC1 is completed, an instruction sequence for duplicating the test circuit TC1 and an instruction sequence for starting the duplicated circuit are issued from the test execution control unit 101, as in the duplicate instruction shown in FIG. The Alphanumeric characters drawn on the path from the test execution control unit 101 back to the test circuit TC1 are the instruction sequence.
[0088]
In FIG. 10, alphanumeric characters are values in hexadecimal notation of data transferred on the built-in part (BP) layer at the time of a test, and mean an instruction delimiter. A white circle represents a signal transition from high to low, and means a break between instructions.
[0089]
Then, all the instruction sequences are issued from the test execution control unit 101, and the test mechanism (the entire test circuit TC1) is duplicated to the right according to the instruction sequences.
[0090]
FIG. 11 is a diagram showing a built-in part (BP) that is being duplicated in the above embodiment, and is a diagram showing a way in which a part near the end of the test target circuit in the test circuit adjacent to the test circuit TC1 is being duplicated. It is.
[0091]
FIG. 11 shows a state in which the information of the test circuit TC1 is sucked out and discharged to an area to be duplicated. That is, in FIG. 11, the thick horizontal bar drawn in the test target circuit 201 of the test circuit TC1 reads the test target circuit 201, and the thick horizontal bar drawn on the right side of the test circuit TC1 This shows that the test target circuit 201 is written on the right side of the test circuit TC1 in the middle of copying.
[0092]
FIG. 12 is a diagram showing the variable part (PP) during duplication at the same timing as the mid-duplication timing shown in FIG. 11 in the above embodiment.
[0093]
In FIG. 12, the portion near the end of the test target circuit 202 is not yet duplicated, indicating that it is in the middle of duplication.
[0094]
Thereafter, when the replication is completed, the copied circuit is activated in the second half of the instruction sequence issued by the replication instruction shown in FIG.
[0095]
FIG. 13 is a diagram showing the variable unit (PP) in operation after the test circuit TC is replicated once in the above embodiment.
[0096]
In the state shown in FIG. 13, all of the portions that were in the middle of duplication in the variable section (PP) shown in FIG. 12 are duplicated, and the wiring in the circuit shown in FIG. 13 changes compared to the wiring shown in FIG. The test circuit is activated by the start command.
[0097]
FIG. 14 is an enlarged view of the test circuits TC1 and TC2 shown in FIG.
[0098]
FIG. 15 is an enlarged view of the test circuits TC1 and TC2 shown in FIG.
[0099]
In FIGS. 14 and 15, the operating wiring is indicated by a broken line, and the non-operating wiring is indicated by a solid line.
[0100]
The state shown in FIG. 14 is a state in the middle of duplicating the test circuit TC2, and most of the wiring of the test circuit TC2 is not operating (mostly shown by a solid line), but the state shown in FIG. The copy of the test circuit TC2 is completed and the variable part (PP) is in operation. The upper left part and the lower right part of the test circuit TC2 are almost operated (mostly indicated by broken lines). Part of the part is working (partially indicated by a broken line).
[0101]
The operation of this test circuit is the same as the test operation in the first test circuit TC1 shown in FIG. 7, FIG. 8, and FIG.
[0102]
FIG. 16 is a diagram illustrating a built-in unit (BP) at the time of a test after the first replication (after the second test circuit TC2 is replicated) in the above embodiment.
[0103]
The test operation in the second test circuit TC2 shown in FIG. 16 is the same as the test operation in the first test circuit TC1 shown in FIG. That is, the test execution control unit 102 in the second test circuit TC2 shown in FIG. 16 gives a test pattern to the test target circuit 202, and the output path from the test target circuit 202 to the same output terminal as in FIG. And the data is sent out.
[0104]
FIG. 17 is a diagram illustrating the variable portion (PP) after the test is performed a plurality of times in the above embodiment.
[0105]
When the above operation is repeated, a variable part (PP) after a plurality of tests shown in FIG. 17 is obtained. The test circuit TCk that is operating after duplication exists on the rightmost side (the side close to the output terminal), and on the left side is a test circuit TC (k−1) that was duplicated immediately before, and A previously duplicated test circuit TC (k-2) continues to its left.
[0106]
FIG. 18 is a diagram showing a built-in unit (BP) that has issued a duplication instruction after testing a plurality of times in the above embodiment.
[0107]
Of course, when looking at the state of operation, in the built-in unit (BP) that issued the duplication instruction after testing a plurality of times as shown in FIG. 18, the test circuit TCk duplicates the circuit further to the right on the rightmost side. As a result, it can be confirmed that the instruction sequence is issued in the same manner as the duplicate instruction shown in FIG.
[0108]
In the same way as the variable part (PP) shown in FIG. 17, in FIG. 18, the built-in part (BP) is provided on the left side of the circuit TC (k−1) duplicated one time before, and further duplicated before. The circuit TC (k-2) thus made continues to the left adjacent to it.
[0109]
As described above, a new test target circuit is tested each time the circuit duplicates one test circuit TC partially from left to right while referring to the display of the device simulation.
[0110]
In the above embodiment, when the test circuit TC1 is divided into four equal parts, the test target circuit 201 is one part of the four divisions, that is, a part having an area of 1/4 of the test circuit TC1. . Therefore, focusing on the test circuit TC1, only the upper right part of the test circuit TC1 is tested as the test target circuit 201, that is, only 1/4 of the test circuit TC1 is tested. If the above test is not performed on the remaining 3/4 portion of the test circuit TC1, all the test circuits TC1 are not tested.
[0111]
In order to test the remaining 3/4 portion of the test circuit TC1, the test target circuit 201 is newly set in the upper left portion of the test circuit TC1, and the test is performed. In addition, the test target circuit 201 is set in the lower left portion of the test circuit TC1. 201 may be set again, a test may be performed, and the test target circuit 201 may be set again in the lower right part of the test circuit TC1 to perform the test. That is, if the test circuit TC1 shown in FIG. 10 is rotated by 90 degrees around the center point of the test circuit TC1 and the test is executed each time, all the test circuits TC1 are tested. .
[0112]
In FIG. 10, the instruction sequence can be issued in the vertical direction, and the test target circuit can be arranged at an arbitrary position in the test circuit TC1, such as the bottom or the middle. As described above, the test can be performed in a state rotated by 90 degrees.
[0113]
Also, test circuits other than the test circuit TC1, such as the test circuits TC2, TC3,..., TCn, etc., when tested in a state rotated by 90 degrees as described above, all parts of the reconfigurable circuit RCC are You can test without omission.
[0114]
According to the above-described embodiment, since the homogeneous structure is duplicated and tested by duplicating the test circuit itself, even if the whole part to be tested is large, it can be handled by the same method. In other words, it has excellent extensibility in testing.
[0115]
Further, according to the above-described embodiment, the test target circuit in one test can be suppressed to a small circuit scale, so that the preparation for the test is simple and the way of the test itself is simple. That means testing is simple.
[0116]
Furthermore, according to the above-described embodiment, it is not necessary to input a test pattern through the input path from the input terminal to the test target circuit, and in addition, the output path for carrying the test result data to the output terminal is programmed every time the test is performed. There is no need to reset the settings. That is, the test path is simplified.
[0117]
In the above embodiment, the test pattern is stored in the test execution control unit 101 of the first test circuit TC1, and the test execution control unit 101 is sequentially replicated. Thus, the test pattern is also duplicated. Therefore, when testing the first test circuit TC1 to the last test circuit TCn, there is no need to input the test pattern from outside the reconfigurable circuit RCC. For this reason, the time for testing all the reconfigurable circuits RCC is very short, that is, the reconfigurable circuit RCC can be tested at high speed. Note that the test is executed at a high speed at the same speed as the operation speed when the reconfigurable circuit RCC is used.
[0118]
Also, only the first test circuit TC1 is supplied with a trigger from the outside of the reconfigurable circuit RCC via a dedicated input path for trigger supply. The trigger may be supplied sequentially from the circuit TC1.
[0119]
Furthermore, in the conventional example by BIST, a test control unit is provided in advance in the LSI, and even after the test is completed, the test control unit remains as it is and cannot be used for purposes other than the test control unit (an overhead occurs). In the above embodiment, when the test is completed, the test execution control unit can be used for purposes other than the test execution control unit.
[0120]
In the above-described embodiment, a test pattern is supplied from the test execution control unit 101 to the test target circuit 201, and this test pattern can be reconfigured via a logic circuit in the test target circuit 201 and via an output path. It is sent to the output terminal of the circuit RCC and compared with a predetermined expected value outside the reconfigurable circuit RCC, and the quality of the test circuit TC1 is determined according to the comparison result. That is, the test execution control unit 101 does not execute the comparison operation. Instead, the test execution control unit 101 may execute the comparison operation.
[0121]
That is, a test pattern is supplied from the test execution control unit 101 to the test target circuit 201, and the test pattern returns to the test execution control unit 101 via the logic circuit in the test target circuit 201. The test execution control unit 101 compares the returned test pattern with a predetermined expected value, determines the quality of the test circuit TC1 according to the comparison result, and re-determines the determination result via the output path. It may be sent to the output terminal of the configurable circuit RCC. In this case, it is necessary to provide the test execution control unit 101 with a comparison circuit that performs the comparison, and it is necessary to provide a function for holding the expected value.
[0122]
In the above case, the test execution control units 102, 103,..., 10n are also provided with a function of holding the comparison circuit and the expected value as in the case of the test execution control unit 101. As the test circuits TC2, TC3,..., TCn are replicated, the comparison circuit and the function for holding the expected value are also replicated.
[0123]
[Second Embodiment]
By the way, in the first embodiment, the test circuit is constituted by the test execution control unit and the test target circuit, and the duplication source test circuit and the duplication destination test circuit are duplicated without overlapping each other. Therefore, in one test circuit, a region duplicated as a test execution control unit does not operate as a test target circuit, and a portion that does not operate as the test target circuit remains as an untested region.
[0124]
That is, for example, a test execution control unit exists in the left block, a test circuit in which the test target circuit exists is used in the right block of the test execution control unit, and the test circuit is arranged in the horizontal direction (right direction). When duplicating, since the test execution control unit occupies an odd-numbered block counting from the left end, this area remains as an untested area.
[0125]
On the other hand, even in the even columns where the circuit to be tested is duplicated, areas that are not tested are left in the vertical direction, and it is necessary to prepare another test circuit in order to test these untested areas (test circuit There is a problem that it is necessary to read from the outside again and repeat the test and replication based on the read test circuit.
[0126]
Here, when reading again from the outside of the test circuit, the write position of the test circuit is changed (for example, on the third and fourth lines), or the external read position is changed, and as a result, the position of the test circuit is changed. Read again from outside the test circuit.
[0127]
In addition, when a test is performed using a plurality of different test target circuits, it is necessary to prepare a test target circuit for each test target circuit among the plurality of test target circuits and perform the test individually. However, it is complicated to prepare the test circuits individually, and there is a problem that the entire test time becomes long. In other words, after the first test target circuit is tested and duplicated, the second test target circuit is read from outside, tested and duplicated, and these operations are performed on the test target circuit to be tested. There is a problem that this operation is complicated, and the entire test time becomes long.
[0128]
Furthermore, if the test target circuit is composed of multiple blocks (for example, 2 × 2 blocks), even if the test circuit is copied so that part of the test circuit's copy destination overlaps the copy source, the test target circuit is tested before There is a problem that an area that cannot be tested may not remain unless there is an overlap with the test target circuit, and there is a problem that it is necessary to prepare another test circuit in order to test the area that is not tested.
[0129]
Second Embodiment The following embodiments are intended to provide a test circuit capable of testing almost all areas in a single test and making the test more efficient (rationalized). .
[0130]
The difference between the first embodiment and the second to fifth embodiments to be described in principle is the method of duplication. The first embodiment is an embodiment in which the entire test circuit is integrated and duplication is performed collectively. On the other hand, the second to fifth embodiments are embodiments that basically perform duplication of the test execution control unit and duplication of the test target circuit individually.
[0131]
In the second embodiment of the present invention, when a test circuit is duplicated, a part of the duplication destination of the test circuit is duplicated so as to overlap the duplication source of the test circuit.
[0132]
FIG. 22 is an explanatory diagram of the second embodiment of the present invention.
[0133]
FIGS. 22 (1) to 22 (3) are explanatory diagrams of the first embodiment and are diagrams for explaining the second embodiment.
[0134]
FIG. 22A is a diagram illustrating a test circuit configured by 2 × 2 blocks, and is a diagram illustrating a test circuit as a copy source. The test circuit includes a test execution control unit having a memory M and a filter circuit F, and a test target circuit T. In this example, two test target circuits T are provided in one test circuit.
[0135]
FIG. 22 (2) is a diagram showing a state in which the test circuit is duplicated to the right of the two test target circuits T in the test circuit after the test in the first embodiment.
[0136]
FIG. 22 (3) shows a state in which the test circuit is duplicated for the second time on the right side after the test target circuit T in the test circuit duplicated for the first time is tested in the first embodiment. FIG.
[0137]
Here, the test target circuit T is not duplicated in the area where the memory M and the filter circuit F are duplicated (the area where the test execution control unit is duplicated).
[0138]
Therefore, in order to test these regions (regions where the test execution control unit is duplicated), in another test circuit (for example, in the test circuit shown in FIG. 22 (1), the test execution control unit and the test target circuit The test must be carried out using a test circuit whose position is reversed from side to side. In other words, in the first embodiment, the test circuits are continuously replicated without overlapping, so that every other row remains in an untested area, so another test circuit is read from the outside and used. Therefore, it is necessary to execute a test including reading from the outside twice.
[0139]
22 (4) to 22 (6) are diagrams for explaining the features of the second embodiment.
[0140]
FIG. 22 (4) is the same test circuit as the test circuit shown in FIG. 22 (1), and shows a state before the test circuit is duplicated.
[0141]
FIG. 22 (5) is a diagram illustrating a state after the first copy is executed after the first test is executed in the second embodiment. In this duplication, half of the test circuit duplication destination is duplicated so as to overlap the test circuit duplication source. That is, half of the duplication destination of the overlapping test circuit is a test execution control unit in the duplication destination of the test circuit.
FIG. 22 (6) is a diagram illustrating a state after the test circuit replicated for the first time is tested and the second replication is executed in the second embodiment. Also in this case, half of the test circuit duplication destination is duplicated so as to overlap the test circuit duplication source.
[0142]
Therefore, the test execution control unit at the duplication destination is duplicated in the area where the test target circuit T exists in the duplication source, and only the test target circuit T is always duplicated in a new area (an area that has not yet been duplicated).
[0143]
It should be noted that a part of the test circuit duplication destination may be duplicated so as to overlap with the test circuit duplication source, including a case where half of the test circuit duplication destination overlaps with the test circuit duplication source.
[0144]
In other words, the second embodiment is a test circuit including a test target circuit and a test execution control unit that applies a test pattern to the test target circuit. The test execution control unit includes the test target circuit and the test execution unit. This is a test circuit that has a means for copying the control unit and for copying so that a part of the copy destination of the test circuit overlaps the copy source of the test circuit.
[0145]
As described above, it is possible to test almost all of the duplicated areas by duplicating the duplication destination test circuit with an overlap with the duplication source test circuit.
[0146]
FIG. 23 is a diagram showing how the duplication and testing are executed by the simulator in the second embodiment.
[0147]
FIG. 24 is an enlarged view of FIG.
[0148]
The upper and lower same circuits shown at the right end in FIG. 23 are the test target circuit T, and in the upper circuit, all the wiring in the circuit is drawn with a solid line, and this circuit is not operating (is in a stopped state). The lower circuit shows that most of the wiring is drawn with light colored lines (dashed lines in the enlarged view of FIG. 24), confirming that the signal is propagating and the test is being performed. it can.
[0149]
The left side of the test target circuit T is a test execution control unit, the upper side of the test execution control unit is the memory M, and the lower side of the test execution control unit is the filter circuit F. Three test execution control units (memory M and filter circuit F) are arranged side by side, and it can be seen that the test circuit is duplicated three times. Among these three test execution control units, only the filter circuit F on the right side (the left side of the test target circuit performing the test operation) has a light color in part of the wiring (the broken line in the enlarged view of FIG. 24). ). This indicates that the test operation of the test target circuit T on the right side is controlled.
[0150]
[Third embodiment]
The third embodiment of the present invention is an embodiment in which only the circuit to be tested is replicated.
[0151]
FIG. 25 is an explanatory diagram of the third embodiment of the present invention.
[0152]
FIGS. 25 (1), (2), and (3) are the same as FIGS. 22 (1), (2), and (3). In this case, the ratio of the area to be tested out of the areas where the test circuit is duplicated, that is, the coverage ratio R, is duplicated together with the test execution control unit and the test target circuit T for each test circuit. So
R = test target circuit / (test execution control unit + test target circuit)
It is.
[0153]
Here, in the first embodiment, since the test circuit is replicated only in the horizontal direction, the area that cannot be tested includes not only the test execution control unit (the location of the memory M and the filter circuit F) but also the test circuit in the horizontal direction. Are all vertical regions except for two rows to be copied. For the area excluding these two lines, it is necessary to repeat the operation of reading the test circuit from the outside, testing it, and copying it.
[0154]
Here, when the test circuit is read again from the outside, the write position of the test circuit is changed to the third and fourth lines, or the external read position is changed, and as a result, the position of the test circuit is similarly changed.
[0155]
FIG. 25 (4) is a diagram showing an embodiment in which a test circuit in which the test execution control unit and the test target circuit T are combined is duplicated, and only the test target circuit T is duplicated in the vertical direction.
[0156]
FIG. 25 (4) shows that the test execution control unit (the memory M and the filter circuit F) at the left end tests the two test target circuits T existing at the uppermost part on the right side, and then the two test target units. Only the circuit T is duplicated one down, the duplicated test target circuit T is tested, and a duplicate of the test target circuit T is performed below the duplicated test target circuit T. The test of the test target circuit T is repeated as many times as necessary.
[0157]
In the embodiment shown in FIG. 25 (4), two test target circuits T are duplicated twice, and a total of six test target circuits T are tested in the vertical direction. As described above, after executing the duplication of only the test target circuit T and the test of the duplicated test target circuit T, the first test circuit (the test execution control unit and the test target circuit T combined) is obtained. Duplicate to the right. Then, the test is performed again, and only the test target circuit T is copied to the lower side and the test of the copied test target circuit T is repeated several times. In this figure, the test circuit is duplicated twice, and the test circuit T of the test circuit duplicated for the second time is displayed up to the stage where the first duplication is completed.
[0158]
As described above, in addition to the horizontal duplication of the test circuit according to the second embodiment, the duplication in the vertical direction of only the test target circuit T according to the third embodiment is performed, thereby covering the test circuit. The rate R is
R = k × test target circuit / (test execution control unit + k × test target circuit)
It can be improved.
[0159]
Note that k indicates the number of test target circuits that have been tested. In other words, under the condition that each copy does not overlap, one test execution control unit is copied between immediately after the test execution control unit is copied and immediately before the next test execution control unit is copied. The number of test target circuits can be k.
[0160]
In the case of the example shown in FIG. 25 (4), after duplicating the test execution control unit, the two test target circuits are duplicated twice in the vertical direction, and immediately before the test execution control unit is duplicated, the two test target circuits are duplicated. Add one copy in the horizontal direction. Therefore, k = 2 × 2 × (number of test target circuits by vertical duplication) + 1 × 2 × (number of test target circuits by horizontal duplication) = 6.
[0161]
FIG. 26 shows a simulation state when only the test target circuit T is duplicated in the vertical direction and the test circuit is duplicated in the horizontal direction so that a part of the duplication destination overlaps the duplication source in the third embodiment. FIG.
[0162]
FIG. 27 is an enlarged view of FIG.
[0163]
In FIG. 26, the left end is a test execution control unit having a memory M and a filter circuit F, and two identical test execution control units are duplicated on the right side, and the test execution control unit is duplicated twice. It shows that it is in a state. Among these, in particular, only the filter circuit F of the test execution control unit existing third from the left part of the wiring changes to a light color (broken line in the enlarged view of FIG. 27), and the test execution control unit Shows the operating state.
[0164]
In FIG. 26, four test target circuits are arranged vertically at the right end. Among these, the test target circuits T arranged below are duplicated only for the test target circuit T. In particular, in the test target circuit (bottom test target circuit) T copied to the fourth block from the top, part of the wiring changes to a light color (broken line in the enlarged view of FIG. 27), and the above operation is performed. The test execution control unit in FIG.
[0165]
In addition, the test target circuit T duplicated in the second to third blocks from the left to the third to sixth blocks from the left duplicates only the first test target circuit T several times, and the test circuit (test execution) This is a test target circuit in which only the test target circuit T is replicated several times after the control unit and the test target circuit T are replicated once.
[0166]
Here, in the result in the middle of the test in FIG. 26 (FIG. 27), the total number k of the test target circuits subjected to the test is the number of test target circuits located in the second and third columns from the left, The vertical direction is 6 × 2 in the horizontal direction, the number of circuits to be tested in the fourth column, and 4 in the vertical direction, and k = 16. In addition, since all the duplicated portions of the test execution control unit are regions where the test target circuit has already been located, only the region where the first one test execution control unit exists is not tested. .
[0167]
Therefore, the coverage ratio at this time is R = 16 × test target circuit / (test execution control unit + 16 × test target circuit).
[0168]
As described above, the test target circuit T is duplicated not only in the horizontal direction but also in the vertical direction by the single test target circuit T, so that the test can be performed more efficiently.
[0169]
That is, in the third embodiment, the test target circuit is a plurality of different test target circuits, and one test execution control unit repeats duplication and testing for the plurality of different test target circuits. This is an example of execution.
[0170]
[Fourth embodiment]
The fourth embodiment of the present invention is an embodiment in which a plurality of different test target circuits are handled (duplicated and tested) almost simultaneously.
[0171]
FIG. 28 is an explanatory diagram of the fourth embodiment of the present invention.
[0172]
FIG. 28 (1) is the same diagram as the third embodiment shown in FIG. 25 (4). In the third embodiment shown in FIG. 28 (1), the test circuit is duplicated in the horizontal direction while overlapping the test circuits, and the duplication of performing only the test target circuit T in the vertical direction is executed k times, thereby improving the test efficiency. Can be achieved. However, in order to test with a plurality of different test target circuits, it is necessary to prepare a plurality of different test target circuits, individually copy and test them, and it is complicated to repeat the individual duplication and test. .
[0173]
In other words, after the first test target circuit is tested and duplicated, the second test target circuit is read from outside, tested and duplicated, and these operations are performed on the test target circuit to be tested. There is a problem that this operation is complicated, and the entire test time becomes long.
[0174]
In the fourth embodiment shown in FIGS. 28 (2) to 28 (4), different test target circuits T1 to T5 are placed in the right adjacent column of the test execution control unit (memory M and filter circuit F). T1, T2, T3, T4, and T5 are arranged in the vertical order from the top. In this case, an area where the test target circuit is not duplicated, that is, an area displayed as “empty” is provided. Then, the test target circuits T1 to T5 are tested, the “empty” region is used, the test target circuits T1 to T5 are moved one by one, copied, tested, and this is repeated. .
[0175]
That is, in the fourth embodiment, the test target circuits T1, T2, T3, T4, and T5 are arranged in the vertical order from the top in the column adjacent to the right of the test execution control unit (the memory M and the filter circuit F). After that, each of the test target circuits T1 to T5 is tested, and the test target circuits are duplicated so as to move down by one. That is, the test target circuit T5 is duplicated in the “empty” area, the test target circuit T4 is duplicated in the area where the copy source test target circuit T5 exists, and the copy source test target circuit T4 exists. The test target circuit T3 is duplicated in the area, the test target circuit T2 is duplicated in the area where the copy source test target circuit T3 exists, and the test is performed in the area where the copy source test target circuit T2 exists. The target circuit T1 is duplicated. In this state, the test target circuits T1 to T5 are tested. By this test, a test by two test target circuits is executed in one area.
[0176]
Here, the test source circuit T1 as the copy source has the same meaning as the “empty” area. That is, even if another test target circuit is copied to the test source circuit T1 that is the copy source, there is another test target circuit T1 that is the copy destination, so that there is no problem in duplicating the test target circuit T1 separately. , Which has the same meaning as the “empty” area. The test target circuit T5 is duplicated in the area having the same meaning as the “empty” area, the test target circuit T4 is duplicated in the area where the copy source test target circuit T5 exists, and the copy source test target circuit is copied. The test target circuit T3 is duplicated in the area where T4 exists, the test target circuit T2 is duplicated in the area where the copy source test target circuit T3 exists, and the copy source test target circuit T2 exists. The test target circuit T1 is duplicated in the area where In this state, the test target circuits T1 to T5 are tested. By this test, a test by three test target circuits is executed in one area.
[0177]
As described above, the test target circuit T5 is copied to an area having the same meaning as the “empty” area, and the test target circuits T4 to T1 are sequentially moved and tested. A test using five test target circuits is executed.
[0178]
In this manner, when the test by the five test target circuits is completed in one area, as shown in FIG. 28 (3), the test target circuits are T2, T3, T4, T5, “empty” from the top. , T1 in order. Here, the test target circuit T1 located at the bottom is duplicated in the uppermost block on the right of one column, and as shown in FIG. 28 (4), the test target circuits T2, T3, T4, and T5 are arranged in this order. Then, duplication is performed continuously under the circuit to be tested T1 as a duplication destination.
[0179]
Then, the test execution control unit (the memory M and the filter circuit F) is duplicated in the right adjacent column, and the duplicated test target circuits T1 to T5 are tested.
[0180]
As described above, a plurality of different test target circuits are arranged in the vertical direction, tested, duplicated to be moved in the vertical direction by duplication, tested, and this is repeated to test different test target circuits in the column. When all the above are completed, the test execution control unit and the test target circuit are duplicated in the horizontal direction. Such an operation makes it possible to test several different types of test target circuits at once.
[0181]
In other words, when testing a plurality of different test target circuits, it is sufficient to read the test circuit including the test target circuit only once from the outside, and the test work is extremely efficient.
[0182]
FIG. 29 is a diagram showing a state on the simulator when handling different types of test target circuits and testing them all at once in the fourth embodiment.
[0183]
The two blocks on the upper left are the memory M, and the lowermost block (the third block from the top) is the filter circuit F. Together, they constitute one test execution control unit. ing.
[0184]
FIG. 30 is an enlarged view of FIG.
[0185]
In FIG. 29, the five blocks at the right end are test circuit T1, T2, T3, T4, and T5 which are all different from each other. Among these five test target circuits T1 to T5, the partial wiring of the test target circuit T5 of the lowermost block (the fifth block from the top) is shown in a light color (broken line in the enlarged view of FIG. 30), The test operation is shown.
[0186]
Further, in FIG. 29, the third filter circuit F from the top in the second row from the right is indicated by a light color (dashed line in the enlarged view of FIG. 30), and the test circuit T5 at the bottom right is tested. This indicates that a control operation is being executed.
[0187]
In FIG. 29, the test execution control unit including the memory M, which is the upper two blocks in the second column and the third column from the right, and the third filter circuit F from the top is the first copy and 2 It was copied by the second copy. Further, the lower three test target circuits in the second and third columns from the right are portions in which duplication is not overwritten after testing by moving different test target circuits one by one by duplication.
[0188]
The fourth embodiment is an embodiment in which different types of test target circuits are handled. However, in the same fourth embodiment, regarding the duplication of only the test target circuit shown in FIG. 28 (2), if attention is paid to each of the test target circuits, the third embodiment described above will be used. It can be seen that duplicating only the test target circuit in the vertical direction is applied to each of all the test target circuits.
[0189]
The first to fourth embodiments may be implemented alone, or a plurality of embodiments of the first to fourth embodiments may be combined and implemented. The test efficiency when performed in combination is synergistically improved, which is important to note.
[0190]
[Fifth embodiment]
In the fifth embodiment, the test target circuit is duplicated so as to fill a gap between the duplicated test target circuits.
[0191]
In the first place, one block described so far corresponds to one PCA cell shown in FIG. Here, looking at the PCA cell of FIG. 1, this variable part (PP) is further composed of two-dimensionally arranged basic cells, and between adjacent PPs, the input / output lines of the basic cells corresponding to the block boundaries Wired at Therefore, the test of the basic cell at the boundary related to the input / output lines extending between the PPs needs to be performed using a plurality of blocks corresponding to them as a test target circuit.
[0192]
FIG. 31 is an explanatory diagram of the fifth embodiment of the present invention.
[0193]
In the test target circuit shown in FIG. 31, the basic cell located at the corner of the variable part is connected to the input / output line with the basic cell included in the upper, lower, left, and right adjacent PP. Occupies an area of 2 × 2 blocks.
[0194]
In the fourth embodiment shown in FIG. 31 (1), only the test target circuit T occupying the area of 2 × 2 blocks is duplicated twice in succession, tested, and then the test execution control unit However, the test target circuit is duplicated on the right side and tested so that it overlaps a part of the duplication source test target circuit. In the same manner as described above, only the test target circuit T is duplicated twice in succession and tested. As described above, when the duplication and the test are performed, the test target circuit T can perform the test so that all the areas are laid down in the vertical direction and the horizontal direction.
[0195]
However, the reason why the test target circuit T has the 2 × 2 block size is that the area spanning the blocks (in the example shown in FIG. 31 (1), the central part of four blocks (intersection part indicated by a broken line) is tested. Because.
[0196]
As described above, when this central portion is indicated by PP in FIG. 1, it corresponds to a basic cell located at the corner of one PP. In a basic cell at a corner of a certain PP, a basic cell included in the adjacent PP, an input signal line, and an output signal line are connected to each other vertically and horizontally.
[0197]
Therefore, in FIG. 31 (1), the intersections of the four blocks (shaded portions) remain untested by such a method.
[0198]
Therefore, when the test target circuit T is duplicated, as shown in FIG. 31B, the test target circuit T is duplicated so as to overlap a part of the test target circuit T that has already been tested. In this case, the test target circuit T is duplicated in a predetermined order. In other words, the copy source is copied before the operation of copying the copy source of the test target circuit T (the area where the circuit configuration information is read) to the copy destination of the test target circuit T (the area where the circuit configuration information is written) ends. If an attempt is made to superimpose first, the duplication will not be performed normally. Therefore, the duplication source of the test target circuit T is duplicated on the duplication destination of the test target circuit T, and then duplicated on the duplication source. The test target circuit T is duplicated in this order.
[0199]
In the fifth embodiment, when the circuit T to be tested is duplicated for the first time and duplicated for the second time, the circuit under test T is duplicated in order downward. In other words, when duplicating for the first time, the circuit to be tested Ta (the circuit with the slanting left slanting line) is duplicated in the 3rd to 4th rows from the top according to the arrow marked with (1) in FIG. When duplicating for the second time, the test target circuit Tb (the circuit with the slanting line on the lower right) is duplicated on the 5th to 6th lines according to the arrow marked with (2).
[0200]
Then, after testing the test target circuits Ta and Tb replicated for the first and second times, the third and fourth times of replication are performed. That is, in the case of duplicating for the third time, according to the arrow marked with (3) in FIG. 31 (2), the test target circuit Tc is duplicated in the second to third rows from the top, and in the case of duplicating for the fourth time, (4) The test target circuit Td is duplicated in the 4th to 5th lines according to the arrow marked with ▼. Then, the test target circuits Tc and Td copied at the third and fourth times are tested.
[0201]
When duplicating in this order, the test target circuit replicated at a certain point (the original test target circuit) and the test target circuit to be replicated at the next point in time (the target test target circuit) will overlap. Absent. When the two columns of the circuit under test are viewed in the vertical direction by the above four times of duplication, the first and second row regions, the second and third row regions, the third and fourth row regions, Since the test target circuit replicated in each of the fifth row area and the fifth and sixth row areas is tested, all the intersections (boundary areas) of the four blocks are tested.
[0202]
The reason why the test target circuit T has a 2 × 2 block size is to test an area extending between the blocks (in the example shown in FIG. 31 (1), the central portion of four blocks (intersection portion indicated by a broken line)). Because.
[0203]
As described above, when this central portion is indicated by PP in FIG. 1, it corresponds to a basic cell located at the corner of one PP. In a basic cell at a corner of a certain PP, a basic cell included in the adjacent PP, an input signal line, and an output signal line are connected to each other vertically and horizontally.
[0204]
FIG. 31 (3) is a diagram illustrating a case where a test circuit in which a test execution control unit and a test target circuit are combined is duplicated in the horizontal direction. First, in FIG. 31 (3), according to the arrow marked with (5) -1, the test target circuit Td existing in the region of the fourth and fifth rows is overlapped by the column adjacent to the right by one column. And it replicates to the first and second lines. That is, this duplication result is the test target circuit Te. Next, in FIG. 31 (3), the test execution control unit having the memory M and the filter circuit F is duplicated to the right side in accordance with the arrow (5) -2.
[0205]
In this way, even when duplicating in the horizontal direction, the test target circuits T overlap each other and are duplicated. Therefore, the boundary of the intersection of the four blocks can be tested without omission in both the vertical direction and the horizontal direction.
[0206]
FIG. 32 is a diagram showing a state in which a simulation operation is performed in the fifth embodiment.
[0207]
FIG. 33 is an enlarged view of FIG.
[0208]
The test execution control unit is composed of two blocks shown at the left end, the upper side is a memory M, and the lower side is a filter circuit F. The test target circuit T is the lowermost 2 × 2 block (2 × 2 blocks corresponding to 2 columns from the right and 5 to 6 rows from the top). Exactly, 2 columns from the right, 2 from the top, and 2 × 2 blocks in the 3rd row are the same circuit under test, but the wirings in this circuit under test are lightly colored (in the enlarged view of FIG. 33). A broken line) indicates a state in which the test operation is performed. Further, the filter circuit F of the test execution control unit adjacent to the left also has a partly light color (dashed line in the enlarged view of FIG. 33), indicating that the test control operation is being performed.
[0209]
Further, in the second and third columns from the left, the test execution control units in the first and second rows are obtained by copying the test execution control units for the first time and the second time, respectively. Further, the area in the third and sixth rows in the second and third columns from the left is a fragment of the circuit to be tested. This area is a trace that the original circuit to be tested has been duplicated and the test has been completed.
[0210]
According to the fifth embodiment, test points scattered on a two-dimensional plane can be efficiently tested.
[0211]
Further, according to the fifth embodiment, as described above, the same test circuit is used, the number of times of duplication is increased, and different test target circuits are handled at once (duplicated and tested). Therefore, since the test circuits to be prepared can be reduced as a whole test, the test preparation work is reduced.
[0212]
Furthermore, in the fifth embodiment, when a test is executed, it is possible to reduce the number of times required to program a test target circuit to be handled separately from the outside. This reduction is replaced by an increase in the internal high-speed replication count. Therefore, the test time is also shortened.
[0213]
It should be noted that the several embodiments described above can be used in various combinations. Various forms are conceivable depending on the combination of these embodiments. However, if the above embodiments are combined, the test time is synergistically shortened.
[0214]
For example, by duplicating only the test target circuit T and duplicating the test circuit so that a part of the test circuit overlaps, the test target circuit is duplicated and the place where the test target circuit is tested can be set in the vertical and horizontal directions. It can be increased two-dimensionally and the coverage of the test can be improved at once.
[0215]
Further, as described in another embodiment, the above test circuit duplication and the duplication of only the test target circuit T are combined, and several different test target circuits are collectively handled as the test target circuit. In other words, if three are combined at a time, the advantages of the three embodiments can be exhibited synergistically. That is, not only different test target circuits but also different test target circuits can be individually viewed one by one, and the test can be executed without fail in all areas of the two-dimensional plane.
[0216]
That is, in a test circuit comprising a test target circuit and a test execution control unit that gives a test pattern to the test target circuit, the test execution control unit duplicates the test target circuit and the test execution control unit, In addition, the test target circuit has a copy destination that overlaps with a part of the test target circuit that has already been tested. In this case, the test target circuit includes a plurality of different test target circuits. Yes, one test execution control unit may repeatedly execute duplication and testing for the plurality of different test target circuits.
[0217]
In addition, as a reference of the present invention, “Hideyuki Tsuboi, Hidefumi Kobayashi, Tsunemichi Shiozawa, Koichi Himi, Akira Nagoya:“ Examination of test method in autonomously reconfigurable hardware, ”IEICE technical report, VLD2000-80, ICD2000-137, FTS2000-45, pp.65-70, Nov.2000 ".
[0218]
[Modification of the first embodiment]
FIG. 34 is a diagram showing a modification of the first embodiment.
[0219]
This modification is an example in which the position of the test circuit TC1 provided in the reconfigurable circuit RCC is changed. FIG. 34 (1) is an example in which a test circuit TC1 is provided above the reconfigurable circuit RCC, and FIG. 34 (2) is an example in which the test circuit TC1 is provided at the center of the reconfigurable circuit RCC. FIG. 34 (3) is an example in which a test circuit TC1 is provided below the reconfigurable circuit RCC.
[0220]
FIG. 35 is a diagram showing another modification of the first embodiment.
[0221]
This modification is an example in which the position of the test target circuit in the test circuit TC1 is changed. FIG. 35 (1) is an example in which a test target circuit 201a is provided in the lower right part of the test circuit TCa, and FIG. 35 (2) is an example in which the test target circuit 201b is provided in the upper right part of the test circuit TCb. FIG. 35 (3) is an example in which a test target circuit 201c is provided in the lower left part of the test circuit TCc, and FIG. 35 (4) is a test target circuit 201e in the upper left part of the test circuit TCe. Is an example provided.
[0222]
That is, another modified example of the first embodiment is a test circuit that tests the test target circuit in a state where the test target circuit is rotated 90 degrees in the test circuit.
[0223]
In another embodiment of the first embodiment, a test pattern is supplied from the test execution control unit to the test target circuit, and the test pattern is output via a logic circuit in the test target circuit. The test circuit includes a circuit that compares the measured value with a predetermined expected value and outputs the comparison result.
[0224]
【The invention's effect】
According to the present invention, since the homogeneous structure is duplicated and tested by duplicating the test circuit itself, even if the whole part to be tested is large, it is possible to cope with the same technique. The test target circuit in this test can be held down to a small circuit scale, so that the test preparation is easy and the test itself is simple, and the input path from the input terminal to the test target circuit is achieved through the input path. There is no need to input a test pattern, and in addition, there is no need to reset the output path for carrying test result data to the output terminal by a program or the like every time the test is performed. It can be executed, and there is an effect that overhead is unnecessary.
[Brief description of the drawings]
FIG. 1 is a diagram showing the structure of a PCA as an example of a reconfigurable logic circuit to be tested by a test circuit TC according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a relationship between an object and a message in PCA.
FIG. 3 is a diagram illustrating a logic circuit realized by writing data as a memory in an LUT on a variable unit (PP) in the embodiment.
FIG. 4 is an explanatory diagram of an operation of duplicating a second test circuit TC2 after testing the first test circuit TC1 of the test circuits TC according to an embodiment of the present invention;
FIG. 5 is a flowchart showing a test operation in the embodiment.
FIG. 6 is a diagram showing a state in which a test circuit TC2 is duplicated next to a test circuit TC1 in a range (for example, on a PCA system) on a reconfigurable logic circuit RCC in the embodiment.
FIG. 7 is a diagram showing an initial circuit after programming a logic circuit (test circuit TC1) in the embodiment.
8 is a diagram simply showing the same state as shown in FIG. 7. FIG.
FIG. 9 is a diagram showing a built-in part (BP) at the time of testing in the embodiment.
FIG. 10 is a diagram showing a replication command output to the first test circuit TC1 in the embodiment.
FIG. 11 is a diagram showing a built-in part (BP) being duplicated in the above embodiment, and a diagram showing a state where a part near the end of a test target circuit in a test circuit adjacent to the test circuit TC1 is being duplicated; It is.
12 is a diagram showing a variable section (PP) during duplication at the same timing as the mid-duplication timing shown in FIG. 11 in the embodiment.
FIG. 13 is a diagram showing a variable section (PP) in operation after the test circuit TC is replicated once in the embodiment.
14 is an enlarged view showing test circuits TC1 and TC2 shown in FIG.
15 is an enlarged view of test circuits TC1 and TC2 shown in FIG.
FIG. 16 is a diagram illustrating a built-in unit (BP) at the time of a test after the first replication (after the second test circuit TC2 is replicated) in the embodiment.
FIG. 17 is a diagram showing a variable section (PP) after a test is performed a plurality of times in the embodiment.
FIG. 18 is a diagram showing a built-in unit (BP) that has issued a replication command after being tested a plurality of times in the embodiment.
FIG. 19 is a diagram for explaining a test method for a reconfigurable circuit according to a first conventional example.
FIG. 20 is a flowchart showing an operation in the first conventional test method when a reconfigurable circuit is tested.
FIG. 21 is an explanatory diagram of a BIST as a second conventional example.
FIG. 22 is an explanatory diagram of a second embodiment of the present invention.
FIG. 23 is a diagram showing how the duplication and the test are executed by the simulator in the second embodiment.
24 is an enlarged view of FIG. 23. FIG.
FIG. 25 is an explanatory diagram of a third embodiment of the present invention.
FIG. 26 shows a simulation state when only the test target circuit T is duplicated in the vertical direction and the test circuit is duplicated in the horizontal direction so that a part of the duplication destination overlaps the duplication source in the third embodiment. FIG.
FIG. 27 is an enlarged view of FIG. 26;
FIG. 28 is an explanatory diagram of a fourth embodiment of the present invention.
FIG. 29 is a diagram illustrating a state on a simulator when different types of test target circuits are handled in the fourth embodiment and tested together at once.
30 is an enlarged view of FIG. 29. FIG.
FIG. 31 is an explanatory diagram of a fifth embodiment of the present invention.
FIG. 32 is a diagram showing a state in which a simulation operation is performed in the fifth embodiment.
33 is an enlarged view of FIG. 32. FIG.
FIG. 34 is a diagram showing a modification of the first embodiment.
FIG. 35 is a diagram showing another modification of the first embodiment.
[Explanation of symbols]
RCC ... reconfigurable circuit,
TC ... Test circuit,
TC1 ... The first test circuit,
TC2 ... The second test circuit,
TCn: nth test circuit,
101, 102 to 10n ... test execution control unit,
201, 202 to 20n: circuit to be tested,
PP ... variable part,
BP ... Built-in part,
M ... memory,
F: Filter circuit,
T, T1 to T5, Ta to Te: Test target circuit.

Claims (13)

In a test circuit comprising a test target circuit and a test execution control unit for giving a test pattern to the test target circuit,
The test execution control unit includes means for replicating the test target circuit and the test execution control unit. In claim 1,
The test circuit, wherein the duplicated test execution control unit has means for starting up the duplicated test execution control unit. In claim 1,
A test circuit comprising means for providing an output path for outputting test result data from the circuit under test to a predetermined output terminal. In claim 1,
A test circuit, wherein the test circuit is provided in any one of an upper part, a middle part, and a lower part of a reconfigurable circuit provided with the test circuit. In claim 1,
A test circuit for testing the test target circuit in a state in which the test target circuit is rotated 90 degrees in the test circuit. In claim 1,
A test pattern is supplied from the test execution control unit to the test target circuit, and the value output by the test pattern via the logic circuit in the test target circuit is compared with a predetermined expected value, and this comparison is performed. A test circuit comprising a circuit for outputting a result. In a test circuit comprising a test target circuit and a test execution control unit for giving a test pattern to the test target circuit,
The test execution control unit duplicates the test target circuit and the test execution control unit,
A test circuit comprising means for copying so that a part of the copy destination of the test circuit overlaps the copy source of the test circuit. In claim 7,
A part of the duplication destination of the overlapping test circuit is the test execution control unit in the duplication destination of the test circuit. In a test circuit comprising a test target circuit and a test execution control unit for giving a test pattern to the test target circuit,
The test execution control unit duplicates the test target circuit and the test execution control unit,
A test circuit comprising means for duplicating only the circuit under test. In claim 9,
A test circuit comprising means for copying only the test target circuit and copying so that a part of the copy destination of the test circuit overlaps the copy source of the test circuit. In any one of Claims 7-10,
The test target circuit is a plurality of different test target circuits, and one test execution control unit repeatedly performs duplication and testing on the plurality of different test target circuits. Test circuit. In a test circuit comprising a test target circuit and a test execution control unit for giving a test pattern to the test target circuit,
The test execution control unit duplicates the test target circuit and the test execution control unit, and duplicates the test target circuit so that the test destination circuit overlaps a part of the test target circuit that has already been tested. A test circuit comprising means. In claim 12,
The test target circuit is a plurality of different test target circuits, and one test execution control unit repeatedly performs duplication and testing on the plurality of different test target circuits. Test circuit.

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