JPH10222389A - Whole reconstitution system fault tolerant information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fault tolerant information processing system easy to satisfy timing restriction without making circuit scale large. SOLUTION: FPGA(field programmable gate array) 10 which can reconstitute a whole circuit is used as a redundant circuit. A logic circuit constituted of plural modules is constituted on FPGA 10. A fault detection circuit for oneself is incorporated in every module. FPGA 10 outputs two types of signals (fault detection signal and a fault detection module identification signal) to a control circuit part 22. The control circuit part 22 loads/stores various data with a storage part 24, generates layout data on the logic circuit, which is to be constituted on FPGA 10, based on the values of the two types of signals from FPGA 10 and data loaded from the storage part 24 and outputs layout data to FPGA 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault-tolerant information processing system that performs information processing without causing a failure in the entire system even if a fault occurs in a part of the system.

[0002]

2. Description of the Related Art As is well known, a fault-tolerant information processing system comprises a redundant circuit comprising a plurality of modules and a redundant circuit controller for controlling the circuit. When detecting a fault, the redundant circuit controller avoids the fault by one of the following two methods. One such method is referred to as a "fault mask method", in which the output of a module in which a fault is detected is masked. Another method is called a “system reconfiguration method”, in which a module in which a fault is detected is replaced with a spare module.

As a fault mask method, NMR is used.
(N-Modular Redundancy) method is known. Part 1
One is, for example, disclosed in JP-A-64-39699 (hereinafter referred to as
(Referred to as prior art). This prior art,
A semiconductor memory device having input ports for addresses, input data, and write / read signals, and having output ports for output data is disclosed. This semiconductor memory device includes, as an internal module, three or more odd-numbered memory cells selected by the same address, and a logic circuit that determines a majority of output data of the odd-numbered memory cells. In a semiconductor memory device having such a configuration, at the time of writing, the same data is written to three or more odd-numbered memory cells selected by the same address. At the time of reading, the output data of the odd number of memory cells selected by the same address are determined by a logic circuit by majority, and the data after the majority is output from the output data port.

On the other hand, the conventional system reconfiguration method is also called a "partial reconfiguration method" because only a module in which a fault is detected is replaced with a spare module. The partial reconfiguration method is classified into two types, a dedicated spare type that prepares a dedicated spare module corresponding to each module, and a general purpose spare type that prepares a general purpose spare module that can be replaced with a plurality of different modules.

[0005]

SUMMARY OF THE INVENTION The conventional NMR described above
The method has a drawback that the circuit scale becomes large because three or more identical modules are required. In addition, the dedicated spare partial reconstruction method has a disadvantage that the circuit scale becomes large because two or more identical preliminary reconstruction methods are required. Furthermore, in the general-purpose spare type partial reconfiguration method, after the module is replaced, the length of the signal lines connected to the module before the replacement generally becomes longer, the delay time of those signal lines increases, and the entire circuit becomes There is a disadvantage that it is difficult to satisfy timing constraints.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a fault tolerant information processing system capable of solving both the problem of increasing the circuit scale and making it difficult to satisfy timing constraints. Is to provide.

[0007]

According to the present invention, the above-mentioned problem is solved by using an entire reconstruction method. The whole reconfiguration method is a kind of the system reconfiguration method. As described above, in the partial reconfiguration method, only a module in which a fault is detected is replaced with a spare module, that is, only a part of the circuit is reconfigured. On the other hand, in the whole reconfiguration method, a circuit is configured on a device capable of reconfiguring the entire circuit including a module in which no fault is detected (hereinafter, referred to as a “reconfigurable device”). If a fault is detected, the entire circuit is reconfigured avoiding the portion where the fault has occurred.

Here, "reconfiguration" refers to reconfiguring a circuit by changing the coupling pattern of components. Also, as the “reconfigurable device”, FPG
A (Field Programmable Gate Array) or FPLA (Fi
eld Programmable Logic Array) can be used. FPG
A is a semi-custom integrated circuit (IC) that can be programmed by a user at hand and that can realize about 2,000 to tens of thousands of logic gates. The basic structure is such that programmable logic modules are regularly arranged and a wiring area is prepared therebetween, and each logic module and the wiring area are programmed to realize a desired logic. FPLA
Also, those that have not been individually programmed at the manufacturing stage are individualized at the site of use. Anyway, the “reconfigurable device” may be any device that can be individualized (programmed) by the user.

That is, according to the present invention, in a fault-tolerant information processing system comprising a redundant circuit composed of a plurality of modules and a controller for controlling the redundant circuit, the entire circuit is used as the redundant circuit by a user. Uses a reconfigurable device that can be reconfigured, thereby providing a fault-tolerant information processing system with an overall reconfiguration method.

By adopting such an overall reconfiguration method, the circuit scale does not increase, and the layout of the module can be flexibly changed, so that the timing constraint can be easily satisfied. Table 1 below shows the fault mask method and the partial reconstruction method (dedicated spare type,
The circuit scale and the timing constraint satisfaction between the general-purpose backup type) and the overall reconstruction method according to the present invention are shown.

[0011]

[Table 1]

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an entire reconfiguration type fault tolerant information processing system according to an embodiment of the present invention.

The illustrated fault-tolerant information processing system comprises an FPGA 10 and an FPGA controller 20.
It is composed of Also, the FTP controller 20
Is composed of a control circuit unit 22 and a storage unit 24. F
The PGA 10 corresponds to a redundant circuit, and the FTP controller 20 corresponds to a redundant circuit controller.

A logic circuit (not shown) composed of a plurality of modules (not shown) is formed on the FPGA 10.
Each module incorporates a fault detection circuit (not shown) for itself. The FPGA 10 outputs two types of signals generated by combining the output signals from the fault detection circuits, that is, a fault detection signal and a fault detection module identification signal to the control circuit unit 22.
Output to Here, the “fault detection signal” is a signal indicating that a certain module has detected a fault, and the “fault detection module identification signal” is a signal for identifying a module that has detected a fault.

The control circuit 22 stores various data in the storage 2
In addition to the load / store between the two, the layout data of the logic circuit to be configured on the FPGA 10 is created based on the values of the two types of signals from the FPGA 10 and the data loaded from the storage unit 23. The layout data is output to the FPGA 10.

The storage unit 24 stores the following four types of data: a net list, a timing constraint list, an available element list, and an element-to-module correspondence list.

Next, with reference to FIG. 2, a specific operation of each part constituting the fault-tolerant information processing system according to the present embodiment will be described focusing on the control circuit unit 22. Here, it is assumed that data of the net list, the timing constraint list, and the usable element list (initial state: all elements are usable) are stored in the storage unit 24 in advance. The active value of the fault detection signal is set to 1 (initial value: 0).

First, the control circuit unit 22 loads each data of the net list, the timing constraint list, and the usable element list from the storage unit 24 (step S1). The control circuit unit 22 performs an FPEG based on the data.
It is determined whether or not a net list can be formed on the device 10 (step S2). If the net list cannot be formed (No in step S2), a non-configurable flag (not shown) in the control circuit unit 22 (active value) : 1, the initial value: 0) is changed to the active value (step S3), and the operation is terminated. On the other hand, if the configuration is possible (Yes in step S2),
The control circuit unit 22 performs the following operation without changing the value of the non-configurable flag.

The control circuit unit 22 creates the layout data of the circuit configured on the FPEG 10 based on the data of the net list, the timing constraint list, and the usable element list, and simultaneously creates the element-to-module correspondence list. It is created (step S4). Here, "element →
The "module correspondence list" describes which module each element is used (/ not used) to constitute. Then, the control circuit unit 22 stores the element-to-module correspondence list in the storage unit 24 (Step S5).

Subsequently, the control circuit unit 22 transmits the layout data created in step S4 to the FPGA 10
(Step S6). Thereby, the FPGA 1
0 forms a circuit according to the same layout data. The control circuit unit 22 checks the value of the fault detection signal (step S7), and the value changes to an active value (that is, a fault is detected in the FPGA 10).
In the case, the FPGA
It is checked which module in 10 has a fault (step S8).

The control circuit unit 22 reads the element from the storage unit 24
The module correspondence list is loaded (step S9), and a group of elements constituting the fault occurrence module is listed (step S10).

The control circuit unit 22 loads the available element list from the storage unit 243 (step S11), deletes the element group listed in step S10 from the list (step S12), and then deletes the list. Storage unit 14
(Step S13).

Thereafter, the flow returns to step S1, and the above operation is repeated.

As described above, in this embodiment, since the FPGA 10 is used as a redundant circuit, it is possible to easily satisfy the timing constraint without increasing the circuit scale.

The present invention is not limited to the above embodiment, and it goes without saying that various modifications can be made without departing from the spirit of the present invention. For example, in the above embodiment, the FPGA is used as the redundant circuit, but it is a matter of course that another reconfigurable device such as FPLA may be used.

[0027]

As described above, the present invention uses a device capable of reconfiguring the entire circuit as a redundant circuit, so that the circuit scale is not increased, and
There is an advantage that timing constraints can be easily satisfied.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a whole reconfiguration fault tolerant information processing system according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of a control circuit unit in FIG. 1;

[Explanation of symbols]

 Reference Signs List 10 FPGA 20 FPGA controller 22 Control circuit unit 24 Storage unit

Claims (3)

[Claims] In a fault-tolerant information processing system including a redundant circuit including a plurality of modules and a controller that controls the redundant circuit, a user may reconfigure the entire circuit as the redundant circuit. An entirely reconfigurable fault-tolerant information processing system using a reconfigurable device. 2. The fully reconfigurable fault tolerant information processing system according to claim 1, wherein the reconfigurable device is an FPGA. 3. The controller includes a control circuit unit and a storage unit. Each module has a built-in fault detection circuit. The reconfigurable device includes a fault detection signal and a fault detection signal. A module identification signal is output to the control circuit unit, and the control circuit unit loads / stores various data between the storage unit and the fault detection signal from the reconfigurable device. Creating layout data of a logic circuit to be configured on the reconfigurable device based on the value of the fault detection module identification signal and the data loaded from the storage unit;
The system of claim 1, wherein data is output to the reconfigurable device.