JP2000111618A - Bist circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the occupying area of a wiring area of a BIST(built-in self test) circuit. SOLUTION: A BIST circuit is divided into a BIST sub-circuit 1, a data input circuit 4 with every memory 2A, 2B, 2C and a data output circuit 5. The data input circuit 4 generates test bit data 16, 17 by the bit number per one word of the memory 2A from respresentative one bit data 13 from the BIST sub-circuit 1 to be written in the memory 2A. The data output circuit 5 generates test bit data 18, 19 read out of the memory 2A and degeneracy one bit data 15 showing a difference from representative one bit data 14. The BIST sub-circuit 1 judges normality and abnormality of the memory 2A by the degeneracy one bit data 15 and the representative one bit data 14 read out of the memory 2A. The data input circuit 4 and the data output circuit 5 are arranged adjacently to the memory 2A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a plurality of memories having different matrix configurations of a memory array.
BIST (Bu) for a plurality of circuits under test having different configurations
lt-in Self Test) circuit.

[0002]

2. Description of the Related Art In recent years, as the size of LSIs has increased, the number and capacity of memories mounted on one LSI have been increasing. In addition, the memory matrix configuration, that is, the number of words and the number of bits per word, have been increasing. However, it is often the case that different memories are mounted. In order to test such an LSI, there is a problem that a test pattern length and a test terminal are increased.
BIST circuits that can judge pass / fail are widely used. However, if the area occupied by the BIST circuit and the test signal wiring of the BIST circuit increases in proportion to the increase in the number and the capacity of the mounted memories, the significance of adopting the BIST method is diminished.

FIG. 6 shows a test method by BIST for a memory described in Japanese Patent Application Laid-Open No. 6-194421. In short, the BIST system is used for large-scale semiconductor integration including three memories 12A, 12B, and 12C having different matrix configurations, in a BIST circuit 100A, 100B, and 100C corresponding to each memory on a one-to-one basis.
And a test is performed while transmitting and receiving the data input / output signal group 10, the address signal group 20, and the control signal group 21 to and from each memory. But,
In this case, the BIST circuits 100A, 100B and 100
The area occupied by C and the signal groups 10, 20, 21 increases.

The technique described in the above publication proposes a test method based on BIST shown in FIG. 7 to solve this problem. This BIST system is a 32 bit × 4K word memory 12A and a 16 bit × 16K word memory 1A.
Only one BIST circuit 100 is provided and shared with the memory 12C of 2B and 8 bits × 1K words, thereby reducing the occupied area of the BIST circuit. Between the BIST circuit 100 and the memories 12A, 12B and 12C, the data input signal group 1
1. A data output signal group 12, an address signal group 20, and a control signal group 21 are transmitted and received. These signal groups have a maximum bit number of 32 bits and a maximum word number so as to cover all memories. 16K words are required. The memory 12
Selection of A, 12B and 12C is performed by the select circuit 3.

[0005]

However, in the conventional BIST system shown in FIG. 7, since it is difficult to arrange the BIST circuit adjacent to all the memories, the signal between the memory and the memory that cannot be arranged adjacent to each other is difficult. The wiring length becomes longer,
Further, since the number of signal lines is large, there is a problem that the area occupied by the wiring region of the test signal lines increases. The present invention
The purpose of the present invention is to solve the above-mentioned problems.
An object of the present invention is to provide a BIST circuit that reduces the area occupied by both the ST circuit and the test signal line. It is also conceivable to perform a test using a bus used during normal operation of the memory, but this would hinder high-speed operation due to the wiring load capacity of the bus.

[0006]

SUMMARY OF THE INVENTION First BIST of the present invention
The circuit has a BIS for a plurality of circuits to be tested having different configurations.
A T circuit, which generates test data according to the configuration and transmits / receives the test data to / from the test target circuit, and an individual circuit which degenerates test data common to all the test target circuits. And a common circuit section for transmitting and receiving. Further, a second BIST circuit of the present invention is a BIST circuit for a plurality of memories having different matrix configurations of a memory array, and generates test bit data according to the matrix configuration, and transmits data to and from the memory for each memory. The input / output circuit is divided into a BIST sub-circuit for degenerating test bit data common to all of the input / output circuits and transmitting / receiving the data to / from the data input / output circuit. Further, the third BIST circuit of the present invention is a BIST circuit for a plurality of memories having different numbers of bits per word line of a memory array, wherein the bit including the representative 1-bit data is inputted from the representative 1-bit data. A data input circuit for each memory for generating and writing a number of test bit data to the memory; and a degeneration 1 indicating the difference between all the bits of the test bit data read from the memory with respect to the written representative 1-bit data. A data output circuit for each memory for outputting bit data, and representative 1-bit data output to all of the data input circuits, and the representative 1-bit data read from the memory and the degeneration from all of the data output circuits. And a BIST sub-circuit for inputting 1-bit data. Further, the semiconductor integrated circuit of the present invention generates a plurality of memories having different numbers of bits per word line of a memory array, and generates test bit data of the number of bits including the representative 1-bit data from the input representative 1-bit data. A data input circuit for each memory to be written to the memory; and a memory for outputting degenerated 1-bit data indicating all bits of test bit data read from the memory with respect to the written representative 1-bit data. And a BI which outputs representative 1-bit data to all of the data input circuits and inputs the representative 1-bit data read from the memory and the degenerated 1-bit data from all of the data output circuits.
The ST sub-circuit is mounted. According to the present invention, a BIST circuit is provided with an individual circuit unit for generating test data corresponding to the configuration of a circuit to be inspected and transmitting / receiving the data to / from the inspected circuit, Since the individual circuit sections can be arranged adjacent to the section to be inspected, the length of a large number of signal lines therebetween can be shortened. Further, since the test data transmitted and received between the common circuit unit and the individual circuit unit is degenerated, the number of relatively long signal lines therebetween can be reduced. Therefore, according to the present invention, not only the occupied circuit of the BIST circuit but also the occupied area of the signal line can be reduced.

[0007]

Next, an embodiment of the present invention will be described. As shown in FIG. 1, the BIST circuit of the present invention tests a memory 2A of 32 bits × 4K words, a memory 2B of 16 bits × 16K words, and a memory 2C of 8 bits × 1K words. BIST sub-circuit 1 mounted on the same LSI as the memory
And three data input circuits 4 and data output circuits 5 corresponding to the memories 2A, 2B and 2C on a one-to-one basis. Since the data input circuit 4 and the data output circuit 5 are arranged adjacent to the memories 2A, 2B, 2C, the signal lines of the test bit data 16, 17 therebetween are short. Although the BIST sub-circuit 1 is relatively far from the data input circuit 4 and the data output circuit 5, the number of representative 1-bit 13 and 14 and degenerate 1-bit data signal lines are small. The BIST sub-circuit 1 outputs the representative 1-bit data to the three data input circuits 4, receives the representative 1-bit data and the degenerated 1-bit data from the three data output circuits 5, and receives the three memories 2A, 2
B, 2C, and an address signal 20 and a control signal group 21 are exchanged. This exchange is performed via the bus 30,
The select circuit 3 outputs an enable signal to only one of the three memories 2A, 2B, and 2C in response to the select signal to activate the memory. The data input circuit 4 is provided for each of the memories 2A, 2B, and 2C, and generates the positive-phase test bit data 16 and the negative-phase test bit data 17 from the representative 1-bit data 13 input from the BIST sub-circuit 1. Write to memory. The test bit data 16 includes the representative 1-bit data 13. The total number of bits of the test bit data 16 and 17 is equal to the number of bits per word of the corresponding memory. Therefore, the memory 2A has 32 bits, the memory 2B has 16 bits, and the memory 2C has 8 bits.
The data output circuit 5 is also provided for each of the memories 2A, 2B and 2C, and reads out the test bit data 18 corresponding to the test bit data 16 and the test bit data 19 corresponding to the test bit data 17 from the corresponding memories. Then, the representative 1-bit data 1 in the test bit data 18
The degenerate 1-bit data 15 is generated from the remaining portion except the representative 1-bit data 14 corresponding to 3 and the test bit data 19 and output to the BIST sub-circuit 1. The degenerated 1-bit data 15 indicates the difference between the representative 1-bit data 14 and the test bit data 18 and 19. BIS
Upon receiving the representative 1-bit data 14, the T sub-circuit 1 compares the received data with the representative 1-bit data 13,
Due to the difference, the memories 2A, 2B and 2C can be tested. Also, when the degenerated 1-bit data 15 is received, the memory 2A, 2B, 2C can be tested by knowing whether it is different from the representative 1-bit data 14 depending on whether it is "1" or "0".

Next, the details of the data input circuit 4 and the data output circuit 5 will be described in detail with reference to FIGS. The data input circuit 4 shown in FIG. 2 is for the memory 2C that generates test bit data 16 and 17 of 8 bits from the representative 1-bit data 13. Test bit data 16
Are four bits of positive phase obtained by dividing the representative 1-bit data 13 into four, and are supplied to even-numbered bit lines of the memory.
The test bit data 17 is 4 bits of opposite phase obtained by inverting the representative 1-bit data 13 by the inverter 41 and branching into four, and is supplied to the odd-numbered bit lines of the memory 2C. Note that for the memory 2B, the representative 1-bit data may be divided into 16 branches for each of the normal phase and the negative phase. The data input circuit 5 shown in FIG. 3 is also for the memory 2C, outputs the representative 1-bit data 14 corresponding to the representative 1-bit data 13, and outputs the test bit data 18 corresponding to the test bit data 16 and the test bit data 18. From the test bit data 19 corresponding to the data 17, 1-bit degenerated 1-bit data 15 is generated and output. The data input circuit 5 includes an inverter 42 for inverting the representative 1-bit data 14 and a 2-bit corresponding to the test bit data 18.
Two NAND circuits 44 and 45 and a NOR circuit 46;
Two NAND circuits 4 corresponding to test bit data 19
7, 48 and a NOR circuit 49, a NAND circuit 44,
And an OR circuit 43 which performs a logical OR operation of the outputs of the 47 circuits. The operation is as follows.

If the representative 1-bit data 14 is "1" and the memory 2C is normal, the test bit data 1
Since 8 is all “1”, the output of the NAND circuit 45 is “0” and the output of the NAND circuit 44 is “1”. In this case, the output of the NOR circuit 46 is irrelevant. Also,
If the memory 2C is normal, the test bit data 19 is all “0”, and the output of the NOR circuit 49 is “1” NA
The output of the ND circuit 47 becomes "1". In this case, NAN
The output of D circuit 48 is irrelevant. Therefore, the degenerated 1-bit data 15 of "0" is output from the OR circuit 43, which proves that the memory 2C is normal. However, there is an abnormality in the memory 2C, and the test bit data 18
Becomes "0", the NAND circuit 45
Is "1" and the output of the NOR circuit 46 is "0", so that the output of the NAND circuit 44 is "0". When any of the test bit data 19 becomes “1”, the output of the NOR circuit 49 becomes “0” and the NAND circuit 48 becomes
Is "1", the output of the NAND circuit 47 is "0". Therefore, from the OR circuit 43,
The degenerated 1-bit data 15 of “1” is output,
It will tell C's abnormality. Representative 1-bit data 14
Is "0", the normality and abnormality of the memory 2C can be similarly confirmed based on whether the degenerate 1-bit data 15 is "0" or "1". In this case, however, N in the case where the representative 1-bit data 14 is “1”
The NOR circuit 46 performs the function of the AND circuit 45,
The function of the circuit 49 is performed by the NAND circuit 48.

Next, FIG. 1 configured as described above will be described.
The operation of the BIST circuit will be described. When the select signal 1 is set to "1" and the select signal 2 is set to "0" after the test mode is set and the enable terminal (not shown) of the memory 2C is set to "0", the memory 2C is selected and operated. become. An address signal is transmitted from the BIST sub-circuit 1 in an address signal group 20 and a control signal group 21
Are valid only in the memory 2C. When the control signal group 21 specifies write, the test bit data 16 and 17 generated by the data input circuit 4 from the representative 1-bit data 13 are written to the memory. Subsequently, when the control signal group 21 designates reading, the test bit data 18 and 19 are read from the memory 2C to the data output circuit 5, and the representative 1-bit data 14 and the data output circuit 5 are tested by the test bit data 18 and 19. And the degenerated 1-bit data 15 generated from BIST are output to the BIST sub-circuit 1. The BIST sub-circuit 1 includes the representative 1-bit data 14 and the representative 1-bit data 1
3 and the degenerate 1-bit data 15 is "1".
It is determined whether the memory 2C is normal or abnormal depending on whether it is "0" or "0". Similarly, the memory 2B is tested by setting the select signal 1 to "0" and the select signal 2 to "1", and the memory 2A is tested by setting the select signal 1 to "1".

FIG. 4 shows another embodiment of the BIST circuit of the present invention. In the present embodiment, all the data output circuits 5 individually output the degenerated 1-bit data 15 to the BIST sub-circuit 1 via the bus 30 in the embodiment of FIG. 5 is provided with a mismatch holding circuit 6 that collectively outputs the degenerated 1-bit data 15 from the BIST 5 to the BIST sub-circuit 1. This eliminates the need to guide each of the degenerate 1-bit data 15 to the BIST sub-circuit 1 by a test signal line, so that the test signal wiring area can be further reduced as compared with the embodiment of FIG.

FIG. 5 shows details of the mismatch holding circuit 6,
It comprises a flip-flop 50 and an OR circuit 51. O
The R circuit 51 performs a logical OR operation on the degenerated 1-bit data 15 from the three data output circuits 5 and outputs the result to the D-type flip-flop 50. Therefore, if the output of the D-type flip-flop 50 is “1”, it is determined that there is an abnormality in the memory. The output of the D-type flip-flop 50 is observed at the test terminal 60.

In the embodiment shown in FIGS. 1 and 4,
The selector circuit 3 may be omitted. In that case, 3
The two memories 2A, 2B, 2C can be tested simultaneously. However, it is needless to say that all of the representative 1-bit data 14 from the memories 2A, 2B, and 2C and the degenerated 1-bit data from the three data output circuits 5 must be simultaneously output to the BIST sub-circuit 1.

As shown in FIG. 2, the test bit data is generated so that "0" and "1" are alternately and alternately applied to the bit lines. However, the present invention is not limited to this. It may be all “0” or all “1”.

[0015]

As described above, according to the present invention, the BI
The ST circuit is divided into an individual circuit unit that exchanges test data depending on the configuration of the circuit under test and a BIST sub-circuit that exchanges test data common to the individual circuit unit, and the individual circuit unit is adjacent to the circuit under inspection. In addition to the arrangement, since the degenerated test data is transmitted and received between the BIST sub-circuit and the individual circuit unit, there is an effect that the occupied area of the BIST circuit and the test wiring area can be reduced.

For example, in the embodiment shown in FIG.
According to the prior art, 64 data input / output lines were required in accordance with the memory 2A. On the other hand, according to the present invention, only three data input / output lines are required, and 61 lines can be reduced. Further, in an example in which three memories 2A, 2B, and 2C are tested at the same time without providing the selector circuit 3, according to the prior art, 32 data input lines and 56 data output lines required a total of 88 lines. In contrast, in the present invention, the number of data input lines is one and the number of data output lines is six, for a total of seven, a reduction of 81 lines. The reduced wiring area is shown in FIGS.
, Is indicated by reference numeral 31.

In recent years, since the scale of LSIs has been increasing, the effect of an increase in the wiring area due to an increase in the number of test signal lines has a great effect. In addition, since the wiring around the memory is congested from the beginning, the reduction in the number of test signal lines has the effect of facilitating the layout design of the LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a BIST circuit of the present invention.

FIG. 2 is a detailed diagram of a data input circuit in the embodiment shown in FIG.

FIG. 3 is a detailed diagram of a data output circuit in the embodiment shown in FIG. 1;

FIG. 4 is a block diagram showing another embodiment of the BIST circuit of the present invention.

FIG. 5 is a detailed diagram of a mismatch holding circuit in the embodiment shown in FIG. 4;

FIG. 6 is a block diagram showing an example of a conventional technique.

FIG. 7 is a block diagram showing another example of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... BIST sub-circuit 2A, 2B, 2C ... Memory 12A, 12B, 12C ... Memory 3 ... Select circuit 4 ... Data input circuit 5 ... Data output circuit 6 ... Mismatch holding circuit 10 ... Data input / output signal group 11 ... Data input signal Group 12 Data output signal group 13, 14 Representative 1-bit data 15 Reduced 1-bit data 16, 17, 18, 19 Test bit data 20 Address signal group 21 Control signal group 30 Bus 31 Reduced Wiring areas 41, 42 ... Inverters 43, 51 ... OR circuits 44, 45, 47, 48 ... NAND circuits 46, 49 ... NOR circuits 50 ... D-type flip-flops 60 ... Test terminals 100, 100A ... BIST circuits 100B, 100C ... BIST circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA07 AD05 AE07 AE08 AE12 AG02 AG10 AH01 AK19 AL00 5L106 DD03 DD08 GG01 9A001 LL06 LZ06

Claims (8)

[Claims] 1. A BIST circuit for a plurality of circuits under test having different configurations, comprising: an individual circuit section for each circuit under test for generating test data corresponding to the configuration and transmitting and receiving the test data to and from the circuit under test; A BIST circuit characterized in that test data common to all of the units is reduced and divided into an individual circuit and a common circuit unit for transmitting and receiving. 2. A BIST circuit for a plurality of memories having different matrix configurations of a memory array, comprising: a data input / output circuit for each memory for generating and transmitting test bit data corresponding to the matrix configuration to and from the memory; A BIST circuit characterized in that test bit data common to all of the input / output circuits is degenerated and divided into a data input / output circuit and a BIST sub-circuit for transmission / reception. 3. A BIST circuit for a plurality of memories having different numbers of bits per word line in a memory array, wherein test bit data of the number of bits including the representative 1-bit data is generated from input representative 1-bit data. A data input circuit for each memory to be written to the memory;
A data output circuit for each memory for outputting degenerated 1-bit data indicating the difference of all bits of the test bit data read from the memory with respect to the written representative 1-bit data; And a BIST sub-circuit for outputting representative 1-bit data and inputting the representative 1-bit data read from the memory and the degenerated 1-bit data from all of the data output circuits. circuit. 4. The system according to claim 1, wherein, instead of directly inputting said degenerated 1-bit data from all of said data output circuits to said BIST sub-circuit, a result of an OR operation is held and said BIS
4. The BIST circuit according to claim 3, further comprising a mismatch holding circuit for outputting to the T sub-circuit. 5. A circuit for selecting said circuit under test or said memory, said common circuit section and individual circuit section, said BIST, and a data input / output circuit or said BI circuit.
5. The BIST according to claim 1, wherein the ST sub-circuit, the data input circuit and the data output circuit are connected by a bus, and a set of test data transmitted and received between the ST sub-circuit and the data input circuit and the data output circuit. circuit. 6. The data input circuit according to claim 3, wherein the data input circuit generates test bit data having a bit pattern in which a normal phase and a negative phase of the representative 1-bit data are alternately repeated. BIST described in any
circuit. 7. The data output circuit compares the representative 1-bit data read from the memory with all other test bit data corresponding to the representative 1-bit data.
6. The compressed 1-bit data indicating whether any of the test bit data is different from the representative 1-bit data is output.
The BIST circuit according to any one of the above. 8. A plurality of memories having different numbers of bits per word line of a memory array, and test bit data of the number of bits including the representative 1-bit data is generated from the input representative 1-bit data and written into the memory. A data input circuit for each memory, a data output circuit for each memory for outputting degenerated 1-bit data indicating all bits of test bit data read from the memory with respect to the written representative 1-bit data, A BIST sub-circuit that outputs representative 1-bit data to all of the data input circuits and inputs the representative 1-bit data read from the memory and the degenerated 1-bit data from all of the data output circuits. A semiconductor integrated circuit characterized by the above.