JP4795936B2 - Self-diagnostic (BIST) architecture with distributed instruction decoding and generalized instruction protocol - Google Patents

Description

  The present disclosure relates to electronic devices, and more particularly to a built-in self-diagnostic architecture for use in electronic devices.

  Built-in self-test (BIST) units are now commonly incorporated into memory chips and other integrated circuits to test their functionality and reliability. For example, a BIST unit embedded in a particular memory module operates by writing various data patterns to and from the associated memory module to detect any possible memory failure To do. By comparing the written data with the data subsequently returned from the memory module, the BIST unit can determine whether any memory cell in the memory module is defective.

  The integrated BIST unit typically generates various predetermined test patterns and asserts the output signal positively or negatively based on the results of the memory test ( deassert). Various algorithms can be used to detect memory failures. For example, an all zero, all one test pattern, or a “checkerboard” pattern with alternating zeros and ones can be written across the memory cell. Moreover, the data can be written to the cells in any order, such as a continuously increasing or decreasing addressing scheme.

  In this way, the BIST unit typically uses or otherwise incorporates a memory module and follows certain pre-determined algorithms to verify the functionality of on-chip circuit elements. Included in many types of integrated circuits that operate. However, electronic devices generally have more than internal circuit elements consisting of a single chip. In general, an electronic device is composed of a plurality of integrated circuit chips mounted on a circuit board and a plurality of supporting components.

  As the complexity of common computing devices increases, the number of memory chips and other integrated circuits increases. For example, conventional computing devices typically include a plurality of different types of memory modules. The memory modules inside one computing device are random access memory (RAM), read-only memory (ROM), flash memory, dynamic random memory Various combinations of dynamic random access memory (DRAM) and the like can be included. These various types of memory modules often require different test procedures and have different bit densities, access speeds, addressing requirements, access protocols, and other uniqueness. As a result, a typical computing device can have a respective BIST unit for each memory module, and each BIST unit may be specialized to test the associated memory module.

[summary]
Generally speaking, this disclosure is directed to a distributed, systematic self-diagnostic architecture for testing the operation of one or more memory modules. As described, the architecture includes three layers of concepts: a centralized BIST controller, a set of sequencers, and a set of memory interfaces connected to memory modules.

  The BIST controller provides a centralized high-level control for memory module testing. The BIST controller communicates test algorithms centrally stored and maintained in the sequencer for application to the memory module. The BIST controller communicates the algorithm as a generalized set of instructions that conform to the instruction protocol described herein. In addition, the instruction protocol allows the algorithm to be comprehensively defined regardless of any timing requirements, physical configuration, or specific interface characteristics of the memory module. As a result, various test algorithms can be easily defined and centrally maintained for distribution throughout the electronic device as needed. As a result, the common test pattern need not be stored extra in the memory module.

  The sequencer provides a second level concept. The sequencer is distributed within a device block that includes one or more memory modules. In this way, each sequencer is associated with one or more memory modules. The sequencer receives high-level instructions from the BIST controller. In response to the instruction, the sequencer issues a sequence of one or more memory operations to each memory interface to execute the instruction. For example, the sequencer can issue an instruction to continuously access a range of addresses in response to one instruction from the BIST controller. The sequencer reports the result of the test to the BIST controller.

  The sequencer controls the application of operations according to the timing characteristics of each memory module. For example, each of the sequencers controls the application rate of the sequence of operations according to the access rate of the respective memory module. One sequencer can control the application of the test algorithm to multiple memory modules operating on a common clock domain. Therefore, the logic for controlling the application timing and sequencing the test pattern domains is built into the sequencer and does not need to be distributed within the individual memory modules or maintained by the BIST controller. There is no need to

  The third layer, the memory interface, handles specific interface requests for each of the memory modules. Each of the memory interfaces can be designed according to specific signal interface requirements and the physical characteristics of each one memory module. Each memory interface receives memory from the sequencer controlling the memory operation and translates the memory operation, including associated address and data signals, as needed, based on the physical characteristics of the respective memory module. For example, the memory interface can translate the address supplied by the controlling sequencer based on the row and column of the memory module to fill the memory in the row or column direction. As another example, a memory interface may be a specific, such as a checkerboard pattern, or a “striped” row or column where adjacent rows or columns have the opposite pattern. Data can be transformed to create a bit pattern.

  In one embodiment, the system comprises a centralized built-in self-test (BIST) controller that stores an algorithm for testing a plurality of memory modules, wherein the BIST controller is based on an instruction protocol. Store the algorithm as a generalized set of instructions that it conforms to. The system further comprises a plurality of distributed sequencers that interpret the instructions and apply the instructions to the memory module.

  In another embodiment, an apparatus includes instructions defining a BIST algorithm for testing a plurality of distributed memory modules that conform to a generalized instruction protocol and have different timing requirements and physical characteristics. Centralized built-in self-diagnostic (BIST) control means for issuing, and distributed means for decoding instructions and applying the instructions to the memory module according to the timing requirements and physical characteristics of the memory module; It comprises.

  In another embodiment, the method includes issuing an algorithm from a centralized controller and in the form of a generalized instruction that conforms to the instruction protocol to test a plurality of memory modules, and according to the instruction protocol Decoding instructions using a set of distributed sequencers to apply the instructions as a sequence of one or more memory operations.

  The techniques described herein can realize one or more advantages. For example, the present technology allows various test algorithms to be easily defined and centrally maintained in the form of generalized instructions. Generalized instructions can be distributed to sequencers located throughout the electronic device for decoding and application to memory modules. As a result, the common test algorithm need not be stored extra in the memory module.

  Furthermore, the present technology can provide simultaneous application of algorithms to different memory modules, which can reduce overall test time and can be more fully tested for inter-memory effects. Moreover, the distributed, systematic nature of the architecture can allow the technology to be easily applied to existing chip designs.

  The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.

[Detailed description]
FIG. 1 is a block diagram illustrating an example electronic device 2 having a distributed, systematic built-in self-diagnosis (BIST) architecture. In particular, the electronic device 2 includes a built-in self-diagnosis (BIST) controller 4 that provides centralized high-level control for testing of device blocks 6A through 6N (collectively, “device block 6”). Each device block 6 includes a sequencer 8 and a set of one or more memory interfaces 10 and one or more respective memory modules 12.

  In general, the BIST controller 4 provides and communicates test algorithms to the sequencer 8 for application to the device block 6. The BIST controller 4 transmits each of the algorithms to the sequencer 8 as a set of instructions that conform to a comprehensive and flexible instruction protocol. Each instruction specifies a set of parameters and an operational code that define one or more memory operations regardless of the physical characteristics and timing requirements of the memory module 12. In this way, the instruction protocol allows various test algorithms to be easily defined and distributed throughout the electronic device 2. Thus, the BIST controller 4 provides centralized control over algorithm maintenance and distribution. As a result, the common test algorithm need not be stored extra in the device block 6.

  The sequencer 8 decodes and executes the test algorithm provided by the BIST controller 4. In particular, the sequencer 8 receives high-level instructions from the BIST controller 4 that defines a complete BIST algorithm. For example, an instruction can define a particular bit pattern to be written over a range of one or more addresses. In response to the instructions, each of the sequencers 8 issues a sequence of one or more memory operations to the respective memory interface 10 to execute the instructions. In addition, the sequencer 8 controls the application of operations according to the timing characteristics of each memory module 12. For example, each of the sequencers 8 controls the application speed of the sequence of operations according to the access speed of the respective memory module 12. A single sequencer 8, eg, sequencer 8A, can control the application of a test algorithm to one or more memory modules, eg, memory module 12A, operating on a common clock domain. The memory modules 12 are grouped and assigned to their respective sequencers 8 based on any of various criteria, such as the clock domain for each of the memory modules and any existing scheme or grouping of memory modules. Can be assigned. Therefore, the logic for controlling the application timing and for sequencing the test patterns for the memory modules 12 operating on the common clock domain can be incorporated within the common sequencer 8. Does not need to be distributed within the individual memory modules.

  The memory interface 10 handles specific interface requests for each of the memory modules 12. For example, each of the memory interfaces 10 can be designed according to a respective physical characteristic of the memory module 12 and specific signal interface requirements. As a result, each of the memory interfaces 10 provides a “wrapper” around the interface around specific interface signals for each respective memory module 12, for example, address signals, data signals, and control signals. Can be seen as. In this way, the BIST architecture of the electronic device 2 comprises a three-tier distributed arrangement including the BIST controller 4, sequencer 8, and memory interface 10.

  The memory module 12 includes random access memory (RAM), read-only memory (ROM), flash memory, dynamic random access memory (dynamic random access memory). memory) (DRAM), SDRAM, RDRAM, DDR-RAM, combinations of these, and others, and the techniques described herein are in this regard Not limited. Moreover, the electronic device 2 can be used for on-board computing systems, computers, servers, personal digital assistants (PDAs), portable computing devices, portable communication devices, digital recording devices, and networks. It may be any device that incorporates a memory module, such as a network appliance, a portable location determination device, and others.

  FIG. 2 is a block diagram illustrating an example embodiment of the BIST controller 4. In the illustrated embodiment, the BIST controller 4 includes an algorithm memory 20 that stores a set of N test algorithms. As described below, each algorithm is defined according to a set of binary instructions. In one embodiment, for example, a complete algorithm can be specified by a set of 32-bit instructions, where the instructions are used to test the functionality of the memory module 12 in the device block 6 ( Define all parameters necessary to perform one or more sequences of memory operations over the address range of FIG.

  The user interface 22 invokes the algorithm controller 26 in response to an external input, such as a control signal from an external test device. Alternatively, the algorithm controller can be called automatically upon powering on the electronic device 2. Once invoked, the algorithm controller 26 provides an algorithm selection signal (ALG_SELECT) to the multiplexer 24 to select one of the algorithms stored within the algorithm memory 20. Once selected, a binary instruction stream comprising the selected algorithm is applied to the device block 6 as instruction data (CMD_DATA).

  The algorithm controller 26 controls the distribution of the algorithm to the device block 6 based on the reception signal (SEQ_ACK) received from each sequencer 8 of the device block. In particular, the algorithm controller 26 sequentially distributes each instruction of the selected algorithm to the plurality of sequencers 8, and when receiving a reception signal from each of the sequencers 8, advances from one instruction to the next instruction. In this way, the algorithm controller 26 ensures that the application of the current instruction to the memory module 12 via the memory interface 10 is completed before each sequencer 8 proceeds to the next instruction. The algorithm controller 26 can be configured programmatically or statically to set the number of device blocks 6 and, in particular, the number of sequencers 8 present inside the electronic device 2. In addition, the algorithm controller 26 is programmatically configured to apply a given algorithm to one, all, or any combination of memory modules 12 that use any combination of device blocks 6. Can do.

  In addition to the algorithms stored in the algorithm memory 20, the user interface 22 can programmably receive the algorithms via external inputs. The user interface 22 receives the multiplexer 24 in a format similar to the stored algorithm format, ie, a sequence of binary commands in which each command defines a test within the entire algorithm. Delivered algorithm In this way, the BIST controller 4 provides a centralized, three-tier first-tier distributed self-diagnostic architecture.

  FIG. 3 is a timing diagram that further illustrates the communication between the BIST controller 4 and the sequencer 8 for one instruction of the generic BIST algorithm. As shown, at time T1, the BIST controller 4 positively asserts a command request (CMD_REQ) interconnect and communicates the current command of the algorithm over the CMD_DATA interconnect.

  Upon receipt and application of the instruction, the sequencer 8 positively asserts the corresponding SEQ_ACK signal. For example, in the illustrated example, each of the sequencers 8 acknowledges the respective signals SEQ_ACK [1], SEQ_ACK [2], SEQ_ACK [N], and SEQ_ACK [0] at times T2, T3, T4, and T5, respectively. Explicitly. In response, the BIST controller 4 de-asserts the command request (CMD_REQ) signal at time T6, and causes the sequencer 8 to negate the respective SEQ_ACK signal. The BIST controller 4 asserts the SEQS_DONE signal positively when all SEQ_ACK signals are asserted negative, allowing the BIST controller 4 to initiate another instruction at time T7.

  FIG. 4 is a block diagram illustrating an example embodiment of a more detailed device block, eg, device block 6A. As shown, the device block 6A includes a sequencer 8A, a set of memory interfaces 10A-10C (collectively, “memory interface 10”), and a set of memory modules 12A-12C (collectively. , “Memory module 12”). As illustrated in FIG. 4, each of the memory interfaces 10 corresponds to a respective memory module 12. The sequencer 8A is programmatically and / or statically set to set characteristics relating to the number of memory interfaces 10 to be controlled, as well as the largest of the memory modules 12, for example the maximum address. Can be configured.

  FIG. 5 is a block diagram illustrating an example embodiment of a more detailed sequencer, eg, sequencer 8A. The sequencer 8A receives high-level instructions from the BIST controller 4 that collectively define the BIST algorithm. As described in detail below, the BIST controller 4 issues instructions in a comprehensive, flexible format, and an instruction is a specific bit to be written over one or more address ranges.・ Patterns can be defined.

  In general, the sequencer 8A receives a generic BIST instruction and controls the application of each instruction as a sequence of one or more memory operations applied to each set of memory modules. In the illustrated embodiment, the sequencer 8A includes a command parser (CMD PARSER) 30 that receives command data (CMD_DATA) from the BIST controller 4. The instruction parser 30 processes the received instruction to identify the specified operation, for example, by identifying the operational code (op-code) specified by the instruction.

  Based on the specified operation, the instruction parser 30 can extract one or more parameters from the instruction and can select one of the corresponding instruction controllers (CMD CONTROLLERs) 34A-34N. In other words, each one of the instruction controllers 34 corresponds to a different instruction that can be specified by CMD_DATA. The instruction parser 30 calls the selected instruction controller 34 and passes parameters extracted from the received instruction. Although illustrated separately, the instruction controller 34 can be integrated and / or integrated into a single functional block having logic to execute each of the supported instructions.

  In response to each instruction, one of the called instruction controllers 34 issues one or more sequences of operations to each memory interface 10. In particular, one of the called instruction controllers 34 in turn drives the appropriate instruction control signal (CMD_CTRL_SIGNALS) to perform each operation in the sequence. As described further below, the instruction control signal performs a read or write operation to invert the signal, as well as a bit for providing the memory address and data to the receiving memory interface 10. Signals for managing the receiving memory interface may be included to invert the row and to do the other.

  In addition, the instruction controller 34 controls the application of operations according to the timing characteristics of each memory module 12. Therefore, the logic for arranging the order of operations related to the memory modules 12 operating on the common clock domain and for controlling the application timing can be incorporated in the common sequencer 8, and the individual memory modules can be incorporated. There is no need to be distributed inside.

  The sequencer 8A receives data from the tested memory module 12 via, for example, signals across MEM [0] _DOUT to MEM [N] _DOUT and returns it to the BIST controller 4 or externally via the multiplexer 37. Data to be returned to the apparatus and a data selection signal 39 are selectively transmitted. In this way, the sequencer 8 enables data analysis to identify any defects.

  In this way, the sequencer 8 allows the BIST controller 4 to centrally manage the storage and issue of algorithms using a comprehensive and flexible instruction format. The sequencer 8 receives a generic BIST instruction according to the instruction protocol and controls the application of the instruction by generating and issuing one or more sequences of memory operations for application to the respective set of memory modules 12. This provides a second layer of a distributed hierarchical self-diagnostic architecture.

  FIG. 6 is a block diagram illustrating an example embodiment of a memory interface 41 that provides a final layer of distributed BIST architecture concepts by handling specific interface requirements for each memory module 12. .

  In the illustrated embodiment, the memory interface 41 includes layers of multiplexers 45, 46 that isolate the memory module 12 from normal functionality when the electronic device 2 is operating in BIST mode. In particular, under normal operating conditions, the BIST enable (BIST_EN) is manifested negatively, eg, as provided by a programmable processor, address signal / control signal (ADDR / CTRL) and data signal (DATA). Are selected by the multiplexers 45 and 46. When the electronic device 2 is operating in the BIST mode, the BIST enable signal is sent to the multiplexer 45, 46 by means of the BIST address signal / control signal (BIST_ADDR / CTRL) and test data provided by the respective higher-level sequencer. Let them choose. In this way, the sequencer controls the multiplexers 45, 46 of the memory interface 41 to selectively isolate each memory module, so that the BIST algorithm is applied to that memory module. enable.

  The memory interface 41 further includes a data generation unit 44 that receives the BIST_DATA signal and default data (DEFAULT_DIN), as provided by the sequencer 8, and includes a control signal (BIST_DATA_GEN_CTRL) provided by the sequencer and the corresponding memory module 12. A converted BIST data signal 49 (BIST_DATA_T) is generated based on certain physical characteristics of More specifically, as will be described in more detail below, the data generation unit 44 generates accurate data (RAM_DIN) applied to the memory input during each operation of the algorithm. The data generation unit 44 is also designated by the sequencer 8A, eg, checkerboard, inverted, etc., based on the physical configuration of each memory module 12, eg, physical row and column configuration. Generate converted BIST data based on the bit pattern.

  For example, the sequencer 8 can request a checkerboard bit pattern that requires the data columns within the memory module to alternate between 1 and 0. However, different memory modules 12 may be arranged in different row and column configurations. As a result, memory cells for a given address may be placed in different rows and columns for memory modules 12 having different row-column configurations. For example, the 256-bit memory module 12 can be arranged as 128 rows and 2 columns, 32 rows x 8 columns, 16 rows x 16 columns, and others. As a result, writing a specific pattern, such as a checkerboard, throughout this matrix requires knowledge of the unique row-column configuration of the memory module. As will be described in more detail below, the data generation unit 44 processes the data provided by the sequencer 8 and, if necessary, ensures that the desired bit pattern is written correctly. Convert the data, for example, invert the data.

  Similarly, the address generation unit 42 generates an address to be applied to the memory module 12 based on the addressing request specified by the sequencer 8A and based on the physical configuration of the memory module rows and columns. . For example, in some BIST tests, the sequencer 8A instructs the memory interface 41 to write BIST data in a row (or column) first manner, ie before proceeding to the next row (or column). Each row (or column) needs to be completely written. Since these requirements are specific to the row and column configuration, the address generation unit 42 is appropriate to move the entire row (or column) the address provided by the sequencer 8A before processing. Convert to

  As a result, the sequencer can initiate operations by sequentially moving through an address space defined by each instruction and limited by the largest memory module associated with the sequencer. Each memory interface, eg, memory interface 41, translates received addresses as needed to apply operations to the appropriate memory cells. For example, with respect to the column first BIST algorithm, the sequencer 8 issues operations to a plurality of addresses in order, while the address generation unit 42 is aligned with the memory cells so as to be along the columns of the memory modules 12. The address received for access is converted by calculation. In this example, the address generation unit 42 is responsive to the memory module 12 in a column-wise fashion from the least significant column to the most important column based on whether the sequencer 8 is increasing or decreasing the address space. Translate addresses to access.

  Comparator 48 determines whether the data read from memory module 12 (RAM_DOUT) is equal to the last data written to that address of the memory module, as expected. If the comparison fails, i.e. when the data read from the memory module 12 is not equal to the previously written data, the comparator 48 will indicate that a memory error has been detected. , The BIST_FAIL signal is clearly indicated.

  In this way, the memory interface 41 processes successive memory operations issued by the higher-level sequencer and is provided by the sequencer as needed based on the specific physical characteristics of the memory module. Data and addresses, thereby providing a third layer of a distributed hierarchical self-diagnostic architecture. As a result, the sequencer can issue operations on complex BIST algorithms without requiring detailed knowledge of the physical characteristics and capacity of each memory module 12.

  FIG. 7 is a block diagram illustrating an example embodiment of the data generation unit 44 (FIG. 6). In the illustrated embodiment, the data generation unit 44 receives a BIST_DATA signal, a default data signal (DEFAULT_DIN) provided by the sequencer 8. In addition, the data generation unit 44 receives a plurality of control signals in the form of BIST_INVERT_BITS, BIST_INVERT_ROWS, LSB_ROW_ADDER, and BIST_WRITE. Based on the received data and these control signals, the data generation unit 44 is converted based on the control signal (BIST_DATA_GEN_CTRL) provided by the sequencer 8 and the specific physical characteristics of the corresponding memory module 12. A BIST data signal 49 (BIST_DATA_T) is generated.

  In particular, the sequencer 8 uses an inverted bit signal (BIST_INVERT_BITS) to specify a data pattern, such as a continuous data pattern, a checkerboard data pattern, a horizontal stripe data pattern, and a vertical stripe data pattern. , Invert row signal (BIST_INVERT_ROWS), and invert column signal (not shown) are positively specified and negatively specified. If neither the inverted bit or the inverted row signal is positively asserted, the BIST_DATA signal passes through the XOR gates 52, 54 without modification. As a result, the data generation unit 44 generates a converted data signal 49 (BIST_DATA_T) to fill the memory module 12 with data instructed from the sequencer 8 without modification.

  If the BIST_INVERT_ROW signal is set, the data generation unit 44 inverts the value each time a row is traversed, as indicated by the least significant (least significant) row address bit (LSB_ROW_ADDR). As a result, the AND gate 50 inverts the value instructed by the sequencer to the XOR gate 52, thereby inverting the value written in the adjacent row. Similar functionality can be provided to invert values when a row is traversed. When the BIST_INVERT_BITS signal is positively asserted, the data generation unit 44 automatically inverts the value indicated by the sequencer. This is useful in inverting values between corresponding cells of different matrices.

  The DEFAULT_DIN field sets a default data value that is applied to the memory module during a read operation to the memory module 12. Multiplexer 56 selects between DEFAULT_DIN data and data generated by XOR gate 54 based on whether a write or read operation is being performed, as indicated by the BIST_WRITE signal.

  FIG. 8 is a block diagram illustrating an example data structure of an instruction issued by the BIST controller 4. In the illustrated embodiment, the instruction 60 includes a sequencer identifier (ID) 62 and a payload 64. As described in more detail below, the sequencer ID 62 identifies the sequencer, for example the sequencer 8A, for which the instruction 60 is to be issued.

  The BIST controller 4 can broadcast instructions to all the sequencers 8 or issue instructions in a unicast manner to a particular one of the sequencers. In particular, the BIST controller 4 sets the sequencer ID 62 to a unique identifier in order for one of the sequencers 8 to send a unicast command to that sequencer. Regarding the broadcast delivery command, the BIST controller 4 sets the sequencer ID 62 to a broadcast delivery identifier such as 0 × 0.

The payload 64 of the instruction 60 carries binary data that defines the instruction itself. In particular, the payload 64 includes an operational code (OP CODE) 66 and a set of parameters 68. In general, the OP CODE 66 specifies a specific function to be executed by the receiving sequencer 8. The following table lists an exemplary set of operational codes.

  In one embodiment, OP CODE 66 and parameter 68 comprise 3 bits and 29 bits, respectively, to form a 32-bit instruction. The format and meaning of the parameter 68 depends on the type of instruction as specified by OP CODE 66.

  FIG. 9A illustrates an example data structure of parameter 68 for the RESET instruction. As shown, the only bit of interest in parameter 68 is bit 28, which is positively specified or negated to selectively enable and disable BIST mode. Can be explicitly specified. When positively stated, the receiving sequencer 8 enters a mode for applying a test algorithm in order to test each device block 6. When negated, the receiving sequencer resets the current algorithm and exits.

  FIG. 9B illustrates an example data structure of parameter 68 for the EXECUTE instruction. As shown, with respect to the EXECUTE instruction, parameter 68 manages the receiving sequencer 8 to apply a sequence of memory operations over a range of addresses according to the unique timing characteristics of each memory module 12.

  Once received, by default, the sequencer 8 repeatedly performs the specified memory operation over the largest memory module 12 address range within each device block. However, if the SINGLE ROW (SR) bit is enabled, the sequencer 8 defines for all columns of the memory module 12 that have the maximum column bit selection while maintaining the row address constant. A series of memory operations performed.

  When applying a sequence of memory operations, the sequencer 8 is supported by the largest of the memory modules 12 within each device block 6 based on the state of the ADD INC / DEC bit of parameter 68. Either increase or decrease over the address range. For example, if ADD INC / DEC is positively manifested, the sequencer 8 applies the memory operation defined for each address starting from 0 and going to the largest address. However, if ADD INC / DEC is specified negatively, the sequencer 8 applies the memory operation specified for each address starting with the largest address and decreasing to zero. The DEF DIN field sets a default data value that is applied to the memory module 12 during a read operation to the memory module.

  The ripple row (RR) field allows the sequencer 8 to apply a specified memory operation in a column-wise manner, that is, by applying the operation to the entire column before proceeding to the next column. to manage. In other words, each of the sequencers 8 keeps the column address constant while applying memory operations and “rippling” the row address.

  Invert bit (IB) field, invert row (IR) field, and invert column (IC) field are continuous data pattern, checkerboard data pattern, horizontal stripe pattern It can be used to specify data patterns for testing the memory module 12, such as data patterns and vertical stripe data patterns. More specifically, if the BIST controller 4 does not set both the IR and IC fields, the receiving sequencer 8 manages the memory interface 10 to fill the memory module with a value commanded by the sequencer. To do. If the IR field is set, the value commanded by the sequencer 8 will invert the value written in the adjacent row. Similarly, if the IC field is set, the value commanded by the sequencer 8 will invert the value written in the adjacent column. As a result, if both the IR field and the IC field are set, the value is inverted between each column and between each row to create a checkerboard pattern within the memory module. Finally, as explained above, a given memory module 12 can be configured as more than one matrix. If the Invert Bit (IB) field is set, the memory interface 10 automatically inverts the value commanded by the sequencer 8 between corresponding cells in different matrices.

  The operation fields (OP1-OP8) can be used to define the set of operations to be applied to each memory address. For example, each operation field, such as OP1, comprises 2 bits. The first bit can be specified positively or negatively to indicate whether the operation is a read or a write. The second bit can be set based on the data to be written, ie 0 or 1. The number of operations (NUM OPS) field instructs the sequencer 8 as to how many operations have been defined for application to each memory address. In this way, one instruction can be used to comprehensively define the steps within the overall BIST algorithm, each step using the device block 6 of the receiving sequencer 8. One or more operations can be defined to apply to each address of the memory module 12.

  FIG. 9C illustrates an example data structure of parameters 68 for the TEST MEM instruction. With respect to this instruction, the parameter 68 includes a FA / BIST bit for decoding the TEST MEM instruction as a failure analysis instruction and as a BIST instruction. When set in a failure analysis instruction, the value specified by the MEM ID field is used by the receiving sequencer 8 to select a specific one data output of the memory module 12 for failure analysis. . When set in the BIST instruction, the value specified by the MEM ID field is the receiving sequencer to select a particular one data output of the memory interface 10 for participation in a particular test. 8 is used. In this way, the algorithm can be selectively applied to individual memory modules 12 within the device block 6. The MEM BUS SLICE field is used to indicate which part of the multiplexed data bus from the memory module 12 is used for failure analysis.

  FIG. 9D is an example data structure of parameters 68 for the SET ADDRESS instruction. For this instruction, parameter 68 includes an address field (ADDRESS) that sets a specific memory address for application of the BIST step. This may be useful in conjunction with the SINGLE WORD ACCESS instruction. The parameter 68 also includes a limit (LIMIT) field for specifying the maximum address limit for the test algorithm. In one embodiment, the LIMIT field comprises a 2-bit data field for setting the following limits: (1) Maximum address of the largest memory module 12 in the device block 6; Maximum address divided, (3) Maximum address divided by 4, and (4) Maximum address divided by 8.

  FIG. 9E is an example data structure of parameters 68 for a SINGLE WORD ACCESS instruction. With respect to this instruction, the parameter 68 includes an enable address change (ENADC) bit that controls whether the receiving sequencer 8 should change each current BIST address after applying the step. If enabled, the address increment / decrement (ADD INC / DEC) bit controls whether the current BIST address should be incremented or decremented. The Inverted Bit (IB) field, Inverted Row (IR) field, and Inverted Column (IC) field are the continuous data pattern, checkerboard data pattern, horizontal stripe data, as described above with respect to the EXECUTE instruction. Can be used to specify data patterns for testing the memory module 12, such as patterns and vertical stripe data patterns. The data field (DATA) is used to provide default values for input data for the read operation of the memory module 12 being tested.

Table 2 illustrates an example checkerboard BIST algorithm that is stored and issued by the BIST controller according to the described instruction protocol. As illustrated, a relatively complex checkerboard memory test algorithm can be described with as few as four instructions using an instruction protocol.

Table 3 illustrates an example of a “Blanket March” BIST algorithm stored and issued by the BIST controller 4 according to the described instruction protocol. As illustrated, this memory test algorithm can be described with as few as six instructions using an instruction protocol. Each of the instructions instructs the receiving sequencer 8 to issue a sequence of memory operations that traverse the entire memory space in a defined direction. In addition, some of the instructions manage to apply multiple memory operations to each address within the memory space available to the sequencer. In this way, complex BIST algorithms can be easily distributed and applied throughout by the components of the hierarchical self-diagnostic architecture.

  FIG. 10 is a flowchart for explaining an operation example of the electronic device 2, and in particular, the distributed three-tier self-diagnostic architecture of the BIST controller 4, the sequencer 8, and the memory interface 10.

  Initially, the BIST controller 4 selects one of the algorithms stored within the internal algorithm memory, eg, the algorithm memory 20 (70). When the algorithm is selected, the BIST controller 4 issues a first instruction defined by the algorithm to one or more sequencers 8 (72).

  Each receiving sequencer 8 parses the instructions to identify the defined motion codes and corresponding parameters (78). For the memory access instruction, each receiving sequencer 8 initializes a start address defined by the instruction (80). Next, the sequencer 8 issues a memory operation, ie, generates appropriate address signals, data signals, and control signals (82).

  In turn, each receiving memory interface 10 converts data and address signals based on the physical characteristics of each respective memory module 12 (92, 94) and applies the converted signals to the memory modules. (96). Further, with respect to read memory accesses (97), the memory interface 10 automatically compares the data read from the respective memory modules with the expected data (98). Based on the comparison, the memory interface 10 updates each BIST failure signal to report the status of the tested memory module 12 (100).

  Once a memory operation is issued by the memory interface 10, the sequencer 8 determines whether additional operations are going to be applied to the current memory address within the sequence (84). If so, the sequencer 8 issues a command to the memory interface 10 in a similar manner (82). If no additional action is required, the sequencer 8 updates the address (86) and whether the entire address range defined by the instruction has been ordered or whether additional addresses remain, Is determined (88). If the entire address range is ordered and the memory operation is applied to an address within the range, the sequencer 8 issues a receipt signal to the BIST controller 4 (90).

  Upon receipt (74) from each of the sequencers 8 targeted using the instructions, the BIST controller 4 determines whether the last instruction for the selected algorithm has been issued. If not, the BIST controller 4 repeats the process and issues an additional command (72). Once all instructions have been issued and applied by the sequencer 8 and memory interface 10 (76), the BIST controller 4 ends the current BIST test.

  Various embodiments have been described. These and other embodiments are within the scope of the claims.

FIG. 1 is a block diagram illustrating an example of a distributed electronic device having a systematic built-in self-diagnosis (BIST) architecture. FIG. 2 is a block diagram illustrating an example embodiment of a BIST controller. FIG. 3 is a timing diagram that further describes the communication between the BIST controller and the sequencer set for one instruction of the generic BIST algorithm. FIG. 4 is a block diagram illustrating an embodiment of an apparatus block. FIG. 5 is a block diagram illustrating an exemplary embodiment of a sequencer. FIG. 6 is a block diagram illustrating an example embodiment of a memory interface. FIG. 7 is a block diagram illustrating an example embodiment of a data generation unit. FIG. 8 is a block diagram illustrating a data structure of an example of an instruction issued by the BIST controller. FIG. 9A illustrates an exemplary data structure in accordance with the instruction protocol described herein. FIG. 9B illustrates an exemplary data structure in accordance with the instruction protocol described herein. FIG. 9C illustrates an exemplary data structure in accordance with the instruction protocol described herein. FIG. 9D illustrates an exemplary data structure in accordance with the instruction protocol described herein. FIG. 9E illustrates an exemplary data structure in accordance with the instruction protocol described herein. FIG. 10 is a flowchart illustrating an example of the operation of a distributed three-tier self-diagnosis architecture.

Explanation of symbols

24 ... Multiplexer, 37 ... Multiplexer, 39 ... Data selection signal, 45 ... Multiplexer, 46 ... Multiplexer, 49 ... BIST data signal, 50 ... AND gate, 52 ... XOR gate, 54 ... XOR gate, 56 ... Multiplexer, 60 ... Instruction 68 ... Parameters.

Claims (38)

A system with:
A centralized built-in self-diagnostic (BIST) controller that stores an algorithm for testing a plurality of memory modules, wherein the BIST controller defines the algorithm as a generalized instruction set that conforms to an instruction protocol. A plurality of distributed sequencers that decode instructions from the BIST controller and apply the generalized instructions to the memory module based on the instruction protocol, each sequencer operating on a common clock domain The plurality of memory modules associated with one or more memory modules are grouped and assigned to each sequencer based on a predetermined criterion .   The system of claim 1, wherein the generalized instructions stored by the built-in self-diagnostic controller specify an algorithm according to the instruction protocol and independent of the timing requirements of the memory module.   The system of claim 1, wherein the generalized instructions specify an algorithm independent of physical characteristics of the memory module.   The system of claim 1, wherein each generalized instruction includes a sequencer identifier that identifies one or more sequencers to process the respective instruction and apply the instruction to the memory module.   The system of claim 4, wherein the sequencer identifier comprises a broadcast identifier for indicating that the generalized instruction is to be decoded and applied by all of the distributed sequencers.   The system of claim 4, wherein the sequencer identifier comprises a unicast identifier that identifies a particular one of the sequencers to cause each memory module of the identified sequencer to decode and apply the generalized instructions. .   5. The system of claim 4, wherein the instruction protocol defines each of the generalized instructions to include an operational code selected from a defined set of operational codes and an associated set of parameters.   The specified set of operational codes prepares the memory module for testing during that period by separating the memory module from the address and data lines used by the sequencer during normal operation. 8. The system of claim 7, comprising an operational code that manages the sequencer to selectively enable and disable the BIST mode to be used.   8. The system of claim 7, wherein the set of defined operational codes includes operational codes that manage the sequencer to apply a sequence of one or more memory operations over a range of addresses specified by parameters. .   The parameter manages the sequencer to apply memory operations to all columns of that memory module for each memory module for the sequencer with maximum column bit selection while maintaining the row address at 0 The system of claim 9, comprising one row (SR) field for   10. The parameter of claim 9, wherein the parameter comprises an inverted bit field for managing the sequencer to invert the data defined by the parameter for each row and column matrix of the memory module when applying a memory operation. system.   The parameter manages the sequencer to keep the column address for each of the memory modules constant and apply memory operations to the memory modules in a column-wise manner by ripple the row address for each of the memory modules. The system of claim 9, comprising a ripping line field for:   10. The parameter of claim 9, wherein the parameter includes an inversion row field for managing the sequencer to invert the data defined by the parameter with respect to adjacent rows of the memory module when applying a memory operation. system.   The parameter of claim 9, wherein the parameter includes an inverted column field for managing the sequencer to invert the data defined by the parameter relative to adjacent columns of the memory module when applying the memory operation. system.   The system of claim 9, wherein the parameter includes a plurality of operational fields for managing the sequencer to apply a plurality of memory operations to each of the memory addresses of the memory module.   The system of claim 9, wherein the parameters include default data in a field that manages the sequencer to apply input data values to the memory module during a read operation.   8. The system of claim 7, wherein the defined set of operational codes includes operational codes that manage the sequencer to perform a memory operation defined at a particular address specified by the parameter.   8. The system of claim 7, wherein the defined set of operational codes includes an operational code that manages the sequencer to test a particular one of the memory modules.   8. The system of claim 7, wherein the parameters include a failure analysis field for managing the sequencer to selectively switch between failure analysis mode and BIST mode.   When operating in failure analysis mode, the parameter's memory identification field is from a specific one of the memory modules for failure analysis and from the selected memory module that is going to be used for failure analysis. 20. The system of claim 19, wherein the sequencer is managed to select data from a bus slice field that points to a portion of the multiplexed data bus.   The defined set of operational codes includes operational codes for managing at least one of the distributed sequencers to apply a memory test algorithm stored within the sequencer. system.   A plurality of memory interfaces connected between the sequencer and the memory module, wherein the memory interface is under the control of the sequencer and according to the physical characteristics of the memory module; The system of claim 1, wherein the instructions are applied to.   The system of claim 1, wherein the BIST controller issues instructions to the sequencer in parallel with application to the memory module.   The system of claim 1, wherein the sequencer applies instructions to each memory module according to the timing requirements of the memory module. Each sequencer has:
A plurality of instruction controllers that implement instructions according to the instruction protocol; and an instruction parser for analyzing each of the instructions to identify a set of operational codes and parameters based on the instruction protocol, wherein the instruction parser is a BIST Selectively calling the instruction controller based on the operational sign of the instruction received from the controller;
The system of claim 1 comprising: A device comprising:
Centralized built-in for issuing multiple instructions that define a BIST algorithm for testing multiple distributed memory modules that conform to a generalized instruction protocol and have different timing requirements and physical characteristics Self-diagnostic (BIST) control means; and applying instructions to the memory module to decode the plurality of instructions issued from the built-in self-diagnosis (BIST) control means and according to the timing requirements and physical characteristics of the memory module Distributed means for,
The distributed means includes a plurality of sequencers, each sequencer associated with one or more memory modules operating on a common clock domain, wherein the plurality of memory modules are grouped and defined Is assigned to each sequencer based on the criteria .   27. The distributed means includes interface means for generating address and data signals that are translated based on physical characteristics of the memory module to apply a BIST algorithm to the memory module. Equipment. A method of testing a memory module, implemented in a system comprising a plurality of sequencers connected to a centralized controller and a memory module connected to the sequencer, the method comprises:
Apply one algorithm from one centralized self-diagnostic (BIST) controller centralized by issuing multiple generalized instructions that conform to a common instruction protocol to test multiple memory modules Deciphering the plurality of instructions using a distributed set of sequencers to apply the plurality of instructions as one or more sequences of a plurality of memory operations according to the instruction protocol; A sequencer is associated with one or more memory modules operating on a common clock domain, wherein the plurality of memory modules are grouped and assigned to each sequencer based on a predetermined criterion .   30. The method of claim 28, wherein the generalized instructions specify an algorithm independent of memory module physical characteristics and timing requirements.   30. The method of claim 29, wherein issuing an algorithm comprises issuing the instructions to a plurality of parallel sequencers for application to the plurality of memory modules.   Managing the application of the algorithm comprises issuing each of the instructions to include a sequencer identifier that identifies the one or more sequencers to process the instructions and apply the instructions to respective memory modules. The method of claim 28.   The sequencer identifier identifies one of the broadcast identifiers that indicates that the instruction is about to be decoded and applied by all distributed sequencers and a specific one of the sequencers to decode the instruction 32. The method of claim 31, comprising a unicast identifier.   29. The method of claim 28, wherein managing the application of the algorithm comprises issuing each of the instructions to include an operational code selected from a defined set of operational codes and an associated set of parameters. .   The specified set of operational codes provides a memory module for testing by isolating the memory module from the address and data lines used by the sequencer during normal operation during the period. 34. The method of claim 33, comprising operational codes for managing the sequencer to selectively enable and disable BIST mode.   35. The defined operational code set includes operational codes that manage at least one of the distributed sequencers to apply a memory test algorithm stored within the sequencer. Method.   34. The method of claim 33, wherein the set of defined operational codes includes operational codes that manage the sequencer to apply a sequence of one or more memory operations over a range of addresses specified by parameters. .   34. The method of claim 33, wherein the defined set of operational codes includes operational codes that manage the sequencer to perform a memory operation defined at a particular address specified by the parameter.   35. The method of claim 33, wherein the set of defined operational codes includes operational codes that manage the sequencer to test a particular one of the memory modules.

Images