JP2011181174A - Semiconductor device and test method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a test method thereof, for achieving a high-speed test at a desired operating frequency. <P>SOLUTION: An SiP 101 includes a logic chip 103A and a memory chip 103B. The memory chip 103B includes a memory circuit to be tested.The logic chip 103A includes an internal logic circuit 20 and a test processing circuit 21 electrically connected thereto. The test processing circuit 21 is connected with an access terminal of the memory circuit to test the memory circuit by supplying a test signal input from an external terminal 23n. The test processing circuit 21 has a high-speed test control circuit for adjusting a signal delay, and supplies in the high-speed test at an actual operating speed, the test signal supplied from the external terminal 23n to the access terminal through the high-speed test control circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an SiP (System in a Package) type semiconductor device in which a logic chip and a memory chip are mounted in a common package, and a test method thereof.

  As a test method of a semiconductor device, there is a method (BIST: Built In Self Test) in which a test pattern generator, a test pattern compressor, a comparator, and the like are incorporated in a device. In BIST, a test pattern generator generates a test pattern to be applied to a test target circuit, a test pattern compressor compresses an output pattern from the test target circuit, and a comparator compares the compressed test pattern with an expected output pattern. By comparing, the test target circuit can be tested.

  For example, in Patent Document 1, in a SiP type semiconductor device in which a logic chip and a memory chip are mounted in a common package, a memory chip test circuit (BIST circuit) and a selector / input / output circuit are built in the logic chip. A semiconductor device that enables testing of a memory chip by the BIST is described.

  FIG. 9 is a diagram illustrating the entire semiconductor device described in Patent Document 1. In FIG. In this semiconductor device, a logic chip 202 and a memory chip 203 are mounted in a common package 201. The logic chip 202 includes a logic circuit 202A, a memory chip test circuit 204, and a selector / input / output circuit 202C. The logic circuit 202A is activated during the normal operation, and the memory chip test circuit 204 is activated during the test of the memory chip 203. This is switched by the selector / input / output circuit 202C to access the memory chip 203.

  The test method of the memory chip 203 is that the memory chip test circuit 204 in the logic chip 202 generates test data, an address and a control signal for the memory chip 203, and compares and collates the write data to the memory chip 203 and the read data. , And the comparison result is output. That is, this conventional semiconductor device has a BIST circuit that performs BIST in the logic chip 202.

  FIG. 10 is an internal block diagram of the memory chip test circuit 204 shown in FIG. In response to the START input signal and the control data signal 249, the initialization circuit 246, the self test circuit 247, and the test mode setting circuit 248 are sequentially operated. Then, WRITE data W-DATA, address Add, and control signal CNT for the memory chip 203 are generated in the memory chip control circuit 241, and the WRITE operation is performed by supplying these signals to the memory chip 203. Further, during the READ operation of the memory chip 203, the determination circuit 242, the OR gate 243, and the flip-flop 244 cause the READ data R-DATA output from the memory chip 203 and the expected value data EXV generated by the memory chip control circuit 241. Comparison comparison is performed, and the result is output to the test result signal terminal 250.

  11 and 12 show first and second internal configuration examples of the selector / input / output circuit 202C shown in FIG. 9, respectively. The memory access signal S1 from the logic circuit 202A is selected during normal operation, the test access signal S2 from the memory chip test circuit 204 is selected during the memory chip test, and the signal S3 from the function macro 231 is selected during the logic circuit test. As a result, the memory chip 203 is accessed.

  Specifically, the selector / input / output circuit 202C shown in FIG. 11 includes a selector circuit 251 that selects any one of the memory access signal S1, the test access signal S2, and the signal S3 from the function macro 231; Flip-flop 252 which is a holding means for temporarily holding the signal, and an output buffer circuit 253 for outputting a signal held by the flip-flop 252 to the output terminals 223, 224 and 225. The selector circuit 251 is configured to select the signal S3 from the function macro circuit 231 in addition to the access signal S1 and the test access signal S2. The selector circuit 251 selects one of the signals S1, S2, and S3 according to a select signal (not shown).

  The selector / input / output circuit 202C includes an input buffer circuit 254 that inputs read data DATA from the memory chip 203 and a flip-flop 255 that holds the input buffer circuit 254. The output of the flip-flop 255 is supplied to the logic circuit 202A, the memory chip test circuit 204, and the function macro 231 in the logic circuit 202A, respectively.

  On the other hand, in the selector / input / output circuit 202C shown in FIG. 12, the selector 251B selects either the test access signal S2 or the signal S3 during the logic circuit test, and the signal selected by the selector 251B and the normal The selector 251A selects one of the access signals S1 from the logic circuit 202A during operation. The output of the selector 251A is directly input to the output buffer 253. Further, a flip-flop 252 that temporarily holds the access signal S1 during normal operation, a flip-flop 255 that temporarily holds the test access signal S2 from the memory chip test circuit, and a signal S3 during the logic circuit test in the wafer state. Flip-flops 256 that are temporarily held are provided in front of the selectors 251A and 251B, respectively. The input circuit configuration is such that the output of the input buffer 254 is supplied to each flip-flop 252, 255, 256.

  By the way, in such a SiP type semiconductor device in which a logic chip and a memory chip are mounted in a common package, the memory cell configuration (row / column configuration) of the memory chip differs for each memory vendor. In addition, even if the memory is from the same vendor, the row / column configuration is different if the manufacturing process (corresponding design rule) is different. Therefore, it is difficult to test a memory chip having a different row / column configuration with one BIST circuit. For this reason, there is a concern that the quality is lowered, and a problem arises that the circuit scale increases. On the other hand, as a method capable of testing even a memory chip having a different row / column configuration, there is means for inputting a test signal from an external terminal to the memory chip and then monitoring an output signal from the memory chip (see, for example, Patent Document 2). ).

  FIG. 13 is a diagram illustrating a semiconductor device described in Patent Document 2. In FIG. As shown in FIG. 13, the SiP type semiconductor device described in Patent Document 2 has a logic chip 311 and a memory chip 312 mounted in a SiP type semiconductor device 310. This SiP type semiconductor device 310 incorporates a test circuit 316 in a logic chip 311 to enable a test at a relatively low speed for the memory chip 312 using an external terminal.

  That is, the logic chip 311 includes the logic circuit 315 and the test circuit 316, is directly connected to the external terminal by the wiring 313 to the external connection terminal, and is connected to the memory chip 312 by the wiring 317. When the mode selection signal provided in the external connection terminal indicates the test mode, the memory circuit 314 can be accessed from the external connection terminal via the wiring 318, the test circuit 316, and the wiring 317 without passing through the logic circuit 315. it can. Thus, a life acceleration test and a multi-bit test in which test data is expanded and written to the memory circuit 314, and read data is degenerated and pass / fail judgment is performed. Similarly, at the time of power-on or after that, the memory circuit 314 can be directly accessed from the external connection terminal via the wiring 318, the test circuit 316, and the wiring 317, and self-diagnosis (BIST) can be performed.

  FIG. 14 is a block diagram showing a detailed configuration of the test circuit 316 shown in FIG. The test circuit 316 includes a memory test circuit 321 and a selection circuit 322, and uses the wiring 317 as a common access path to the memory circuit 314. During normal operation, an output signal of the logic circuit 315 is output from the wiring 319 to the wiring 317 via the test circuit 316, and at the time of testing, a necessary test signal (324 to 324) is transmitted from the wiring 318 to the wiring 317 via the test circuit 316. 329). The test signal includes an access control signal 324, a mode signal 325, a read / write address signal 326, a test write data signal 327, a test data signal 328, and a determination result signal 329, and the memory circuit 314 is accessed by these signals. The life acceleration test, the multi-bit test, and the self-diagnosis (BIST) are performed.

  FIG. 15 shows a specific circuit configuration example of the test circuit 316 shown in FIG. The test circuit 316 includes FF circuits 371 and 378, selectors 372 and 374, a decode circuit 377, a life acceleration test circuit 375, a degeneration circuit 376, and an expansion circuit 373. Further, the test circuit 316 performs input / output with the logic circuit 315 and the external connection terminal, and selects the selector at the time of actual operation (= output of the logic circuit 315) and at the time of test (= the signal processed from the external connection terminal). The selection is made by 372 and the memory circuit (DRAM) 314 is accessed.

JP 2003-77296 A JP 2004-158098 A

  However, as described above, the semiconductor device described in Patent Document 1 uses a memory chip test BIST in a logic chip. Therefore, when testing a memory chip by BIST, it is possible to test at the actual operating speed of the memory chip, but it is necessary to create a BIST circuit corresponding to the row / column configuration of the memory chip. Even if the memory has the same number of bits, the ratio of the optimal number of rows and columns may change depending on the manufacturing process (corresponding design rule). This is because it is difficult to deal with memory chips having different numbers of rows / columns in one BIST.

  The semiconductor device described in Patent Document 2 includes a test circuit for supplying a test signal from an external terminal in a test mode to test a memory chip in a logic chip. Therefore, since a test signal can be input from the outside, a desired test can be performed without changing the internal circuit regardless of the number of rows and the number of columns. However, the signal delay of the test signal input from the test data signal input terminal to the memory chip during the test and the signal delay of the test result signal extracted from the memory chip to the test data signal terminal become obstacles, and the actual operation speed of the memory chip. It may be difficult to test. In other words, when the test frequency becomes high, signal delay in the logic chip becomes an obstacle, and there is a problem that high-speed testing at a desired operating frequency becomes difficult.

The semiconductor device according to the present invention, there is provided a semiconductor device comprising a memory chip and a logic chip, said logic chip is connected to the internal logic circuit, and the internal logic circuit and the memory chip, the memory from an external terminal The memory chip is tested by accessing the chip .

The present invention includes a high-speed test control circuit capable of selecting a signal transfer rate according to a test speed when testing by accessing the memory chip from the external terminal. Therefore, for example, when executing a high-speed test at an actual operating frequency, the memory circuit can be tested by selecting a signal transfer rate corresponding to the test speed, such as a signal transfer rate corresponding to the high-speed test. Here, accessing the memory circuit indicates that the read and write operations of the memory circuit are controlled and the read data can be observed.

  According to the present invention, it is possible to provide a semiconductor device and a test method thereof capable of performing a high-speed test at a desired operating frequency.

1 is a block diagram showing a semiconductor device according to a first embodiment of the present invention. 1 is a block diagram showing a test processing circuit 21 in a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a block diagram showing details of a test processing circuit 21. FIG. It is a figure explaining the principle of a high-speed test adjustment circuit. It is a figure which shows an example of a high-speed test adjustment circuit. 4 is a timing chart in a high-speed test mode in the semiconductor device according to the embodiment of the present invention. It is a block diagram which shows the semiconductor device concerning Embodiment 2 of this invention. It is a block diagram which shows the semiconductor device concerning Embodiment 3 of this invention. 1 is a diagram illustrating an entire semiconductor device described in Patent Document 1. FIG. FIG. 10 is a diagram showing a memory chip test circuit shown in FIG. 9. FIG. 10 is a diagram showing a first internal configuration example of a selector / input / output circuit 202C shown in FIG. 9; FIG. 10 is a diagram showing a second internal configuration example of the selector / input / output circuit 202C shown in FIG. 9; 10 is a diagram showing a semiconductor device described in Patent Document 2. FIG. FIG. 14 is a block diagram illustrating a detailed configuration of a test circuit 316 illustrated in FIG. 13. FIG. 15 is a diagram illustrating a specific example of the test circuit 316 illustrated in FIG. 14.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to a test of a memory chip in a SiP type semiconductor device.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a semiconductor device according to Embodiment 1 of the present invention. In a SiP type semiconductor device (hereinafter referred to as SiP) 101 according to this embodiment, a logic chip 103A and a memory chip 103B are mounted on an organic substrate (interposer) 102.

The logic chip 103A includes an internal logic circuit 20 and a test processing circuit 21, and a plurality of test terminals 23 _n and two test mode selection terminals 24 ₁ and 24 ₂ are connected as external terminals. The test terminal 23 _n and the test mode selection terminals 24 ₁ and 24 ₂ can be set as either an external dedicated terminal or an external shared terminal depending on the number of external terminals used by the user. Further, it is assumed that the logic chip 103A and the memory chip 103B are only directly connected by bumps or wires, and the terminals of the memory chip 103B are not taken out as external terminals.

Here, the test processing circuit 21 according to the present embodiment includes a test circuit 121 and a high-speed test control circuit 122. The test circuit 121 has the same function as the test circuit 316 described in Patent Document 2. On the other hand, high-speed test control circuit 122, in SiP101, is connected to the access terminals of the memory chip 103B through the test circuit 121, and controls the read and write operations of the memory chip 103B from the test terminal 23 _n which is an external terminal, and The memory chip 103B is tested by observing (accessing) the read data. The high-speed test control circuit 122 can select a signal transfer rate corresponding to the test speed between the test terminal 23 _n and the memory chip 103B. That is, in the high-speed test at the actual operation speed, the signal transfer rate between the test terminal 23 _n and the access terminal is set to a desired signal transfer rate, or in the low-speed test, the signal lower than the actual operation speed. Or a transfer rate. Therefore, although the details will be described later, the high-speed test control circuit 122 adjusts the timing of the test signal in accordance with the signal transfer rate corresponding to the test speed, thereby reducing the influence of the delay of the test signal from the synchronization signal. It has a function. This reduces the difficulty of the high-speed test (actual operation speed test) of the memory chip 103B. In addition, a desired test signal can be supplied from the test terminal 23 _n which is an external terminal, and a desired high-speed test can be performed without changing the internal circuit regardless of the number of rows / columns of the memory chip 103B.

  FIG. 2 is a block diagram showing the test processing circuit 21. The test processing circuit 21 includes a test circuit 121 and a high-speed test control circuit 122. The test circuit 121 includes an input / output switching circuit B28, and the high-speed test control circuit 122 includes a test mode switching circuit 25, an input / output switching circuit A26, and a signal switching circuit 27.

The test mode selection terminals 24 ₁ and 24 ₂ are connected to the test mode switching circuit 25 of the high-speed test control circuit 122 via the wirings 7 and 8. Each output signal of the test mode switching circuit 25 is input to the input / output switching circuit A 26, the input / output switching circuit B 28, and the signal switching circuit 27. Based on the signals from the test mode selection terminals 24 ₁ and 24 ₂ , the test mode switching circuit 25 selects whether to perform the unit test mode of the memory chip 103B and the low-speed test mode or the high-speed test mode. Each circuit of the switching circuit A26, the input / output switching circuit B28, and the signal switching circuit 27 is set to a predetermined mode.

Further, the input-output switching circuit A26 via line 1-6 from the test terminal 23 _n, each of the data signal A, the address signal A, the control signal A, the clock signals A, I / O control signals I1, I2 is supplied Is done. Further, the I / O control signal I1 is also supplied to the input / output switching circuit B28. In the low-speed test mode, the I / O control signal I2 is invalidated, the data signal A and the data signal B are enabled by the I / O control signal I1, and the WRITE / READ control of the data signal to the memory chip 103B is performed. On the other hand, in the high-speed test mode, enable switching of the data signal B is individually performed by the I / O control signal I1 and the data signal A by the I / O control signal I2, and the WRITE / READ control of the data signal to the memory chip 103B is performed at high speed. To do.

  A data signal, an address signal, a control signal, and a clock signal, which are output signals of the input / output switching circuit A26, are supplied to the signal switching circuit 27, and the clock signal is also supplied to the input / output switching circuit B28. A data signal, an address signal, and a control signal, which are output signals of the signal switching circuit 27, are supplied to the input / output switching circuit B28.

  Further, a data signal, an address signal, a control signal, a clock signal, and a data enable signal at the time of actual operation are supplied from the internal logic circuit 20 to the input / output switching circuit B28 via the wirings 13 to 17, respectively. Further, a user mode signal during actual operation is supplied from the internal logic circuit 20 to the input / output switching circuit A 26 of the high-speed test control circuit 122 via the wiring 18.

  In the test mode, the input / output switching circuit B28 selects the data signal from the signal switching circuit 27, the address signal, the control signal, and the clock from the input / output switching circuit A26, while the actual operation mode (user mode). In this case, a data signal, an address signal, a control signal, and a clock signal from the internal logic circuit 20 are selected and supplied to the memory chip 103B via the wirings 9-12.

FIG. 3 is a diagram showing an example of the details of the test processing circuit 21 shown in FIG. As described above, the high-speed test control circuit 122 is connected to the test terminals 23 _n (23 ₁ to 23 ₆ ) that are external terminals. Then, the data signal A, the address signal A, and the control signal A are input via the test terminals 23 ₁ to 23 ₃ . These signals are input to one input terminal of AND gates 42, 43, and 44 through buffers 31, 32, and 33, respectively. The other input terminals of the AND gates 42, 43 and 44 are ORed with the test mode selection signal I1 and the test mode selection signal I2 input from the test mode selection terminals 24 ₁ and 24 ₂ as external terminals as inputs. An output signal of the gate 41 is input.

  Further, the output signals of the AND gates 42, 43, and 44 are directly connected to one input terminal of the selectors 51, 52, and 53, and the outputs of the high-speed test adjustment circuits 47, 48, and 49 are input to the other input terminal. The The selectors 51, 52, 53 select the output signals of the AND gates 42, 43, 44 in the low speed test mode, and the output signals of the high speed test adjustment circuits 47, 48, 49 in the high speed test mode. Is selected. Therefore, a test mode selection signal I2 is supplied to the selectors 51, 52 and 53 as a selection signal. Further, the output signals of the selectors 51, 52, 53 are supplied to one input terminal of the selectors 54, 56, 57, and the other input terminal of the selectors 54, 56, 57 is inputted with a signal from the internal logic circuit 20. Is done. Further, the output of the OR gate 41 is supplied as a selection signal. The output signal of the selectors 51, 52, 53 is selected in the test mode, and the signal from the internal logic circuit 20 is selected in the actual operation mode. Select output. The output signals of the selectors 54, 56, and 57 are output to the memory chip 103B as the data signal B, the address signal B, and the control signal B through the buffers 60, 62, and 63, respectively.

  The data signal B is supplied from the memory chip 103 </ b> B and connected to one input terminal of the AND gate 50 and the internal logic circuit 20 through the buffer 59. The output signal of the OR gate 41 is supplied to the other input terminal of the AND gate 50. Further, the output signal of the AND gate 50 is supplied to one input terminal of the selector 39, and the output signal of the high-speed test adjustment circuit 46 is supplied to the other input terminal. The selector 39 selects the output signal of the AND gate 50 in the low speed test mode, and selects the output signal of the high speed test adjustment circuit 46 in the high speed test mode. Therefore, the test mode selection signal I2 is supplied to the selector 39 as a selection signal.

Further, the output signal of the selector 39 is supplied to one input terminal of the selector 37, the wiring 18 is connected to the other input terminal, and the user mode signal of the internal logic circuit 20 is supplied. The output signal of the OR gate 41 is supplied as a selection signal, and the output of the selector 39 is selected and output in the test mode, and the user mode signal of the internal logic circuit 20 is selected and output in the actual operation mode. The output of the selector 37 through the buffer 30, is output from the test terminal 23 _1.

The clock signal A is input from the test terminal 23 ₄ is an external terminal, is supplied to one input terminal of the further AND gate 45 via the buffer 34. The output signal of the OR gate 41 is supplied to the other input terminal of the AND gate 45. Further, the output signal of the AND gate 45 becomes a clock input signal for the high-speed test adjustment circuits 46, 47, 48 and 49 and is supplied to one input terminal of the selector 58. The other input terminal of the selector 58 is connected to the wiring 16 and supplied with the clock signal of the internal logic circuit 20. The output signal of the OR gate 41 is supplied as a selection signal, the test mode clock signal A from the test terminal 23 ₄ is selectively outputted when the actual operation mode, the clock signal of the internal logic circuit 20 is selectively output . The output of the selector 58 is supplied to the memory chip 103B as the clock signal B through the buffer 64.

I / O control signal I1, and I / O control signal I2 is supplied from the test terminal ₂₃ 5, 23 _6, which is an external terminal, via the buffer 35 and 36, respectively, are input to the selector 40. The selector 40 is supplied with a test mode selection signal I2 as a selection signal, and I / O selection signals I1 and I2 are selectively output in accordance with the low speed test mode or the high speed test mode.
The output of the selector 40 is connected to one input terminal of the selector 38, the other input terminal is connected to the wiring 18, and the user mode signal of the internal logic circuit 20 is supplied. The selector 38 is supplied with the output signal of the OR gate 41 as a selection signal, the output of the selector 40 is selected and output in the test mode, and the user mode signal of the internal logic circuit 20 is selected and output in the actual operation mode. The output of the selector 38 becomes an enable signal for the buffer 30.

  The output of the buffer 35 to which the I / O control signal I1 is supplied is connected to one input terminal of the selector 55, the other input terminal is connected to the wiring 17, and the data enable signal of the internal logic circuit 20 is supplied. . The selector 55 is supplied with the output of the OR gate 41 as a selection signal, selects and outputs the I / O control signal I1 in the test mode, and selectively outputs the data enable signal of the internal logic circuit 20 in the actual operation mode. The output of the selector 55 becomes an enable signal for the buffer 60 via the inverter 61. Note that the circuit configuration example is not limited to this, and can be changed to any circuit configuration as long as a desired function can be realized.

  Next, the high-speed test adjustment circuit will be described. Here, first, the principle of the high-speed test adjustment circuit in this embodiment will be described before the description thereof. In general, variations in delay time due to variations in element characteristics due to variations in PVT (process, voltage, temperature), and an increase in delay time due to the length of a signal wiring lead to an increase in setup time of a flop-flop, for example. That is, conventionally, it has been difficult to perform a high-speed test due to an increase in the setup time of the flip-flop due to the variation or increase in the delay time. On the other hand, in this embodiment, by providing a plurality of Retiming flip-flops as a high-speed test adjustment circuit, variations in delay time due to variations in element characteristics are suppressed. This makes it possible to propagate a high-speed signal over a long distance and, as a result, enable a high-speed test.

  FIG. 4 is a diagram for explaining the principle of the high-speed test adjustment circuit. As shown in FIG. 4A, when the flip-flop FFa is connected to the circuit 151 having the resistors Ra and the Rb capacitors Ca and Cb, the variation in element characteristics such as the threshold value based on the PVT variation is shown in the right diagram. Is Δ. It is assumed that the delay time variation due to the threshold variation Δ is ΔT1. When the values of the resistors Ra and Rb and the capacitors Ca and Cb of the circuit 151 are increased, the delay time variation ΔT1 is increased, and for example, the setup time of the flip-flop FFa is increased, so that a high-speed test cannot be performed.

  On the other hand, as shown in FIG. 4B, when FFb is provided between the circuits 151, circuits 152a and 152b are obtained. As shown in the right diagram, the fluctuations in the threshold values of these circuits 152a and 152b are Δ as in FIG. 4A, but the fluctuations in the delay time for the flip-flops FFb and FFc are as short as ΔT2. Therefore, the setup time can be shortened and a high-speed test can be performed. In this embodiment, by utilizing this principle, as a high-speed test adjustment circuit, as many flip-flops for Retiming as necessary are arranged in the logic chip 103A, thereby suppressing delay time fluctuation, It enables testing. Specifically, in the present embodiment, among the test signals used for the high-speed test of the memory, the data signal, the address signal, and the control signal are supplied to the memory via the high-speed test adjustment circuit, thereby performing the high-speed test. Make it possible. The clock signal used in the test is supplied to the memory as it is without going through the high-speed test adjustment circuit.

  FIG. 5 is an example showing the high-speed test adjustment circuits 46 to 49 in FIG. The high-speed test adjustment circuit in the present embodiment is composed of a plurality of stages of flip-flops. In FIG. 5, only two flip-flops 70 and 71 are shown for simplicity. The clock input signal is supplied to the clock input of each flip-flop 70, 71, respectively. Further, the data input signal is input to the data input of the flip-flop 70, and the output of the flip-flop 70 is converted into a data output signal from the output of the flip-flop 71 which is the final stage via the flip-flop group connected in a shift register configuration. Is output. The number of stages of the flip-flop can be arbitrarily set according to a desired test frequency. That is, the data signal is sequentially transferred by the flip-flop, thereby absorbing the timing shift due to the signal delay therebetween. Therefore, for example, when the signal wiring in which the high-speed test adjustment circuit is arranged is long and the test frequency is high, the signal delay becomes large. Therefore, the number of stages of this flip-flop may be increased.

Next, the operation of the SiP according to the present embodiment will be described. First, an outline of a test method for the memory chip 103B will be described. The test mode selection terminals 24 ₁ and 24 _{2 of the} external terminals are set to the test processing circuit 21 in the logic chip 103A as to the actual operation mode or the unit test mode of the memory chip 103B. Set the low-speed test mode or high-speed test mode. Next, using the test terminal 23 _n which is an external terminal, using the high-quality test program owned by the memory vendor, the WRITE and READ operations are performed to the memory chip 103B via the logic chip 103A, and the memory chip 103B The product is judged as good / defective. A test program exists for each test item according to the low-speed test and the high-speed test.

Next, the operation of the test processing circuit 21 will be described. First, the test mode selection signal I1 and the test mode selection signal I2 are input from the test mode selection terminals 24 ₁ and 24 ₂ to the test mode switching circuit 25 using the wirings 7 and 8, and the actual operation mode (user mode) and low speed are input. Set various modes of test mode or high-speed test mode. The test mode switching circuit 25 sets each mode for the input / output switching circuit A26, the signal switching circuit 27, and the input / output switching circuit B28.

The input / output switching circuit A26 performs switching setting between the actual operation mode and the test mode based on the output signal of the test mode switching circuit 25. In the test mode of the low-speed test or the high-speed test, the data signal A, the address signal A, the control signal A, and the clock signal A input from the test terminal 23 _n via the wirings 1 to 4 are converted into the data signal, the address signal, The control signal and the clock signal are output to the signal switching circuit 27. Further, the enable of the data signal A for the low speed test or the high speed test is switched by the I / O control signal I1 and the I / O control signal I2 input using the wirings 5 and 6. In the present embodiment, the I / O control signal I1 is used as an enable signal in the low-speed test mode, and the I / O control signal I2 is used as an enable signal in the high-speed test mode.

  On the other hand, in the actual operation mode, a user mode signal is supplied to the high-speed test control circuit 122 via the wiring 18. At this time, the data signal A, address signal A, control signal A, and clock signal A are internally disabled to reduce power consumption.

A data signal, an address signal, a control signal, and a clock signal, which are output signals of the input / output switching circuit A26, are input to the signal switching circuit 27. The signal switching circuit 27 outputs the data signal, the address signal, and the control signal via a high-speed test adjustment circuit for a high-speed test.
In the low-speed test mode, the above signals are output through. The data signal, address signal, and control signal, which are output signals of the signal switching circuit 27, are input to the input / output switching circuit B28.

  In the test mode, the input / output switching circuit B28 routes the data signal, the address signal, the control signal and the clock signal output from the input / output switching circuit A26 through the wirings 9 to 12 as the output of the signal switching circuit 27. And output to the memory chip 103B. The I / O control signal I1 input using the wiring 5 is used as an enable signal for the data signal B.

  On the other hand, in the actual operation mode, the input / output switching circuit B28 exchanges the data signal of the internal logic circuit 20 via the wiring 13, and the address signal and control from the internal logic circuit 20 via the wirings 14 to 17, respectively. The signal, clock signal, and data enable signal are received and output to the memory chip 103B. The data enable signal of the wiring 17 is used as an enable signal for the data signal B.

Next, details of the test method of the memory chip 103B will be described. First, the test mode selection terminals 24 ₁ and 24 ₂ which are external terminals set the test mode and the high-speed test mode or the low-speed test mode for the test processing circuit 21 in the logic chip 103A. In the present embodiment, the single test mode of the memory chip 103B can be set by setting either one of the test mode selection signals I1 and I2 to "H" or both to "H". Further, the low-speed test mode can be set by setting the test mode selection signal I1 to “H” and the test mode selection signal I2 to “L”. On the other hand, the high-speed test mode can be set by setting the test mode selection signal I1 to “L” or “H” and the test mode selection signal I2 to “H”.

  The low-speed test mode is a test mode for performing an item to be tested at a relatively low speed (Loose Function Test, STATIC HOLD, etc.) in a high-quality test program owned by a memory vendor. In the low-speed test mode, the I / O control signal I2 is invalidated, the data signal A and the data signal B are enabled by the I / O control signal I1, and the WRITE / READ control of the data signal to the memory chip 103B is performed. Do. Each input signal of the data signal A, the address signal A, and the control signal A passes through the test processing circuit 21 in the logic chip 103A and is directly output as the data signal B, the address signal B, and the control signal B. . Further, the clock signal A is also directly output as the clock signal B, and using these signals, the WRITE / READ of the data signal to the memory chip 103B is performed, and the non-defective / defective product of the memory chip 103B is determined.

  In the actual operation, the AND gates 42, 43, 44, and 45 shown in FIG. 3 set the data of the test mode selection signals I1 and I2 to the “L” state in order to reduce power consumption. Each input signal of the signal A, the address signal A, the control signal A, and the clock signal A can be disabled. In the low-speed test mode, even if there is a signal delay or the like in the test processing circuit 21, it is low-speed, so that it is possible to perform a test with sufficient synchronization without using a high-speed test adjustment circuit or the like.

  On the other hand, the high-speed test mode is a test mode for items to be tested at high speed (MARCH, BANK PING-PONG, etc.) in a high-quality test program owned by a memory vendor. The data signal B is individually switched by the I / O control signal I1 and the data signal A is switched by the I / O control signal I2, and the WRITE / READ control of the data signal to the memory chip 103B is performed at high speed. Further, at the time of WRITE, the input signals of the data signal A, the address signal A, and the control signal A are transferred to the clock signal A via the high-speed test adjustment circuits 47, 48, and 49 in the test processing circuit 21 in the logic chip 103A. Synchronously output to the data signal B, the address signal B, and the control signal B.

  In the high-speed test adjustment circuits 47, 48, and 49, a plurality of flip-flops are incorporated in order to correspond to a desired high-speed test frequency, and the data signal A, address signal A, and control signal A are transferred at high speed by the clock signal A. By temporarily storing in the flip-flop with the clock and outputting with the next clock, the physical signal delay generated in the logic chip 103A can be shortened, and writing to the memory chip 103B can be performed at high speed. Similarly, at the time of READ, the input signal of the data signal B is output to the data signal A in synchronization with the clock signal A via the high-speed test adjustment circuit 46.

  As described above, by incorporating a high-speed test adjustment circuit in the test processing circuit 21 in the logic chip 103A, the WRITE / READ of the data signal to the memory chip 103B is performed at high speed, and the non-defective / defective products of the memory chip 103B are detected. Judgment can be made.

  FIG. 6 is a timing chart in the high-speed test mode (WRITE to READ, CL = 2, BL = 1). In this example, two stages of flip-flops are incorporated in the high-speed test adjustment circuit. Further, the terminal names and signal names in FIG. 6 correspond to the terminal names and signal names of the test processing circuit 21 shown in FIG.

  First, in order to set the high-speed test mode, the test mode selection signal I1 is set to “L” (or “H”), and the test mode selection signal I2 is set to “H”. Next, an “ACT” command, a “WRITE” command, and a “READ” command are input from the address signal A and the control signal A in the order of T1 to T3 cycles.

  In response to the clock signal A, the F / F1 and F / F2 in the high-speed test adjustment circuits 48 and 49 shift each signal by two clocks and output it as an address signal B and a control signal B. Write. In accordance with the above operation, the WRITE data is input from the data signal A in the T2 cycle, and the WRITE data is shifted by two clocks by the F / F1 and F / F2 in the high-speed test adjustment circuit 47 by the clock signal A. Write WRITE data to the memory chip 103B. At this time, the I / O control signal I1 is set to enable “L” only for the WRITE period (T4 cycle), and the data signal B is set to the output mode.

  In addition, it is ideal that the READ data output from the memory chip 103B in the T7 cycle is originally tested at a high speed, and the comparison / matching of the WRITE data with the READ data a in the T7 cycle is required. However, in reality, there is a case where the delay is up to the T8 cycle READ data b due to the influence of the signal delay in the logic chip 103A, the output buffer delay due to the large external load capacity, etc., and it becomes difficult to test at high speed. . On the other hand, by using the high-speed test adjustment circuit 46, the F / F1 in the high-speed test adjustment circuit 46 temporarily holds the READ data during the T7 cycle, and the READ data is shifted by the F / F2 so that 2 In the T9 cycle after the clock, the READ data c is output as the data signal a shown in FIG. By comparing the READ data c with the WRITE data and detecting coincidence / non-coincidence, the non-defective / defective product of the memory chip 103B can be determined at high speed. At this time, the I / O control signal I2 is set to enable “H” only for the READ period (T9 cycle), and the data signal A is set to the output mode. In the above description, the high-speed test at the time of READ for the memory chip 103B is mentioned in particular. However, the present invention is not limited to this, and the same applies at the time of WRITE.

In the present embodiment, the test mode for the memory chip 103B is set from the test mode selection terminals 24 ₁ and 24 ₂ , and the test of the memory chip 103B is performed using the test program owned by the memory vendor from the test terminal 23 _n. Therefore, the memory chip 103B can be tested without being affected by the difference in the row / column configuration which differs depending on the memory vendor and the process used, which has been a problem in the BIST test method, and without the need to create a BIST circuit. Further, since a high-speed test of the memory chip 103B can be performed using a test program owned by the memory vendor, a high-quality test can be performed.

  In addition, by incorporating the high-speed test adjustment circuit of FIG. 5 and arbitrarily changing the number of flip-flop stages according to a desired test frequency, it has been possible to realize a high-speed test of a memory chip using an external terminal, which has been difficult in the past. Is possible.

In other words, in FIG. 3, for example, the chip size of the logic chip 103A is large, and due to restrictions on terminal arrangement, the test terminal 23 _n such as the test terminal 23 ₁ (data signal A) and the memory chip 103B such as the data signal B terminal are connected. In some cases, the terminal position of the input / output terminal for the output from the memory chip or the input from the memory chip is physically separated. In this case, since the influence of the gate delay and the wiring delay between the test terminal 23 _n and the input / output terminal is large, the READ data a at the timing T7 shown in FIG. Is output at timing T8 or later. As described above, since the read timing is delayed, it is difficult to perform coincidence comparison with the WRITE data at a desired frequency in the high-speed test. In contrast, in the present embodiment, by providing a high-speed test control circuit, signal delay caused by gate delay and wiring delay between the input / output terminal and the test terminal 23n can be suppressed.

That is, even when the large chip size of the logic chip 103A, and terminal positions of the input and output terminals to the test terminals 23 _n and the memory chip 103B from constraints terminal arrangement is physically separated, the layout of the logic chip 103A At this time, the influence of the gate delay and the wiring delay can be easily suppressed only by arranging the flip-flop in the high-speed test adjustment circuit at an optimum position in consideration of the frequency during the high-speed test. Also, the READ data a output from the memory chip 103B at the timing of T7 is extracted as the READ data c at a predetermined timing, that is, the timing of T9 in this embodiment, through the high-speed test adjustment circuit. This makes it possible to easily perform a high-speed test at a desired frequency. Therefore, it becomes possible to perform a test at the signal transfer rate during actual operation.

Embodiment 2. FIG.
FIG. 7 is a diagram showing a semiconductor device according to the second embodiment of the present invention. A difference from the first embodiment shown in FIG. 1 is that two memory chips are connected to one logic chip on the same data bus. Even if two memory chips are connected, the test processing circuit 21 is changed to a circuit configuration that enables the individual reading of the memory chips 103B and 103C, and the high-speed testing of the memory chips 103B and 103C can be performed individually. Easy to do.

Embodiment 3 FIG.
FIG. 8 is a diagram showing a semiconductor device according to the third embodiment of the present invention. The difference from the second embodiment shown in FIG. 7 is that two test processing circuits 21A and 21B are provided so that the test circuits can be connected to the memory chips 103B and 103C on a one-to-one basis. In the second embodiment, the memory chips 103B and 103C are individually tested. In this embodiment, the memory chips 103B and 103C can be simultaneously tested at a high speed, thereby reducing the test time. Can do.

As described above, the present invention has the following effects.
1. 1. BIST design is not required, and memory chips can be tested without being affected by memory vendors or processes used. 2. It becomes possible to test the memory chip at the actual operating frequency. Since it is possible to adopt memory-dedicated test programs from all memory vendors, high chip quality can be ensured. The circuit scale is smaller than the memory chip test method using the BIST circuit, and the overhead of the entire circuit is reduced (for example, the conventional BIST circuit has about 100 Kgate, and the test circuit of this embodiment is configured with about 2 Kgate, etc. Is possible.)
5. Package cost can be reduced because there is no need for external terminals for testing.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

23 ₁ to 23 ₆ , 23 _n Test terminals 24 ₁ , 24 ₂ Test mode selection terminal 20 Internal logic circuits 21, 21 A, 22 B Test processing circuit 25 Test mode switching circuit 26 Input / output switching circuit A
27 Signal switching circuit 28 Input / output switching circuit B
30 to 36, 59, 60, 62, 63, 64 Buffer 37 to 40, 51 to 58 Selector 41 to 45, 50 Gate 46 to 49 High-speed test adjustment circuit 61 Inverter 70, 71 Flip-flop 101 SiP
102 Interposer 103B, 103C Memory chip 103A Logic chip 121, 121A, 121B Test circuit 122, 122A, 122B High-speed test control circuit

Claims (15)

A semiconductor device including a memory chip and a logic chip,
The logic chip is
Internal logic circuit,
A test processing circuit connected to the internal logic circuit and the memory chip and accessing the memory chip from an external terminal to test the memory chip ;
The test processing circuit, when testing prior Symbol memory chip, a semiconductor device having a high-speed test control circuit selectable in accordance with signal transfer rate to the test speed between the external terminal and the memory chip. The high-speed test control circuit, when the test processing circuit Gath strike, the semiconductor device according to claim 1, further comprising a high-speed test adjustment circuit for the signal transfer rate and the desired signal transfer rate. The semiconductor device according to claim 1 or 2 , wherein during the test, the high-speed test control circuit supplies a test signal from the external terminal to the memory chip directly or via the high-speed test adjustment circuit. . The test processing circuit has a first selector,
Wherein the first selector, in response to the first selection signal, the test signal from the external terminal, according to claim 2 or 3 selectively outputs one of the test signal through the pre-Symbol fast test adjustment circuit The semiconductor device described. The test processing circuit includes a second selector,
It said second selector in response to the second selection signal, either the test signal from the external terminal, before Symbol claims 1 to 4 selectively outputs one of the user signals from the internal logic circuit A semiconductor device according to claim 1. 6. The semiconductor device according to claim 2, wherein the high-speed test adjustment circuit includes a plurality of stages of flip-flops.   The plurality of flip-flops are serially connected.
The semiconductor device according to claim 6.   A clock input from an external terminal is supplied to the plurality of flip-flops.
The semiconductor device according to claim 6, wherein:   The semiconductor device according to claim 8, wherein the external terminal to which the clock is input is provided separately from the clock of the internal logic circuit. A plurality of said memory chips connected to said logic chip, any one of claims 1 to 9, characterized in that to test individually the plurality of memory chip, the test processing circuit of the logic chip Semiconductor device. A plurality of the test processing circuits in the logic chip;
The semiconductor device of any one of claims 1 to 10, characterized in that it comprises a plurality of memory chips to-one correspondence with the plurality of test processing circuit.   13. The semiconductor device according to claim 1, wherein the semiconductor device is SiP (System In Package). It has a main Morichippu, internal logic circuits, and a logic chip having a test processing circuitry electrically connected to the memory chip and the internal logic circuit, the test processing circuit, the test input from the external terminal a method of testing a semiconductor device to perform a test of the memory chip by supplying a signal to the memory chip,
Supplying pre Symbol test signal, the provided test processing circuit, to the external terminal and the said memory chip via the high-speed test control circuit selectable in accordance with signal transfer rate between the memory circuit to the test speed And testing a semiconductor device for testing the memory chip . When the test processing circuit performs a high-speed test at an actual operation speed, a high-speed test adjustment circuit of the high-speed test control circuit is used, and a signal transfer rate between the external terminal and the memory chip is set to a desired signal transfer 14. The method of testing a semiconductor device according to claim 13 , wherein the high-speed test is executed as a rate. When the test processing circuit performs a low-speed test at a speed slower than the actual operation speed, the high-speed test control circuit causes a signal transfer rate between the external terminal and the memory chip to be a signal slower than the actual operation speed. claim 13 or 14 test method of a semiconductor device, wherein performing said low speed test as the transfer rate.

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