JP2003338751A - Reconstructable hardware and diagnosis thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent hardware from being restricted by the chip border of a PCA chip during diagnosis of a variable part. <P>SOLUTION: In the reconstructable hardware, which has unit components arranged in the shape of a secondary array so as to transfer the input/output signals among one another and capable of reconstructible an optional logic circuit, a peripheral mechanism for diagnosis, which returns signals transferred between adjacent unit components, is provided. More specifically, this hardware is provided with peripheral mechanisms X1-X3 for diagnosis, which return signals between the basic cells BC on the same side around the variable part PP. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reconfigurable hardware having a unit configuration section which is arranged in a two-dimensional array and exchanges input / output signals between adjacent ones so that an arbitrary logic circuit can be realized and its diagnosis. It is about the method.

[0002]

2. Description of the Related Art As an example of hardware capable of reconfiguring an arbitrary logic circuit, a variable part PP (Plastic Part) and an embedded part BP for exchanging signals with the variable part PP.
(Built-in Part) and PCA (Plastic Cell Ar)
chitecture) (reference: Akira Nagoya, Kiyoshi Oguri: “Outline of Plastic Cell Architecture (PCA) Technology”, NTT R & D, Vol.49, No.9, pp.513-517, Sep.20)
00.).

FIG. 15 shows the internal structure of the PCA chip 10. One PCA chip 10 has a configuration in which N × N (N: natural number) PCA cells 20 are arranged in an array, and each PCA cell 20 is composed of a variable part PP and a built-in part BP. . The variable parts PP are two-dimensionally arranged on the PP layer, and the input and output of the adjacent variable parts PP are connected to each other to form a PP plane. Further, the built-in portion BP is two-dimensionally arranged in a BP layer different from the PP layer. In the PCA cell 20, a logic circuit (reference numeral R in FIG. 15 is used) on the PP surface (a single or a plurality may be used, but an arbitrary number of variable parts PP is used).
1 and R2), and an input / output signal (embedded part B) between this logic circuit and the outside via the path L1 and the embeded part BP.
P ← → variable part PP). Further, as shown in FIG. 16, one variable part PP is a basic cell BC having a four-direction lookup table LUT (Look Up Table).
The configuration is such that only M × M (M: natural number) (Basic Cells) are arranged in a two-dimensional array.

Here, a diagnostic method for reconfigurable hardware will be described. The object of diagnosis in the reconfigurable hardware is not limited to the PCA chip 10, and extends to a system having a structure having the reconfigurable hardware characteristics such as a board or a device formed of a reconfigurable LSI chip.

In order to deal with a diagnosis target including such a system, it is necessary to use not only chips but also a condition of arranging a plurality of chips, that is, a technique that takes into account the condition of a chip boundary logically.

In the PCA cell 20 to be taken up, the built-in section BP handles the exchange of signals (data signals, control signals, etc.) between the logic circuits formed in the variable section PP, so that the built-in section can be controlled by input / output signals. BP can be diagnosed. However, since the other variable part PP can be diagnosed by using a plurality of adjacent variable parts PP to realize an arbitrary logic circuit, the input / output signals between the adjacent variable parts PP are taken into consideration. Need to handle. In the case where the inside of the variable part PP has a two-dimensional array structure in which only the basic cells BC shown in FIG. 16 are arranged, the input / output signals of the basic cells BC located in the peripheral part of the variable part PP are adjacent to each other. It corresponds to the input / output signal between. Therefore, in the PCA cell 20, it is important to comprehensively diagnose all the basic cells BC forming the variable part PP.

As a method for comprehensively diagnosing this basic cell BC, it has been known that there is a functional diagnosis method using a copy of a diagnostic circuit reconfigured on the PP surface of the PCA cell 20 (reference). : Hideyuki Tsuboi, Hidefumi Kobayashi, Tsunemichi Shiozawa, Koichi Nagami, Akira Nagoya, "Examination of test method for autonomously reconfigurable hardware," Technical Report of IEICE, VLD2000-80, ICD2000-137, FTS2000 -45, pp.6
5-70.Nov.2000).

The diagram on the left side of FIG. 17 shows P of the PCA cell 20.
It is a figure which shows the diagnostic method using the replication of the circuit of P surface. This PP plane has a boundary 10A of a PCA chip 10 having N × N PCA cells 20. Although there is no connection between the adjacent variable parts PP on the boundary 10A of the PCA chip 10, signals can be exchanged through the built-in part BP.

The diagnostic circuit TST used for diagnosis comprises a block of the variable portion PP of the 2 × 2 PCA cells 20, and in FIG. 17, the variable portion of the 2 × 2 PCA cells 10 in the upper left corner of the PCA chip boundary 10A. Programmed in PP. A thin hatched portion TST1 of the diagnostic circuit TST is a diagnostic control unit TST1 that controls all operations of the diagnostic circuit TST.
And the dark hatch portion TST2 is the diagnosis target circuit TST.
It is 2. The black square portion in the diagnosis target circuit TST2 is the basic cell BC to be diagnosed. The diagnostic circuit TST is
While diagnosing the basic cell BC in one diagnosis target circuit TST2 (functional test of all lookup tables LUT which are constituent elements of the basic cell BC), the same diagnostic circuit TST is duplicated on the right side. The diagnostic result at this time is
It is sent to the chip boundary 10A located at the right end and measured from an external terminal (not shown). The duplicated diagnostic circuit TST also makes a diagnosis in the same manner, and further repeats self-duplication to the right.

The right side of FIG. 17 shows the diagnosis target circuit TST2. This diagnosis target circuit TST2 is composed of one PCA cell 20.
Of the variable part PP. This diagnostic target circuit TS
At T2, the basic cell BC to be diagnosed is shown by a black square. The wiring connecting the input and output of signals in all directions up to the basic cell BC to be diagnosed is the PCA cell 2 concerned.
It is set in another basic cell BC within 0. In the center of FIG. 17, an example of the wiring structure by the basic cell BC is shown. Since the basic cell BC to be diagnosed shown in this case is not located in the peripheral portion of the variable portion PP, the diagnosis target circuit TST2B is included in the variable portion PP in one PCA cell.

The diagnosis and duplication by the diagnosis circuit TST will be described in more detail. FIG. 18 is a diagram showing a typical scene of the diagnostic method. The left side of FIG. 18 shows the path setting and diagnosis execution, and the right side shows the command issuance and copying.

First, in the route setting, the diagnostic control unit TST1
Data is read from. Part of the data is a command string for setting a route in the built-in section BP.
When executing the diagnosis, a path (message path) is connected from the diagnosis control unit TST1 to the diagnosis target circuit TST2, and an output path from the diagnosis target circuit TST2 to the external terminal is also set. Thereafter, the diagnostic data and the diagnostic result are transmitted via these routes, and the diagnostic is executed.

When the diagnostic execution at one location is completed, the issue of a duplication command and the duplication operation start next. Diagnostic control unit TST
1 issues a command, and a duplicate command string is formed on the embedded part BP and buffered therein. In accordance with this copy command, the configuration information of the diagnostic circuit TST is read from the variable part PP, a route for propagating duplicated data is set, and the configuration information is written to the variable part PP at an adjacent position.
In this way, the duplication of the diagnostic circuit TST is realized.

On the left side of FIG. 19, there is shown a flowchart in which the diagnostic circuit TST on the PCA cell 20 operates. First, there is the step of programming the diagnostic circuit TST. here,
The diagnostic circuit TST is realized by inputting the configuration information of the diagnostic circuit TST from outside the PCA cell 20 and writing it in the variable part PP. The writing position is, for example, the left end of the PCA chip. Further, after the writing of the configuration information of the diagnostic circuit TST is completed, a start signal (Open or the like) of the diagnostic circuit TST is also input from the outside.

Second, there is the step of route setting and diagnostic execution. When receiving the above-mentioned start signal, the data is automatically read from the diagnostic control unit TST1 of the diagnostic circuit TST. This data sets a path (between the diagnosis control unit TST1 and the diagnosis target circuit TST2 and between the diagnosis target circuit TST2 and the external terminal) necessary for the diagnosis, and the diagnosis data and the diagnosis result are propagated on this path to make the diagnosis. To be executed. The diagnostic result is observed from the external terminal and the expected value is collated externally. The external terminal is set at the right end of the PCA chip 10.

Third, there is the step of erasing the path. When a series of diagnostic data input to the diagnostic circuit TST is read from the diagnostic control unit TST1, the path is erased. That is, when the diagnosis target circuit TST2 receives a peculiar input, a termination command (Clear) is output, and the termination command realizes the elimination of the path between the diagnosis target circuit TST2 and the external output. The diagnosis control unit TST1-diagnosis target circuit T
The route between ST2 is not specifically deleted. This path is set by the signal corresponding to the activation of the reading from the diagnostic control unit TST1, so that this path is automatically erased when the reading of all data is completed.

Fourth, there is the step of performing the duplication. For the duplication, the duplication command sequence of the data immediately before the reading of the data of the diagnostic control unit TST1 is finished is used. Once this is embedded part B
It is sent to P and buffered on the built-in part BP.
For the diagnostic control unit TST1 that has finished sending the data string,
The buffered duplicate command sequence is the diagnostic circuit TST.
Of the configuration information and writing to the adjacent variable part PP. The diagnostic circuit TST is duplicated by this series of procedures. The adjacent variable part PP refers to, for example, the right side of the copy source.

Fifth, there is the step of activating the duplicated diagnostic circuit TST. In the previous duplication, following the duplication command sequence buffered in the built-in unit BP, the activation command is added in the same manner. The added command activates the duplicated diagnostic circuit TST.

In the flowchart on the left side of FIG.
The procedure from path setting and diagnostic execution to the activation of the duplicate diagnostic circuit is repeated. The branch condition of this repetition is PCA
By repeating this procedure, the diagnostic circuit TST programmed at the left end of the chip 10 is gradually copied to the right as shown on the right side of FIG.
The condition is that the right end of 0 is reached and this row direction is ended.

Then, each time the diagnosis in the row direction is completed, the diagnostic circuit TST is newly programmed from the outside, and the diagnosis and duplication by the diagnostic circuit TST are repeated as described above. When the repetition of this diagnosis is completed over the entire surface of the PCA chip 10, the diagnosis by this method is completed.

In the diagnosis of the PCA chip 10 described above, the diagnostic circuit TST used by repeatedly copying is important. The diagnostic circuit having a small size has a large number of duplications in the PCA chip 10 as compared with the diagnostic circuit having a large size, which enables efficient diagnosis.

[0022]

On the left side of FIG. 20, the basic cell BC to be diagnosed is located at the lower right corner of the variable part PP, and the diagnosis target circuit TS is set in order to set the input / output wiring for the diagnosis.
An example is shown in which the variable portion PP of 2 × 2 PCA cells for 20 is required as T2. Here, as shown on the right side of FIG. 20, in order to diagnose the basic cell BC at the lower right corner of the upper left variable portion PP of the 2 × 2 variable portions PP,
Wiring is set using the upper right variable portion PP and the lower left variable portion PP. As described above, the size of the diagnosis target circuit TST2 does not fit in the variable part PP of one PCA cell, and it spans four PCA cells 20. In addition to this case, when the basic cell BC to be diagnosed is located in the peripheral part of the variable part PP, the wiring connecting the input signal and the output signal must be set in the variable part PP region of the adjacent PCA cell 20. I don't get it.

Thus, the left side of FIG. 20 shows how the diagnostic circuit TST2 is duplicated when the diagnostic target circuit TST2 does not fit in the variable part PP in one PCA cell. This diagnostic circuit TST has a diagnostic control unit TST1 which is provided with two vertical P
The diagnosis target circuit TST2 is composed of 2 × 2 PCA cells 20 as described above, and as a result, the diagnosis circuit TST is composed of 2 × 3 PCA cells 20. Will be configured.

Here, when one PCA chip 10 is composed of N × N PCA cells 20, “N” is 2
, All diagnostic circuits TST are 2 x 2 PCs
If the A cell 20 is used, there is no limitation on the copy, and the copy can be performed “N / 2” times in the horizontal and vertical directions (right side of FIG. 19). However, as the diagnostic circuit TST, 2 × 3 PCs
If the A cell 20 is required, it is subject to replication restrictions, even if "N" is a multiple of 3.

The reason for this is that one PCA cell 20 is placed at an arbitrary position in the diagnostic circuit TST of the 2 × 2 PCA cells 20.
The same diagnosis target circuit TST2 (diagnosis circuit TST2 in FIG.
Even if the diagnosis target circuit TST2 is located at the upper right position in ST), all the variable parts PP can be diagnosed by duplicating the diagnosis circuit TST under the same conditions.

However, in the diagnostic circuit TST of the 2 × 3 PCA cells 20, even if the same diagnostic target circuit TST2 of the 2 × 2 PCA cells 20 is rearranged to the left and right, the PCA cells 20 correspond to three columns. In one diagnostic circuit TST, the variable portion PP for one column cannot be diagnosed. In addition, the diagnostic circuit T which has two lines
Diagnosis is also impossible for the variable parts PP on one side above and below ST.

Therefore, it is necessary to preliminarily provide an offset for one PCA cell in the right or down direction for duplication, or to use another different diagnosis target circuit.

However, when the offset of one PCA cell 20 is preset to the right and copying is performed, the boundary 10 of the PCA chip 10 as shown on the lower side of the left side of FIG.
In A, that is, in a portion where there is no mutual connection between the adjacent variable parts PP, the diagnosis target circuit TST2 cannot be reconfigured (duplication is impossible). Therefore, the diagnostic circuit TST of 2 × 3 PCA cells
Is subject to chip boundary restrictions during replication.

Due to this limitation, in order to diagnose all the basic cells BC (all basic cells BC including the basic cells BC located in the peripheral portion of the variable portion PP), various types having different sizes are used. (In the case of being composed of a plurality of variable parts PP, the basic cell BC in each variable part PP is covered)
There is a problem that the diagnostic circuit TST including ST2 must be prepared and the diagnostics must be performed individually.

Here, the "problems" described above will be summarized from the viewpoint of the variable parts PP arranged in a two-dimensional array. FIG. 21 shows a connection between the variable parts PP adjacent to each other in the normal time. The variable parts PP arranged in a two-dimensional array and capable of realizing an arbitrary logic circuit can exchange input / output signals with the adjacent variable parts PP. In FIG. 21, when focusing on a certain variable part (C-PP), there are adjacent variable parts (N-PP, S-PP, W-PP, E-PP) in the upper, lower, left, and right directions. ,
Input / output signals can be exchanged between each of these and the C-PP.

Therefore, as shown in FIG. 15 and described above, the reconfigurable hardware uses not only one variable part PP but also a number of variable parts PP connected to each other as necessary. Logic circuits of different scales can be realized.

However, when diagnosing the variable parts PP having such characteristics, it is necessary to consider the input / output signals between the adjacent variable parts PP. Therefore, even in the conventional diagnostic method using the duplication of the diagnostic circuit,
It is not sufficient to diagnose each variable part PP over the entire surface by using the diagnosis target circuit set in one variable part PP, and it cannot be said that the complete variable part PP is diagnosed.

For example, in consideration of the input / output signals between the variable parts PP which are vertically adjacent to each other, the diagnosis using the diagnosis target circuit including C-PP and N-PP (or S-PP) is performed. Separately, considering input and output signals between each other in the horizontal direction,
A diagnostic target circuit including C-PP and W-PP (or E-PP) is used. Furthermore, a diagnosis target circuit that simultaneously considers input / output signals between the variable parts PP that are adjacent in the vertical and horizontal directions is also required.

The present invention has been made in view of the above points, and an object thereof is to provide a reconfigurable hardware that is provided with a diagnostic mechanism and is not restricted by chip boundaries. And to provide a diagnostic method using the same.

[0035]

According to a first aspect of the present invention, there is provided a reconfiguration having a unit configuration section which is arranged in a two-dimensional array and input / output signals are exchanged between adjacent ones to realize an arbitrary logic circuit. The reconfigurable hardware is characterized in that a diagnostic peripheral mechanism that folds back signals exchanged between the adjacent unit components is provided.

According to a second aspect of the present invention, in the invention according to the first aspect, the unit constituent parts are arranged in a two-dimensional array, and input / output signals are exchanged between adjacent ones, so that an arbitrary basic logic circuit is formed. A reconfiguring device having a basic constituent part that can be configured, wherein the diagnostic peripheral mechanism folds a signal back and forth between two basic constituent parts located on the same side outside the array in the unit constituent part. With possible hardware.

The invention according to claim 3 is the invention according to claim 1 or 2.
In the invention described in paragraph 1, the reconfigurable hardware is characterized in that the diagnostic peripheral mechanism includes switching means for switching between a signal exchanged between adjacent unit components and the return signal. .

The invention according to claim 4 is the invention according to claim 1, 2 or 3, wherein the diagnostic peripheral mechanism is provided at a connection position for exchanging a control signal between the logic circuit of the unit component and the outside. Is set, the control signal is connected to the logic circuit at another position of the unit component, and the reconfigurable hardware is provided.

According to a fifth aspect of the present invention, there is provided reconfigurable hardware having a unit configuration section which is arranged in a two-dimensional array and exchanges input / output signals between adjacent ones so that an arbitrary logic circuit can be realized. The reconfigurable hardware is characterized in that a diagnostic scan mechanism for inputting / outputting a signal to / from the unit constituent unit is provided on the outermost side of the group of unit constituent units arranged in an array.

According to a sixth aspect of the present invention, in the invention according to the fifth aspect, the unit constituent parts are arranged in a two-dimensional array, and input / output signals are exchanged between adjacent unit parts, so that an arbitrary basic logic circuit is formed. The reconfigurable hardware is characterized in that it has a basic component that can be configured, and the diagnostic scan mechanism scans the basic component that is diagonally aligned in the unit component.

According to a seventh aspect of the present invention, a reconfigurable hardware diagnosing method having a unit configuration section which is arranged in a two-dimensional array and exchanges input / output signals between adjacent ones to realize an arbitrary logic circuit. In the above, in the same manner, by repeatedly diagnosing a block composed of a plurality of the unit constituent parts located at one end of the hardware as a diagnostic circuit, and duplicating the same diagnostic circuit in the direction of the other end. The diagnostic peripheral mechanism according to claim 1, 2, 3 or 4 is used as a wiring path for a diagnostic signal when the diagnostic is performed and the unit constituent portion at the other end is diagnosed. The diagnostic method is to

The invention according to claim 8 is a diagnosis of reconfigurable hardware having a unit constituent part which is arranged in a two-dimensional array and exchanges input / output signals between adjacent ones so that an arbitrary logic circuit can be realized. In the method, a diagnostic method is characterized in that the diagnostic scan mechanism according to claim 5 scans and outputs a signal with respect to the unit constituent portion to perform diagnosis.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 shows the configuration of a variable portion PP of a PCA cell 20 having a diagnostic peripheral mechanism according to the first embodiment. Here, a “diagnostic peripheral mechanism” that folds back a signal is provided around each variable portion PP of the N × N PCA cells 20 that configure the PCA chip 10, and a basic cell BC located in the peripheral portion of the variable portion PP is provided. When diagnosing, the diagnostic peripheral mechanism connects the outputs and inputs of the basic cells BC located on the same side of the variable portion PP to each other, and returns the signal. The variable part PP is one of the unit components described in the claims, and the basic cell BC is one of the basic components described in the claims.

The diagnostic peripheral mechanism X1 provided on the right side and the lower side around the variable part PP in FIG. 1 outputs from the basic cell BC (lookup table LUT therein) located there to the adjacent variable part PP. And the adjacent variable part P
The input from P to the basic cell BC is connected to the same input and the same output of the adjacent basic cell BC.
The right side and the lower side where the diagnostic peripheral mechanism X1 is provided are locations where signals are not exchanged with the built-in portion BP.

Signals are exchanged with the built-in section BP on the left side and the upper side of the variable section PP. First, the input of a signal that communicates with the outside via the built-in unit BP, that is, the signal connection from the built-in unit BP to the variable unit PP is located on the left side of the variable unit PP. Further, the output of a signal that communicates with the outside through the built-in unit BP, that is, the position where the output signal from the variable unit PP to the built-in unit BP is connected corresponds to the upper side of the variable unit PP. A diagnostic peripheral mechanism X2 is provided on the left side, and a diagnostic peripheral mechanism X3 is provided on the upper side. These diagnostic peripherals X
2 and X3 are signals input from the built-in unit BP to the basic cell BC (built-in unit BP → variable unit PP) or signals output from the basic cell BC to the built-in unit BP (variable unit PP → built-in unit BP). 2) and the return signal (basic cell BC → basic cell BC).

That is, the diagnostic peripheral mechanism X on the left side
In 2, the logical sum (o1) of the input signal (incorporated portion BP → variable portion PP, a and c in FIG. 1) fetched from the outside via the incorporated portion BP and the return signal (b and d in FIG. 1) , O2)
And the basic cell B located around the variable part PP.
Input to C.

Further, in the diagnostic peripheral mechanism X3 on the upper side, the output signal (variable portion PP → incorporating portion BP) output to the outside via the assembling portion BP is branched. One of the branch signals is used as its output signal (variable part PP → built-in part BP), and the other of the branch signals is input to the basic cell BC located in the peripheral part of the variable part PP. Regarding the connection between the built-in unit BP-variable unit PP and the adjacent variable unit PP, Japanese Patent Application No. 2001-2001
No. 142728.

FIG. 2 is a diagram showing an example in which the diagnostic peripheral mechanism X1 shown in FIG. 1 is used. The diagnosis circuit TST includes a diagnosis control unit TST1 and a diagnosis target circuit TST2, and the position of the basic cell BC to be diagnosed is the lower right corner of the variable part PP of the diagnosis target circuit TST2. As shown on the right side of FIG. 2, the basic cell BC (black portion) to be diagnosed is connected to the basic cell BC from the adjacent basic cell BC via the diagnostic peripheral mechanism X1. 2 × 2 P explained
Circuit to be diagnosed TS which required variable part PP for CA cells
T2 fits in the variable part PP of one PCA cell.

2 × 2 shown above the PP surface on the left side of FIG.
In the diagnostic circuit TST including the individual variable parts PP, the diagnostic target circuit TST2 is arranged on the upper right side. In the lower diagnostic circuit TST, the diagnosis target circuit TST2 is on the upper left side. When the PCA chip 10 has N × N variable parts PP, and this N is “a multiple of 2,” both diagnostic circuits TST perform diagnosis and duplication from the left end of the PCA chip boundary 10A. Repeatedly, the right edge of the PCA chip boundary 10A can be reached. In this way, the diagnostic circuit TST is 2 ×
Since it is possible to make a small fixed size consisting of two variable parts PP, it is possible to avoid the demerit that the interval of duplicating the diagnostic circuit TST next to the adjacent diagnostic circuit TST is enlarged when the diagnostic circuit TST for diagnosing all the variable parts PP is duplicated. Chip boundary 10A
It does not have to be restricted by.

FIG. 3 shows the same case as that of FIG. 2, but the position of the basic cell BC to be diagnosed in the diagnosis object circuit TST2 is different. The case of FIG. 3 uses the diagnostic peripherals X2 and X3, and the position of the basic cell BC to be diagnosed is
Input and output (variable part PP → built-in part B) and output (signal-built-in part BP → variable part PP) of signals exchanged with the outside through the built-in part BP
This is where P) is both. In this case, the input to the left side of the variable part PP of one PCA cell (the place corresponding to the built-in part BP → the variable part PP) uses the input that is the logical sum in the diagnostic peripheral mechanism X2. In addition, the signal output to the upper side of the PCA (where the variable unit PP → the built-in unit BP hits) is once sent to the output signal, and the diagnostic peripheral mechanism X3 branches the signal before performing the diagnosis. It is led to the cell BC.

The case shown on the right side of FIG. 3 is also a PCA.
The diagnostic target circuit TST2 fits in the variable part PP for cells,
Similar to the case of FIG. 2, as shown on the left side of FIG. 3, in the duplication used for diagnosis, it is possible to avoid the expansion of the interval for duplicating the diagnostic circuit TST to the adjacent side, and to avoid the influence of the PCA chip boundary. The diagnosis of the variable part PP can be completed.

[Specific Example of Diagnostic Peripheral Mechanism] In the diagnostic peripheral mechanism, the three necessary for performing functional diagnosis of all the basic cells BC in the diagnostic target circuit TST2 of one PCA cell.
Two functions are required. The first is, as mentioned above,
This is a return function of the input and output of the basic cell BC located around the PCA cell. In other words, it is a function of connecting the input / output of the basic cell BC in the peripheral portion within the same PCA cell at the time of diagnosis. However, in the pin assign portion that handles input / output signals with the built-in unit BP, the signal from the built-in unit BP to the variable unit PP is ORed, and the signal from the variable unit PP to the built-in unit BP is branched. And fold back.

The second is the diagnostic mode function. Switching between input / output loopback during diagnosis and input / output connection of the basic cell BC located around the PCA cell during normal operation is performed. The loopback is performed in the diagnostic mode, and the normal connection is switched to the normal mode.

The third function is to switch the pin assignment for control at two places. Variable part PP of one PCA cell
In addition to the pin assignments (PP_din, PP_dout) relating to the input / output data signals between the embedded section BP and the variable section PP, the input control signals (in_req, in_ac from the embedded section BP to the variable section PP are also included.
k) and the output control signal (out from the variable unit PP to the built-in unit BP)
_req, out_ack) exists. In addition, there is also a signal pin that is specially assigned so as to erase the route set in the built-in section BP. In the diagnosis of the basic cell BC of the portion related to the input / output located at the pin assignment of the control signal,
Since the control signal and the data signal cannot be mixed, it is necessary to replace the pin assignment of the control signal with another position in the diagnostic mode. In FIG. 4, it is assumed that these control signals are associated with the upper left corner. When diagnosing the basic cell BC other than this position, the signal of the built-in part BP shown by the broken line is folded back (the above-mentioned diagnostic peripheral mechanism X1).
The control signal is handled as it is, but when diagnosing the basic cell BC at this position, the signal turn-back (diagnosis peripheral mechanism X1) shown by the broken line is used, and at this time, the control signal is different. Handle so that the pin assignment is for the position (not shown). Note that the diagnosis of the basic cell BC of the portion related to the control signal is omitted in FIGS.

As described above, basically, due to the signal folding function and the diagnostic mode function, the diagnostic circuit having the diagnostic target circuits TST2 of various sizes as in the prior art is provided for most of the basic cells BC at the boundary of the PCA chip 10. The need to diagnose with TST is eliminated. Further, the same effect is exhibited by the control signal switching function for the basic cell BC in which the control signal is pin-assigned. With the diagnostic peripheral mechanism having the above three functions, only one diagnostic circuit TST having one PCA cell 20 as the diagnostic target circuit TST2 is prepared, and the diagnostic circuit TST having the same size is duplicated for all PCA cells to perform diagnostics. can do.

Before specifically explaining, the basic cell BC will be explained again. The variable part PP has a structure in which M × M basic cells BC are arranged in a plane, and the structure of each basic cell BC is, as shown on the right side of FIG. 4, a memory as a lookup table LUT of 4 inputs and 1 output. It consists of four blocks. The 4-bit input signal to each lookup table LUT is common, and N (top), E (right),
Input signals are output signals from the adjacent basic cells BC of W (left) and S (bottom). Each look-up table LUT outputs the content of one of 16 memory cells (SRAM) selected according to the 4-bit input signal as a 1-bit output signal.

Each output signal is logically ANDed with a 1-bit input signal LUT_connect input from the built-in portion BP before being output to the outside of the basic cell BC before being output. That is, for adjacent basic cells BC, LUT_connect
Are logically connected to each other only when is "1". This can prevent inadvertent occurrence of ring oscillation that may occur depending on the contents of the lookup table LUT.

Next, 1 in the lookup table LUT
The six SRAMs will be described. The SRAM layer of the variable part PP is
For example, a 2 ^Na word memory, an SRAM address line has Na bits, and a data line has Nd bits for both input and output. The address line (add) is divided into a row address (row_add) and a column address (col_add). The row address generates an exclusive signal at the input decoder and selects one row of the memory cells. The column address is input to the selection circuit, and Nd bit data (Mdata_I, Mdata) is selected from Nd memory cells in one row selected in the write or read direction by the 1-bit write_enable and read_enable signals.
Write or read _O).

Next, the external interface and peripheral circuits will be described. FIG. 5 shows input / output signals for one variable part PP. The external interface signals of the variable part PP are roughly classified into the following three types (i) to (iii). For details of (i) and (iii), refer to Japanese Patent Application No. 2001-1.
42728.

(I) Signal to adjacent variable part PP: As described above, the basic cells BC inside the variable part PP are connected by 1-bit input and output signals in four directions, respectively. Of the basic cells BC, the input / output ports facing the outside of the basic cell BC located at the outermost side are directly connected to the corresponding input / output ports of the external basic cell BC of another adjacent variable portion PP. It That is, when viewed from the layer of the basic cell BC, it seems as if the network (Sea of LUTs) of the basic cell BC extends beyond the boundary of the variable part PP. Looking at each variable part PP, these signals are N (upper), E (right), W (left),
There are input and output signals in each direction of S (bottom) (N_PPO, N_PPI, E_PPO, E_PPI, W_PPO, W_PPI, S_PP).
O, S_PPI).

(Ii) Memory interface signal: This memory interface signal is the SR described in the SRAM.
This is an interface signal between the AM layer and the embedded section BP.
Note that the LUT_connect described in the basic cell BC is used here.
Signals are included.

(Iii) Object interface signal between built-in part BP-variable part PP: A look-up table LUT inside the variable part PP is used to construct a functional circuit (object) by the memory interface signal of the previous section (ii). Later, this corresponds to the signal group of the interface between the functional circuit and the built-in unit BP that controls the functional circuit. As shown in FIG. 5, the breakdown of the signals is as follows: data input and output signals (PP_din, PP_dout), and one pair of these asynchronous control signals (in_req, in_ack, out_req, out_ack),
Whether a pair of signals (reset_req, reset_ack) used for initializing the asynchronous registers formed by the set of lookup tables LUT in the variable part PP and the adjacent variable part PP in the peripheral part of the variable part PP are used. , Or embedded part BP
It is composed of a select signal (sel_BP) for selecting whether to perform between and.

As shown in FIG. 4, the connection of each object interface signal on the variable part PP side is branched as it is in the output direction from some of the signals with the adjacent variable part PP described above. Regarding the input direction, the sel_BP signal is used as a selection control signal to select whether the signal from the adjacent variable unit PP is input to the variable unit PP or the object interface signal is input to the variable unit PP.

Next, the diagnostic peripheral mechanism added around the variable part PP will be described in detail. The diagnostic peripheral mechanism differs depending on the location and signal type (X1, X2, and X3 described above), and the circuit added accordingly and the operating speed to be satisfied by the circuit also differ.

First, the connection between the built-in unit BP and the variable unit PP will be described. The diagnostic peripheral mechanism required for the improvement using the replication so far is basically the variable unit PP (PC
It is provided in the outermost peripheral portion of each A cell 20). This part is also a place for connecting the built-in part BP and the variable part PP. The signal connection between the built-in part BP and the variable part PP has been described with reference to FIGS. 4 and 5. In FIGS. 4 and 5, the classification / contents of signals to be connected, and the object interface signals among them, are explained by what means are actually connected between the variable parts PP of the adjacent PCA cells. However, at this point, the points added by the diagnostic peripheral mechanism are not described.

Next, although there are various kinds of signals for connecting the built-in part BP and the variable part PP as shown in FIG. 5, another variable part PP located in the peripheral part of each variable part PP and adjacent thereto is used. Built-in part BP related to the peripheral device for diagnosis inserted between
The connection signal between the variable parts PP is limited to the object interface signal shown in FIG. Specifically, in FIG.
The diagnostic peripheral mechanism is added to the fan-out point shown in (a) and the selector SEL portion shown in (b) of FIG.

The diagnostic peripheral mechanism in each case will now be described. First, the adjacent basic cell B in the same PCA cell
FIG. 7 shows the diagnostic peripheral mechanism X1 that handles only the return of the signal between the Cs. This diagnostic peripheral mechanism X1 is shown in FIGS.
In the right side and the lower side of the variable part PP in FIG. A specific circuit example of the diagnostic peripheral mechanism X1 is shown in FIG. Basically, two selectors SEL similar to those shown in FIG. 6B are used to input / output signals to / from the basic cell BC of another adjacent PCA cell 20 during normal use, and the diagnostic peripheral mechanism X1 is used. 7 when used as
It realizes the circuit of (a).

Next, FIG. 8 shows a diagnostic peripheral mechanism X2 which receives an input signal from the built-in section BP. This diagnostic peripheral mechanism X2 is seen on the left side of the variable part PP in FIGS. As shown in FIG. 8B, the diagnostic peripheral mechanism X2 is composed of a two-stage selector SEL and one 3-input OR circuit OR. The signals A2 and B2 in FIG.
Is connected to A1 and B1 in FIG. 7 (b).

Next, FIG. 9 shows a diagnostic peripheral mechanism X3 for outputting a signal to the built-in section BP. This diagnostic peripheral mechanism X3 can be seen on the upper side of the variable portion PP in FIGS. In this diagnostic peripheral mechanism X3, four fan-outs (one to the built-in part BP and two on the same side) are provided for the output from the basic cell BC.
It is necessary to take one for each of the basic cells BC and one for the basic cells BC of the adjacent PCA cells. For this reason,
In addition to the selector SEL, an amplifier AMP for signal amplification is connected. The signals A3 and A3 in FIG. 9B are connected to the signals A1 and B1 in FIG. 7B.

Finally, the priority for the delay of velocity propagation will be described. In the connection described in FIG. 8 and FIG. 9 above, multi-stage signal connection and branching occur, but the signal propagation speed to be considered at that time depends on the connection signal with the basic cell BC between adjacent PCA cells. , The connection data signal with the built-in unit BP and the connection signal with another basic cell BC in the same PCA cell are secured in this order to ensure high speed. Is an additional signal for diagnosis, the speed requirement may be limited to a low level. This is shown in FIG.
9 (c) and 9 (c).

Here, the first embodiment will be summarized.
FIG. 10 shows input / output signals between the variable parts PP that are turned back at the time of diagnosis. The variable parts PP arranged in a two-dimensional array could be connected to the adjacent variable parts PP and exchange input / output signals in the normal state (FIG. 21). At the time of diagnosis, the input / output signal between the variable parts PP is folded back so that the input signal of a certain variable part PP becomes an output signal.

That is, normally, the C-PP is adjacent to the N
I / O signals could be exchanged with -PP, S-PP, W-PP, and E-PP. C-PP at the time of diagnosis
To N-PP, S-PP, W-PP, E-PP respectively
Output signal line to the N-PP, S-PP, W-PP, E
Switch to connect with the input signal line from -PP to C-PP.

As a result, the variable portions PP that are vertically adjacent to each other are
Input / output signals between them are C-PP to N-PP and S-.
The output signal of PP is from N-PP and S-PP to C-PP.
Given as the input signal of. Similarly, the input / output signals between them in the horizontal direction are changed from C-PP to W-PP and E-P.
The output signal of P becomes the input signal of C-PP from W-PP and E-PP. Moreover, the input / output signals folded back in both the vertical and horizontal directions are considered at the same time.

Therefore, in the diagnostic method using the duplication of the diagnostic circuit, it is possible to diagnose the individual PP over the entire surface by using the diagnostic target circuit set in one variable portion PP, and it fully functions as a complete PP diagnostic.

[Second Embodiment] FIG. 11 shows a diagnostic scan mechanism Y according to a second embodiment. Figure 11
The figure on the right shows the PP surface of the PCA chip 10.
The CA chip 10 has N × N PCA cells 20, and the variable part PP of one PCA cell 20 is M × M.
It is composed of individual basic cells BC. The diagnostic scan mechanism Y is provided on each of the left and right sides and the outer sides of the upper and lower sides of the entire PP surface including the entire variable portion PP in the PCA chip 10.

As shown on the left side of FIG. 11, the diagnostic scanning mechanism Y comprises a shift register Y1 for handling an input signal to the basic cell BC and a shift register Y2 for handling an output signal from the basic cell BC, and a PCA chip. All Ps in 10
The shift registers Y1 and Y2 are respectively connected to the input and output of the basic cell BC located at the outermost periphery of the P plane. The shift registers Y1 and Y2 can write / read data to / from the shift register from the outside by scanning in the scan path for diagnosis.

FIG. 12 is a diagram showing a specific example of the diagnostic scan mechanism Y. When diagnosing the basic cell BC, PCA
On all PP planes of the chip 10, the diagnostic logic is set for a plurality of basic cells BC to be diagnosed arranged diagonally, and for the other basic cells BC, upper, lower, left, and right wiring paths (lookup table LUT 1 input 1 output logic) is set. After setting all the PP planes in this manner, input data (diagnosis data) from the shift register Y1 of the diagnostic scan mechanism Y provided on the upper, lower, left and right sides of the entire PP plane is used as a lookup table in the basic cell BC to be diagnosed. The result is input to the LUT, the output (diagnosis result data) from the lookup table LUT is output to the shift register Y2, and diagnosis is performed.

During this diagnosis, the PP surface is treated as one unit over the entire chip, and the adjacent basic cells BC are all connected to each other for input / output. That is, it is essential to switch the diagnostic mode different from the normal use, and the scan data input / output and diagnostic execution control are performed while the diagnostic mode is set.

Next, the procedure of diagnosis by this scan will be described. The entire procedure is shown in the diagnostic time chart of FIG. The method of arranging and diagnosing the diagnostic scan mechanism Y can be roughly classified into a setting change of the PP surface and a diagnosis mode, and these are alternately repeated a necessary number of times.

In the setting change of the PP plane, memory writing (handling as RAM) is performed so as to change the logic of the lookup table LUT in the basic cells BC to be diagnosed on all PP planes and the position of the basic cell BC. . As a result,
The diagnostic logic is set in the basic cells BC arranged diagonally as shown in the lower side of FIG. However, at the beginning, there is also a meaning of initializing the entire PP plane, and all the basic cells B arranged diagonally on the PP plane
The diagnostic logic write shown in FIG.
The wiring paths shown in FIG. 12 are set in all the remaining basic cells BC on the PP surface. After the diagnosis of the individual basic cells BC to which the diagnostic logic has been written is sequentially performed by scanning, the diagnostic logic of each basic cell BC is changed and the diagnostics are similarly sequentially performed. Next, a new diagnostic logic is similarly written to a plurality of basic cells BC arranged in diagonal directions on different PP planes, and the wiring paths shown in FIG. To set. Hereinafter, this is repeated.

In the diagnostic mode, the diagnostic scan mechanism Y scan input of diagnostic data, diagnostic execution control, diagnostic diagnostic scan mechanism Y to the diagnostic scan mechanism Y while maintaining the PP plane on which diagnostic logic and wiring paths are set. The following three processes are performed for scan output of the diagnosis result of. This is sequentially repeated for each of the basic cells BC arranged in the diagonal direction. The scan input of the diagnostic data and the scan output of the diagnostic result are handled in the same way as in the general bandary scan diagnosis. The execution control of the diagnosis is performed by applying the value obtained by scanning and inputting the diagnostic data by the diagnostic scanning mechanism Y to the logic configured by the multi-stage connection of the lookup table LUT set on the PP surface, and the output result of the basic cell BC is displayed. Latching to the output of the diagnostic scan.

As described above, in the diagnostic scanning mechanism Y of the second embodiment, the setting of the PP plane once configures one basic cell BC for each row and each column, that is, the entire PP plane. When both the number of rows and the number of columns of each basic cell BC are the same, since the basic cells BC of the number of columns (or the number of rows) can be simultaneously diagnosed by scanning, a large number of locations can be diagnosed.

Now, the second embodiment will be summarized.
FIG. 14 shows a diagnostic scanning mechanism Y provided on the PP surface. The diagnostic scan mechanism Y is composed of a plurality of unit diagnostic scan mechanisms Y3 corresponding to one variable part PP.
The variable parts PP arranged in a two-dimensional array can realize arbitrary logic circuits. Also, input / output signals can be exchanged with the adjacent variable part PP. Therefore, FIG.
As shown in the upper left part of the PP plane,
A diagnostic scan mechanism Y that handles input / output signals for the outermost portion is arranged.

In order to more accurately describe the arrangement and connection of the diagnostic scan mechanism, the matrix representation is applied to each variable part PP. The top row is PP (0,0), PP (0,1),
PP (0,2), PP (0,3),… PP (0, j),… PP (0, n), and the leftmost column is PP (0,0), PP ( 1, 0), PP
(2,0), PP (3,0), ... PP (i, 0), ... PP (n, 0). Here, N × N variable parts PP are used, but the number of variable parts PP in the vertical and horizontal directions may be different.
PP (i, j), where i and j are integers less than or equal to n.

In this way, the unit diagnostic scan mechanism Y3 arranged on the outermost side of the PP plane can set / observe the input / output signal on the left side of PP (0, j). Similarly, above PP (i, 0),
The input / output signals of the right side of PP (n, j) and the lower side of PP (i, n) can be handled.

Therefore, when diagnosing PP (i, j), the circuit to be diagnosed is set in this PP (i, j) and at the same time PP (h,
The variable parts PP corresponding to k), h ≠ i, and k ≠ j are all set as a logic circuit for passing the input / output signals of the upper, lower, left and right sides. Then, input signals are set to the top and bottom of the “j” row and the left and right of the “i” column and the diagnostic scan mechanism, and the output signals obtained from the same diagnostic scan mechanism are observed.

By doing so, it becomes possible to diagnose PP (i, j). Moreover, this diagnosis can be performed simultaneously in parallel with the variable parts PP in different rows and columns.

[0088]

According to the present invention, by using the diagnostic peripheral mechanism, the basic constituent parts such as the basic cells located in the peripheral part of the unit constituent parts such as the variable part are duplicated even when the diagnosis is made. The size of the circuit to be diagnosed can be always fixed to one basic component. Therefore, as compared with the conventional technique, it is possible to duplicate the diagnostic circuit once programmed at the same interval (pitch) at the time of diagnosis, and the problem at the PCA chip boundary can be solved. As a result of this,
Since the area to be diagnosed expands in proportion to the number of basic constituent parts to be diagnosed, efficient diagnosis is possible. Also,
Since it is possible to deal with all the basic constituent parts of the unit constituent parts in the same way of duplication, preparation for this diagnosis can be facilitated.

By using the diagnostic scan mechanism, a plurality of basic constituent parts can be diagnosed at once.
Further, the problem at the boundary of the PCA chip is solved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a variable portion PP having a diagnostic peripheral mechanism according to a first embodiment.

FIG. 2 is an explanatory diagram for performing diagnosis using the diagnostic peripheral mechanism of the first embodiment.

FIG. 3 is another explanatory diagram for performing diagnosis by using the diagnostic peripheral mechanism of the first embodiment.

FIG. 4 is a specific explanatory diagram of a variable portion PP having a diagnostic peripheral mechanism according to the first embodiment.

FIG. 5 is an explanatory diagram of input / output signals of the variable section PP with respect to the built-in section PP.

FIG. 6 is an explanatory diagram of signal exchange between variable units PP and a built-in unit BP in a connection unit between adjacent variable units PP.

FIG. 7 is an explanatory diagram of signal folding between basic cells BC in the variable portion PP of the PCA cell.

FIG. 8 is an explanatory diagram of signal folding between the basic cells BC in the variable unit PP that receives a signal from the built-in unit BP.

FIG. 9 is an explanatory diagram of signal folding between the basic cells BC in the variable unit PP that outputs a signal to the built-in unit BP.

FIG. 10 is an explanatory diagram of a summary of the diagnostic peripheral mechanism of the first embodiment.

FIG. 11 is an explanatory diagram of the entire PP surface of the PCA chip having the diagnostic scan mechanism of the second embodiment.

FIG. 12 is an explanatory diagram of all PP surfaces of a PCA chip having a specific diagnostic scan mechanism of the second embodiment.

FIG. 13 is a time chart of diagnosis by the diagnostic scan mechanism.

FIG. 14 is an explanatory diagram of a summary of the diagnostic scan mechanism according to the second embodiment.

FIG. 15 is an explanatory diagram of a structure of a conventional PCA.

FIG. 16 is an explanatory diagram of a structure of a conventional PCA cell.

FIG. 17 is an explanatory diagram of conventional diagnosis.

FIG. 18 is an explanatory diagram of diagnosis by a conventional diagnosis circuit and duplication of the diagnosis circuit.

FIG. 19 is a flowchart of a conventional diagnosis procedure and an explanatory diagram of duplication.

FIG. 20 is an explanatory diagram of a problem caused by a conventional diagnosis.

FIG. 21 is an explanatory diagram of connection between adjacent PPs in normal time.

[Explanation of symbols]

10: PCA chip, 10A: chip boundary 20: PCA cells X1 to X3: diagnostic peripheral mechanism Y: diagnostic scan mechanism, Y1, Y2: shift register, Y3: unit diagnostic scan mechanism PP: variable part BP of PCA cell : PCA cell embedded part BC: Basic cell

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Nakata             2-3-1, Otemachi, Chiyoda-ku, Tokyo             Inside Telegraph and Telephone Corporation (72) Inventor Hideyuki Ito             2-3-1, Otemachi, Chiyoda-ku, Tokyo             Inside Telegraph and Telephone Corporation (72) Inventor Ryusuke Konishi             2-3-1, Otemachi, Chiyoda-ku, Tokyo             Inside Telegraph and Telephone Corporation F-term (reference) 5J042 BA01 BA02 BA09 BA19 CA00                       CA22 CA23 DA05

Claims (8)

[Claims] 1. In reconfigurable hardware having a unit constituent unit arranged in a two-dimensional array and capable of realizing an arbitrary logic circuit by exchanging input / output signals between the adjacent unit constituent units. Reconfigurable hardware that is equipped with a diagnostic peripheral that folds back and forth signals that communicate with each other. 2. The reconfigurable hardware according to claim 1, wherein the unit configuration section is arranged in a two-dimensional array, and input / output signals are exchanged between adjacent units to configure an arbitrary basic logic circuit. Reconfigurable, characterized in that the diagnostic peripheral mechanism has a basic constituent part that can be provided, and the diagnostic peripheral mechanism folds back and forth signals between two basic constituent parts located on the same side outside the array in the unit constituent part. Hardware. 3. The reconfigurable hardware according to claim 1 or 2, wherein the diagnostic peripheral mechanism includes switching means for switching between a signal exchanged between adjacent unit components and the return signal. Reconfigurable hardware characterized by comprising. 4. The reconfigurable hardware according to claim 1, 2 or 3, wherein the diagnostic peripheral mechanism is provided at a connection position for exchanging a control signal between the logic circuit of the unit component and the outside. Reconfigurable hardware, characterized in that when set, the control signal is connected to the logic circuit at another location of the unit component. 5. Reconfigurable hardware having a unit configuration unit arranged in a two-dimensional array and capable of realizing an arbitrary logic circuit by exchanging input / output signals between adjacent ones, arranged in the array form. Reconfigurable hardware, characterized in that a diagnostic scan mechanism for inputting / outputting a signal to / from the unit constituent unit is provided on the outermost side of the group of unit constituent units. 6. The reconfigurable hardware according to claim 5, wherein the unit configuration section is arranged in a two-dimensional array, and input / output signals are exchanged between adjacent units to configure an arbitrary basic logic circuit. Reconfigurable hardware having a basic configuration unit capable of performing the diagnosis, and the diagnostic scan mechanism scans the basic configuration units arranged in a diagonal direction in the unit configuration unit. 7. A method of diagnosing reconfigurable hardware, which has a unit configuration unit that is arranged in a two-dimensional array and exchanges input / output signals between adjacent ones so that an arbitrary logic circuit can be realized. A block consisting of a plurality of the unit constituent parts located at one end is diagnosed as a diagnostic circuit, and the same diagnostic circuit is repeatedly duplicated in the direction of the other end to perform the same diagnostic, A diagnostic method, wherein the diagnostic peripheral mechanism according to any one of claims 1, 2, 3 or 4 is used as a wiring path for a diagnostic signal when diagnosing a unit component portion at the other end. 8. A method of diagnosing reconfigurable hardware, comprising a unit constituent unit arranged in a two-dimensional array and exchanging input / output signals between adjacent ones so that an arbitrary logic circuit can be realized. On the other hand, a diagnostic method comprising scanning and inputting and outputting a signal by the diagnostic scan mechanism according to claim 5 or 6.