JP3855844B2 - Regulator circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a regulator circuit, and more particularly to a regulator circuit that stabilizes and outputs a DC power source using a MOS transistor.
[0002]
[Prior art]
Conventionally, there is a regulator circuit that stabilizes and outputs a DC voltage using a MOS transistor. FIG. 5 shows a circuit configuration diagram of an example of a conventional regulator circuit.
In the figure, a DC input voltage Vin is supplied to the input terminal 10 from the outside, and the terminal 11 is grounded. A reference voltage generation circuit 12 is connected between the terminals 10 and 11, and the reference voltage Vref generated by the reference voltage generation circuit 12 is supplied to the non-inverting input terminal of the error amplifier 14.
[0003]
The input terminal 10 is connected to the source and back gate of an output P-channel MOS transistor M1. In the MOS transistor M1, an error voltage is supplied to the gate, and the drain is connected to the output terminal 16. The output terminal 16 is grounded via resistors R1 and R2 connected in series, and the connection point of the resistors R1 and R2 is connected to the inverting input terminal of the error amplifier 14.
[0004]
The error amplifier 14 differentially amplifies the voltage obtained by dividing the output voltage Vout by the resistors R1 and R2 and the reference voltage Vref to generate an error voltage. This error voltage is supplied to the gate of the N-channel MOS transistor M2. The MOS transistor M2 has a source grounded, a drain connected to the gate of the MOS transistor M1, and a resistor R3 connected to the input terminal 10. The MOS transistor M2 inverts the error voltage and supplies it to the gate of the MOS transistor M1. The output terminal 16 is grounded via a capacitor Cout for voltage stabilization, and a load 18 is connected.
[0005]
Here, for example, when the voltage at the output terminal 16 increases, the divided voltage by the resistors R1 and R2 increases, the error voltage decreases, and the inversion error voltage increases. Therefore, the drain current of the MOS transistor M1 decreases and the output voltage Control is performed so that Vout decreases, and the voltage of the output terminal 16 is kept constant.
[0006]
[Problems to be solved by the invention]
In the conventional circuit of FIG. 5, a parasitic capacitance C1 exists at the gate of the output MOS transistor M1. For this reason, when the load 18 is not connected, the cut-off frequency at the output voltage Vout is sufficiently low, so that the gain at the output terminal 16 indicated by the solid line Ic in FIG. Since the phase rotation indicated by is positive, there is no possibility of oscillation. Note that broken lines Ia and Ib in FIG. 6 indicate gains at the gates of the MOS transistors M2 and M1, respectively.
[0007]
However, when the load 18 is connected, since the impedance at the gate of the MOS transistor M1 is low, the cutoff frequency at the output voltage Vout is high. At this time, since the cutoff frequencies of the gate of the MOS transistor M1 and the gate of the MOS transistor M2 are close to each other, the phase is rapidly rotated. Accordingly, there is a problem that oscillation may occur because the phase rotation indicated by the broken line IId in FIG. 7 is negative at the frequency at which the gain at the output terminal 16 indicated by the solid line IIc in FIG. 7 becomes zero. Note that broken lines IIa and IIb in FIG. 7 indicate gains at the gates of the MOS transistors M2 and M1, respectively.
[0008]
The present invention has been made in view of the above points, and an object thereof is to provide a regulator circuit that does not oscillate when a load is connected.
[0009]
[Means for Solving the Problems]
According to the first aspect of the present invention, the voltage based on the voltage of the output terminal (26) which is grounded via the voltage stabilizing capacitor (Cout) and to which the load (28) is connected and the reference voltage generating circuit (22). The error voltage is generated from the reference voltage generated in step), and the output MOS transistor (M11) whose drain and source are connected to the output terminal (26) and the input terminal (20) is connected to the output voltage in accordance with the error voltage. A regulator circuit that drives and controls the output terminal (26) to have a constant voltage , wherein the regulator circuit may oscillate due to a phase rotation that occurs when a load is connected to the output terminal ;
Impedance that is turned on when a load (28) is connected to the output terminal (26) between the gate and source of the output MOS transistor (M11) and lowers the impedance of the gate of the output MOS transistor (M11). By providing the lowering MOS transistors (M13, M14),
When a load (28) is connected to the output terminal (26), the rotation of the phase becomes positive at a frequency at which the gain at the output terminal (26) becomes zero, and oscillation can be prevented.
[0010]
Note that the reference numerals in the parentheses are given for ease of understanding, are merely examples, and are not limited to the illustrated modes.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a circuit configuration diagram of a first embodiment of a regulator circuit of the present invention. In the figure, the input terminal 20 is supplied with a DC input voltage Vin from the outside, and the terminal 21 is grounded. A reference voltage generation circuit 22 is connected between the terminals 20 and 21, and the reference voltage Vref generated by the reference voltage generation circuit 22 is supplied to the non-inverting input terminal of the error amplifier 24.
[0012]
The input terminal 20 is connected to the source and back gate of an output P-channel MOS transistor M11. In the MOS transistor M11, an error voltage is supplied to the gate, and the drain is connected to the output terminal 26. The output terminal 26 is grounded via resistors R11 and R12 connected in series, and the connection point of the resistors R11 and R12 is connected to the inverting input terminal of the error amplifier 24.
[0013]
The error amplifier 24 differentially amplifies the voltage obtained by dividing the output voltage Vout by the resistors R11 and R12 and the reference voltage Vref to generate an error voltage. This error voltage is supplied to the gate of the N-channel MOS transistor M12. The MOS transistor M12 has a source grounded, a drain connected to the gate X of the MOS transistor M11, and a resistor R13 connected to the input terminal 20. The MOS transistor M12 inverts the error voltage and supplies it to the gate of the MOS transistor M11. The output terminal 26 is grounded via a capacitor Cout for voltage stabilization, and a load 28 is connected.
[0014]
The gate and drain of a P-channel MOS transistor M13 are connected to the drain of the MOS transistor M12, and the source of the MOS transistor M13 is connected to the input terminal 20. The impedance lowering MOS transistor M13 is turned on when the load 28 is connected to the output terminal 26 and the output current Iout flows, and turned off when the load 28 is not connected to the output terminal 26.
[0015]
When the parasitic capacitance C1 exists at the gate of the output MOS transistor M11 and the load 28 is not connected, the MOS transistor M13 is off but the cut-off frequency at the output voltage Vout is sufficiently low. Since the phase rotation indicated by the broken line IIId in FIG. 2 is positive at the frequency at which the gain at the output terminal 26 indicated by the solid line IIIc is 0, there is no possibility of oscillation. 2 indicate the gains at the gates of the MOS transistors M12 and M11, respectively.
[0016]
Next, when the load 28 is connected, the MOS transistor M13 is turned on to lower the impedance at the gate of the MOS transistor M11, and the cutoff frequency at the gate of the MOS transistor M11 is increased as compared with the prior art. At the frequency at which the gain at the output terminal 26 indicated by the solid line IVc in FIG. 3 is zero, the rotation of the phase indicated by the broken line IVd in FIG. 3 becomes positive and oscillation can be prevented. Note that broken lines IVa and IVb in FIG. 3 indicate gains at the gates of the MOS transistors M12 and M11, respectively.
[0017]
Here, for example, when the voltage at the output terminal 26 rises, the divided voltage by the resistors R11 and R12 rises, the error voltage is lowered and the inversion error voltage is raised, so the drain current of the MOS transistor M11 is reduced and the output voltage is increased. Control is performed so that Vout decreases, and the voltage of the output terminal 26 is kept constant.
[0018]
FIG. 4 shows a circuit configuration diagram of a second embodiment of the regulator circuit of the present invention. In the figure, the same parts as those in FIG. In FIG. 4, a DC input voltage Vin is supplied to the input terminal 20 from the outside, and the terminal 21 is grounded. A reference voltage generation circuit 22 is connected between the terminals 20 and 21, and the reference voltage Vref generated by the reference voltage generation circuit 22 is supplied to the non-inverting input terminal of the error amplifier 24.
[0019]
The input terminal 20 is connected to the source and back gate of an output P-channel MOS transistor M11. In the MOS transistor M11, an error voltage is supplied to the gate, and the drain is connected to the output terminal 26. The output terminal 26 is grounded via resistors R11 and R12 connected in series, and the connection point of the resistors R11 and R12 is connected to the inverting input terminal of the error amplifier 24.
[0020]
The error amplifier 24 differentially amplifies the voltage obtained by dividing the output voltage Vout by the resistors R11 and R12 and the reference voltage Vref to generate an error voltage. This error voltage is supplied to the gate of the N-channel MOS transistor M12. The MOS transistor M12 has a source grounded, a drain connected to the gate X of the MOS transistor M11, and a resistor R13 connected to the input terminal 20. The MOS transistor M12 inverts the error voltage and supplies it to the gate of the MOS transistor M11. The output terminal 26 is grounded via a capacitor Cout for voltage stabilization, and a load 28 is connected.
[0021]
The drain of the MOS transistor M12 is connected to the drain of the N-channel MOS transistor M14, and the gate and source of the MOS transistor M14 are connected to the input terminal 20. The impedance lowering MOS transistor M14 is turned on when the load 28 is connected to the output terminal 26 and the output current Iout is flowing, and turned off when the load 28 is not connected to the output terminal 26.
[0022]
A parasitic capacitance C1 exists at the gate of the output MOS transistor M11. When the load 28 is not connected, the MOS transistor M14 is off, but the cut-off frequency at the output voltage Vout is sufficiently low. Therefore, the phase rotation is positive at a frequency at which the gain at the output terminal 26 is zero. There is no risk of oscillation.
[0023]
Next, when the load 28 is connected, the MOS transistor M14 is turned on to lower the impedance at the gate of the MOS transistor M11, and the cutoff frequency at the gate of the MOS transistor M11 is increased as compared with the conventional case. At a frequency at which the gain at the output terminal 26 becomes zero, the phase rotation becomes positive and oscillation can be prevented.
[0024]
Here, for example, when the voltage at the output terminal 26 rises, the divided voltage by the resistors R11 and R12 rises, the error voltage is lowered and the inversion error voltage is raised, so the drain current of the MOS transistor M11 is reduced and the output voltage is increased. Control is performed so that Vout decreases, and the voltage of the output terminal 26 is kept constant.
[0025]
【The invention's effect】
As described above, by providing an impedance lowering MOS transistor which is turned on when a load is connected to the output terminal between the gate and source of the output MOS transistor and reduces the impedance of the gate of the output MOS transistor, the output terminal is provided. When a load is connected, the rotation of the phase becomes positive at a frequency at which the gain at the output terminal becomes 0, and oscillation can be prevented.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a first embodiment of a regulator circuit of the present invention.
FIG. 2 is a diagram illustrating frequency characteristics in each part of FIG. 1 when a load is not connected.
FIG. 3 is a diagram showing frequency characteristics in each part of FIG. 1 when a load is connected.
FIG. 4 is a circuit configuration diagram of a second embodiment of the regulator circuit of the present invention.
FIG. 5 is a circuit configuration diagram of an example of a conventional regulator circuit.
6 is a diagram showing frequency characteristics in each part of FIG. 5 when a load is not connected.
7 is a diagram showing frequency characteristics in each part of FIG. 5 when a load is connected.
[Explanation of symbols]
20 Input terminal 22 Reference voltage generation circuit 24 Error amplifier 26 Output terminal 28 Load Cout Capacitor M11, M13 P-channel MOS transistors M12, M14 N-channel MOS transistors R11 to R13 Resistance

Claims (3)

An error voltage is generated from the voltage based on the voltage of the output terminal connected to the load and grounded through the voltage stabilizing capacitor and the reference voltage generated by the reference voltage generating circuit, and is connected to the output terminal and the input terminal. A regulator circuit that drives a gate of an output MOS transistor having a drain and a source connected in accordance with the error voltage and controls the output terminal voltage to be constant, and a load is connected to the output terminal In the regulator circuit that may oscillate due to the rotation of the phase that occurs when
A regulator characterized in that an impedance lowering MOS transistor is provided between the gate and source of the output MOS transistor, which is turned on when a load is connected to the output terminal and lowers the impedance of the gate of the output MOS transistor. circuit. The regulator circuit according to claim 1,
The regulator circuit, wherein the impedance lowering MOS transistor is a P-channel MOS transistor. The regulator circuit according to claim 1,
The regulator circuit, wherein the impedance lowering MOS transistor is an N-channel MOS transistor.

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