JP3853448B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

Info

Publication number
JP3853448B2
JP3853448B2 JP33955996A JP33955996A JP3853448B2 JP 3853448 B2 JP3853448 B2 JP 3853448B2 JP 33955996 A JP33955996 A JP 33955996A JP 33955996 A JP33955996 A JP 33955996A JP 3853448 B2 JP3853448 B2 JP 3853448B2
Authority
JP
Japan
Prior art keywords
memory
data
line
circuit
comparison
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33955996A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10188591A5 (enExample
JPH10188591A (ja
Inventor
哉圭 森嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP33955996A priority Critical patent/JP3853448B2/ja
Publication of JPH10188591A publication Critical patent/JPH10188591A/ja
Publication of JPH10188591A5 publication Critical patent/JPH10188591A5/ja
Application granted granted Critical
Publication of JP3853448B2 publication Critical patent/JP3853448B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP33955996A 1996-12-19 1996-12-19 半導体記憶装置 Expired - Fee Related JP3853448B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33955996A JP3853448B2 (ja) 1996-12-19 1996-12-19 半導体記憶装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33955996A JP3853448B2 (ja) 1996-12-19 1996-12-19 半導体記憶装置

Publications (3)

Publication Number Publication Date
JPH10188591A JPH10188591A (ja) 1998-07-21
JPH10188591A5 JPH10188591A5 (enExample) 2004-11-18
JP3853448B2 true JP3853448B2 (ja) 2006-12-06

Family

ID=18328623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33955996A Expired - Fee Related JP3853448B2 (ja) 1996-12-19 1996-12-19 半導体記憶装置

Country Status (1)

Country Link
JP (1) JP3853448B2 (enExample)

Also Published As

Publication number Publication date
JPH10188591A (ja) 1998-07-21

Similar Documents

Publication Publication Date Title
US5577050A (en) Method and apparatus for configurable build-in self-repairing of ASIC memories design
EP1368812B1 (en) Circuit and method for test and repair
EP0219413A2 (en) An array reconfiguration apparatus and method particularly adapted for use with very large scale integrated circuits
JPH0684393A (ja) アレイ組込み自己試験システム
JPH06216757A (ja) 故障の代替のための予備回路を備えるプログラマブル・ロジック・デバイス
US6021512A (en) Data processing system having memory sub-array redundancy and method therefor
JPH05198683A (ja) ラッチ支援ヒューズテスト回路及びラッチ支援ヒューズテスト方法
US20040015758A1 (en) Method and device for testing configuration memory cells in programmable logic devices (PLDS)
JPH11316264A (ja) 半導体装置の並列テスト回路
KR950014247B1 (ko) 다중 워드 라인 선택기를 구비한 다이내믹 랜덤 억세스 메모리 장치
US4254477A (en) Reconfigurable memory circuit
US8707114B2 (en) Semiconductor device including a test circuit that generates test signals to be used for adjustment on operation of an internal circuit
JP3022990B2 (ja) 種々の検査パターンを有する並列検査による半導体メモリの検査回路装置
EP0715178B1 (en) Integrated circuit comprising a testing pad
KR0174338B1 (ko) 간단하게 테스트할 수 있는 구성을 갖는 랜덤 액세스 메모리
US6868021B2 (en) Rapidly testable semiconductor memory device
US7134059B2 (en) Pad connection structure of embedded memory devices and related memory testing method
KR0185643B1 (ko) 반도체 메모리장치의 스트레스 전압 인가장치
JP3853448B2 (ja) 半導体記憶装置
EP0074305A2 (en) Fault isolating memory decoder
US7202692B2 (en) Semiconductor chip and method of testing the same
JP3650627B2 (ja) マトリクスメモリー
US6601194B1 (en) Circuit configuration for repairing a semiconductor memory
KR100565410B1 (ko) 리던던시 기능을 갖는 반도체 장치
KR100924579B1 (ko) 리던던시 메모리 셀 억세스 회로, 이를 포함하는 반도체메모리 장치, 및 반도체 메모리 장치의 테스트 방법

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060810

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060905

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060906

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees