JP3852335B2 - Scan path processing system, scan path processing method, and scan path processing program - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a scan path processing system, a scan path processing method, and a scan path processing program, and more particularly to a scan path processing system, a scan path processing method, and a scan path processing program that execute a test at high speed.
[0002]
[Prior art]
Conventionally, a scan path circuit can automatically generate a test pattern and easily obtain a high failure detection rate by using flip-flops as shift registers during testing and combining flip-flops into a circuit. It has been widely used for LSI design. However, in spite of the demand for high-speed LSI testing as LSI speeds up, the scan circuit is operated at high speed from the area and delay overhead of the scan path circuit. It was difficult.
[0003]
For example, “ 9-171054 “Scan path configuration circuit” described in the Japanese Patent Publication No. JP-A-2001-228657 shows a scan path configuration circuit that can obtain high-speed operation during normal operation.
[0004]
[Problems to be solved by the invention]
The first problem of the above-described conventional technique is that the test signal distribution such as the shift mode cannot be performed at high speed.
[0005]
The reason for this is that although the number of F / Fs increases in the same way for large-scale LSI designs, it is not considered that the distribution delay of the test holding control signal and the shift mode control signal becomes large. . For example, if a test signal is distributed so as to enable high-speed operation such as a clock, a large area overhead is required.
[0006]
The second problem is that high-speed operation at the time of switching from scan operation to normal operation is not considered.
[0007]
This is because a general LSI tester requires several hundred to several thousand times longer than the required high-speed operation to switch the tester command between the scan operation and the normal operation.
[0008]
The third problem is that high-speed scanning operation is not considered.
[0009]
The reason is that the scan path test is not designed to operate the scan path at high speed, so the test is performed at different test rates during the scan operation and during the normal operation. This is because in such a case, a general LSI tester requires several hundred times to several thousand times the required high-speed operation for switching the test rate.
[0010]
The fourth problem is that described in the above-mentioned “ 9-171054 In the configuration as in the invention described in “Gazette”, the area overhead of the flip-flop itself is large.
[0011]
This is because the test holding control is added in addition to the shift control of the scan flip-flop itself, so that the area impact is large for an LSI design that is becoming larger and larger.
[0012]
The fifth problem is that "Japanese Patent Laid-Open No. 9-171054 In the configuration as in the invention described in the “Gazette”, the delay overhead of the flip-flop itself is large.
[0013]
The reason is that two selectors are required for the test hold control selector, the shift control selector and the flip-flop input, and a delay overhead is added to the normal data input. This is because the delay impact is large in the LSI design.
[0014]
An object of the present invention is to solve the above-described problem and to realize a system that performs a scanning operation at high speed even if the area increase is small.
[0015]
[Means for Solving the Problems]
The following are typical solutions. The first scan path processing system of the present invention includes logical connection information including connection information of design logic, technology information including block size, terminal position information used in the logical connection information, and logic design information. A terminal assigned from the restriction, a timing constraint including a delay value between F / Fs, and a placement processing unit that places a block based on the timing constraint, and a placement result of the placement processing unit once, A scan path replacement processing unit that cuts the scan path and changes the scan path connection so as to shorten the scan path wiring length, and a delay between scan F / Fs with respect to the scan path changed by the scan path replacement processing unit When the delay between the scan path delay calculation processing unit that calculates the scan F / F and the scan F / F does not satisfy the required value, the scan F / F is And having a scan F / F insertion processing unit for pressure.
[0016]
A second scan path processing system according to the present invention includes logical connection information including connection information of design logic, technology information including block size, terminal position information used in the logical connection information, and logic design information. A terminal allocated from the constraint, a timing constraint including a delay value between F / Fs is input, a placement processing unit that places blocks based on the timing constraint, a shift mode distribution processing unit that distributes the shift mode, and a shift Calculating a delay value of the mode distribution tree, determining whether or not the required value is satisfied, and when not satisfying the required value, a shift mode distribution delay calculation processing unit that causes the shift mode distribution processing unit to perform redistribution; It is characterized by having.
[0017]
The third scan path processing system according to the present invention includes logical connection information including connection information of design logic, technology information including block size, terminal position information used in the logical connection information, and logic design information. Terminals allocated from the constraints, timing constraints including delay values between F / Fs are input, and a placement processing unit that places blocks based on the timing constraints, and for ordering one shift mode from scan-out The shift mode distribution processing unit that distributes the shift mode so as to insert the F / F and the delay value of the shift mode distribution tree are calculated to determine whether the required value is satisfied, and the required value is not satisfied A shift mode distribution delay calculation processing unit that causes the shift mode distribution processing unit to perform redistribution.
[0018]
The fourth scan path processing system of the present invention includes logical connection information including connection information of design logic, technology information including block size, terminal position information used in the logical connection information, and logic design information. A terminal assigned from the restriction, a timing constraint including a delay value between F / Fs, and a placement processing unit that places a block based on the timing constraint, and a placement result of the placement processing unit once, A scan path replacement processing unit that cuts the scan path and changes the scan path connection so as to shorten the scan path wiring length, and a delay between scan F / Fs with respect to the scan path changed by the scan path replacement processing unit When the delay between the scan path delay calculation processing unit for calculating the scan F / F and the scan F / F does not satisfy the required value, the scan F / F And having a drive buffer insertion processing unit for a scan path drive buffer on the path insertion.
[0019]
A fifth scan path processing system according to the present invention includes logical connection information including connection information of design logic, size of blocks used in the logical connection information, technology information including information on terminal positions, and logic design information. A terminal assigned from the restriction, a timing constraint including a delay value between F / Fs, and a placement processing unit that places a block based on the timing constraint, and a placement result of the placement processing unit once, A scan path replacement processing unit that cuts the scan path and changes the scan path connection so as to shorten the scan path wiring length, and a delay between scan F / Fs with respect to the scan path changed by the scan path replacement processing unit When the delay between the scan path delay calculation processing unit that calculates the scan F / F and the scan F / F does not satisfy the required value, the scan F / F is The delay value of the scan F / F insertion processing unit to be added, the shift mode distribution processing unit for distributing the shift mode, and the distribution tree of the shift mode is calculated, it is determined whether the required value is satisfied, and the required value is satisfied If not, a shift mode distribution delay calculation processing unit that causes the shift mode distribution processing unit to perform redistribution is provided.
[0020]
A sixth scan path processing system according to the present invention includes logical connection information including connection information of design logic, technology information including block size, terminal position information used in the logical connection information, and logic design information. A terminal assigned from the restriction, a timing constraint including a delay value between F / Fs, and a placement processing unit that places a block based on the timing constraint, and a placement result of the placement processing unit once, A scan path replacement processing unit that cuts the scan path and changes the scan path connection so as to shorten the scan path wiring length, and a delay between scan F / Fs with respect to the scan path changed by the scan path replacement processing unit When the delay between the scan path delay calculation processing unit that calculates the scan F / F and the scan F / F does not satisfy the required value, the scan F / F is A scan F / F insertion processing section to be added, a shift mode distribution processing section for distributing the shift mode so as to insert an F / F for shift mode distribution in order from scan-out, and a shift mode distribution tree And a shift mode distribution delay calculation processing unit that causes the shift mode distribution processing unit to perform redistribution when the required value is not satisfied. And
[0021]
A seventh scan path processing system according to the present invention includes logical connection information including connection information of design logic, technology information including block size, terminal position information used in the logical connection information, and logic design information. A terminal assigned from the restriction, a timing constraint including a delay value between F / Fs, and a placement processing unit that places a block based on the timing constraint, and a placement result of the placement processing unit once, A scan path replacement processing unit that cuts the scan path and changes the scan path connection so as to shorten the scan path wiring length, and a delay between scan F / Fs with respect to the scan path changed by the scan path replacement processing unit When the delay between the scan path delay calculation processing unit for calculating the scan F / F and the scan F / F does not satisfy the required value, the scan F / F A drive buffer insertion processing unit that inserts a drive buffer on the scan path path of the scan buffer, and a scan F / F insertion processing unit that adds a scan F / F when the required value is not satisfied when the drive buffer is inserted. It is characterized by.
[0022]
An eighth scan path processing system according to the present invention includes logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including information on terminal positions, and logic design information. A terminal assigned from the restriction, a timing constraint including a delay value between F / Fs, and a placement processing unit that places a block based on the timing constraint, and a placement result of the placement processing unit once, A scan path replacement processing unit that cuts the scan path and changes the scan path connection so as to shorten the scan path wiring length, and a delay between scan F / Fs with respect to the scan path changed by the scan path replacement processing unit When the delay between the scan path delay calculation processing unit for calculating the scan F / F and the scan F / F does not satisfy the required value, the scan F / F A drive buffer insertion processing unit for inserting a drive buffer on the scan path path, a scan F / F insertion processing unit for adding a scan F / F if the drive buffer insertion does not satisfy the required value, and a scan-out The shift mode distribution processing unit that distributes the shift mode so that one F / F for distributing the shift mode is inserted, and the delay value of the shift mode distribution tree is calculated, and whether the required value is satisfied A shift mode distribution delay calculation processing unit that causes the shift mode distribution processing unit to perform redistribution when the requested value is not satisfied.
[0023]
A first scan path processing method according to the present invention includes logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including terminal position information, and logic design information. A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure If the delay between the scan path delay calculation processing procedure and the scan F / F does not satisfy the required value, the scan F delay Characterized in that it comprises a scan F / F insertion process procedure for adding a F.
[0024]
The second scan path processing method of the present invention includes logical connection information including connection information of design logic, technology information including block size, terminal position information used in the logical connection information, and logic design information. A terminal assigned from the restriction, a timing constraint including a delay value between F / Fs, an arrangement processing procedure for arranging blocks based on the timing constraint, a shift mode distribution processing procedure for distributing a shift mode, and a shift Calculating a delay value of the mode distribution tree, determining whether or not the required value is satisfied, and if not satisfying the required value, a shift mode distribution delay calculation processing procedure for causing the shift mode distribution processing procedure to perform redistribution; It is characterized by including.
[0025]
A third scan path processing method according to the present invention includes logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including information on terminal positions, and logic design information. Terminals allocated from constraints, timing constraints including delay values between F / Fs are input, an arrangement processing procedure for arranging blocks based on the timing constraints, and an order from scan-out for one shift mode distribution The shift mode distribution processing procedure for distributing the shift mode so as to insert the F / F and the delay value of the shift mode distribution tree are calculated to determine whether the required value is satisfied, and the required value is not satisfied The shift mode distribution processing procedure includes a shift mode distribution delay calculation processing procedure for causing redistribution.
[0026]
According to a fourth scan path processing method of the present invention, logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including information of terminal positions, and logic design A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure The scan path delay calculation processing procedure for calculating the scan path and the scan F / F delay when the delay does not satisfy the required value / Characterized in that it comprises a drive buffer insertion procedure in the scan path on the path between F to insert the driving buffer.
[0027]
According to a fifth scan path processing method of the present invention, logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including information on terminal positions, and logic design A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure If the delay between the scan path delay calculation processing procedure and the scan F / F does not satisfy the required value, the scan F delay The scan F / F insertion processing procedure for adding F, the shift mode distribution processing procedure for distributing the shift mode, and the delay value of the shift mode distribution tree are calculated to determine whether the required value is satisfied, and the required value If the condition is not satisfied, the shift mode distribution processing procedure includes a shift mode distribution delay calculation processing procedure for causing redistribution.
[0028]
According to a sixth scan path processing method of the present invention, logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including terminal position information, and logic design A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure If the delay between the scan path delay calculation processing procedure and the scan F / F does not satisfy the required value, the scan F delay A scan F / F insertion processing procedure for adding F, a shift mode distribution processing procedure for distributing a shift mode so as to insert one shift mode distribution F / F in order from scan-out, and a shift mode Calculating a delay value of the distribution tree, determining whether or not the required value is satisfied, and including a shift mode distribution delay calculating process procedure for causing the shift mode distributing process procedure to perform redistribution when the required value is not satisfied It is characterized by.
[0029]
According to a seventh scan path processing method of the present invention, there is provided logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and logic design information. A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure The scan path delay calculation processing procedure for calculating the scan path and the scan F / F delay when the delay does not satisfy the required value A drive buffer insertion processing procedure for inserting a drive buffer on the scan path path between / F, and a scan F / F insertion processing procedure for adding a scan F / F if the drive buffer insertion does not satisfy the required value It is characterized by including.
[0030]
An eighth scan path processing method according to the present invention includes logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including information on terminal positions, and logic design information. A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure The scan path delay calculation processing procedure for calculating the scan path and the scan F / F delay when the delay does not satisfy the required value A drive buffer insertion processing procedure for inserting a drive buffer on the scan path path between / F, and a scan F / F insertion processing procedure for adding a scan F / F if the drive buffer insertion does not satisfy the required value , Order from scan-out-shift mode distribution processing procedure for distributing the shift mode so that one F / F for shift mode distribution is inserted, and the delay value of the shift mode distribution tree is calculated, and the required value is calculated A shift mode distribution delay calculation processing procedure for redistributing the shift mode distribution processing procedure when it is determined whether or not the required value is not satisfied is included.
[0031]
The first scan path processing program of the present invention includes logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including information on terminal positions, and logic design information. A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure The scan path delay calculation processing procedure for calculating the scan path and the delay between the scan F / F does not satisfy the required value, the scan Wherein the executing of the scan F / F insertion process procedure for adding a F / F on the computer.
[0032]
The second scan path processing program of the present invention includes logical connection information including connection information of design logic, technology information including block size, terminal position information used in the logical connection information, and logic design information. A terminal assigned from the restriction, a timing constraint including a delay value between F / Fs, an arrangement processing procedure for arranging blocks based on the timing constraint, a shift mode distribution processing procedure for distributing a shift mode, and a shift Calculating a delay value of the mode distribution tree, determining whether or not the required value is satisfied, and if not satisfying the required value, a shift mode distribution delay calculation processing procedure for causing the shift mode distribution processing procedure to perform redistribution; The computer is executed.
[0033]
The third scan path processing program of the present invention includes logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including information on terminal positions, and logic design information. Terminals allocated from constraints, timing constraints including delay values between F / Fs are input, an arrangement processing procedure for arranging blocks based on the timing constraints, and an order from scan-out for one shift mode distribution The shift mode distribution processing procedure for distributing the shift mode so as to insert the F / F and the delay value of the shift mode distribution tree are calculated to determine whether the required value is satisfied, and the required value is not satisfied A shift mode distribution delay calculation processing procedure that causes the shift mode distribution processing procedure to perform redistribution. To.
[0034]
A fourth scan path processing program of the present invention includes logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including terminal position information, and logic design information. A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure If the delay between scan path delay calculation processing procedure and the scan F / F does not satisfy the required value, Characterized in that to execute the driving buffer insertion processing procedure for inserting a driving buffer on the scan path route between catcher down F / F on the computer.
[0035]
The fifth scan path processing program of the present invention includes logical connection information including connection information of design logic, technology information including block size, terminal position information used in the logical connection information, and logic design information. A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure The scan path delay calculation processing procedure for calculating the scan path and the delay between the scan F / F does not satisfy the required value, the scan The scan F / F insertion processing procedure for adding the F / F, the shift mode distribution processing procedure for distributing the shift mode, and the delay value of the distribution tree of the shift mode are calculated to determine whether the required value is satisfied. When the required value is not satisfied, the computer is caused to execute a shift mode distribution delay calculation processing procedure for causing the shift mode distribution processing procedure to perform redistribution.
[0036]
A sixth scan path processing program according to the present invention includes logical connection information including connection information of design logic, size of a block used in the logical connection information, technology information including information on terminal positions, and logic design information. A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure The scan path delay calculation processing procedure for calculating the scan path and the delay between the scan F / F does not satisfy the required value, the scan A scan F / F insertion processing procedure for adding F / Fs, and a shift mode distribution processing procedure for distributing a shift mode so as to insert one F / F for shift mode distribution in order from scan-out, A shift mode distribution delay calculation processing procedure for calculating a delay value of the shift mode distribution tree, determining whether or not the required value is satisfied, and re-distributing the shift mode distribution processing procedure if the required value is not satisfied; Is executed by a computer.
[0037]
The seventh scan path processing program according to the present invention includes logical connection information including connection information of design logic, technology information including size of a block used in the logical connection information, terminal position information, and logic design information. A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure If the delay between scan path delay calculation processing procedure and the scan F / F does not satisfy the required value, Drive buffer insertion processing procedure for inserting the drive buffer on the scan path path between the scan F / Fs, and scan F / F insertion for adding a scan F / F if the drive buffer insertion does not satisfy the required value The processing procedure is executed by a computer.
[0038]
An eighth scan path processing program according to the present invention includes logical connection information including connection information of design logic, technology information including block size, terminal position information used in the logical connection information, and logic design information. A timing constraint including a terminal allocated from the constraint and a delay value between F / Fs is input, and a placement processing procedure for placing blocks based on the timing constraint, and a placement result of the placement processing procedure, once, Scan path replacement processing procedure for cutting scan path and changing scan path connection so as to shorten scan path wiring length, and delay between scan F / Fs for scan path changed by scan path replacement processing procedure If the delay between scan path delay calculation processing procedure and the scan F / F does not satisfy the required value, Drive buffer insertion processing procedure for inserting the drive buffer on the scan path path between the scan F / Fs, and scan F / F insertion for adding a scan F / F if the drive buffer insertion does not satisfy the required value A processing procedure, a shift mode distribution processing procedure for distributing a shift mode so as to insert an F / F for shift mode distribution in order from a scan-out, and a delay value of a shift mode distribution tree; It is characterized in that it is determined whether or not the required value is satisfied, and when the required value is not satisfied, the computer executes a shift mode distribution delay calculation processing procedure for causing the shift mode distribution processing procedure to perform redistribution.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
Next, a first embodiment of the present invention will be described in detail with reference to the drawings.
[0040]
FIG. 1 is a block diagram showing the configuration of the first exemplary embodiment of the present invention.
[0041]
Referring to FIG. 1, the first embodiment of the present invention includes logical connection information 10, technology information 20, timing constraints 30, a scan path processing device 40, and an arrangement result 50.
[0042]
The scan path processing device 40 receives the logical connection information 10, the technology information 20, and the timing constraint 30, and performs placement based on the timing constraint 30, and a placement result of the placement processing unit 41. Once, the scan path is cut and the scan path connection processing unit 42 changes the scan path connection so that the scan path wiring length is shortened, and the scan path changed by the scan path replacement processing unit 42 A scan path delay calculation processing unit 43 that calculates a delay between F (flip flops), and a scan F / F insertion that adds a scan F / F when a delay between scan F / Fs does not satisfy a required value And a processing unit 44.
[0043]
The logical connection information 10 is a file including connection information between primitives (blocks) of design logic.
[0044]
FIG. 3 is an explanatory diagram showing the contents of the logic circuit and the logic connection information 10.
[0045]
Referring to FIG. 3A, the logic circuit is connected to the F / F of name AAA (block name is SFF) and F / F of name BBB (block name is SFF). The data input terminal, the SI terminal is a scan data input terminal, the SMC terminal is a shift mode input terminal, the C terminal is a clock (CLOCK) input terminal, and the DO terminal is a data output terminal. Referring to FIG. 3B, as shown in FIG. 3A, the signal names INDATA1, SCANIN1, SFTMODE, CLOCK, and OUTDATA1 are respectively connected to the DI, SI, SMC, C, and DO terminals of AAA. The signal names INDATA2, OUTDATA1, SFTMODE, CLOCK, and OUTDATA2 are connected to the DI, SI, SMC, C, and DO terminals of the BBB, respectively.
[0046]
The technology information 20 is a file that includes information on the size and terminal position of the primitive used in the logical connection information 10 in addition to the size, wiring width, and power supply of the base of the LSI.
[0047]
FIG. 4 is an explanatory diagram showing the contents of the technology information 20.
[0048]
Referring to FIG. 4, the information of the block name SFF in FIG. 3 is that the reference transistor size TRSIZE is a × b, and the relationship DELAY between the wiring length and the delay value is f (l) (where l is from the output) F (l) is a function with l as a variable), the block definition identifier is COMPONENT_DEFINE, the block name definition NAME is SFF, and the size definition SIZE is A The pin definition PIN is DI, SI, SMC, C, DO, and the delay definition DELAY is c, f, e, f,... (These values are the delay time from the input, the setup time. , Hold time, etc.).
[0049]
The timing constraint 30 is a file including delay values assigned from design constraints with respect to paths between design logic input terminals and F / F, between F / F and F / F, and between F / F and output terminals.
[0050]
FIG. 5 is an explanatory diagram showing the contents of the timing constraint 30.
[0051]
Referring to FIG. 5, the clock cycle clock is g [ps], and n cycle paths nTG, X *, Y *.
[0052]
The placement processing unit 41 is used in the logical connection information 10 so as to satisfy the delay value indicated in the timing constraint 30 after the placement of the external terminals and the placement of the hard macro such as the RAM according to the technology information 20. A primitive including an F / F is placed. Subsequently, the scan path replacement processing unit 42 refers to the F / F arrangement result, peels off the already connected scan path, and changes the scan path connection so that the scan path wiring length as the LSI is shortened. To do. Further, the scan path delay calculation processing unit 43 calculates the scan path delay for each of the exchanged scan F / Fs, and determines whether or not the required value of the high-speed test is satisfied. If not, the scan F / F insertion processing unit 44 inserts a scan F / F in the vicinity of the scan path route.
[0053]
Next, the operation of the first exemplary embodiment of the present invention will be described with reference to the drawings.
[0054]
FIG. 2 is a flowchart showing the operation of the first exemplary embodiment of the present invention.
[0055]
Referring to FIG. 2, the arrangement processing unit 41 of the scan path processing device 40 first reads the logical connection information 10, the technology information 20, and the timing constraint 30 (step A1 to step A3 in FIG. 2). Next, the placement processing unit 41 places hard macros such as external terminals and RAM based on the technology information 20 first read in step A2 (step A4 in FIG. 2), and continues to satisfy the timing constraint 30. A primitive including an F / F used in the logical connection information 10 is arranged (step A5 in FIG. 2).
[0056]
Next, the scan path replacement processing unit 42 pays attention to the F / F arrangement result, and changes the scan path connection order, that is, the scan path replacement so that the scan path wiring length of the entire LSI is shortened. Perform (step A6 in FIG. 2). Next, the scan path delay calculation processing unit 43 calculates the scan path delay between the scan F / Fs (step A7 in FIG. 2), and determines whether the delay value satisfies the required value for the high speed test (FIG. 2). Step A8), if not satisfied (step A8 / NO in FIG. 2), the scan F / F insertion processing unit 44 inserts a scan F / F in the vicinity of the scan path path between the scan F / Fs (FIG. 2). Step A9). Next, it is determined whether or not delay processing has been performed for all scan paths (step A10 in FIG. 2). If there is still an unexecuted scan path (step A10 / NO in FIG. 2), the delay of the next scan path is determined. Return to Step A7 for calculation. When delay processing is performed for all scan paths (step A10 / YES in FIG. 2), an arrangement result 50 is created and the processing ends. If the delay value satisfies the required value for the high-speed test (step A8 / YES in FIG. 2), the process returns to step A7 for delay calculation of the next scan path.
[0057]
Next, further details will be described with reference to the drawings.
[0058]
FIG. 6 is an explanatory diagram showing scan path connections.
[0059]
FIG. 7 is an explanatory diagram showing a scan path connection method.
[0060]
Referring to FIG. 6A, the processing result of the placement processing unit 41 does not consider the F / F placement and the scan path length. In FIG. 6B, the processing result of the scan path replacement processing unit 42 considers the distance between F / Fs, and the scan path is shortened.
[0061]
FIG. 7A shows the result of the placement processing unit 41 sequentially processing the F / Fs according to an algorithm for connecting scan paths in order of increasing distance. FIG. 7B shows the result of processing performed by the placement processing unit 41 in accordance with an algorithm for connecting the scan paths in the order of the paths with the shortest distance between the F / Fs.
[0062]
FIG. 8 is an explanatory diagram showing a location targeted by the scan path delay calculation processing unit 43.
[0063]
Referring to FIG. 8, the scan path delay calculation processing unit 43 calculates the value of scan path delay (F / F internal delay, scan path wiring path delay + F / F setup time) + clock skew (FIG. 8). 2 step A7). The delay in the wiring path of the scan path at this time is obtained from the relationship between the wiring length based on the technology information 20 and the delay value (f (l) in FIG. 4) with respect to the wiring length of the X coordinate difference + Y coordinate difference.
[0064]
FIG. 9 is an explanatory diagram showing scan F / F insertion.
[0065]
Next, the required value for the high-speed test is compared with the <scan path delay + clock skew value> obtained in step A7. If the value is smaller than the required value for the high-speed test (step A8 / YES in FIG. 2), the next Returning to the scan path calculation process, if the value is large, as shown in FIG. 9, the scan F / F insertion processing unit 44 arranges the scan F / F in the vicinity of the scan path route, and connects the scan path. Do.
[0066]
Next, a second embodiment of the present invention will be described in detail with reference to the drawings.
[0067]
FIG. 10 is a block diagram showing the configuration of the second exemplary embodiment of the present invention.
[0068]
Referring to FIG. 10, the second embodiment of the present invention includes logical connection information 10, technology information 20, timing constraint 30, shift mode processing device 70, and shift mode distribution result 80. .
[0069]
The shift mode processing device 70 receives the logical connection information 10, the technology information 20, and the timing constraint 30, and performs an arrangement processing unit 41 that performs arrangement based on the timing constraint 30, and a shift mode distribution processing unit that distributes the shift mode. 72 and a shift mode distribution delay calculation processing unit 73 for determining whether or not the delay value of the distribution tree satisfies the required value of the high-speed test.
[0070]
Next, the operation of the second exemplary embodiment of the present invention will be described with reference to the drawings.
[0071]
FIG. 11 is a flowchart showing the operation of the second exemplary embodiment of the present invention.
[0072]
Referring to FIG. 11, the placement processing unit 41 of the shift mode processing device 70 first reads the logical connection information 10, the technology information 20, and the timing constraint 30 (step A1 to step A3 in FIG. 11). Next, the placement processing unit 41 places hard macros such as external terminals and RAM based on the technology information 20 first read in step A2 (step A4 in FIG. 11), and continues to satisfy the timing constraint 30. A primitive including the F / F used in the logical connection information 10 is arranged (step A5 in FIG. 11).
[0073]
Next, based on the F / F arrangement result, the shift mode distribution processing unit 72 uses the distribution F / F number (the total number of F / Fs) and the technology information 20 to distribute F with one F / F. / F number is derived, F / F for shift mode distribution is added to the design circuit in consideration of arrangement location and scan path order, and shift mode distribution including when not using F / F is configured (Step B1 in FIG. 11). Next, the shift mode distribution delay calculation processing unit 73 calculates the delay time of the distributed shift mode signal (step B2 in FIG. 11), and determines whether or not the delay time of the shift mode signal satisfies the required value for the high speed test. Judgment is made (step B3 in FIG. 11), and if satisfied (step B3 / YES in FIG. 11), the shift mode distribution result 80 is created and terminated. If not satisfied (step B3 / NO in FIG. 11), Returning to Step B1, for example, adjustment such as relaxation of the number of F / Fs that can be distributed by one F / F is performed (Step B1 in FIG. 11).
[0074]
Next, further details will be described with reference to the drawings.
[0075]
As described above, regarding the shift operation, it has become possible to make a circuit configuration capable of high-speed operation, but switching from shift mode to normal mode, normal mode to shift mode, and shift mode distribution delay require high-speed operation. It becomes. A mode switching delay time, that is, a configuration for performing shift mode distribution at high speed will be described.
[0076]
FIG. 12 shows a shift mode distribution circuit whose distribution is determined by the shift mode distribution processing unit 72.
[0077]
FIG. 13 is a block diagram showing the configuration of the F / F.
[0078]
FIG. 14 is an explanatory diagram showing a scan test operation.
[0079]
FIG. 15 is an explanatory diagram showing the operation of the test sequence.
[0080]
Referring to FIG. 12, F / Fa to i are portions of the original logic by the designer, and are F / Fs of the type shown in FIG. F / Fj to o are added in order to distribute the shift mode at high speed. F / Fj, k, l, and n are F / Fs of the type shown in FIG. F / Fm, o is a circuit that is in the shift mode when a clock is applied in the normal mode, and that does not cause the shift operation to malfunction during the shift mode, and is an F / F of the type shown in FIG.
[0081]
In FIG. 13, a selection circuit 131 is a circuit that selects DI (data input terminal) when SMC (shift mode signal) = 0, and SI (scan data input terminal) when SMC = 1. The selection circuit 132 is a circuit that selects one clamp (logic = 1) when SMC = 0, and selects SI when SMC = 1. The selection circuit 133 is a circuit that selects the output of the internal F / F when SMC = 0, and selects one clamp (logic = 1) when SMC = 1.
[0082]
Generally, the shift mode signal is distributed from the external terminal (SMC) to 1: n (F / F number). However, since the LSI is large-scale, the number of F / Fs to be mounted is increased and high speed is achieved. It becomes difficult to distribute the required operation value. Therefore, the distribution from the original external terminal is very small (in FIG. 12, only F / Fm, o), and the others distribute the F / F output as a shift mode signal (in FIG. 12, F / F). The output of Fk is distributed to F / Fa, b, c, d and e via F / Fo, and the output of F / Fj is distributed to F / Ff, g, h and i via F / Fn and m).
[0083]
In FIG. 12, scan-in (SOT) through F / Fa to F / Fl, scan-out (SOT) is taken as a scan path, and scan paths are not incorporated into F / Fm, n, and o. In addition, in order to perform the shift operation accurately, an extra clock applied is taken into consideration, and the -1 [number] F / Fs from the scan-out (SOT) are inserted into the distribution path. That is, (2-1) = 1 [pieces] of F / Fo are inserted after the F / Fk of order 2, and (3-1) = 2 [ Pieces] of F / Fn, m.
[0084]
Further, when the shift-in shift operation is completed, the shift mode distribution F / F (F / Fj, k, l) is collected on the scan-out side in order to change from the shift mode to the normal mode. For Fj, k, l, and n, the scan-in data value that is always set to the normal mode is set at the end of the scan-in, and conversely, the final F / of the shift mode distribution for changing from the normal mode to the shift mode. For F (F / Fm, o), when a clock is applied in the normal mode using a circuit as shown in FIG. 13 (3), the normal mode is one cycle, and in the next cycle, the shift mode is To be.
[0085]
Referring to FIG. 14, the hatched portion is a logic portion designed by a designer and is a circuit under test.
[0086]
The test sequence will be described with reference to FIG. Here, SMC = 0 is the normal mode, and SMC = 1 is the shift mode. The clamp block in FIG. 13 (3) has one output.
[0087]
First, by setting SMC = 0 and applying a clock, F / Fm, o is set to 1, and the shift mode is set (step C1 in FIG. 15). Since F / Fm, o is the F / F of FIG. 13 (3) type, when SMC = 0 and the clock is applied, the internal F / F is set to 1, and the output of DO is the internal It is 1 of F / F.
[0088]
Next, scan-in is performed with SMC = 1, and data is set. At this time, the scan-in data is set such that 0 is set in F / Fj, k, and l collected on the scan-out side so that the normal mode is set immediately after the scan-in shift operation is completed (step in FIG. 15). C2).
[0089]
Next, a normal operation test is performed by applying a clock with SMC = 0, and since the circuit configuration shown in FIG. 10 (3) is used at this time, the mode is switched from the normal mode to the shift mode. (Step C3 in FIG. 15).
[0090]
Further, the value of the test result is output by scanning out (step C4 in FIG. 15). By repeating this series of sequences (step C2 to step C4 in FIG. 15), more points are tested (step C5 in FIG. 15).
[0091]
FIG. 16 is a time chart showing the operation of the second exemplary embodiment of the present invention.
[0092]
Referring to FIG. 16, in the shift mode, data sequentially scanned in from F1 to F / Fa propagates through F / F and reaches F / F1 in cycle 12. In cycle 12, the normal mode is entered, and from cycle 13, the shift mode is entered again, scan-out occurs, and the outputs of F / Fl are sequentially read out.
[0093]
Next, a third embodiment of the present invention will be described in detail with reference to the drawings.
[0094]
FIG. 17 is a block diagram showing the configuration of the third exemplary embodiment of the present invention.
[0095]
Referring to FIG. 17, in the third embodiment of the present invention, a drive buffer insertion processing unit 45 is added to the first embodiment of the present invention. That is, the scan path processing device 90 receives the logical connection information 10, the technology information 20, and the timing constraint 30, and performs a placement processing unit 41 that performs placement based on the timing constraint 30, and a result of placement of the placement processing unit 41. On the other hand, once the scan path is cut and the scan path connection is changed so that the scan path wiring length is shortened, the scan path replacement processing unit 42 and the scan path changed by the scan path replacement processing unit 42 are scanned. A scan path delay calculation processing unit 43 that calculates a delay between F / Fs (flip flops), and a scan F / that adds a scan F / F when the delay between the scan F / Fs does not satisfy the required value It comprises an F insertion processing unit 44 and a drive buffer insertion processing unit 45 for adding a drive buffer for improving the delay value. .
[0096]
Next, the operation of the third exemplary embodiment of the present invention will be described in detail with reference to the drawings.
[0097]
FIG. 18 is a flowchart showing the operation of the third exemplary embodiment of the present invention.
[0098]
Referring to FIG. 18, the placement processing unit 41 of the scan path processing apparatus 90 first reads the logical connection information 10, the technology information 20, and the timing constraint 30 (step A1 to step A3 in FIG. 17). Next, the placement processing unit 41 places hard macros such as external terminals and RAM based on the technology information 20 first read in step A2 (step A4 in FIG. 17), and continues to satisfy the timing constraint 30. A primitive including the F / F used in the logical connection information 10 is arranged (step A5 in FIG. 17).
[0099]
Next, the scan path replacement processing unit 42 pays attention to the F / F arrangement result and changes the scan path connection order, that is, the scan path replacement so that the scan path wiring length of the entire LSI is shortened. This is performed (step A6 in FIG. 17). Next, the scan path delay calculation processing unit 43 calculates the scan path delay between the scan F / Fs (step A7 in FIG. 17), and determines whether the delay value satisfies the required value for the high speed test (FIG. 17). Step D1) If the requested value is not satisfied and the requested value is satisfied by the drive buffer insertion even if the scan F / F is not inserted (Step D1 / NO), the drive buffer insertion processing unit 45 A drive buffer is inserted on the scan path path between the scan F / Fs (step D2). Next, it is determined whether or not delay processing has been performed for all scan paths (step A10 in FIG. 17). If there is an unexecuted scan path (step A10 / NO in FIG. 17), the delay of the next scan path is determined. Return to Step A7 for calculation. When delay processing is performed for all scan paths (step A10 / YES in FIG. 17), an arrangement result 50 is created and the processing ends. If the delay value satisfies the required value for the high-speed test (step D1 / YES in FIG. 17), the process returns to step A7 for delay calculation of the next scan path. Further, when the required value is not satisfied by the drive buffer insertion, the scan F / F insertion processing unit 44 can also insert the scan F / F.
[0100]
Next, a specific example will be described.
[0101]
FIG. 19 shows a location targeted by the scan path delay calculation processing unit 43.
[0102]
The scan path delay calculation processing unit 43 calculates a value of scan path delay (F / F internal delay, delay in scan path wiring path + F / F setup time) + clock skew (step A7 in FIG. 17). The delay in the wiring path of the scan path at this time is obtained from the relationship between the wiring length based on the technology information 20 and the delay value (f (l) in FIG. 4) with respect to the wiring length of the X coordinate difference + Y coordinate difference.
[0103]
Next, in step D1, the value obtained in step A7 is compared with the required value of the high-speed test. If the value is smaller than the requested value, the process returns to the next scan path calculation process, and the scan F is calculated with a larger value. If the required value for high-speed operation is satisfied even if it is not / F insertion, the drive buffer is arranged in the scan path path by the drive buffer insertion processing unit 45 as shown in FIG.
[0104]
For example, f (l)> f (l1) + f (l2) + f (l3) + d1 + d2. Here, l, l1, l2, and l3 are wiring lengths, and d1 and d2 are drive buffer delay times.
[0105]
Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings.
[0106]
In the fourth embodiment of the present invention, the logical connection information 10, the technology information 20, and the timing constraint 30 are input, and a placement processing procedure for placing blocks based on the timing constraint 30 (step A4 in FIG. 2), A scan path replacement processing procedure for cutting the scan path once and changing the scan path connection so as to shorten the scan path wiring length with respect to the result of the placement processing procedure placement (step A6 in FIG. 2), and the scan path replacement A scan path delay calculation processing procedure for calculating the delay between the scan F / Fs for the scan path changed by the processing procedure (step A7 in FIG. 2), and when the delay between the scan F / Fs does not satisfy the required value. And a drive buffer insertion processing procedure for inserting a drive buffer on the scan path path between the scan F / Fs (step D1 in FIG. 18) ) When the drive buffer insertion does not satisfy the required value, the scan F / F insertion processing procedure for adding the scan F / F (step A9 in FIG. 2), and the shift mode distribution in the order of scan-one The shift mode distribution processing procedure for distributing the shift mode so as to insert the F / F for use (step B1 in FIG. 11), the delay value of the shift mode distribution tree is calculated, and it is determined whether the required value is satisfied. When the required value is not satisfied, the shift mode distribution processing procedure includes a shift mode distribution delay calculation processing procedure (steps B2 and B3 in FIG. 11).
[0107]
Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings.
[0108]
In the fifth embodiment of the present invention, the logical connection information 10, the technology information 20, and the timing constraint 30 are input, and the placement processing procedure for placing blocks based on the timing constraint 30 (step A4 in FIG. 2), A scan path replacement processing procedure for cutting the scan path once and changing the scan path connection so as to shorten the scan path wiring length with respect to the result of the placement processing procedure placement (step A6 in FIG. 2), and the scan path replacement A scan path delay calculation processing procedure for calculating the delay between the scan F / Fs for the scan path changed by the processing procedure (step A7 in FIG. 2), and when the delay between the scan F / Fs does not satisfy the required value. And a drive buffer insertion processing procedure for inserting a drive buffer on the scan path path between the scan F / Fs (step D1 in FIG. 18) ) When the drive buffer insertion does not satisfy the required value, the scan F / F insertion processing procedure for adding the scan F / F (step A9 in FIG. 2), and the shift mode distribution in the order of scan-one The shift mode distribution processing procedure for distributing the shift mode so as to insert the F / F for use (step B1 in FIG. 11), the delay value of the shift mode distribution tree is calculated, and it is determined whether the required value is satisfied. If the required value is not satisfied, a shift mode distribution delay calculation processing procedure (steps B2 and B3 in FIG. 11) for causing the shift mode distribution processing procedure to perform redistribution and the computer (for example, scan path processing device 40) are executed. It is a program to let you.
[0109]
【The invention's effect】
The first effect of the present invention is that the shift operation can be performed at high speed.
[0110]
The reason is that, regarding data transfer between flip-flops during the shift operation, it is determined whether it can operate at high speed, and if it is not possible, one or more scan F / Fs or drive buffers are inserted. It is.
[0111]
The second effect is that a shift path signal can be distributed at high speed, so that a scan path circuit capable of switching between normal operation and shift operation at high speed can be configured.
[0112]
This is because the F / F is used for the distribution in the shift mode and the distribution through the F / F is performed without using the F / F in consideration of the scan path order.
[0113]
The third effect is that there is no area overhead and delay overhead of the F / F itself.
[0114]
The reason is that the shift mode is distributed at high speed and the shift mode is changed to the normal mode after the shift operation is completed, and the normal mode is changed to the shift mode after the clock is applied in the normal mode. This is because no additional circuit is required for the F / F.
[0115]
A fourth effect is that a test in which both the shift operation and the normal operation are performed at high speed is possible.
[0116]
This is because there is no need to switch the test rate in the LSI tester.
[0117]
The fifth effect is that a test that does not use switching of tester commands of the LSI tester can be performed at a higher speed.
[0118]
The reason for this is that LSI testers require several hundred to several thousand times longer than required high-speed operations to switch between scan operations and normal operation tester commands. This is because the switching between the scan operation and the normal operation can be performed at high speed by the test sequence without using the tester command switching of the LSI tester.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.
FIG. 2 is a flowchart showing the operation of the first exemplary embodiment of the present invention.
FIG. 3 is an explanatory diagram showing the contents of a logic circuit and logic connection information 10;
FIG. 4 is an explanatory diagram showing the contents of technology information.
FIG. 5 is an explanatory diagram showing the contents of timing constraints.
FIG. 6 is an explanatory diagram showing scan path connections;
FIG. 7 is an explanatory diagram showing a scan path connection method;
FIG. 8 is an explanatory diagram showing locations targeted by a scan path delay calculation processing unit;
FIG. 9 is an explanatory diagram showing scan F / F insertion.
FIG. 10 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.
FIG. 11 is a flowchart showing the operation of the second exemplary embodiment of the present invention.
FIG. 12 is a shift mode distribution circuit whose distribution is determined by a shift mode distribution processing unit.
FIG. 13 is a block diagram illustrating a configuration of an F / F.
FIG. 14 is an explanatory diagram showing a scan test operation.
FIG. 15 is an explanatory diagram showing the operation of a test sequence.
FIG. 16 is a time chart showing the operation of the second exemplary embodiment of the present invention.
FIG. 17 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.
FIG. 18 is a flowchart showing the operation of the second exemplary embodiment of the present invention.
FIG. 19 is an explanatory diagram showing locations targeted by a scan path delay calculation processing unit;
[Explanation of symbols]
10 Logical connection information
20 Technology Information
30 Timing constraints
40 Scampus processing equipment
41 Arrangement processing part
42 Scan campus replacement processing department
43 Scan campus delay calculation processing part
44 Scan F / F insertion processing part
45 Drive buffer insertion processing section
50 Placement result
70 Shift mode processor
72 Shift mode distribution processor
73 Shift Mode Distribution Delay Calculation Processing Unit
80 Shift mode distribution result
90 Scan campus processing equipment

Claims (15)

  Logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and terminals allocated from logical design constraints, delay between F / Fs Input a timing constraint including a value, calculate a delay value of a placement mode processing unit that performs block placement based on the timing constraint, a shift mode distribution processing unit that distributes a shift mode, and a shift mode distribution tree. A scan path processing system comprising: a shift mode distribution delay calculation processing unit that determines whether or not a value is satisfied and causes the shift mode distribution processing unit to perform redistribution when the required value is not satisfied. Logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and terminals allocated from logical design constraints, delay between F / Fs Input a timing constraint including a value, an arrangement processing unit for arranging blocks based on the timing constraint, and one or more first shift mode distribution F / Fs are added to the first shift mode distribution A shift mode distribution processing unit that distributes the shift mode so as to insert the second shift mode distribution F / F in order from the scan-out for each F / F, and a shift mode distribution tree A delay value is calculated, it is determined whether the required value is satisfied, and if the required value is not satisfied, the shift mode distribution processing unit that causes the shift mode distribution processing unit to perform redistribution. A scan path processing system comprising a distribution delay calculation processing unit.   Logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and terminals allocated from logical design constraints, delay between F / Fs A timing constraint including a value is input, a placement processing unit that places blocks based on the timing constraint, and a scan path is cut once with respect to a placement result of the placement processing unit, and a scan path wiring length is shortened A scan path replacement processing unit for changing the scan path connection, a scan path delay calculation processing unit for calculating a delay between scan F / Fs for the scan path changed by the scan path replacement processing unit, and a scan When the delay between F / Fs does not satisfy the required value, a scan F / F insertion processing unit for adding a scan F / F, and a shift A shift mode distribution processing unit for distributing a mode and a delay value of the distribution tree of the shift mode, determine whether or not the required value is satisfied, and if the required value is not satisfied, the shift mode distribution processing unit A scan path processing system comprising: a shift mode distribution delay calculation processing unit for performing redistribution. Logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and terminals allocated from logical design constraints, delay between F / Fs A timing constraint including a value is input, a placement processing unit that places blocks based on the timing constraint, and a scan path is cut once with respect to a placement result of the placement processing unit, and a scan path wiring length is shortened A scan path replacement processing unit for changing the scan path connection, a scan path delay calculation processing unit for calculating a delay between scan F / Fs for the scan path changed by the scan path replacement processing unit, and a scan If the delay between F / F does not satisfy the required value, and the scan F / F insertion processing unit for adding the F / F for the scan, one or more The first shift mode distribution F / Fs are added, and each of the first shift mode distribution F / Fs in order from the scan-out for each of the first shift mode distribution F / Fs is one second shift mode distribution F / F. A shift mode distribution processing unit that distributes the shift mode so as to insert the delay mode, and calculates a delay value of the shift mode distribution tree, determines whether the required value is satisfied, and if the required value is not satisfied, the shift A scan path processing system comprising: a shift mode distribution delay calculation processing unit that causes the mode distribution processing unit to perform redistribution. Logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and terminals allocated from logical design constraints, delay between F / Fs A timing constraint including a value is input, a placement processing unit that places blocks based on the timing constraint, and a scan path is cut once with respect to a placement result of the placement processing unit, and a scan path wiring length is shortened A scan path replacement processing unit for changing the scan path connection, a scan path delay calculation processing unit for calculating a delay between scan F / Fs for the scan path changed by the scan path replacement processing unit, and a scan When the delay between F / Fs does not satisfy the required value, a drive buffer is inserted on the scan path path between the scan F / Fs That the driving buffer insertion processing unit, in the insertion of the driving buffer is not satisfied required value, and the scan F / F insertion processing unit for adding the F / F for scanning one or more of the first shift mode distribution for F / F is added, and the shift mode is distributed so that each of the first shift mode distribution F / Fs is inserted in order from the scan-out-one second shift mode distribution F / F. The shift mode distribution processing unit and the shift mode distribution tree delay value are calculated to determine whether the required value is satisfied. If the required value is not satisfied, the shift mode distribution processing unit performs redistribution. A scan path processing system comprising: a mode distribution delay calculation processing unit. The placement processing unit includes logical connection information including design logic connection information, size of a block used in the logical connection information, technology information including information on terminal positions, and terminals allocated based on logical design constraints, F A placement processing procedure for inputting a timing constraint including a delay value between / F and placing a block based on the timing constraint;
A shift mode distribution processing unit in which the shift mode distribution processing unit distributes the shift mode;
The shift mode distribution delay calculation processing unit calculates a delay value of the shift mode distribution tree, determines whether or not the required value is satisfied, and if the required value is not satisfied, redistributes the shift mode distribution processing procedure. Shift mode distribution delay calculation processing procedure,
Including a scan path processing method. The placement processing unit includes logical connection information including design logic connection information, size of a block used in the logical connection information, technology information including information on terminal positions, and terminals allocated based on logical design constraints, F A placement processing procedure for inputting a timing constraint including a delay value between / F and placing a block based on the timing constraint;
The shift mode distribution processing unit adds one or more first shift mode distribution F / Fs, and each of the first shift mode distribution F / Fs in the order from the scan-out of the second shift mode distribution F / Fs . a shift mode distribution processing procedure for distributing the shift mode to insert the F / F for the shift mode distribution,
The shift mode distribution delay calculation processing unit calculates a delay value of the shift mode distribution tree, determines whether or not the required value is satisfied, and if the required value is not satisfied, redistributes the shift mode distribution processing procedure. Shift mode distribution delay calculation processing procedure,
Including a scan path processing method. The placement processing unit includes logical connection information including design logic connection information, size of a block used in the logical connection information, technology information including information on terminal positions, and terminals allocated based on logical design constraints, F A placement processing procedure for inputting a timing constraint including a delay value between / F and placing a block based on the timing constraint;
The scan path replacement processing unit once disconnects the scan path and changes the scan path connection so that the scan path wiring length is shortened with respect to the result of the placement processing procedure placement,
A scan path delay calculation processing unit that calculates a delay between scan F / Fs for the scan path changed by the scan path replacement processing procedure;
A scan F / F insertion processing unit that adds a scan F / F when a delay between the scan F / Fs does not satisfy a required value;
A shift mode distribution processing unit in which the shift mode distribution processing unit distributes the shift mode;
The shift mode distribution delay calculation processing unit calculates a delay value of the shift mode distribution tree, determines whether or not the required value is satisfied, and if the required value is not satisfied, redistributes the shift mode distribution processing procedure. Shift mode distribution delay calculation processing procedure,
Including a scan path processing method. The placement processing unit includes logical connection information including design logic connection information, size of a block used in the logical connection information, technology information including information on terminal positions, and terminals allocated based on logical design constraints, F A placement processing procedure for inputting a timing constraint including a delay value between / F and placing a block based on the timing constraint;
A scan path replacement process, in which the scan path replacement process cuts the scan path once and changes the scan path connection so that the scan path wiring length is shortened with respect to the result of the arrangement in the arrangement process procedure,
A scan path delay calculation processing unit that calculates a delay between scan F / Fs for the scan path changed by the scan path replacement processing procedure;
A scan F / F insertion processing unit that adds a scan F / F when a delay between the scan F / Fs does not satisfy a required value;
The shift mode distribution processing unit adds one or more first shift mode distribution F / Fs, and each of the first shift mode distribution F / Fs in the order from the scan-out of the second shift mode distribution F / Fs . a shift mode distribution processing procedure for distributing the shift mode to insert the F / F for the shift mode distribution,
The shift mode distribution delay calculation processing unit calculates a delay value of the shift mode distribution tree, determines whether or not the required value is satisfied, and if the required value is not satisfied, redistributes the shift mode distribution processing procedure. Shift mode distribution delay calculation processing procedure,
Including a scan path processing method. The placement processing unit includes logical connection information including design logic connection information, size of a block used in the logical connection information, technology information including information on terminal positions, and terminals allocated based on logical design constraints, F A placement processing procedure for inputting a timing constraint including a delay value between / F and placing a block based on the timing constraint;
The scan path replacement processing unit once disconnects the scan path and changes the scan path connection so that the scan path wiring length is shortened with respect to the result of the placement processing procedure placement,
A scan path delay calculation processing unit that calculates a delay between scan F / Fs for the scan path changed by the scan path replacement processing procedure;
A drive buffer insertion processing procedure for inserting a drive buffer on a scan path path between the scan F / Fs when a delay between the scan F / Fs does not satisfy a request value;
A scan F / F insertion processing unit for adding a scan F / F when the scan F / F insertion processing unit does not satisfy the required value in the drive buffer insertion;
The shift mode distribution processing unit adds one or more first shift mode distribution F / Fs, and each of the first shift mode distribution F / Fs in the order from the scan-out of the second shift mode distribution F / Fs . a shift mode distribution processing procedure for distributing the shift mode to insert the F / F for the shift mode distribution,
The shift mode distribution delay calculation processing unit calculates a delay value of the shift mode distribution tree, determines whether or not the required value is satisfied, and if the required value is not satisfied, redistributes the shift mode distribution processing procedure. Shift mode distribution delay calculation processing procedure,
Including a scan path processing method. Logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and terminals allocated from logical design constraints, delay between F / Fs A placement processing procedure for inputting a timing constraint including a value and placing a block based on the timing constraint;
A shift mode distribution processing procedure for distributing the shift mode;
A shift mode distribution delay calculation processing procedure for calculating a delay value of the shift mode distribution tree, determining whether or not the required value is satisfied, and re-distributing the shift mode distribution processing procedure if the required value is not satisfied; ,
A scan path processing program for causing a computer to execute. Logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and terminals allocated from logical design constraints, delay between F / Fs A timing constraint including a value is input, a placement processing procedure for placing blocks based on the timing constraint, and one or more first shift mode distribution F / Fs are added to the first shift mode distribution The order from the scan-out for each F / F—the shift mode distribution processing procedure for distributing the shift mode so as to insert one F / F for the second shift mode distribution, and the shift mode distribution tree A delay value is calculated to determine whether or not the required value is satisfied. If the required value is not satisfied, the shift mode distribution processing procedure performs redistribution. A scan path processing program for causing a computer to execute a command distribution delay calculation processing procedure.   Logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and terminals allocated from logical design constraints, delay between F / Fs Input a timing constraint including a value and place the block based on the timing constraint, and the result of the placement processing procedure placement is that the scan path is cut once and the scan path wiring length is short. A scan path replacement processing procedure for changing the scan path connection, a scan path delay calculation processing procedure for calculating a delay between scan F / Fs for the scan path changed by the scan path replacement processing procedure, and a scan If the delay between the F / Fs does not satisfy the required value, a scan F / F insertion process for adding a scan F / F A shift mode distribution processing procedure for distributing the shift mode, a delay value of the distribution tree of the shift mode is calculated, it is determined whether the required value is satisfied, and if the required value is not satisfied, the shift mode distribution processing A scan path processing program for causing a computer to execute a shift mode distribution delay calculation processing procedure for causing a procedure to be redistributed. Logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and terminals allocated from logical design constraints, delay between F / Fs Input a timing constraint including a value and place the block based on the timing constraint, and the result of the placement processing procedure placement is that the scan path is cut once and the scan path wiring length is short. A scan path replacement processing procedure for changing the scan path connection, a scan path delay calculation processing procedure for calculating a delay between scan F / Fs for the scan path changed by the scan path replacement processing procedure, and a scan If the delay between the F / Fs does not satisfy the required value, a scan F / F insertion process for adding a scan F / F If, by adding one or more of the first shift mode distribution F / F are, shift mode distribution order -1 second from the scan-out for each of the first shift mode distribution F / F are The shift mode distribution processing procedure for distributing the shift mode so as to insert the F / F and the delay value of the shift mode distribution tree are calculated to determine whether the required value is satisfied, and the required value is not satisfied A scan path processing program for causing a computer to execute a shift mode distribution delay calculation processing procedure for causing the shift mode distribution processing procedure to perform redistribution. Logical connection information including design logic connection information, block size used in the logical connection information, technology information including terminal position information, and terminals allocated from logical design constraints, delay between F / Fs Input a timing constraint including a value and place the block based on the timing constraint, and the result of the placement processing procedure placement is that the scan path is cut once and the scan path wiring length is short. A scan path replacement processing procedure for changing the scan path connection, a scan path delay calculation processing procedure for calculating a delay between scan F / Fs for the scan path changed by the scan path replacement processing procedure, and a scan When the delay between the F / Fs does not satisfy the required value, the drive back is on the scan path path between the scan F / Fs. A drive buffer insertion procedure of inserting the §, if the insertion of the driving buffer does not satisfy the required value, and the scan F / F insertion process procedure for adding a F / F for scanning one or more of the first shift mode distribution Shift mode so that F / F for distribution is added to each of the first shift mode distribution F / Fs in order from the scan-out to each of the first shift mode distribution F / Fs The shift mode distribution processing procedure for distributing the value and the delay value of the shift mode distribution tree are calculated to determine whether the required value is satisfied. If the required value is not satisfied, redistribution to the shift mode distribution processing procedure is performed. A scan path processing program for causing a computer to execute a shift mode distribution delay calculation processing procedure for causing

Images