JP3850761B2 - Multilevel demodulator clock recovery circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock recovery circuit of a multilevel demodulator using a multilevel modulation system, and more particularly to a stable clock by detecting a phase transmission and advance at a convergence point of a reception signal of a recovered clock and performing clock recovery. The present invention relates to a clock recovery circuit of a multi-level demodulator that enables reproduction.
[0002]
[Prior art]
Conventionally, in the clock recovery circuit of this type of demodulator, as shown in FIG. 5, the recovered clock (radio symbol CLK) is based on the timing of crossing zero of the I (in-phase wave) signal after removing the carrier component from the received signal. ) Is detected by the error detector 1 and the output of the error detector 1 is applied to the oscillator 3 via the loop filter 2 to reproduce the radio symbol CLK from the oscillator 3. ing.
[0003]
In FIG. 5, the reproduction clock (radio symbol CLK) is reproduced based on the timing of crossing zero of the I (in-phase wave) signal, but at the timing of crossing zero of the Q (quadrature wave) signal. Based on this, the radio symbol CLK may be reproduced.
[0004]
[Problems to be solved by the invention]
However, in the clock recovery circuit of the above conventional demodulator, if the QPSK signal as shown in FIG. 6 is used, the phase jitter component is small at the timing when the I signal crosses zero, so that a stable clock recovery can be achieved to some extent. In the case of a multi-level modulation system such as the 64QAM signal shown in FIG. 7, there is a large jitter component at the timing itself when the I signal crosses zero, and as a result, the wireless signal is transmitted based on the conventional phase delay or advance of the timing crossing zero. The configuration for reproducing the symbol CLK has a problem that stable clock reproduction cannot be performed.
[0005]
Accordingly, an object of the present invention is to provide a clock recovery circuit of a multilevel demodulator capable of stable clock recovery.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a storage means for storing N hard decision data obtained by sampling a received signal with a recovered clock in a clock recovery circuit of a multilevel demodulator using a multilevel modulation system; Of the N hard decision data stored in the storage means, comparison means for comparing the n (1 <n <N) th hard decision data with the hard decision data before and after the hard decision data, and the nth hard decision data Error detection means for detecting the distance between the corresponding soft decision data and its convergence point, and whether the detection output of the error detection means is output as phase information for generating the recovered clock based on the comparison output of the comparison means Determining means for determining whether or not and the sign thereof.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a clock recovery circuit of a multilevel demodulator according to the present invention will be described below in detail with reference to the accompanying drawings.
[0008]
FIG. 1 is a block diagram showing an embodiment of a digital demodulator 100 to which a clock recovery circuit of a multilevel demodulator according to the present invention is applied.
[0009]
In FIG. 1, the digital demodulator 100 includes a 0 ° distributor 11, phase detectors 12a and 12b, A / D converters 13a and 13b, a determination circuit 14, a CLK recovery circuit 15, a loop filter 16, and oscillators 17 and 90. ° Consists of a distributor 18.
[0010]
Here, the 0 ° distributor 11 distributes the received signal into two received signals having the same phase, and outputs the two received signals to the phase detector 12a and the phase detector 12b.
[0011]
The phase detector 12a and the phase detector 12b each receive two reproduced carrier signals having a 90 ° phase shift output from the 90 ° distributor 18, and each of the two reproduced carrier signals is supplied to the 0 ° distributor 11 as described above. By multiplying the two received signals output from the received signal, the received signal is phase-detected to output signals of an I (in-phase wave) signal component and a Q (quadrature wave) signal component.
[0012]
The A / D converter 13a and the A / D converter 13b synchronize the I signal component and the Q signal component output from the phase detector 12a and the phase detector 12b with the recovered clock output from the clock recovery circuit 15, respectively. Analog-to-digital conversion is performed to output a digital I signal and a digital Q signal, respectively.
[0013]
The digital I signal and digital Q signal output from the A / D converter 13a and A / D converter 13b, respectively, are added to the determination circuit 14, and the determination circuit 14 receives the input digital I signal and digital Q signal, respectively. The convergence point is determined and output as I data and Q data.
[0014]
The determination circuit 14 detects the phase of the reproduced carrier wave based on the input digital I signal and digital Q signal, and outputs the phase error as a carrier error signal.
[0015]
The carrier error signal is applied to the oscillator 17 via the loop filter 16 to control the phase of the regenerated carrier signal generated from the oscillator 17, and the regenerated carrier signal generated from the oscillator 17 is a 90 ° distributor. 18 is added.
[0016]
The digital I signal output from the A / D converter 13 a is applied to the CLK recovery circuit 15.
[0017]
The CLK recovery circuit 15 recovers a clock (radio symbol CLK) synchronized with the received signal based on the digital I signal output from the A / D converter 13a.
[0018]
The recovered clock recovered by the CLK recovery circuit 15 is applied to the A / D converter 13a and the A / D converter 13b as described above, and sampling of the digital I signal and the digital Q signal, that is, the I signal component and The timing of analog-digital conversion of the Q signal component is controlled.
[0019]
FIG. 2 is a block diagram showing a detailed configuration of the CLK recovery circuit 15 shown in FIG.
[0020]
2, the CLK recovery circuit 15 includes a determination circuit unit 151, a comparison determination unit 152, delay circuits 153a, 153b, and 153c, an error detection unit 154, a code determination unit 155, a loop filter 156, and an oscillator 157. Is done.
[0021]
Here, the determination circuit unit 151 branches and inputs the digital I signal from the A / D converter 13a shown in FIG. 1, and performs a convergence point determination with a natural code at the convergence point. As a result, the I signal after the code determination becomes a signal of 0 to 11 values as shown in FIG. In this case, the reason why it is expressed by 12 values from 0 to 11 is that this system adopts the 128QAM system.
[0022]
In this specification, data after code determination in the determination circuit unit 151 is referred to as hard decision data, and data before code determination in the determination circuit unit 151 is referred to as soft determination data.
[0023]
The hard decision data subjected to the code decision by the decision circuit unit 151 is delayed by one radio symbol clock (T) by the delay circuits 153 a and 153 b and added to the comparison decision unit 152.
[0024]
As a result, the hard decision data D-1 that has been sign-determined by the decision circuit 151, the hard decision data D0 obtained by delaying the hard decision data by one radio symbol clock (T), and the hard decision data are sent to the comparison decision unit 152. Further, hard decision data D1 delayed by one radio symbol clock (T) is input.
[0025]
The digital I signal branched from the A / D converter 13a shown in FIG. 1 is delayed by one radio symbol clock (T) by the delay circuit 153c and added to the error detection unit 154.
[0026]
The error detection unit 154 detects the distance (error) between the soft decision data D0 ′ and its convergence point based on the soft decision data D0 ′ corresponding to the hard decision data D0.
[0027]
Whether or not the comparison determination unit 152 outputs the detection output of the error detection unit 154 as phase information for generating a reproduction clock based on the hard determination data D-1, the hard determination data D0, and the hard determination data D1. And a signal for determining the sign.
[0028]
That is, the comparison / determination unit 152 compares the amplitude relationship among the hard decision data D-1, the hard decision data D0, and the hard decision data D1 at the three convergence points, and the comparison result is shown in FIG. By determining which pattern of the table shown here is applicable, whether or not to output the detection output of the error detection unit 154 as phase information for generating a reproduction clock and a signal for determining the sign thereof are output.
[0029]
Here, “0” of the output value from the comparison / determination unit 152 means that the detection output of the error detection unit 154 is not output as phase information for generating the recovered clock, and “1” is the error detection unit. This means that the detection output of 153 is output as positive phase information for generating a recovered clock, and “−1” indicates that the detection output of the error detector 154 is negative phase information for generating a recovered clock. Means to output.
[0030]
Also, in the values corresponding to the hard decision data D-1, hard decision data D0, and hard decision data D1 in the table shown in FIG. 4, "+" indicates that the hard decision data D-1 or the hard decision data D1 is the decision data D0. "-" Means that the hard decision data D-1 or the hard decision data D1 is smaller than the decision data D0, and "0" means the hard decision data D-1 or the hard decision data. This means that the data D1 is equal to the determination data D0.
[0031]
That is, in the comparison determination unit 152, for example, in FIG. 3, when performing comparison determination processing of three convergence points 2T, 3T, and 4T, the hard determination data (D−1) at the convergence point of 2T is 3T ( Since the hard decision data of the hard decision data (D1) at the convergence point of 4T is smaller than the hard decision data of DO) and equal to 3T (D0), it matches the second pattern from the top of the table shown in FIG. Therefore, the output signal “0” is output.
[0032]
For example, in FIG. 3, when performing comparison determination processing of three convergence points of 5T, 6T, and 7T, hard determination data (D-1) at the convergence point of 5T is hard determination data of 6T (D0). Since the hard decision data of the hard decision data (D1) at the convergence point of 7T is smaller than 6T (D0), it matches the seventh pattern from the top of the table shown in FIG. -1 "is output.
[0033]
Further, for example, in FIG. 3, when the comparison determination process of three convergence points 11T, 12T, and 13T is performed, the hard determination data (D-1) at the convergence point of 11T is the hard determination data of 12T (D0). Since the hard decision data (D1) at the convergence point of 13T is larger than the hard decision data of 12T (D0), the output signal “1” corresponds to the third pattern from the top of the table shown in FIG. Is output.
[0034]
The sign determination unit 155 generates the recovered clock from the detection output of the error detection unit 154 based on the signal (any one of “0”, “−1”, and “1”) output from the comparison determination unit 152. Whether or not to output as phase information and the sign of error. In response to this determination, an error signal is output.
[0035]
That is, in the code determination unit 155, for example, in the code determination process at three convergence points 2T, 3T, and 4T in FIG. 3, the “0” signal output from the comparison determination unit 152 is input, and this “0” is input. Based on the signal, it is determined that the detection output of the error detection unit 154 is not output as phase information for generating a recovered clock, and no error signal is output.
[0036]
Further, for example, in the sign determination processing of three convergence points 5T, 6T, and 7T in FIG. 3, the “−1” signal output from the comparison determination unit 152 is input, and based on the “−1” signal, It is determined that the detection output of the error detection unit 154 is output as negative phase information for generating a reproduction clock, and an error signal for correcting the phase delay at the convergence point is output.
[0037]
Further, for example, in the sign determination processing of three convergence points 11T, 12T, and 13T in FIG. 3, the “1” signal output from the comparison determination unit 152 is input, and error detection is performed based on the “1” signal. It is determined that the detection output of the unit 154 is output as positive phase information for generating a reproduction clock, and an error signal for correcting the phase advance at the convergence point is output.
[0038]
The error signal output from the code determination unit 155 is added to the oscillator 157 via the loop filter 156, and the phase of the radio symbol clock reproduced from the oscillator 157 is controlled.
[0039]
In other words, in the sign determination processing results at the three convergence points 5T, 6T, and 7T in FIG. 3, an error signal as negative phase information is added to the oscillator 157, so that the clock for correcting the phase delay in the oscillator 157 is obtained. Will be played.
[0040]
In addition, in the sign determination processing results of the three convergence points 11T, 12T, and 13T in FIG. 3, an error signal as positive phase information is added to the oscillator 157. Therefore, the clock for correcting the phase advance in the oscillator 157 Will be played.
[0041]
By performing such processing, stable clock reproduction can be performed.
[0042]
【The invention's effect】
As described above, in the present invention, the phase lag and advance of the recovered clock are detected at the convergence point of the received signal. In addition, since clock regeneration is performed, more stable clock regeneration can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a digital demodulator to which a clock recovery circuit of a multilevel demodulator according to the present invention is applied.
FIG. 2 is a block diagram showing a detailed configuration of a CLK recovery circuit shown in FIG.
FIG. 3 is a table showing a state of an I signal after code determination by a determination circuit unit shown in FIG.
4 is a diagram showing a configuration of a table held by a comparison / determination unit in FIG. 2;
FIG. 5 is a diagram showing a configuration of a conventional clock recovery circuit.
FIG. 6 is a waveform diagram showing an I signal component of QPSK.
FIG. 7 is a waveform diagram showing an I signal component of 64QAM.
[Explanation of symbols]
100 digital demodulator circuit 11 0 ° distributor 12a, 12b phase detector 13a, 13b A / D converter 14 determination circuit 15 CLK recovery circuit 16 loop filter 17 oscillator 18 90 ° distributor 151 determination circuit unit 152 comparison determination unit 153a, 153b, 153c Delay circuit 154 Error detection unit 155 Sign determination unit 156 Loop filter 157 Oscillator

Claims (1)

In the clock recovery circuit of the multilevel demodulator using the multilevel modulation method,
Storage means for storing N hard decision data obtained by sampling a received signal with a reproduction clock;
Comparison means for comparing the n (1 <n <N) th hard decision data of the N hard decision data stored in the storage means with the hard decision data before and after the hard decision data.
Error detection means for detecting a distance between the soft decision data corresponding to the nth hard decision data and its convergence point;
And a determination means for determining whether to output the detection output of the error detection means as phase information for generating the regenerated clock based on the comparison output of the comparison means, and for determining the sign thereof. Clock recovery circuit of value demodulator.

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