JP2004048292A - Clock recovery circuit for multi-value demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain stable clock recovery by detecting a lag / lead of a phase of a recovered clock at a converging point of a received signal so as to recover a clock. <P>SOLUTION: A clock recovery circuit 15 is provided with: a delay circuit 153 for storing N hard decision data resulting from sampling a received signal by a recovery clock; a comparison discrimination section 152 for comparing n-th hard decision data (1<n<N) among the N hard decision data stored in the delay circuit with preceding and succeeding hard decision data to the n-th hard decision data; an error detection section 154 for detecting a distance between soft decision data corresponding to the n-th hard decision data and a converging point of the soft decision data; and a sign decision section 155 for discriminating whether or not a detection output of the error detection section 154 is outputted as phase information to produce a recovery clock and its sign on the basis of a comparison output of the comparison discrimination section 152. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock recovery circuit of a multi-level demodulator using a multi-level modulation method, and more particularly to a clock recovery circuit that detects a phase shift and advancing of a phase at a convergence point of a received signal of a recovered clock and performs clock recovery by performing clock recovery. The present invention relates to a clock recovery circuit of a multi-level demodulator that enables reproduction.
[0002]
[Prior art]
Conventionally, in a clock recovery circuit of this type of demodulator, as shown in FIG. 5, a recovered clock (wireless symbol CLK) is generated based on the timing of crossing zero of an I (in-phase) signal after removing a carrier component from a received signal. ) Is detected by the error detector 1 and the output of the error detector 1 is applied to the oscillator 3 via the loop filter 2 to reproduce the wireless symbol CLK from the oscillator 3. ing.
[0003]
In FIG. 5, the reproduction clock (radio symbol CLK) is reproduced based on the timing at which the I (in-phase wave) signal crosses zero. It may be configured to reproduce the wireless symbol CLK on the basis of the radio symbol CLK.
[0004]
[Problems to be solved by the invention]
However, in the clock recovery circuit of the above-mentioned conventional demodulator, if the QPSK signal as shown in FIG. 6 is used, the phase jitter component is small at the timing when the I signal crosses zero. In the case of a multilevel modulation scheme such as the 64QAM signal shown in FIG. 7, a large jitter component exists at the timing when the I signal crosses zero, and as a result, the radio signal is generated based on the phase delay or advance of the conventional timing of crossing zero. The configuration for reproducing the symbol CLK has a problem that stable clock reproduction cannot be performed.
[0005]
Therefore, an object of the present invention is to provide a clock recovery circuit of a multi-level demodulator capable of performing stable clock recovery.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a clock recovery circuit of a multilevel demodulator using a multilevel modulation scheme, wherein a storage means for storing N hard decision data obtained by sampling a received signal with a recovered clock, Comparing means for comparing the n (1 <n <N) th hard decision data of the N hard decision data stored in the storage means with the hard decision data before and after the nth hard decision data; Error detection means for detecting the distance between the corresponding soft decision data and the convergence point, and whether to output a detection output of the error detection means as phase information for generating the reproduction clock based on a comparison output of the comparison means. Determination means for determining whether or not the sign is present and the sign thereof.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a clock recovery circuit of a multilevel demodulator according to the present invention will be described in detail with reference to the accompanying drawings.
[0008]
FIG. 1 is a block diagram showing an embodiment of a digital demodulator 100 to which a clock recovery circuit of a multilevel demodulator according to the present invention is applied.
[0009]
1, the digital demodulation apparatus 100 includes a 0 ° distributor 11, phase detectors 12a and 12b, A / D converters 13a and 13b, a determination circuit 14, a CLK regeneration circuit 15, a loop filter 16, oscillators 17 and 90. ° It comprises the distributor 18.
[0010]
Here, the 0 ° distributor 11 divides the received signal into two received signals having the same phase, and outputs the two received signals to the phase detector 12a and the phase detector 12b.
[0011]
Each of the phase detectors 12a and 12b receives two reproduced carrier signals having a 90 ° phase shift and output from the 90 ° distributor 18, and separates the two reproduced carrier signals into the 0 ° distributor 11b. By multiplying the two received signals output from, the received signal is subjected to phase detection to output a signal of an I (in-phase) signal component and a Q (quadrature wave) signal component.
[0012]
The A / D converter 13a and the A / D converter 13b synchronize the I signal component and the Q signal component output from the phase detector 12a and the phase detector 12b, respectively, with the reproduced clock output from the clock recovery circuit 15. , And outputs a digital I signal and a digital Q signal, respectively.
[0013]
The digital I signal and the digital Q signal output from the A / D converter 13a and the A / D converter 13b, respectively, are applied to a decision circuit 14, where the inputted digital I signal and digital Q signal are respectively inputted. The convergence point is determined and output as I data and Q data.
[0014]
The determination circuit 14 detects the phase of the reproduced carrier based on the input digital I signal and digital Q signal, and outputs the phase error as a carrier error signal.
[0015]
This carrier error signal is applied to an oscillator 17 via a loop filter 16 to control the phase of a reproduced carrier signal generated from the oscillator 17. The reproduced carrier signal generated from the oscillator 17 is supplied to a 90 ° splitter. 18 is added.
[0016]
The digital I signal output from the A / D converter 13a is applied to the CLK recovery circuit 15.
[0017]
The CLK reproducing circuit 15 reproduces a clock (wireless symbol CLK) synchronized with the received signal based on the digital I signal output from the A / D converter 13a.
[0018]
The reproduction clock reproduced by the CLK reproduction circuit 15 is applied to the A / D converter 13a and the A / D converter 13b as described above, and samples the digital I signal and the digital Q signal, that is, the I signal component and The timing of analog-to-digital conversion of the Q signal component is controlled.
[0019]
FIG. 2 is a block diagram showing a detailed configuration of the CLK recovery circuit 15 shown in FIG.
[0020]
2, the CLK recovery circuit 15 includes a determination circuit unit 151, a comparison determination unit 152, delay circuits 153a, 153b, 153c, an error detection unit 154, a sign determination unit 155, a loop filter 156, and an oscillator 157. Is done.
[0021]
Here, the determination circuit section 151 branches and inputs the digital I signal from the A / D converter 13a shown in FIG. 1 and performs convergence point determination using a natural code at the convergence point. As a result, the I signal after the sign determination becomes a signal having 0 to 11 values as shown in FIG. In this case, the value is represented by 12 values from 0 to 11 because the system adopts the 128 QAM method.
[0022]
In this specification, data after the sign determination in the determination circuit unit 151 is called hard decision data, and data before the sign determination in the determination circuit unit 151 is called soft decision data.
[0023]
The hard decision data for which the sign is judged by the judgment circuit 151 is delayed by one radio symbol clock (T) by delay circuits 153a and 153b, respectively, and added to the comparison judgment unit 152.
[0024]
As a result, the comparison / decision unit 152 includes the hard decision data D-1 whose sign is determined by the decision circuit unit 151, the hard decision data D0 obtained by delaying the hard decision data by one radio symbol clock (T), and the hard decision data D0. Further, hard decision data D1 delayed by one radio symbol clock (T) is input.
[0025]
The digital I signal branched from the A / D converter 13a shown in FIG. 1 is delayed by one radio symbol clock (T) by the delay circuit 153c and added to the error detection unit 154.
[0026]
The error detector 154 detects the distance (error) between the soft decision data D0 'and its convergence point based on the soft decision data D0' corresponding to the hard decision data D0.
[0027]
Further, the comparison / determination unit 152 determines whether or not to output the detection output of the error detection unit 154 as phase information for generating a reproduction clock based on the hard decision data D-1, hard decision data D0, and hard decision data D1. And a signal for determining the sign thereof is output.
[0028]
That is, the comparison determination unit 152 compares the magnitude relationship between the amplitude values of the hard decision data D-1, the hard decision data D0, and the hard decision data D1 at the three convergence points, and the comparison result is shown in FIG. By determining which of the patterns in the table shown applies, a signal is output to determine whether or not to output the detection output of error detection section 154 as phase information for generating a reproduced clock, and to determine the sign thereof.
[0029]
Here, “0” of the output value from the comparison determination unit 152 means that the detection output of the error detection unit 154 is not output as phase information for generating a reproduction clock, and “1” indicates that the error detection unit 153 means to output the detected output as positive phase information for generating a reproduced clock, and “−1” indicates that the detected output of the error detector 154 is used as negative phase information for generating a reproduced clock. Means to output.
[0030]
In the values corresponding to the hard decision data D-1, the hard decision data D0, and the hard decision data D1 in the table shown in FIG. 4, “+” indicates that the hard decision data D-1 or the hard decision data D1 is the decision data D0. "-" Means that hard decision data D-1 or hard decision data D1 is smaller than decision data D0, and "0" means hard decision data D-1 or hard decision data. This means that the data D1 is equal to the determination data D0.
[0031]
That is, in the comparison determination unit 152, for example, when performing the comparison determination processing of three convergence points of 2T, 3T, and 4T in FIG. 3, the hard determination data (D-1) at the convergence point of 2T is 3T ( Since the hard decision data of the hard decision data (D1) at the convergence point of 4T is smaller than the hard decision data of 4T and is equal to 3T (D0), the pattern matches the pattern in the second row from the top of the table shown in FIG. Therefore, the output signal “0” is output.
[0032]
In addition, for example, in FIG. 3, when comparing and determining three convergence points of 5T, 6T, and 7T, the hard decision data (D-1) at the convergence point of 5T is the hard decision data of 6T (D0). Since the hard decision data of the hard decision data (D1) at the convergence point of 7T is smaller than 6T (D0), it matches the pattern of the seventh stage from the top of the table shown in FIG. -1 "is output.
[0033]
Further, for example, in FIG. 3, when performing the comparison determination process of three convergence points of 11T, 12T, and 13T, the hard decision data (D-1) at the convergence point of 11T is the hard decision data of 12T (D0). Since the hard decision data (D1) at the convergence point of 13T is larger than the hard decision data of 12T (D0), the output signal “1” matches the pattern in the third row from the top of the table shown in FIG. Is output.
[0034]
The sign judging section 155 uses the signal (one of “0”, “−1”, and “1”) output from the comparing and judging section 152 to generate a reproduction clock based on the detection output of the error detecting section 154. , And the sign of the error. Then, an error signal is output according to this determination.
[0035]
That is, for example, in the sign determination process of the three convergence points 2T, 3T, and 4T in FIG. 3, the sign determination unit 155 receives the “0” signal output from the comparison determination unit 152 and receives the “0” signal. Based on the signal, it is determined that the detection output of the error detection unit 154 is not output as phase information for generating a reproduction clock, and no error signal is output.
[0036]
In addition, for example, in the sign determination processing of three convergence points 5T, 6T, and 7T in FIG. 3, a “−1” signal output from the comparison determination unit 152 is input, and based on the “−1” signal, It is determined that the detection output of error detection section 154 is to be output as negative phase information for generating a reproduced clock, and an error signal for correcting a phase delay at the convergence point is output.
[0037]
In addition, for example, in the sign determination processing of three convergence points 11T, 12T, and 13T in FIG. 3, the “1” signal output from the comparison determination unit 152 is input, and error detection is performed based on the “1” signal. It determines that the detection output of the section 154 is to be output as positive phase information for generating a reproduced clock, and outputs an error signal for correcting the advance of the phase at the convergence point.
[0038]
The error signal output from the sign determination unit 155 is applied to the oscillator 157 via the loop filter 156, and controls the phase of the radio symbol clock reproduced from the oscillator 157.
[0039]
That is, in the result of the sign determination processing of the three convergence points 5T, 6T and 7T in FIG. 3, an error signal as negative phase information is added to the oscillator 157. Will be played.
[0040]
In addition, in the sign determination processing result of the three convergence points 11T, 12T, and 13T in FIG. 3, an error signal as positive phase information is added to the oscillator 157. Will be played.
[0041]
By performing such processing, stable clock reproduction can be performed.
[0042]
【The invention's effect】
As described above, the delay and advance of the phase of the reproduced clock are conventionally detected at the timing of crossing zero of the received signal. In the present invention, the delay and advance of the phase of the reproduced clock are detected at the convergence point of the received signal. Since the clock is reproduced, more stable clock reproduction can be performed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a digital demodulator to which a clock recovery circuit of a multilevel demodulator according to the present invention is applied.
FIG. 2 is a block diagram showing a detailed configuration of a CLK recovery circuit shown in FIG.
FIG. 3 is a table showing a state of an I signal after code determination by a determination circuit unit shown in FIG. 2;
FIG. 4 is a diagram showing a configuration of a table held by a comparison determination unit in FIG. 2;
FIG. 5 is a diagram showing a configuration of a conventional clock recovery circuit.
FIG. 6 is a waveform chart showing an I signal component of QPSK.
FIG. 7 is a waveform chart showing an I signal component of 64QAM.
[Explanation of symbols]
Reference Signs List 100 Digital demodulation circuit 110 0 ° dividers 12a, 12b Phase detectors 13a, 13b A / D converter 14 Judgment circuit 15 CLK regeneration circuit 16 Loop filter 17 Oscillator 18 90 ° divider 151 Judgment circuit unit 152 Comparison judgment unit 153a, 153b, 153c Delay circuit 154 Error detection unit 155 Sign determination unit 156 Loop filter 157 Oscillator

Claims (1)

In a clock recovery circuit of a multilevel demodulator using a multilevel modulation scheme,
Storage means for storing N hard decision data obtained by sampling a received signal by a reproduction clock;
Comparing means for comparing the n (1 <n <N) th hard decision data among the N hard decision data stored in the storage means with the hard decision data before and after the nth hard decision data;
Error detection means for detecting the distance between the soft decision data corresponding to the n-th hard decision data and the convergence point thereof,
A determination unit for determining whether or not to output the detection output of the error detection unit as phase information for generating the reproduced clock based on the comparison output of the comparison unit and determining the sign thereof; Clock recovery circuit for value demodulator.

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