JP3848228B2

JP3848228B2 - Wiring device manufacturing method, electron source substrate manufacturing method, and image display device manufacturing method

Info

Publication number: JP3848228B2
Application number: JP2002261466A
Authority: JP
Inventors: 尚史東
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2002-09-06
Filing date: 2002-09-06
Publication date: 2006-11-22
Anticipated expiration: 2022-09-06
Also published as: JP2004103325A

Description

【０００１】
【発明の属する技術分野】
本発明は、配線装置の製造方法および配線装置に係わり、特に下部導電層上に、一方向に延びた層間絶縁膜を介して、同方向に延びた上部導電層が形成され、該層間絶縁膜の開孔を通して下部の導電層と上部の導電層とが接続された配線装置の製造方法および配線装置に関する。
【０００２】
【従来の技術】
下部導電層上に一方向に延びた層間絶縁膜を介して、同方向に延びた上部導電層を形成し、層間絶縁膜の開孔を通して両導電層を接続する配線装置は、マトリクス配線を用いる、プラズマディスプレイ、アクティブマトリクス液晶表示素子、電子放出素子を用いたフラットディスプレイ、光電変換部にアモルファスシリコンを用いた二次元光センサ等に用いられている。以下、電子放出素子を用いたフラットディスプレイの電子源基板を例にとって配線構造を説明する。電子源基板は基板上に配線をマトリクス状に配置し、上部配線と下部配線との交差部近傍にそれぞれ上部配線と下部配線とに接続される電子放出素子を配置したものである。電子放出素子としてはここでは、薄膜に設けられた電子放出部から電子を放出する表面伝導型電子放出素子と呼ばれる素子を用いている。
【０００３】
図１１はマトリクス方式の配線を有する電子源基板の配線交差部近傍を示す構成図であり、図１２は図１１の上部配線の一部を切り欠いて、開孔部と下部配線を示した構成図である。
【０００４】
図１１及び図１２において、１０１は表面伝導型電子放出素子であり、電子放出部が形成される電子放出部形成用薄膜１０４、薄膜１０４の両端とそれぞれ接続される素子電極１０２及び１０３から構成される。１０５は素子電極１０３と接続される第一導電層、１０６は層間絶縁層、１０７は層間絶縁層１０６に設けられる抜けパターン（コンタクトホール）、１０８は第二導電層である。抜けパターン１０７を介して素子電極１０２（下部導電層）と第二導電層１０８（上部電極層）とが接続され、表面伝導型電子放出素子に電流を流すことで、薄膜１０４に形成される電子放出部から電子が放出される。
【０００５】
【発明が解決しようとする課題】
ここで、素子電極１０２と第二導電層１０８が接続される部分では、層間絶縁層１０６に設けられた抜けパターン１０７によって第二導電層１０８が落ち込む構成で形成されるために、少なからず第二導電層１０８の膜厚が厚くなる。さらに、低抵抗マトリクス配線を実現するに際しても、各導電層の膜厚は厚くなる傾向にある。
【０００６】
第二導電層１０８は、低抵抗化の目的から金属含有成分比が大きく、線膨張係数が下地の層間絶縁層１０６よりも大きい。図１２中のB-B'断面図である図１３を参照しながら説明する（図１３では素子電極１０２は省略されている。）。焼成時の収縮と線膨張係数の差により、焼成後、室温に戻した際に層間絶縁層１０６に大きな引張り応力が作用してしまう。すると、層間絶縁層１０６と絶縁性基板３１との境界領域に破壊が生じてしまい、最悪の場合には素子電極１０２が引き裂かれてしまい、不良素子を発生させることになる。
【０００７】
【課題を解決するための手段】
本発明の配線装置の製造方法は、下部導電層と上部導電層とが層間絶縁膜に設けられたコンタクトホールを通して接続された配線装置の製造方法であって、
全周が囲まれたコンタクトホールを備え、Ｘ方向に延びる層間絶縁膜であって、前記Ｘ方向に対して垂直なＹ方向における前記層間絶縁膜の幅を規定する前記層間絶縁膜の両端部のうちの一方の端部よりも他方の端部の近くに前記コンタクトホールが位置している層間絶縁膜を、前記コンタクトホールが下部導電層上に位置するように設ける工程と、
遮蔽部と前記Ｘ方向に延びた開口部とを備えるマスクを、前記コンタクトホールの一部であって、少なくとも前記層間絶縁膜の前記他方の端部側に位置する部分が前記遮蔽部で覆われ、前記コンタクトホールの他の部分が前記開口部で露出されるように、前記層間絶縁膜上に施し、前記マスクの開口部を介して上部導電層の材料を付与する工程と、
を含むことを特徴とする。
また本発明の配線装置の製造方法は、下部導電層と上部導電層とが層間絶縁膜に設けられたコンタクトホールを通して接続された配線装置の製造方法であって、
全周が囲まれたコンタクトホールを備え、Ｘ方向に延びる層間絶縁膜を、前記コンタクトホールが下部導電層上に位置するように設ける工程と、
遮蔽部と前記Ｘ方向に延びた開口部とを備えるマスクを、前記Ｘ方向に対して垂直なＹ方向における前記コンタクトホールの両端が前記遮蔽部で覆われ、前記コンタクトホールの前記Ｙ方向における前記両端の間に位置する他の部分が前記開口部で露出されるように、前記層間絶縁膜上に施し、前記マスクの開口部を介して上部導電層の材料を付与する工程と、
を含むことを特徴とする。
【０００８】
本発明の電子源基板の製造方法は、上部導電層と、電子放出素子に接続された下部導電層とが、層間絶縁膜に設けられたコンタクトホールを通して接続された電子源基板の製造方法であって、
全周が囲まれたコンタクトホールを備え、Ｘ方向に延びる層間絶縁膜であって、前記Ｘ方向に対して垂直なＹ方向における前記層間絶縁膜の幅を規定する前記層間絶縁膜の両端部のうちの一方の端部よりも他方の端部の近くに前記コンタクトホールが位置している層間絶縁膜を、基板上に設けられた下部導電層上に前記コンタクトホールが位置するように設ける工程と、
遮蔽部と前記Ｘ方向に延びた開口部とを備えるマスクを、前記コンタクトホールの一部であって、少なくとも前記層間絶縁膜の前記他方の端部側に位置する部分が前記遮蔽部で覆われ、前記コンタクトホールの他の部分が前記開口部で露出されるように、前記層間絶縁膜上に施し、前記マスクの開口部を介して上部導電層となる材料を付与する工程と、
を含むことを特徴とする。
また本発明の電子源基板の製造方法は、上部導電層と、電子放出素子に接続された下部導電層とが、層間絶縁膜に設けられたコンタクトホールを通して接続された電子源基板の製造方法であって、
全周が囲まれたコンタクトホールを備え、Ｘ方向に延びる層間絶縁膜を、基板上に設けられた下部導電層上に前記コンタクトホールが位置するように設ける工程と、
遮蔽部と前記Ｘ方向に延びた開口部とを備えるマスクを、前記Ｘ方向に対して垂直なＹ方向における前記コンタクトホールの両端が前記遮蔽部で覆われ、前記コンタクトホールの前記Ｙ方向における前記両端の間に位置する他の部分が前記開口部で露出されるように、前記層間絶縁膜上に施し、前記マスクの開口部を介して上部導電層の材料を付与する工程と、
を含むことを特徴とする。
【０００９】
本発明の画像表示装置の製造方法は、（ｉ）複数の電子放出素子を備えており、該複数の電子放出素子の各々が、層間絶縁膜に設けられた複数のコンタクトホールを通して上部導電層に接続された複数の下部導電層の各々に接続されてなる電子源基板と、（ｉｉ）前記複数の電子放出素子から放出された電子により発光する蛍光体膜を有する基板と、を備えた画像表示装置の製造方法であって、
全周が囲まれた複数のコンタクトホールを備え、Ｘ方向に延びる層間絶縁膜であって、前記Ｘ方向に対して垂直なＹ方向における前記層間絶縁膜の幅を規定する前記層間絶縁膜の両端部のうちの一方の端部よりも他方の端部の近くに前記コンタクトホールが位置している層間絶縁膜を、基板上に前記Ｘ方向に並んで設けられた複数の下部導電層の各々の上に前記複数のコンタクトホールの各々が位置するように設ける工程と、
遮蔽部と前記Ｘ方向に延びた開口部とを備えるマスクを、前記複数のコンタクトホールの各々の一部であって、少なくとも前記層間絶縁膜の前記他方の端部側に位置する部分が前記遮蔽部で覆われ、前記複数のコンタクトホールの各々の他の部分が前記開口部で露出されるように、前記層間絶縁膜上に施し、前記マスクの開口部を介して上部導電層となる材料を付与する工程を含む、ことを特徴とする。
また本発明の画像表示装置の製造方法は、（ｉ）複数の電子放出素子を備えており、該複数の電子放出素子の各々が、層間絶縁膜に設けられた複数のコンタクトホールを通して上部導電層に接続された複数の下部導電層の各々に接続されてなる電子源基板と、（ｉｉ）前記複数の電子放出素子から放出された電子により発光する蛍光体膜を有する基板と、を備えた画像表示装置の製造方法であって、
全周が囲まれた複数のコンタクトホールを備え、Ｘ方向に延びる層間絶縁膜を、基板上にＸ方向に並んで設けられた複数の下部導電層の各々の上に前記複数のコンタクトホールの各々が位置するように設ける工程と、
遮蔽部と前記Ｘ方向に延びた開口部とを備えるマスクを、前記Ｘ方向に対して垂直なＹ方向における前記複数のコンタクトホールの各々の両端が前記遮蔽部で覆われ、前記複数のコンタクトホールの各々の前記Ｙ方向における前記両端の間に位置する他の部分が前記開口部で露出されるように、前記層間絶縁膜上に施し、前記マスクの開口部を介して上部導電層となる材料を付与する工程を含む、ことを特徴とする。
【００１０】
また、前記上部電極層は印刷配線層であるとよい。
【００１１】
【発明の実施の形態】
以下、図面を用いて、本発明の好適な実施形態について説明する。ここでは、電子放出素子を用いたフラットディスプレイの電子源基板を例にとって説明を行う。電子源基板は基板上に配線をマトリクス状に配置し、上部配線と下部配線との交差部近傍にそれぞれ上部配線と下部配線とに接続される電子放出素子を配置したものである。電子放出素子としてはここでは、薄膜に設けられた電子放出部から電子を放出する表面伝導型電子放出素子と呼ばれる素子を用いている。
【００１２】
上記表面伝導型電子放出素子としては、本件出願人により、多数の素子を配列して駆動するための方法が特開昭６４−３１３３２号公報に開示され、画像表示装置への応用が本出願人によるＵＳＰ５，０６６，８８３号や特開平２−２５７５５１号公報、特開平４−２８１３７号公報等において開示されている。
【００１３】
図１に、本発明の実施形態に係る画像表示装置で用いられる電子源基板の製造方法を示す。図１では、層間絶縁層１０６まで作成した電子源基板に第二導電層１０８（図１において不図示）をパターンニングするためのマスク１１１をアライメント後の上面図を示す。なお、図１１及び図１２と同一構成部材については同一符号を付する（以下の図３以降の各図でも同様とする。）。
【００１４】
図１において、１０１は表面伝導型電子放出素子であり、電子放出部が形成される電子放出部形成用薄膜１０４、薄膜１０４の両端と接続される素子電極１０２及び１０３から構成される。１０５は素子電極１０３と接続される第一導電層、１０６はＸ方向に延びた層間絶縁層、１０７は層間絶縁層１０６に設けられる抜けパターン（コンタクトホール）である、また、１１１は第二導電膜１０８（図１において不図示）をパターンニングするための金属マスクであり、１１０は金属マスク１１１の開口部、１０９は金属マスク１１１の遮蔽部である。抜けパターン１０７を介して素子電極１０２（下部導電層）とマスク１１１を用いて層間絶縁膜１０６上に形成される第二導電層１０８（上部導電層）とが接続され、表面伝導型電子放出素子に電流を流すことで、薄膜１０４に形成される電子放出部から電子が放出される。
【００１５】
図１の通りに作成した層間絶縁層１０６の抜けパターン１０７の断面図（図１中のB-B'断面）を第二導電層１０８も含めて、図２に示す。第二導電層１０８はマスク１１１を用いて層間絶縁膜１０６上に形成される。図１に示すように、マスク１１１は、マスク１１１の開口部１１０内に抜けパターン１０７全体が含まれるように設けられておらず、抜けパターン１０７のＸ方向に沿った側壁側の一方がマスク１１１の遮蔽部１０９で覆われるように配置されている。このようにマスク１１１を配置することで図２に示すように、層間絶縁膜の一方の側壁（図２中左側の側壁）と第二導電層１０８との間には隙間ｄが設けられている。ここで隙間ｄは一方の側壁の上端部と第二導電層１０８とが接していない空間をいい、側壁の上端部と接していなければ第二導電層１０８が側壁と接するように破線部１０８ａまで延びて形成されてもよい。
【００１６】
上記のように隙間ｄを設けることで、図１３で応力集中が発生していた層間絶縁層１０６と絶縁基板３１の境界領域への応力集中が低減された。この原因は必ずしも明確でないが、次のように考察することができる。図１３を用いて説明すると、焼成時の収縮と第二導電層１０８との線膨張係数の差により生じた層間絶縁層１０６に引張り応力が作用しても図１３の開孔を形成する部分の層間絶縁層１０６の幅Ｄに比べて、図２に示すように開孔を形成する部分の層間絶縁層１０６の幅Ｄ₁を大きくすれば（Ｄ₁＞Ｄ）、基板３１と層間絶縁層１０６との接着力が強くなり層間絶縁層１０６と絶縁性基板３１との境界領域の応力集中を緩和することができる。また、層間絶縁層１０６に引張り応力が作用しても第二導電層１０８と層間絶縁層１０６との接触面積が小さければ層間絶縁層１０６にかかる引張り応力の値は小さくなり、層間絶縁層１０６と絶縁性基板３１との境界領域の応力集中を緩和することができる。
【００１７】
つまり、コンタクトホールを左側に寄せたことによる、層間絶縁層１０６の右側の応力低減効果と、図１に示す印刷マスクの開口からコンタクトホールの開孔の一部が見えないように（側壁側の一方がマスク１１１の遮蔽部１０９で覆われるように）印刷し、層間絶縁層１０６と第二導電層１０８の接触部面積が減少したことによる、層間絶縁層１０６の左側の応力低減効果によるものと考えられる。特に、図１、２のように、非対称な構成とすると、図２中右側の応力は、図２中左側の応力よりも３０％程度更に小さくなることが、確認されている。よって、図１、２の形態はより好適な形態となっている。
【００１８】
なお、本発明の他の実施形態として、図９に示すように、抜けパターン１０７のＸ方向に沿った側壁の両側がマスク１１１の遮蔽部１０９で覆われるようにして、層間絶縁層１０６と第二導電層１０８の接触部面積の減少による応力低減効果のみで、層間絶縁層１０６と絶縁性基板３１との境界領域の応力集中を緩和することが可能である。また、さらに他の実施形態として、図１０に示すように、図１に示した構成にさらに、抜けパターン１０７のＸ方向に沿った側壁のもう一方をマスク１１１の遮蔽部１０９で覆われるようにして、層間絶縁層１０６と第二導電層１０８の接触部面積の減少による応力低減効果を側壁のもう一方にも実現することができる。
【００１９】
以下、図３の工程フロー図を参照して、各実施態様に係る電子源基板の製造方法を説明する。
【００２０】
まず、基板（不図示）に、素子電極２、３を形成する（図３（ａ））。素子電極２、３は、電子放出部形成用薄膜４と第一導電層５及び第二導電層８とのオーミックな電気的接触とするために設けられるものである。
【００２１】
素子電極２、３の形成方法としては、真空蒸着法、スパッタリング法、プラズマCVD法等の真空系を用いる方法や、溶媒にAg成分及びガラス成分を混合した厚膜ペーストを印刷、焼成することにより形成する厚膜印刷法、さらにはPtペーストを用いたオフセット印刷法、等がある。なお、配線用の各導電層５及び８を、例えばスパッタリング法により薄膜にて構成する場合は、必ずしも素子電極２、３を設ける必要は無く、配線用の第一導電層５と同時に形成することが可能である。
【００２２】
次に、素子電極対の一方（本例では素子電極３）と接続する第一導電層５を形成する（図３（ｂ））。第一導電層５の形成方法には、素子電極２、３の形成方法と同様の手法が適用可能であるが、低抵抗配線の必要性から、厚膜印刷法を用いるのが有利である。
【００２３】
近年、厚膜ペースト印刷にフォトリソグラフィー技術を導入したフォトペースト法による膜形成技術も開発されており、フォトペースト法による形成も、勿論可能であり、配線（第一導電層５）の幅が狭くなる場合、大型基板に対応して位置精度が要求される場合などは、フォトペースト法が有利である。
【００２４】
次に、層間絶縁層６を形成する（図３（ｃ））。層間絶縁層６は、第一導電層５の一部、具体的には第一導電層５の第二導電層８との交差部を覆うようにして、形成する。
【００２５】
層間絶縁層６の構成材料は絶縁性を保てるものであればよく、例えば金属成分を含有しない厚膜ペーストである。勿論、金属成分を含有しないフォトペーストの適用も可能である。
【００２６】
次に、第二導電層８を形成する（図３（ｄ））。形成方法は第一導電層５と同様の方法が適用可能である。この場合、低抵抗配線の必要性から、厚膜印刷法を用いるのが有利である。
【００２７】
本実施形態では、素子電極対の片方（本実施態様では素子電極２）と第二導電層８との接続を確保するために設けられる層間絶縁層６の抜けパターン７の開孔エッジの一方のＸ方向に沿う側壁側または両方の側壁側が第二導電層８のパターンニング用金属マスク１１開口上から不可視である（マスク１１の遮蔽部で覆われている）。また、層間絶縁層６の抜けパターン７と層間絶縁層が偏心して配置されている。すなわち、図４に示すように、Ｘ方向と垂直なＹ方向の層間絶縁層１０６又は第二導電層８の幅の中心Ｃ₁に対して（ここでは、層間絶縁層１０６の幅の中心と第二導電層８の幅の中心は一致している。）、抜けパターン７のＹ方向の幅の中心Ｃ₂を距離ｄ_Cだけずらして（偏心して）配置している。
【００２８】
次に、電子放出部形成用薄膜４を形成して冷陰極電子ビーム源用の素子１が完成する（図３（ｅ））。電子放出部形成用薄膜４の成膜方法および電子放出部の形成方法は、従来の方法をそのまま適用することが可能である。
【００２９】
このようにして、単純マトリクス構成の電子源基板が完成する。
【００３０】
なお表面伝導型電子放出素子の構成及び製造方法、特性については、例えば特開平２−５６８２２号公報に開示されており、本実施形態でもその構成および製造方法を用いることができる。ここでは表面伝導型電子放出素子の構成及び製造方法、特性の概要を述べるに留める。
【００３１】
図５は、本発明に係る典型的な表面伝導型電子放出素子の構成を示す図である。図５において、３１は絶縁性基板、３２と３３は素子電極、３４は素子電極３２、３３が両端にそれぞれ接続される電子放出部形成用薄膜、３５は電子放出部形成用薄膜３４に形成された電子放出部である。
【００３２】
本実施形態における、電子放出部３５を含む電子放出部形成用薄膜３４のうち電子放出部３５としては、粒径が数ｎｍの電気伝導性粒子からなり、電子放出部３５を含む電子放出部形成用薄膜３４のうち電子放出部３５以外の部分は、微粒子膜よりなる。なお、ここで述べる微粒子膜とは、複数の微粒子が集合した膜であり、その微細構造として、微粒子が個々に分散した状態のみならず、微粒子が互いに隣接あるいは重なり合った状態（島状も含む）の膜を指す。
【００３３】
電子放出部を含む電子放出部形成用薄膜３４の構成原子又は分子の具体例としては、Ｐｄ、Ｒｕ、Ａｇ、Ａｕ、Ｔｉ、Ｉｎ、Ｃｕ、Ｃｒ、Ｆｅ、Ｚｎ、Ｓｎ、Ｔａ、Ｗ、Ｐｂ等の金属、ＰｄＯ、ＳｎＯ₂、Ｉｎ₂Ｏ₃、ＰｂＯ、Ｓｂ₂Ｏ₃等の酸化物、ＨｆＢ₂、ＺｒＢ₂、ＬａＢ₆、ＣｅＢ₆、ＹＢ₄、ＧｄＢ₄等のホウ化物、ＴｉＣ、ＺｒＣ、ＨｆＣ、ＴａＣ、ＳｉＣ、ＷＣ等の炭化物、ＴｉＮ、ＺｒＮ、ＨｆＮ等の窒化物、Ｓｉ、Ｇｅ等の半導体、さらにはカーボン、ＡｇＭｇ、ＮｉＣｕ、ＰｂＳｎ等である。
【００３４】
また、電子放出部形成用薄膜３４の形成方法としては、真空蒸着法、スパッタリング法、化学的気相成長法、分散塗布法、ディッピング法、スピナー法等がある。
【００３５】
図５に示した表面伝導型電子放出素子の形成方法としては、様々な手法があるが、その一例を図６に示す。
【００３６】
以下、素子の形成方法を説明する。なお、以下の説明は単一の素子の形成方法を説明したものであるが、本発明の実施態様による電子源基板の製造方法にも適用されるものである。
（１）絶縁性基板３１を洗剤、純水および有機溶剤により十分に洗浄後、真空蒸着技術、フォトリソグラフィー技術により該絶縁性基板３１の面上に素子電極３２，３３を形成する（図６（ａ））。素子電極３２、３３の材料としては電気伝導性を有するものであれば、どのようなものであっても構わないが、例えばニッケル金属が挙げられる。素子電極３２、３３の寸法については、例えば、素子電極間隔Lは１０μｍ、素子電極長さＷは３００μｍ、膜厚ｄ₁は１００ｎｍである。素子電極３２、３３の形成方法として、厚膜印刷法を用いても良い。印刷法の材料としては有機金属ペースト（ＭＯＤ）等がある。
（２）絶縁性基板３１上に設けられた素子電極３２と３３との間に、有機金属溶液を塗布して放置することにより、有機金属薄膜を形成する。なお、有機金属溶液とは、Ｐｄ、Ｒｕ、Ａｇ、Ａｕ、Ｔｉ、Ｉｎ、Ｃｕ、Ｃｒ、Ｆｅ、Ｚｎ、Ｓｎ、Ｔａ、Ｗ、Ｐｂ等の金属を主元素とする有機化合物の溶液である。この後、有機金属薄膜を加熱焼成してリフトオフ、エッチング等によりパターンニングし、電子放出部形成用薄膜３４を形成する（図６（ｂ））。
（３）続いて、フォーミングと呼ばれる通電処理により素子電極３２、３３間に電圧を印加することにより、電子放出部形成用薄膜３４の部分に構造的変化を生じた電子放出部３５が形成される（図６（ｃ））。この通電処理により電子放出部形成用薄膜３４を局所的に破壊、変形もしくは変質せしめ、構造の変化した部位を電子放出部３５と呼ぶ。先に説明したように電子放出部３５は金属微粒子で構成されていることが観察された。
【００３７】
フォーミング処理中の電圧波形を図７に示す。図７中、Ｔ１およびＴ２はそれぞれ電圧波形のパルス幅とパルス間隔であり、Ｔ１を１マイクロ秒〜１０ミリ秒、Ｔ２を１０マイクロ秒〜１００ミリ秒、三角波の波高値（フォーミング時のピーク電圧）は４Ｖから１０Ｖ程度とし、フォーミング処理は真空雰囲気下で数十秒間で適時設定した。
【００３８】
以上、説明した電子放出部を形成する際に、素子電極間の三角波パルスを印加してフォーミング処理を行っているが、素子電極間に印加する波形は三角波に限定することなく、矩形波など所望の波形を用いても良く、その波高値およびパルス幅、パルス間隔等についても上述の値に限るものではなく、電子放出部を良好に形成されれば所望の値を選択することが出来る。
【００３９】
上記の通りに作成した電子源基板を用いた画像表示装置９１の構成と製造方法について説明する。図８に示すように、基板８１上に電子放出素子を複数個配置し、Ｘ方向配線８６とＹ方向配線８５と電気的に接続し、単純マトリクス配線構造としている。基板８１の２ｍｍ上方にフェースプレート９０（ガラス基板８７の内面に蛍光体膜８８とメタルバック８９が形成されている）を支持枠８３を介して配置し、フェースプレート９０、支持枠８３、基板８１の接合部にフリットガラスを塗布し、大気中もしくは窒素雰囲気中にて４００℃乃至５００℃で１０分間程度焼成することにより封着した。図８において、３５は電子放出素子、８５，８６はそれぞれ第一、第二導電層（Ｙ,Ｘ方向配線）である。
【００４０】
このようにして作成された画像表示装置内を不図示の排気管を通じて真空ポンプにて十分な真空度まで排気する。その後、容器外の引き出し配線３０を通じ、素子電極間に電圧を印加して、前述のフォーミング処理を行い、電子放出部を形成し、電子放出素子３５を作成する。最後に、１０^-4Ｐａ程度以下の真空度にて、排気管を熱して溶着し、真空外囲気の封止を行う。さらに、封止後に真空度を維持するために、ゲッター処理工程を行う。これは、封止後に抵抗加熱或いは高周波過熱により、画像表示装置内部に設置されたゲッター（不図示）を加熱して、ゲッター蒸着膜を形成する。ゲッターとしては通常、Ｂａ等が主成分であり、該蒸着膜のポンプ作用により真空度を維持するものである。
【００４１】
上述のとおりに作成された画像表示装置に画像表示を行うには、引き出し配線３０を通じて素子に走査信号と表示信号の電圧を印加する駆動ドライバーと、フェースプレートのメタルバックに印加に高電圧を印加する高圧電源を不図示の高圧端子に接続する。このようにして画像を表示することが可能となる。
【００４２】
なお、本実施形態では電子放出素子として冷陰極素子を用いたが、熱陰極素子を用いてもよい。また冷陰極素子としては、表面伝導型電子放出素子の他に、電界放出型素子（以下、ＦＥ型と記す）、金属／絶縁層／金属型放出素子（以下、ＭＩＭ型と記す）、カーボンナノチューブを用いた電子放出素子等があるがこれらのいずれの素子を用いてもよい。
【００４３】
本発明の配線装置とその製造方法は、上述したような電子放出素子を用いたフラットディスプレイの他に、マトリクス配線を用いる、プラズマディスプレイ、液晶表示素子、光電変換部にアモルファスシリコンを用いた二次元光センサ等に用いることができる。
【００４４】
【実施例】
以下、具体的な実施例を挙げて本発明を説明するが、本発明はこれらの実施例に限定されるものではなく、本発明の目的が達成される範囲内での各要素の置換や設計変更がなされたものも包含する。
【００４５】
（実施例１）
本発明の第１の実施例を図１及び図２を参照して説明する。
【００４６】
本実施例は、層間絶縁層１０６の抜けパターン（コンタクトホール）１０７の一方のエッジ（図１中では下辺）が、第二導電層１０８のパターンニング用マスク１１１の開口部１１０上から不可視（遮蔽部１０９に隠蔽される）となった形態である。また、層間絶縁層１０６の中心と抜けパターン１０７の中心が一致せず、抜けパターン１０７が図１の紙面下方向へ偏心した形態としたものである。
【００４７】
次に、電子源基板の製造方法について、図３を参照しつつ詳述する。
【００４８】
まず、素子電極２、３を形成する。本実施例では、Ｐｔターゲットによりスパッタリング法により膜を形成した。膜厚は５０ｎｍ程度である。スパッタリング法により基板全面に膜を形成後、フォトリソグラフィーにより、所望のパターンを形成した（図３（ａ））。
【００４９】
次に、第一導電層５を形成する（図３（ｂ））。形成方法は、スクリーン印刷法を用いた。印刷に使用した材料は、導体成分としてＡｇを含有したスクリーン印刷用ペーストである。
【００５０】
次に、抜けパターン（コンタクトホール）７を紙面下方向へ偏心させた層間絶縁層６を形成する（図３（ｃ））。ペースト材料はＰｂＯを主成分としたガラスバインダーと樹脂及び感光成分を混合した感光性絶縁ペーストである。焼成温度は４８０℃で、ピーク保持時間は１０分である。通常、層間絶縁層６は第一、第二導電層５、８間の絶縁性を十分確保するために、全面印刷、パターン露光、現像、乾燥、焼成を繰り返す。パターン形成方法は種々可能であるが、本実施例では（１）全面印刷、（２）パターン露光、（３）現像、（４）乾燥、（５）焼成の順番で工程を実施した。なお、膜総数は、絶縁性を考慮して増減される。
【００５１】
次に、第二導電層８を形成する（図３（ｄ））。形成方法は厚膜スクリーン印刷法を用いた。その際に、先に説明した図１のＳＵＳ製の金属マスクを用いた。こうしたマスクを用いることにより、図２に示すような第二導電層１０８が得られる。図２は図１中のB-B'断面を示すものであり、同一の部材には同一符号を付してある。
【００５２】
このような形態により、層間絶縁層１０６と基板３１の界面に作用する応力が低減されるため、この界面での剥離、破壊がほとんど見られなくなった。すなわち、素子欠陥が激減したことを意味する。
【００５３】
なお、抜けパターン（コンタクトホール）１０７の位置、及びエッジと第二導電層１０８のマスクエッジの位置関係の具体的な値は、それぞれのサイズ、ペースト物性（粘弾性、粘度）、印刷条件等により適宜決められる。
【００５４】
以上で、マトリクス配線の部分が完成するが、ペースト材料、印刷方法等は、ここで記載されたものに限定されるものではない。
【００５５】
配線完成後、電子放出部形成用薄膜４（図３（ｄ））を形成する。具体的には、上記配線基板上に有機パラジウム（ＣＣＰ４２３０、奥野製薬工業（株）製）をスピンナーにより回転塗布後、３００℃で１０分間の加熱処理を実施し、Ｐｄからなる薄膜を形成する。このようにして形成されたＰｄ薄膜は、Ｐｄを主元素とする微粒子から構成され、その膜厚は１０ｎｍ、シート抵抗は５×１０⁴Ω／□であった。シート抵抗値は長さと幅が等しい導体の単位長さ換算の抵抗値として定義される。このＰｄ薄膜をフォトリソグラフィー法を用いて、パターニングすることにより電子放出部形成用薄膜４を形成した。
【００５６】
この基板を用いて図８に示したような画像表示装置９１を組み立てた。
【００５７】
次に、フォーミング処理を施す。フォーミング方法は、従来の方法を導入することが可能であり、本実施例では、以下の条件とした。図７（ａ）中、Ｔ１及びＴ２は電圧波形のパルス幅とパルス間隔であり、本実施例ではＴ１を１ミリ秒、Ｔ２を１０ミリ秒とし、三角波の波高値（フォーミング時のピーク電圧）は１４Ｖとしフォーミング処理は約１．３×１０^-4Ｐａの真空雰囲気下で６０秒間実施した。このようにして作成された電子放出部は、パラジウム元素を主成分とする微粒子が分散配置された状態となり、その微粒子の平均粒径は３ｎｍであった。なお、真空引きは不図示の排気管からスクロールポンプにて行った。
【００５８】
そして、排気管をガスバーナーで熱して溶着し、外囲気の封止を行った。
【００５９】
なお、封止後の真空度を維持するために、ゲッター処理を実施した。これは、封止を行う直前に高周波加熱により、画像表示装置内の所定の位置（不図示）に配置されたゲッターを加熱し、蒸着膜を形成する処理である。ゲッターとしてはＢａゲッターを用いた。
【００６０】
以上のとおりに完成した本実施例の画像表示装置において、容器外配線３０に走査信号及び変調信号を信号発生手段（不図示）から印加し、電子放出素子から電子放出させ、高圧導入端子（不図示）を通じてメタルバック８９に数ｋＶ（本実施例では６ｋｖ）を印加し、電子ビームを加速して蛍光体膜に衝突、励起、発光させることで画像を表示させた。
【００６１】
比較例として、図１１、図１２に示す第二導電層１０８を形成した画像表示装置を作成し、比較のために画像表示を行ったところ、本発明による製造方法による画像表示装置の方が明らかに画素欠陥が激減していることが確認された。すなわち、画像パネルの量産性、歩留りを向上させるために必要な技術であることが確認された。本実施例では、数百個の画素欠陥が数個〜数十個まで減少し、発生率としては１０％以下となった。
【００６２】
（実施例２）
本発明の第２の実施例を図９を参照して説明する。
【００６３】
本実施例は、層間絶縁層１０６の抜けパターン（コンタクトホール）１０７の両方のエッジ（図８中では上下辺）が、第二導電層１０８のパターンニング用マスク１１１の開口部１１０上から不可視（遮蔽部１０９に隠蔽される）となった形態である。本実施例では実施例１と異なり、層間絶縁層１０６の中心と抜けパターン１０７の中心が一致した形態としている。
【００６４】
上記以外の電子源基板及び画像表示装置の製造方法は、実施例１と全く同様であり、省略する。
【００６５】
以上のとおりに完成した本実施例の画像表示装置において、容器外配線３０に走査信号及び変調信号を信号発生手段（不図示）から印加して電子放出素子から電子放出させ、高圧導入端子（不図示）を通じてメタルバック８９に数ｋＶ（本実施例では６ｋｖ）を印加して電子ビームを加速して蛍光体膜に衝突、励起、発光させることで画像を表示させた。
【００６６】
比較例として、図１１、図１２に示す第二導電層１０８を形成した画像表示装置を作成し、比較のために画像表示を行ったところ、本発明による製造方法による画像表示装置の方が明らかに画素欠陥が激減していることが確認された。すなわち、画像パネルの量産性、歩留りを向上させるために必要な技術であることが確認された。本実施例では数百個の画素欠陥が数個〜数十個まで減少し、発生率としては１０％以下となった。
【００６７】
（実施例３）
本発明の第３の実施例を図１０を参照して説明する。
【００６８】
本実施例は、層間絶縁層１０６の抜けパターン（コンタクトホール）１０７の両方のエッジ（図８中では上下辺）が、第二導電層１０８のパターンニング用マスク１１１の開口部１１０上から不可視（遮蔽部１０９に隠蔽される）となった形態である。また、層間絶縁層１０６の中心と抜けパターン１０７の中心が一致せず、抜けパターン１０７が図１の紙面下方向へ偏心した形態としたものである。
【００６９】
上記以外の電子源基板及び画像表示装置の製造方法は、実施例１、２と全く同様であり、省略する。
【００７０】
以上のとおりに完成した本実施例の画像表示装置において、容器外配線３０に走査信号及び変調信号を信号発生手段（不図示）から印加して電子放出素子から電子放出させ、高圧導入端子（不図示）を通じてメタルバック８９に数ｋＶ（本実施例では６ｋｖ）を印加して電子ビームを加速して蛍光体膜に衝突、励起、発光させることで画像を表示させた。
【００７１】
比較例として、図１１、図１２に示す第二導電層１０８を形成した画像表示装置を作成し、比較のために画像表示を行ったところ、本発明による製造方法による画像表示装置の方が明らかに画素欠陥が激減していることが確認された。すなわち、画像パネルの量産性、歩留りを向上させるために必要な技術であることが確認された。本実施例では数百個の画素欠陥が数個〜数十個まで減少し、発生率としては１０％以下となった。
【００７２】
【発明の効果】
以上説明したように、本発明によれば、層間絶縁層と基板界面間に作用する応力を緩和させることが可能となり、その結果、例えば画像表示装置に本発明を用いた場合には画素欠陥（不良素子）を従来に比較して、激減させることが可能とり、画像表示装置の信頼性向上とともに、歩留り向上も可能となる。
【図面の簡単な説明】
【図１】本発明に係る電子源基板の製造方法の一実施形態を示す概略図である。
【図２】本発明により製造された電子源基板の一実施形態を示す概略断面図である。
【図３】本発明に係る一実施形態の電子源基板の製造方法フロー図である。
【図４】本発明による配線構造を説明するための図である。
【図５】表面伝導型電子放出素子の典型的な構成を示す図である。
【図６】表面伝導型電子放出素子の作製方法のプロセス工程を示す図である。
【図７】フォーミング処理に用いる典型的な波形を示す図である。
【図８】本発明の一実施形態に係る画像表示装置の一部を切り欠いて示す斜視図である。
【図９】本発明により製造された電子源基板の第二実施形態を示す概略断面図である。
【図１０】本発明に係る電子源基板の製造方法の第三実施形態を示す概略図である。
【図１１】従来の電子源基板の一部を模式的に示す図である。
【図１２】従来の電子源基板の一部を模式的に示す図である。
【図１３】従来例の応力集中を模式的に示す説明図である。
【符号の説明】
２，３素子電極、４電子放出部、５第一導電層、６層間絶縁層、７抜けパターン（コンタクトホール）、８第二導電層、
３１絶縁性基板、３２，３３素子電極、３４電子放出部形成用薄膜、３５電子放出部、
８１電子源基板、８３支持枠、８５第一導電層（Ｙ方向配線）、８６第二導電層（Ｘ方向配線）、８７ガラス基板、８８蛍光体膜、８９メタルバック、９０フェースプレート、９１画像表示装置
１０２，１０３素子電極、１０４電子放出部、１０５第一導電層、１０６層間絶縁層、１０７抜けパターン（コンタクトホール）、１０８第二導電層。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a wiring device and a wiring device, and in particular, an upper conductive layer extending in the same direction is formed on the lower conductive layer via an interlayer insulating film extending in one direction. The present invention relates to a method of manufacturing a wiring device in which a lower conductive layer and an upper conductive layer are connected through a hole and a wiring device.
[0002]
[Prior art]
A wiring device that forms an upper conductive layer extending in the same direction through an interlayer insulating film extending in one direction on the lower conductive layer and connects both the conductive layers through the openings in the interlayer insulating film uses a matrix wiring It is used in plasma displays, active matrix liquid crystal display elements, flat displays using electron-emitting devices, two-dimensional photosensors using amorphous silicon in the photoelectric conversion part, and the like. Hereinafter, a wiring structure will be described by taking an electron source substrate of a flat display using electron emitting elements as an example. In the electron source substrate, wirings are arranged in a matrix on the substrate, and electron-emitting devices connected to the upper wiring and the lower wiring are arranged near the intersection of the upper wiring and the lower wiring, respectively. Here, an element called a surface conduction electron-emitting device that emits electrons from an electron-emitting portion provided in a thin film is used as the electron-emitting device.
[0003]
11 is a configuration diagram showing the vicinity of a wiring intersection of an electron source substrate having matrix type wiring, and FIG. 12 is a configuration in which a part of the upper wiring in FIG. FIG.
[0004]
11 and 12, reference numeral 101 denotes a surface conduction electron-emitting device, which includes an electron-emitting portion forming thin film 104 on which an electron-emitting portion is formed, and device electrodes 102 and 103 connected to both ends of the thin film 104, respectively. The Reference numeral 105 denotes a first conductive layer connected to the device electrode 103, 106 denotes an interlayer insulating layer, 107 denotes an opening pattern (contact hole) provided in the interlayer insulating layer 106, and 108 denotes a second conductive layer. The device electrode 102 (lower conductive layer) and the second conductive layer 108 (upper electrode layer) are connected via the missing pattern 107, and an electron is formed in the thin film 104 by passing a current through the surface conduction electron-emitting device. Electrons are emitted from the emission part.
[0005]
[Problems to be solved by the invention]
Here, in the portion where the device electrode 102 and the second conductive layer 108 are connected to each other, the second conductive layer 108 is formed so as to drop due to the removal pattern 107 provided in the interlayer insulating layer 106. The thickness of the conductive layer 108 is increased. Furthermore, the thickness of each conductive layer tends to increase when realizing a low-resistance matrix wiring.
[0006]
The second conductive layer 108 has a large metal-containing component ratio for the purpose of reducing resistance, and has a larger linear expansion coefficient than the underlying interlayer insulating layer 106. The description will be made with reference to FIG. 13 which is a cross-sectional view along the line BB ′ in FIG. 12 (the device electrode 102 is omitted in FIG. 13). Due to the difference between the shrinkage during firing and the linear expansion coefficient, a large tensile stress acts on the interlayer insulating layer 106 when the temperature is returned to room temperature after firing. Then, the boundary region between the interlayer insulating layer 106 and the insulating substrate 31 is broken, and in the worst case, the device electrode 102 is torn and a defective device is generated.
[0007]
[Means for Solving the Problems]
  The method for manufacturing the wiring device according to the present invention includes:A method of manufacturing a wiring device in which a lower conductive layer and an upper conductive layer are connected through a contact hole provided in an interlayer insulating film,
  An interlayer insulating film having a contact hole surrounded by the entire circumference and extending in the X direction, at both ends of the interlayer insulating film defining the width of the interlayer insulating film in the Y direction perpendicular to the X direction Providing an interlayer insulating film in which the contact hole is located closer to the other end than one end so that the contact hole is located on the lower conductive layer;
  A mask having a shielding portion and an opening extending in the X direction is a portion of the contact hole, and at least a portion located on the other end side of the interlayer insulating film is covered with the shielding portion. Applying the material of the upper conductive layer through the opening of the mask so as to expose the other part of the contact hole at the opening, and
It is characterized by including.
  The wiring device manufacturing method of the present invention is a manufacturing method of a wiring device in which a lower conductive layer and an upper conductive layer are connected through a contact hole provided in an interlayer insulating film,
  Providing an interlayer insulating film having a contact hole surrounded by the entire circumference and extending in the X direction so that the contact hole is located on the lower conductive layer;
  A mask having a shielding part and an opening extending in the X direction is covered with the shielding part at both ends of the contact hole in the Y direction perpendicular to the X direction, and the contact hole in the Y direction is Applying the material of the upper conductive layer through the opening of the mask, applying on the interlayer insulating film so that other portions located between both ends are exposed in the opening;
  It is characterized by including.
[0008]
  The electron source substrate manufacturing method of the present invention is an electron source substrate manufacturing method in which an upper conductive layer and a lower conductive layer connected to an electron-emitting device are connected through a contact hole provided in an interlayer insulating film. And
  An interlayer insulating film having a contact hole surrounded by the entire circumference and extending in the X direction, at both ends of the interlayer insulating film defining the width of the interlayer insulating film in the Y direction perpendicular to the X direction Providing an interlayer insulating film in which the contact hole is located closer to the other end than one of the ends so that the contact hole is located on a lower conductive layer provided on the substrate; ,
  A mask having a shielding portion and an opening extending in the X direction is a portion of the contact hole, and at least a portion located on the other end side of the interlayer insulating film is covered with the shielding portion. Applying on the interlayer insulating film so that the other part of the contact hole is exposed at the opening, and applying a material to be an upper conductive layer through the opening of the mask;
It is characterized by including.
  The electron source substrate manufacturing method of the present invention is an electron source substrate manufacturing method in which an upper conductive layer and a lower conductive layer connected to an electron-emitting device are connected through a contact hole provided in an interlayer insulating film. There,
  A step of providing an interlayer insulating film having a contact hole surrounded by the entire circumference and extending in the X direction so that the contact hole is located on a lower conductive layer provided on the substrate;
  A mask having a shielding part and an opening extending in the X direction is covered with the shielding part at both ends of the contact hole in the Y direction perpendicular to the X direction, and the contact hole in the Y direction is Applying the material of the upper conductive layer through the opening of the mask, applying on the interlayer insulating film so that other portions located between both ends are exposed in the opening;
  It is characterized by including.
[0009]
  The method for manufacturing an image display device according to the present invention includes (i) a plurality of electron-emitting devices, and each of the plurality of electron-emitting devices is formed on the upper conductive layer through a plurality of contact holes provided in the interlayer insulating film. An image display comprising: an electron source substrate connected to each of a plurality of connected lower conductive layers; and (ii) a substrate having a phosphor film that emits light by electrons emitted from the plurality of electron-emitting devices. A device manufacturing method comprising:
  An interlayer insulating film having a plurality of contact holes surrounded by the entire circumference and extending in the X direction, both ends of the interlayer insulating film defining the width of the interlayer insulating film in the Y direction perpendicular to the X direction An interlayer insulating film in which the contact hole is located closer to the other end than one end of the portions is provided on each of the plurality of lower conductive layers provided side by side in the X direction on the substrate. Providing each of the plurality of contact holes on the upper surface;
  A mask having a shielding portion and an opening extending in the X direction is a part of each of the plurality of contact holes, and at least a portion located on the other end side of the interlayer insulating film is the shielding. A material that is covered on the interlayer insulating film so that the other part of each of the plurality of contact holes is exposed at the opening, and serves as an upper conductive layer through the opening of the mask Including a step of imparting.
The image display device manufacturing method according to the present invention includes (i) a plurality of electron-emitting devices, each of the plurality of electron-emitting devices passing through a plurality of contact holes provided in the interlayer insulating film. An electron source substrate connected to each of a plurality of lower conductive layers connected to the substrate, and (ii) a substrate having a phosphor film that emits light by electrons emitted from the plurality of electron-emitting devices. A method for manufacturing a display device, comprising:
  Each of the plurality of contact holes includes a plurality of contact holes surrounded by the entire periphery, and an interlayer insulating film extending in the X direction is provided on each of the plurality of lower conductive layers arranged in the X direction on the substrate. Providing a position so that
  A mask having a shielding portion and an opening extending in the X direction is covered with the shielding portion at both ends of the plurality of contact holes in the Y direction perpendicular to the X direction, and the plurality of contact holes A material that is applied on the interlayer insulating film so that the other portion located between the both ends in the Y direction of each of the first and second layers is exposed at the opening, and becomes an upper conductive layer through the opening of the mask Including a step of imparting.
[0010]
The upper electrode layer may be a printed wiring layer.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. Here, a description will be given taking an electron source substrate of a flat display using an electron-emitting device as an example. In the electron source substrate, wirings are arranged in a matrix on the substrate, and electron-emitting devices connected to the upper wiring and the lower wiring are arranged near the intersection of the upper wiring and the lower wiring, respectively. Here, an element called a surface conduction electron-emitting device that emits electrons from an electron-emitting portion provided in a thin film is used as the electron-emitting device.
[0012]
As the above surface conduction electron-emitting device, the present applicant has disclosed a method for arranging and driving a large number of devices in Japanese Patent Application Laid-Open No. 64-31332, and its application to an image display device has been disclosed. U.S. Pat. No. 5,066,883, JP-A-2-257551, JP-A-4-28137, and the like.
[0013]
FIG. 1 shows a method for manufacturing an electron source substrate used in an image display apparatus according to an embodiment of the present invention. FIG. 1 shows a top view after alignment of a mask 111 for patterning the second conductive layer 108 (not shown in FIG. 1) on the electron source substrate formed up to the interlayer insulating layer 106. In addition, the same code | symbol is attached | subjected about the same structural member as FIG.11 and FIG.12. (It is the same also in each figure after the following FIG. 3.).
[0014]
In FIG. 1, reference numeral 101 denotes a surface conduction electron-emitting device, which includes an electron-emitting portion forming thin film 104 in which an electron-emitting portion is formed, and device electrodes 102 and 103 connected to both ends of the thin film 104. 105 is a first conductive layer connected to the device electrode 103, 106 is an interlayer insulating layer extending in the X direction, 107 is a void pattern (contact hole) provided in the interlayer insulating layer 106, and 111 is a second conductive layer. A metal mask for patterning the film 108 (not shown in FIG. 1), 110 is an opening of the metal mask 111, and 109 is a shielding part of the metal mask 111. The device electrode 102 (lower conductive layer) is connected to the second conductive layer 108 (upper conductive layer) formed on the interlayer insulating film 106 using the mask 111 via the blank pattern 107, and the surface conduction electron-emitting device is connected. When an electric current is passed through, electrons are emitted from the electron emission portion formed in the thin film 104.
[0015]
FIG. 2 shows a cross-sectional view (cross-section BB ′ in FIG. 1) of the missing pattern 107 of the interlayer insulating layer 106 prepared as shown in FIG. The second conductive layer 108 is formed on the interlayer insulating film 106 using the mask 111. As shown in FIG. 1, the mask 111 is not provided so that the entire omission pattern 107 is included in the opening 110 of the mask 111, and one side of the side wall side along the X direction of the omission pattern 107 is the mask 111. It arrange | positions so that it may be covered with the shielding part 109. By disposing the mask 111 in this way, as shown in FIG. 2, a gap d is provided between one side wall (the left side wall in FIG. 2) of the interlayer insulating film and the second conductive layer 108. . Here, the gap d refers to a space where the upper end portion of one side wall and the second conductive layer 108 are not in contact with each other, and if not in contact with the upper end portion of the side wall, the second conductive layer 108 is in contact with the side wall up to the broken line portion 108a. It may be formed to extend.
[0016]
By providing the gap d as described above, the stress concentration in the boundary region between the interlayer insulating layer 106 and the insulating substrate 31 where the stress concentration occurred in FIG. 13 was reduced. The cause of this is not necessarily clear, but can be considered as follows. Referring to FIG. 13, even if tensile stress acts on the interlayer insulating layer 106 caused by the difference between the shrinkage during firing and the linear expansion coefficient between the second conductive layer 108, the portion that forms the opening in FIG. Compared with the width D of the interlayer insulating layer 106, as shown in FIG. 2, the width D of the portion of the interlayer insulating layer 106 where the hole is formed as shown in FIG.₁(D₁> D), the adhesive force between the substrate 31 and the interlayer insulating layer 106 is increased, and the stress concentration in the boundary region between the interlayer insulating layer 106 and the insulating substrate 31 can be reduced. Even if a tensile stress is applied to the interlayer insulating layer 106, if the contact area between the second conductive layer 108 and the interlayer insulating layer 106 is small, the value of the tensile stress applied to the interlayer insulating layer 106 is reduced, and the interlayer insulating layer 106 The stress concentration in the boundary region with the insulating substrate 31 can be relaxed.
[0017]
That is, the stress reduction effect on the right side of the interlayer insulating layer 106 due to the contact hole being moved to the left side, and a part of the contact hole opening is not visible from the opening of the printing mask shown in FIG. This is due to the stress reduction effect on the left side of the interlayer insulating layer 106 due to the reduction of the contact area between the interlayer insulating layer 106 and the second conductive layer 108. Conceivable. In particular, as shown in FIGS. 1 and 2, it is confirmed that the stress on the right side in FIG. 2 is about 30% smaller than the stress on the left side in FIG. Therefore, the form of FIGS. 1 and 2 is a more preferable form.
[0018]
As another embodiment of the present invention, as shown in FIG. 9, both sides of the side wall along the X direction of the missing pattern 107 are covered with the shielding portion 109 of the mask 111 so that the interlayer insulating layer 106 and the The stress concentration in the boundary region between the interlayer insulating layer 106 and the insulating substrate 31 can be alleviated only by the stress reduction effect due to the reduction of the contact area of the two conductive layers 108. As still another embodiment, as shown in FIG. 10, the other side wall along the X direction of the missing pattern 107 is covered with the shielding portion 109 of the mask 111 in the configuration shown in FIG. Thus, the stress reduction effect due to the reduction of the contact area between the interlayer insulating layer 106 and the second conductive layer 108 can also be realized on the other side wall.
[0019]
Hereinafter, with reference to the process flow diagram of FIG. 3, a method for manufacturing the electron source substrate according to each embodiment will be described.
[0020]
First, device electrodes 2 and 3 are formed on a substrate (not shown) (FIG. 3A). The device electrodes 2 and 3 are provided to make ohmic electrical contact between the electron emission portion forming thin film 4, the first conductive layer 5, and the second conductive layer 8.
[0021]
The element electrodes 2 and 3 can be formed by using a vacuum system such as a vacuum deposition method, a sputtering method, or a plasma CVD method, or by printing and baking a thick film paste in which an Ag component and a glass component are mixed in a solvent. There are a thick film printing method to be formed, an offset printing method using a Pt paste, and the like. In addition, when each conductive layer 5 and 8 for wiring is comprised with a thin film by sputtering method, for example, it is not always necessary to provide the device electrodes 2 and 3 and it is formed simultaneously with the first conductive layer 5 for wiring. Is possible.
[0022]
Next, the first conductive layer 5 connected to one of the element electrode pairs (the element electrode 3 in this example) is formed (FIG. 3B). A method similar to the method for forming the device electrodes 2 and 3 can be applied to the method for forming the first conductive layer 5, but it is advantageous to use the thick film printing method because of the necessity of low resistance wiring.
[0023]
In recent years, a film forming technique based on a photo paste method in which a photolithography technique is introduced for thick film paste printing has been developed. Of course, formation by a photo paste method is possible, and the width of the wiring (first conductive layer 5) is narrow. In this case, the photo paste method is advantageous when position accuracy is required for a large substrate.
[0024]
Next, the interlayer insulating layer 6 is formed (FIG. 3C). The interlayer insulating layer 6 is formed so as to cover a part of the first conductive layer 5, specifically, the intersection of the first conductive layer 5 with the second conductive layer 8.
[0025]
The constituent material of the interlayer insulating layer 6 is not particularly limited as long as it can maintain insulation, and is, for example, a thick film paste containing no metal component. Of course, it is also possible to apply a photo paste containing no metal component.
[0026]
Next, the second conductive layer 8 is formed (FIG. 3D). A method similar to that for the first conductive layer 5 can be applied. In this case, it is advantageous to use a thick film printing method because of the necessity of low resistance wiring.
[0027]
In the present embodiment, one of the opening edges of the opening pattern 7 of the interlayer insulating layer 6 provided to ensure the connection between one of the element electrode pairs (the element electrode 2 in the present embodiment) and the second conductive layer 8. The side wall side or both side wall sides along the X direction is invisible from the opening of the patterning metal mask 11 of the second conductive layer 8 (covered by the shielding portion of the mask 11). Further, the missing pattern 7 of the interlayer insulating layer 6 and the interlayer insulating layer are arranged eccentrically. That is, as shown in FIG. 4, the center C of the width of the interlayer insulating layer 106 or the second conductive layer 8 in the Y direction perpendicular to the X direction.₁(Here, the center of the width of the interlayer insulating layer 106 and the center of the width of the second conductive layer 8 coincide), the center C of the width in the Y direction of the missing pattern 7.₂The distance d_CThey are only shifted (eccentric).
[0028]
Next, the electron emission portion forming thin film 4 is formed to complete the element 1 for the cold cathode electron beam source (FIG. 3E). Conventional methods can be applied as they are to the method for forming the electron emission portion forming thin film 4 and the method for forming the electron emission portion.
[0029]
In this way, an electron source substrate having a simple matrix configuration is completed.
[0030]
The configuration, manufacturing method, and characteristics of the surface conduction electron-emitting device are disclosed in, for example, Japanese Patent Laid-Open No. 2-56822, and the configuration and manufacturing method can also be used in this embodiment. Here, only the outline of the structure, manufacturing method, and characteristics of the surface conduction electron-emitting device will be described.
[0031]
FIG. 5 is a diagram showing a configuration of a typical surface conduction electron-emitting device according to the present invention. In FIG. 5, 31 is an insulating substrate, 32 and 33 are element electrodes, 34 is an electron emission portion forming thin film to which the element electrodes 32 and 33 are connected at both ends, and 35 is formed on an electron emission portion forming thin film 34. The electron emission part.
[0032]
In the present embodiment, among the electron emission portion forming thin film 34 including the electron emission portion 35, the electron emission portion 35 is made of electrically conductive particles having a particle size of several nanometers and includes an electron emission portion 35. The portion of the thin film 34 other than the electron emission portion 35 is made of a fine particle film. The fine particle film described here is a film in which a plurality of fine particles are aggregated, and the fine structure is not only in a state where the fine particles are dispersed individually, but also in a state where the fine particles are adjacent to each other or overlap (including island shapes). Refers to the membrane.
[0033]
Specific examples of constituent atoms or molecules of the electron emission portion forming thin film 34 including the electron emission portion include Pd, Ru, Ag, Au, Ti, In, Cu, Cr, Fe, Zn, Sn, Ta, W, and Pb. Metals such as PdO, SnO₂, In₂O_Three, PbO, Sb₂O_ThreeOxides such as HfB₂, ZrB₂, LaB₆, CeB₆, YB_Four, GdB_FourBorides such as TiC, ZrC, HfC, TaC, SiC, and WC, nitrides such as TiN, ZrN, and HfN, semiconductors such as Si and Ge, and carbon, AgMg, NiCu, and PbSn.
[0034]
Examples of the method for forming the electron emission portion forming thin film 34 include a vacuum deposition method, a sputtering method, a chemical vapor deposition method, a dispersion coating method, a dipping method, and a spinner method.
[0035]
There are various methods for forming the surface conduction electron-emitting device shown in FIG. 5, and one example is shown in FIG.
[0036]
Hereinafter, a method for forming the element will be described. Although the following description explains a method for forming a single element, it is also applicable to a method for manufacturing an electron source substrate according to an embodiment of the present invention.
(1) After the insulating substrate 31 is sufficiently washed with a detergent, pure water and an organic solvent, element electrodes 32 and 33 are formed on the surface of the insulating substrate 31 by a vacuum deposition technique and a photolithography technique (FIG. 6 ( a)). Any material can be used as the material for the device electrodes 32 and 33 as long as it has electrical conductivity. For example, nickel metal is used. Regarding the dimensions of the device electrodes 32 and 33, for example, the device electrode interval L is 10 μm, the device electrode length W is 300 μm, and the film thickness d.₁Is 100 nm. As a method for forming the device electrodes 32 and 33, a thick film printing method may be used. As a material for the printing method, there is an organic metal paste (MOD) or the like.
(2) An organic metal thin film is formed by applying and leaving an organic metal solution between the device electrodes 32 and 33 provided on the insulating substrate 31. The organometallic solution is a solution of an organic compound containing a metal such as Pd, Ru, Ag, Au, Ti, In, Cu, Cr, Fe, Zn, Sn, Ta, W, and Pb as a main element. Thereafter, the organic metal thin film is heated and fired and patterned by lift-off, etching, or the like to form the electron emission portion forming thin film 34 (FIG. 6B).
(3) Subsequently, by applying a voltage between the device electrodes 32 and 33 by an energization process called forming, an electron emitting portion 35 having a structural change is formed in the portion of the electron emitting portion forming thin film 34. (FIG. 6C). The portion where the structure is changed by locally destroying, deforming or altering the electron emission portion forming thin film 34 by this energization process is called an electron emission portion 35. As described above, it was observed that the electron emission portion 35 is composed of metal fine particles.
[0037]
FIG. 7 shows voltage waveforms during the forming process. In FIG. 7, T1 and T2 are the pulse width and pulse interval of the voltage waveform, respectively, T1 is 1 microsecond to 10 milliseconds, T2 is 10 microseconds to 100 milliseconds, the peak value of the triangular wave (peak voltage at the time of forming) ) Was set to about 4V to 10V, and the forming process was set in a timely manner for several tens of seconds in a vacuum atmosphere.
[0038]
As described above, the forming process is performed by applying the triangular wave pulse between the device electrodes when forming the electron emission portion described above. However, the waveform applied between the device electrodes is not limited to the triangular wave, and a rectangular wave or the like is desired. The wave height value, pulse width, pulse interval, and the like are not limited to the above values, and a desired value can be selected if the electron emission portion is well formed.
[0039]
A configuration and a manufacturing method of the image display device 91 using the electron source substrate created as described above will be described. As shown in FIG. 8, a plurality of electron-emitting devices are arranged on a substrate 81 and are electrically connected to an X-direction wiring 86 and a Y-direction wiring 85 to form a simple matrix wiring structure. A face plate 90 (a phosphor film 88 and a metal back 89 are formed on the inner surface of the glass substrate 87) is disposed 2 mm above the substrate 81 via a support frame 83, and the face plate 90, the support frame 83, and the substrate 81 are disposed. A frit glass was applied to the bonded portion and sealed by firing at 400 ° C. to 500 ° C. for about 10 minutes in the air or in a nitrogen atmosphere. In FIG. 8, 35 is an electron-emitting device, and 85 and 86 are first and second conductive layers (Y and X direction wirings), respectively.
[0040]
The image display device thus created is evacuated to a sufficient degree of vacuum by a vacuum pump through an exhaust pipe (not shown). Thereafter, a voltage is applied between the device electrodes through the lead-out wiring 30 outside the container, the forming process described above is performed, an electron-emitting portion is formed, and the electron-emitting device 35 is formed. Finally, 10^-FourThe exhaust pipe is heated and welded at a degree of vacuum of about Pa or less to seal the vacuum envelope. Further, a getter treatment step is performed in order to maintain the degree of vacuum after sealing. This heats a getter (not shown) installed inside the image display device by resistance heating or high-frequency overheating after sealing to form a getter vapor deposition film. As the getter, Ba or the like is usually the main component, and the degree of vacuum is maintained by the pumping action of the deposited film.
[0041]
In order to display an image on the image display device created as described above, a driving driver that applies a voltage of a scanning signal and a display signal to the element through the lead-out wiring 30, and a high voltage to be applied to the metal back of the face plate Connect the high voltage power supply to the high voltage terminal (not shown). In this way, an image can be displayed.
[0042]
In this embodiment, a cold cathode device is used as the electron-emitting device, but a hot cathode device may be used. In addition to surface conduction electron-emitting devices, cold cathode devices include field emission devices (hereinafter referred to as FE types), metal / insulating layer / metal emission devices (hereinafter referred to as MIM types), carbon nanotubes. However, any of these elements may be used.
[0043]
In addition to the flat display using the electron-emitting device as described above, the wiring device and the manufacturing method of the present invention are a two-dimensional plasma display, a liquid crystal display device using a matrix wiring, an amorphous silicon for a photoelectric conversion part. It can be used for an optical sensor or the like.
[0044]
【Example】
Hereinafter, the present invention will be described by way of specific examples. However, the present invention is not limited to these examples, and the replacement and design of each element within the scope of achieving the object of the present invention. Includes changes made.
[0045]
(Example 1)
A first embodiment of the present invention will be described with reference to FIGS.
[0046]
In this embodiment, one edge (the lower side in FIG. 1) of the pattern (contact hole) 107 of the interlayer insulating layer 106 is invisible (shielded) from above the opening 110 of the patterning mask 111 of the second conductive layer 108. This is a form that is concealed by the portion 109. Further, the center of the interlayer insulating layer 106 and the center of the missing pattern 107 do not coincide with each other, and the missing pattern 107 is decentered in the downward direction in FIG.
[0047]
Next, a method for manufacturing the electron source substrate will be described in detail with reference to FIG.
[0048]
First, the device electrodes 2 and 3 are formed. In this example, a film was formed by sputtering using a Pt target. The film thickness is about 50 nm. After forming a film on the entire surface of the substrate by sputtering, a desired pattern was formed by photolithography (FIG. 3A).
[0049]
Next, the first conductive layer 5 is formed (FIG. 3B). As a forming method, a screen printing method was used. The material used for printing is a screen printing paste containing Ag as a conductor component.
[0050]
Next, an interlayer insulating layer 6 is formed in which the missing pattern (contact hole) 7 is decentered downward in the drawing (FIG. 3C). The paste material is a photosensitive insulating paste in which a glass binder mainly composed of PbO, a resin, and a photosensitive component are mixed. The firing temperature is 480 ° C. and the peak retention time is 10 minutes. In general, the interlayer insulating layer 6 is repeatedly printed on the entire surface, patterned, developed, dried, and fired in order to ensure sufficient insulation between the first and second conductive layers 5 and 8. Various pattern forming methods are possible, but in this example, the steps were performed in the order of (1) full surface printing, (2) pattern exposure, (3) development, (4) drying, and (5) firing. Note that the total number of films is increased or decreased in consideration of insulation.
[0051]
Next, the second conductive layer 8 is formed (FIG. 3D). A thick film screen printing method was used as the forming method. At that time, the metal mask made of SUS described above in FIG. 1 was used. By using such a mask, the second conductive layer 108 as shown in FIG. 2 is obtained. FIG. 2 shows a BB ′ cross section in FIG. 1, and the same members are denoted by the same reference numerals.
[0052]
With such a configuration, the stress acting on the interface between the interlayer insulating layer 106 and the substrate 31 is reduced, so that peeling and destruction at this interface are hardly observed. That is, it means that the element defects have been drastically reduced.
[0053]
The specific values of the position of the missing pattern (contact hole) 107 and the positional relationship between the edge and the mask edge of the second conductive layer 108 depend on the size, paste physical properties (viscoelasticity, viscosity), printing conditions, etc. It is decided appropriately.
[0054]
Although the matrix wiring portion is completed as described above, the paste material, the printing method, and the like are not limited to those described here.
[0055]
After the wiring is completed, the electron emission portion forming thin film 4 (FIG. 3D) is formed. Specifically, organic palladium (CCP4230, manufactured by Okuno Pharmaceutical Co., Ltd.) is spin-coated with a spinner on the wiring board, and then heat-treated at 300 ° C. for 10 minutes to form a thin film made of Pd. The Pd thin film thus formed is composed of fine particles containing Pd as a main element, the film thickness is 10 nm, and the sheet resistance is 5 × 10.^FourIt was Ω / □. The sheet resistance value is defined as a resistance value in terms of unit length of a conductor having the same length and width. The thin film 4 for forming an electron emission portion was formed by patterning the Pd thin film using a photolithography method.
[0056]
An image display device 91 as shown in FIG. 8 was assembled using this substrate.
[0057]
Next, a forming process is performed. As a forming method, a conventional method can be introduced. In this embodiment, the following conditions are used. In FIG. 7A, T1 and T2 are the pulse width and pulse interval of the voltage waveform. In this embodiment, T1 is 1 millisecond and T2 is 10 milliseconds, and the peak value of the triangular wave (peak voltage at the time of forming). Is 14V and the forming process is about 1.3 × 10^-FourIt was carried out for 60 seconds in a vacuum atmosphere of Pa. The electron emission portion thus prepared was in a state where fine particles mainly composed of palladium element were dispersed and the average particle size of the fine particles was 3 nm. The evacuation was performed by a scroll pump from an unillustrated exhaust pipe.
[0058]
Then, the exhaust pipe was heated and welded with a gas burner to seal the outer atmosphere.
[0059]
In addition, in order to maintain the vacuum degree after sealing, getter processing was performed. This is a process in which a getter disposed at a predetermined position (not shown) in the image display device is heated by high-frequency heating immediately before sealing to form a deposited film. A Ba getter was used as the getter.
[0060]
In the image display apparatus according to the present embodiment completed as described above, the scanning signal and the modulation signal are applied to the external wiring 30 from the signal generating means (not shown), the electrons are emitted from the electron emitting device, and the high voltage introduction terminal (not shown) An image was displayed by applying several kV (6 kv in the present embodiment) to the metal back 89 through the drawing and accelerating the electron beam to collide, excite and emit light on the phosphor film.
[0061]
As a comparative example, an image display device in which the second conductive layer 108 shown in FIGS. 11 and 12 was formed and an image display was performed for comparison. The image display device according to the manufacturing method according to the present invention is clearer. It was confirmed that pixel defects were drastically reduced. That is, it was confirmed that this technique is necessary for improving the mass productivity and yield of the image panel. In this example, several hundreds of pixel defects were reduced to several to several tens, and the occurrence rate was 10% or less.
[0062]
(Example 2)
A second embodiment of the present invention will be described with reference to FIG.
[0063]
In this embodiment, both edges (upper and lower sides in FIG. 8) of the pattern (contact hole) 107 of the interlayer insulating layer 106 are invisible from above the opening 110 of the patterning mask 111 of the second conductive layer 108 ( This is a form that is concealed by the shielding portion 109. In this embodiment, unlike the first embodiment, the center of the interlayer insulating layer 106 and the center of the missing pattern 107 are aligned.
[0064]
The manufacturing method of the electron source substrate and the image display device other than those described above is exactly the same as that of the first embodiment, and will be omitted.
[0065]
In the image display apparatus according to the present embodiment completed as described above, the scanning signal and the modulation signal are applied to the external wiring 30 from the signal generating means (not shown) to emit electrons from the electron-emitting device, and the high-voltage introduction terminal (not shown). An image was displayed by applying several kV (6 kv in the present embodiment) to the metal back 89 through the illustration and accelerating the electron beam to collide, excite and emit light on the phosphor film.
[0066]
As a comparative example, an image display device in which the second conductive layer 108 shown in FIGS. 11 and 12 was formed and an image display was performed for comparison. The image display device according to the manufacturing method according to the present invention is clearer. It was confirmed that pixel defects were drastically reduced. That is, it was confirmed that this technique is necessary for improving the mass productivity and yield of the image panel. In this embodiment, several hundreds of pixel defects are reduced to several to several tens, and the occurrence rate is 10% or less.
[0067]
(Example 3)
A third embodiment of the present invention will be described with reference to FIG.
[0068]
In this embodiment, both edges (upper and lower sides in FIG. 8) of the pattern (contact hole) 107 of the interlayer insulating layer 106 are invisible from above the opening 110 of the patterning mask 111 of the second conductive layer 108 ( This is a form that is concealed by the shielding portion 109. Further, the center of the interlayer insulating layer 106 and the center of the missing pattern 107 do not coincide with each other, and the missing pattern 107 is decentered in the downward direction in FIG.
[0069]
The manufacturing method of the electron source substrate and the image display device other than those described above is exactly the same as in the first and second embodiments, and will be omitted.
[0070]
In the image display apparatus according to the present embodiment completed as described above, the scanning signal and the modulation signal are applied to the external wiring 30 from the signal generating means (not shown) to emit electrons from the electron-emitting device, and the high-voltage introduction terminal (not shown). An image was displayed by applying several kV (6 kv in the present embodiment) to the metal back 89 through the illustration and accelerating the electron beam to collide, excite and emit light on the phosphor film.
[0071]
As a comparative example, an image display device in which the second conductive layer 108 shown in FIGS. 11 and 12 was formed and an image display was performed for comparison. The image display device according to the manufacturing method according to the present invention is clearer. It was confirmed that pixel defects were drastically reduced. That is, it was confirmed that this technique is necessary for improving the mass productivity and yield of the image panel. In this embodiment, several hundreds of pixel defects are reduced to several to several tens, and the occurrence rate is 10% or less.
[0072]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the stress acting between the interlayer insulating layer and the substrate interface. As a result, when the present invention is used for an image display device, for example, pixel defects ( It is possible to drastically reduce the number of defective elements) as compared with the prior art, and it is possible to improve the reliability of the image display device and the yield.
[Brief description of the drawings]
FIG. 1 is a schematic view showing an embodiment of a method for producing an electron source substrate according to the present invention.
FIG. 2 is a schematic cross-sectional view showing an embodiment of an electron source substrate manufactured according to the present invention.
FIG. 3 is a flowchart of a method for manufacturing an electron source substrate according to an embodiment of the present invention.
FIG. 4 is a diagram for explaining a wiring structure according to the present invention.
FIG. 5 is a diagram showing a typical configuration of a surface conduction electron-emitting device.
FIG. 6 is a diagram showing process steps of a method for manufacturing a surface conduction electron-emitting device.
FIG. 7 is a diagram illustrating a typical waveform used for forming processing.
FIG. 8 is a perspective view showing a part of the image display device according to the embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view showing a second embodiment of an electron source substrate manufactured according to the present invention.
FIG. 10 is a schematic view showing a third embodiment of a method for manufacturing an electron source substrate according to the present invention.
FIG. 11 is a diagram schematically showing a part of a conventional electron source substrate.
FIG. 12 is a diagram schematically showing a part of a conventional electron source substrate.
FIG. 13 is an explanatory diagram schematically showing stress concentration in a conventional example.
[Explanation of symbols]
2, 3 Device electrode, 4 Electron emission part, 5 First conductive layer, 6 Interlayer insulating layer, 7 Omission pattern (contact hole), 8 Second conductive layer,
31 Insulating substrate, 32, 33 Device electrode, 34 Thin film for forming electron emission portion, 35 Electron emission portion,
81 electron source substrate, 83 support frame, 85 first conductive layer (Y direction wiring), 86 second conductive layer (X direction wiring), 87 glass substrate, 88 phosphor film, 89 metal back, 90 face plate, 91 image Display device
102, 103 Device electrode, 104 Electron emission portion, 105 First conductive layer, 106 Interlayer insulating layer, 107 Omission pattern (contact hole), 108 Second conductive layer.

Claims

A method of manufacturing a wiring device in which a lower conductive layer and an upper conductive layer are connected through a contact hole provided in an interlayer insulating film,
An interlayer insulating film having a contact hole surrounded by the entire circumference and extending in the X direction, at both ends of the interlayer insulating film defining the width of the interlayer insulating film in the Y direction perpendicular to the X direction Providing an interlayer insulating film in which the contact hole is located closer to the other end than one end so that the contact hole is located on the lower conductive layer;
A mask having a shielding portion and an opening extending in the X direction is a portion of the contact hole , and at least a portion located on the other end side of the interlayer insulating film is covered with the shielding portion. Applying the material of the upper conductive layer through the opening of the mask so as to expose the other part of the contact hole at the opening, and
A method for manufacturing a wiring device comprising:

A method of manufacturing a wiring device in which a lower conductive layer and an upper conductive layer are connected through a contact hole provided in an interlayer insulating film,
Providing a contact hole surrounded by the entire circumference and extending in the X direction so that the contact hole is positioned on the lower conductive layer;
A mask having a shielding part and an opening extending in the X direction is covered with the shielding part at both ends of the contact hole in the Y direction perpendicular to the X direction, and the contact hole in the Y direction is Applying the material of the upper conductive layer through the opening of the mask, applying on the interlayer insulating film so that other portions located between both ends are exposed in the opening;
A method for manufacturing a wiring device comprising:

In the manufacturing method of a wiring apparatus according to claim 2, and characterized with respect to the center of the width of the interlayer insulating film before Symbol Y direction, the center of the width of the contact hole in the Y direction is shifted, the A method for manufacturing a wiring device.

Wherein the manufacturing method of a wiring apparatus according to claim 1 or 3, wherein with respect to the center of the width of the upper conductive layer in the Y direction, the center of the width of the contact hole in the Y direction is shifted, the A method for manufacturing a wiring device.

5. The method for manufacturing a wiring device according to claim 1, wherein the upper conductive layer is formed by a printing method. 6.

A method of manufacturing an electron source substrate, wherein an upper conductive layer and a lower conductive layer connected to an electron-emitting device are connected through a contact hole provided in an interlayer insulating film,
An interlayer insulating film having a contact hole surrounded by the entire circumference and extending in the X direction, at both ends of the interlayer insulating film defining the width of the interlayer insulating film in the Y direction perpendicular to the X direction Providing an interlayer insulating film in which the contact hole is located closer to the other end than one of the ends so that the contact hole is located on a lower conductive layer provided on the substrate; ,
A mask having a shielding portion and an opening extending in the X direction is a portion of the contact hole , and at least a portion located on the other end side of the interlayer insulating film is covered with the shielding portion. Applying on the interlayer insulating film so that the other part of the contact hole is exposed at the opening, and applying a material to be an upper conductive layer through the opening of the mask;
The manufacturing method of the electron source board | substrate characterized by the above-mentioned.

A method of manufacturing an electron source substrate, wherein an upper conductive layer and a lower conductive layer connected to an electron-emitting device are connected through a contact hole provided in an interlayer insulating film,
A step of providing an interlayer insulating film having a contact hole surrounded by the entire circumference and extending in the X direction so that the contact hole is located on a lower conductive layer provided on the substrate;
A mask having a shielding part and an opening part extending in the X direction is set to be perpendicular to the X direction. On the interlayer insulating film, both ends of the contact hole in the direction are covered with the shielding portion, and other portions located between the both ends in the Y direction of the contact hole are exposed at the opening. Applying the material of the upper conductive layer through the opening of the mask,
The manufacturing method of the electron source board | substrate characterized by including.

(I) A plurality of electron-emitting devices are provided, and each of the plurality of electron-emitting devices is connected to each of the plurality of lower conductive layers connected to the upper conductive layer through the plurality of contact holes provided in the interlayer insulating film. A method of manufacturing an image display device, comprising: an electron source substrate connected; and (ii) a substrate having a phosphor film that emits light by electrons emitted from the plurality of electron-emitting devices,
An interlayer insulating film having a plurality of contact holes surrounded by the entire circumference and extending in the X direction, both ends of the interlayer insulating film defining the width of the interlayer insulating film in the Y direction perpendicular to the X direction one other than the end portion of the interlayer insulating film where the contact hole near the edge portion is positioned within the part, each of the plurality of lower conductive layer provided side by side in the X direction on the substrate Providing each of the plurality of contact holes on the upper surface;
A mask having a shielding portion and an opening extending in the X direction is a part of each of the plurality of contact holes, and at least a portion located on the other end side of the interlayer insulating film is the shielding. A material that is covered on the interlayer insulating film so that the other part of each of the plurality of contact holes is exposed at the opening, and serves as an upper conductive layer through the opening of the mask The manufacturing method of the image display apparatus characterized by including the process to provide.

(I) A plurality of electron-emitting devices are provided, and each of the plurality of electron-emitting devices is connected to each of the plurality of lower conductive layers connected to the upper conductive layer through the plurality of contact holes provided in the interlayer insulating film. A method of manufacturing an image display device, comprising: an electron source substrate connected; and (ii) a substrate having a phosphor film that emits light by electrons emitted from the plurality of electron-emitting devices,
Each of the plurality of contact holes includes a plurality of contact holes surrounded by the entire periphery, and an interlayer insulating film extending in the X direction is provided on each of the plurality of lower conductive layers arranged in the X direction on the substrate. Providing a position so that
A mask having a shielding portion and an opening extending in the X direction is covered with the shielding portion at both ends of the plurality of contact holes in the Y direction perpendicular to the X direction, and the plurality of contact holes A material that is applied on the interlayer insulating film so that the other portion located between the both ends in the Y direction of each of the first and second layers is exposed at the opening, and becomes an upper conductive layer through the opening of the mask The manufacturing method of the image display apparatus characterized by including the process of providing.