JP3835684B2 - Via hole formation method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a connection hole (via hole).
[0002]
[Prior art]
The via contact is formed in an interlayer insulating film in order to electrically connect two different layers of metal wiring in an LSI. In forming this contact, a metal for connecting the two layers of metal wiring is embedded. It is necessary to form a connection hole (via hole) for this purpose.
[0003]
In the conventional via contact formation method, first, after forming a lower layer metal wiring, an interlayer insulating film for electrically insulating the metal wiring is formed, and a resist is applied on the insulating film to perform photolithography. Then, a connection hole (via hole) pattern is formed by performing an etching process. Next, based on this pattern, the interlayer insulating film on the lower layer metal wiring is etched by RIE (Reactive Ion Etching) method. Remove to form a via hole.
[0004]
Subsequently, in order to form a buried metal inside the via hole, a metal (Au is generally used) is uniformly deposited on the resist to electrically connect the buried metal and the lower layer metal wiring. The resist is removed using a solvent. In this resist removal step, the metal adhering to the resist is also lifted off and removed.
[0005]
[Problems to be solved by the invention]
However, according to such a conventional via hole forming process, the so-called “side etching” occurs in the above-described interlayer insulating film etching process, and the interlayer insulating film is not etched in accordance with the resist pattern, and the resist is shaped like a ridge. The remaining undercut is formed. When the metal is deposited in this state, the metal gradually adheres to the patterned resist side surface, and the amount of undercut formed in the etching process increases more and more, and the extent of the overhang of the resist and the metal becomes more intense. . Such overhang of the ridge reduces the opening area of the via hole and reduces the amount of metal embedded in the via hole. As a result, the cross-sectional shape of the embedded metal is not a rectangular parallelepiped, but a trapezoidal shape whose base is wide (thick) and narrows toward the tip.
[0006]
For example, when Au, which is a buried metal, is buried in a fine contact hole having a width of 1 μm by about 0.7 μm, the resist and the metal on the resist are removed by a lift-off method for the buried metal having a trapezoidal cross-sectional shape. As a result, the distance between the embedded metal tip and the edge of the interlayer insulating film increases to 0.3 μm or more, and a gap of 0.3 μm on one side is generated. Even if the upper metal wiring is formed on the via contact in such a state, the metal cannot sufficiently fill the gap, and the wiring is cracked, and the reliability is deteriorated due to the conduction failure caused by the disconnection. There was a problem of doing.
[0007]
The present invention has been made in view of such problems, and an object of the present invention is to provide a via hole forming method for eliminating a connection failure between a via hole metal and an upper metal wiring formed thereon. It is to provide.
[0008]
[Means for Solving the Problems]
In order to achieve such an object, the present invention provides a method for forming a via hole for electrically connecting a lower layer metal material and an upper layer metal material, wherein A first step of forming a film; a second step of patterning a shape of a via hole opening in a resist applied on the insulating film; and etching away the interlayer insulating film based on the via hole opening pattern A third step of forming a via hole, a fourth step of applying a heat treatment to the resist to smooth the angle of the resist side wall portion of the via hole opening pattern, and the inside of the via hole and on the resist. A fifth step of depositing a metal and a sixth step of removing the resist to lift off the metal on the resist are provided.
[0009]
The invention according to claim 2 is the method for forming a via hole according to claim 1, wherein the resist is exposed to oxygen plasma between the third step and the fourth step. The method further comprises a seventh step of enlarging the via hole opening pattern pattern and simultaneously reducing the thickness of the resist.
[0010]
The invention according to claim 3 is the method for forming a via hole according to claim 2, wherein the thickness of the resist after completion of the seventh step is 1.0 μm or less and 0.5 μm or more. It is characterized by.
[0011]
Further, according to a fourth aspect of the present invention, in the method for forming a via hole according to any one of the first to third aspects, the resist side wall surface and the interlayer insulating film surface at the end of the fourth step are formed. The angle is 45 ° or more and 75 ° or less.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0013]
FIG. 1 is a diagram for explaining an example of a method for forming a via hole according to the present invention. FIG. 1A shows a state immediately after etching an underlying interlayer insulating film using a resist opening as a mask. Yes. That is, after applying a resist 13 on, for example, an SOG (Spin on Glass) interlayer insulating film 12 covering the lower metal wiring 11, this is developed so as to remove only the opening 14 of the via hole, and then RIE is performed. The SOG interlayer insulating film 12 is etched using this opening pattern as a mask. Note that CF ₄ is generally used as a reactive gas for RIE, but is not limited thereto, and etching is performed on an interlayer insulating film such as SiON, SiN, SiO ₂ , and SOG as long as it is a fluorine-based gas. Applicable as gas.
[0014]
In this etching step, although depending on the conditions, etching proceeds slightly (side etching) in the lateral direction of the interlayer insulating film 12 simultaneously with the etching of the interlayer insulating film 12 in the depth direction. The shape of the opening hole 14 is wide at the surface side and narrow at the deep part. In this state, if the metal is to be embedded in the opening 14 portion, the resist 13 plays a role of so-called soot, and the metal is concentrated on the upper corner portion of the resist 14. The overhang will become larger and the opening area of the via hole will be reduced more and more. Therefore, in the method for forming a via hole according to the present invention, the shape of the resist 13 is changed by performing heat treatment (baking) on the resist 13 before the metal is deposited.
[0015]
FIG. 1B is a view for explaining the resist shape after the resist 13 is baked, and the edge angle of the resist after baking (side wall angle: θ _a ) is before baking (FIG. 1 ( The edge angle of the resist (a) is changed from 85 ° to 90 ° to 45 ° to 75 ° (side wall angle: θ _b ).
[0016]
This baking condition (temperature / time) depends on the type of resist 13 to be used (basic material resin), but this baking treatment is meaningful in that the edge angle of the resist 13 is in the range of 45 ° to 75 °. Therefore, a temperature of about 150 ° C. or higher at which the pattern shape is rounded or a temperature of 100 ° C. or lower at which no change occurs in the resist shape is not suitable, and hard baking (this is performed in a temperature range of 120 ° C. to 150 ° C. This is done by holding the patterned wafer in a furnace heated to a temperature for a predetermined time (tens of minutes).
[0017]
Further, when the edge angle after baking is 45 ° or less, too much metal adheres to the side surface of the resist 13, and lift-off performed in the subsequent process becomes impossible. This is not preferable because the formation suppressing effect is lowered.
[0018]
After changing the resist shape by performing such baking, metal deposition is performed using the resist 13 as a mask.
[0019]
FIG. 1C is a diagram for explaining a state after metal deposition. In this example, Ti, Pt, and Au are used as embedded metals, and Ti (20 nm) / Pt (40 nm) / Au. A metal layer 15 having a three-layer structure (300 nm) was continuously formed. Here, the lowermost Ti layer 15a increases the adhesion with the lower layer metal wiring 11 (in this case, the electrode metal, heat-treated Pt / Ti / Pt / Au). The Au layer 15c is provided to suppress the solid-phase reaction of the layer 15c and dominates the conductive function.
[0020]
In such a metal vapor deposition process, the vapor deposited metal is most easily deposited on the edge portion of the resist 13. However, in the via hole forming method of the present invention, the edge angle of the resist 13 is dulled in advance. Even if metal is deposited on the edge portion, the resist opening is not narrowed. Therefore, although the metal shape after being embedded in the via hole becomes a trapezoidal shape, the difference in length between the upper base and the lower base is not remarkable, and a shape close to a square is obtained.
[0021]
In order to obtain a metal shape close to a square shape, it is also effective to recede the resist 13 on the interlayer insulating film 12 in the lateral direction before performing metal vapor deposition. That is, when the hole diameters of the resist 13 and the lower insulating film 12 after RIE are compared, the opening diameter of the interlayer insulating film 12 is larger. For example, the resist shape is dulled to suppress metal deposition on the edge portion. However, due to the difference in opening diameter between the resist 13 and the lower insulating film 12, there may still be a difference between the via hole embedded metal and the via hole opening diameter. In order to avoid this, metal deposition is performed. The resist opening diameter is widened in advance.
[0022]
Specifically, the substrate on which the resist 13 is patterned is exposed to oxygen plasma, and the resist 13 is etched to widen the hole diameter. The etching conditions are preferably isotropic, and therefore the plasma mode is selected over the RIE mode (the former is when the gas pressure is low and the power of the applied high-frequency signal is high, that is, individual oxygen molecules / radicals). Corresponds to the condition where the oxygen ions / radicals are easily accelerated isotropically when the gas pressure is high and the high frequency power is small).
[0023]
Under this condition, the resist 13 is etched almost equally in both the vertical and horizontal directions, so that the resist thickness can be reduced and the hole diameter can be increased at the same time. Thickness decreases). The receding distance of the resist 13 (about opening diameter increase) is preferably about 0.1 to 0.3 μm on one side, and the resist thickness after this etching step is 1.0 μm or less and 0.5 μm or more. It is preferable.
[0024]
FIG. 1D is a diagram for explaining the state after resist removal after metal deposition, and a via contact in which a substantially rectangular metal layer 15 is embedded in a via hole is obtained. The surplus metal deposited on the resist is lifted off when the resist is removed with an organic solvent or the like. In this resist removal process, although some metal is deposited on the side surface of the resist (side surface of the opening portion), the amount thereof is very small, and impedes the penetration of the organic solvent for resist removal into the resist. That doesn't happen. Note that the lift-off of the metal is promoted by executing the removal process while applying vibration to the resist using an ultrasonic wave in an organic solvent.
[0025]
〔Example〕
Hereinafter, an embodiment in which a via contact is formed in a transistor using the via hole forming method of the present invention will be described.
[0026]
FIG. 2 is a diagram for explaining a structural example of a heterobipolar transistor (HBT) in which a via contact is formed by using the via hole forming method of the present invention. This HBT is formed on a semi-insulating InP substrate 21. n ⁺ a -In _x Ga _{1 -x} as subcollector layer 22, an _n-In x Ga _{1 -x} as collector layer ^23, a p + _-In x Ga _{1 -x} as base layer 24, n-InP emitter layer 25 and an n ⁺ -In _x Ga _{1 -x} As emitter contact layer 26 are sequentially stacked.
[0027]
The collector electrode 27 (C electrode), the base electrode 28 (B electrode), and the emitter electrode 29 (E electrode) are provided on the subcollector layer 22, the base layer 24, and the emitter contact layer 26, respectively. As these electrode materials, Pt / Ti / Pt / Au is commonly used. The base electrode 28 is configured to be connected to the base layer 24 through a thin emitter layer 25. In the process of heat-treating the electrode metal, the base metal is sintered in the semiconductor and penetrates the emitter layer 25. Thus, the base electrode 28 is formed by reaching the base layer 24.
[0028]
An outline of a process for forming a via contact on each electrode of the HBT having the configuration shown in FIG. 2 will be described below.
[0029]
The height (thickness) of the HBT having the configuration shown in FIG. 2 is as high as 1.3 μm from the substrate 21 to the top of the emitter electrode 29. Flattening is performed because it is difficult to stably form an emitter lead-out wiring (˜1.5 μm) without disconnection.
[0030]
FIG. 3 is a diagram for explaining the outline of the flattening process. In this figure, the internal structure of the HBT is simplified.
[0031]
As shown in FIG. 3A, an interlayer insulating film 33 having a thickness of about 850 nm is deposited on the substrate 31 on which the HBT 32 is formed, for example, by a plasma CVD method. Here, the material of the interlayer insulating film 33 can be SiN, SiON, SiO ₂ or the like.
[0032]
Next, SOG 34 or the like is applied while rotating the wafer. SOG 34 is a liquid (high viscosity) at room temperature, and is a material that is converted to SiO ₂ (glass material) by performing a temperature rise process. When this is applied onto the wafer using a spinner like a resist, the base film is thin on the emitter electrode and thick on the collector electrode, and the whole is flattened. In this state, the temperature is increased (100 ° C. to 200 ° C.) to solidify the SOG 34, and then the entire wafer is etched. At this time, it is important to keep the etching rate of the solidified SOG 34 and the etching rate of the interlayer insulating film 33 substantially equal to each other, and the shape after the etching is as shown in FIG.
[0033]
In the present embodiment, a SiON film is applied as the interlayer insulating film 33 to a thickness of 850 nm and SOG 34 to a thickness of about 500 nm, and the whole is etched back by about 1 μm. In this case, a SiON film of about 350 nm is left on the emitter electrode, about 700 nm on the base electrode, and about 1 μm on the collector electrode.
[0034]
In place of SOG 34, polyimide, resist, or the like can be used. However, in that case, if a method similar to SOG is applied to the resist, the resist remains even after the planarization etching at the portion where the resist is deposited thick, so that the interlayer insulating film 33 is deposited thicker, It is necessary to etch until the resist is completely removed.
[0035]
Next, via contacts are formed. The thicknesses of the SiON films remaining on the respective electrodes are different from each other. In particular, 1 μm is formed on the collector electrode at the deepest position, and the shallowest position is formed on the collector electrode. Since a SiON film of about 0.35 μm remains on a certain emitter electrode, it is impossible to form a via contact to each electrode in a single process. That is, when the thickness of the buried metal is matched with the collector electrode, the metal film thickness is left on the emitter electrode. Conversely, when the thickness is matched with the emitter electrode, the via hole on the collector electrode is buried. I can't do that. Therefore, in this embodiment, the via holes of the base electrode and the collector electrode are embedded in the same process, and the emitter electrode is embedded in a separate process.
[0036]
The specific procedure is as already described with reference to FIG. 1. In the case of this embodiment, the insulating film of 700 nm to 1000 nm must be etched in the via hole for the collector electrode and the base electrode. It is inevitable that side etching of about 200 nm is introduced into the interlayer insulating film. Therefore, it is effective to adjust the shape of the via hole embedded metal by retreating the resist by about 100 nm to 300 nm.
Subsequent to the via hole metal filling, a first layer wiring is performed.
[0037]
4 and 5 are diagrams for explaining a process example of the first layer wiring, FIG. 4 is a diagram for explaining a wiring process of a method using milling, and FIG. 5 is a lift-off used for via hole embedding. It is a figure for demonstrating the wiring process by a method.
[0038]
In the method using milling shown in FIG. 4, the wiring metal 45 (TiW (45a) / Au (45b) = 20 nm is formed on the entire surface of the wafer of the substrate 41 on which the lower metal wiring 42, the interlayer insulating layer 43, and the via contact 44 are formed. / 500 nm) (FIG. 4A), and a resist 46 is patterned thereon so as to cover the wiring portion (FIG. 4B). Using this resist pattern as a mask, the unnecessary part of the Au wiring metal 45b is removed by milling (FIG. 4C).
[0039]
Milling uses Ar ions, and the milling with Ar ions ends with the TiW layer 45a because the milling rate of TiW is low. Thereafter, the remaining TiW layer 45a is etched by RIE using an F-based gas, thereby completing wiring formation (FIG. 4D).
[0040]
In the case of the method using lift-off shown in FIG. 5, since there is no interlayer insulating film, a multilayer resist of resist / insulating film / resist is used. That is, a three-layer structure including a resist 55, an insulating film 56, and a resist 57 is formed on the entire surface of the substrate 51 on which the lower metal wiring 52, the interlayer insulating layer 53, and the via contact 54 are formed (FIG. 5A). )), Only the upper resist 57 is used to pattern the wiring metal, and the insulating film of the intermediate layer is etched using this pattern as a mask.
[0041]
Next, the lower resist 55 is etched with oxygen plasma using the etched insulating film as a mask. It is important to perform the conditions at this time under the condition of strong anisotropy described above, and the etching conditions that are not so large in the lateral direction are applied in which more etching proceeds in the depth direction. By this etching, the lower resist 55 is patterned, and a mask shape is obtained in which side etching is slightly applied to the opening of the insulating film 56 (FIG. 5B).
[0042]
By etching the lower resist 55 with oxygen plasma, the entire upper resist 57 is completely etched. In the shape of the mask thus obtained, the insulating film 56 serves as a so-called soot, and the underlying resist 55 serves as an insulating film in the via hole metal filling process.
[0043]
This step does not require the resist receding or tilting required for via hole filling. This is because the width of the opening is about 1 μm in the via hole process, but at least 2 μm or more is secured in this wiring process. This is because, when the opening diameter of the via hole is narrow, metal adhesion to the resist shoulder (corner) becomes a big problem, but this does not become a big problem when the opening width is wide as in the wiring process.
[0044]
Next, a wiring metal 58 is formed on the entire surface (FIG. 5C). In this case, Ti (58a) 20 nm / Pt (58b) 20 nm / Au (58c) 600 nm is used as the metal. The Ti layer 58a is for ensuring adhesion with the base metal (Au, the uppermost layer metal of the via hole embedded metal), and the Pt layer 58b is an interaction between the Ti layer 58a and the Au layer 58c (in the long term). If both are mixed, it leads to an increase in wiring resistance), and the Au layer 58c plays the role of the original wiring metal.
[0045]
After metal deposition, the excess metal on the resist (and the insulating film) is removed by a lift-off method to complete the wiring (FIG. 5D). In this method, a metal such as TiW or WSi can be used instead of the intermediate insulating film. In short, when the lower resist 55 is etched with oxygen plasma, it is a metal that is not affected by the oxygen plasma, and the film itself needs to be easily etched. Further, it is a necessary condition that the shape can be formed at a temperature (150 ° C. or less) that does not change the resist. For example, when SiO ₂ is used, RIE etching can be performed with a fluorine-based gas, and when TiW or WSi is used, etching can be performed with a fluorine-based gas in the same manner.
[0046]
In the case where the next process is performed, an integrated circuit can be manufactured by performing insulating film coating, via hole metal embedding, and second layer wiring formation again.
[0047]
【The invention's effect】
As described above, according to the present invention, the resist edge angle is changed from 45 ° to 75 ° by baking the resist, or the resist on the interlayer insulating film is laterally moved before metal deposition. Since it is made to recede, a metal shape of a via contact close to a square shape is obtained, and it becomes possible to eliminate a connection failure between the via hole metal and the upper metal wiring formed thereon.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an example of a method for forming a via hole according to the present invention.
FIG. 2 is a diagram for explaining a structural example of a hetero bipolar transistor (HBT) in which a via contact is formed using the via hole forming method of the present invention.
FIG. 3 is a diagram for explaining an outline of a planarization process in an example in which an HBT is manufactured using the via hole forming method of the present invention.
FIG. 4 is a diagram for explaining a wiring process of a method using milling in an example in which an HBT is manufactured by using the via hole forming method of the present invention.
FIG. 5 is a diagram for explaining a wiring process by a lift-off method used for via hole embedding in an example in which an HBT is manufactured by using the via hole forming method of the present invention.
[Explanation of symbols]
11, 42, 52 Lower metal wiring 12, 33, 43, 53 Interlayer insulating film 13, 46, 55, 57 Resist 14 Open hole 15 Metal layer 44, 54 Via contact 21, 31, 41, 51 Substrate 22 Subcollector layer 23 Collector layer 24 Base layer 25 Emitter layer 26 Emitter contact layer 27 Collector electrode 28 Base electrode 29 Emitter electrode 32 HBT
34 SOG
45, 58 Wiring metal 56 Insulating film

Claims (4)

A method of forming a via hole for electrically connecting a lower layer metal material and an upper layer metal material,
A first step of forming an interlayer insulating film;
A second step of patterning the shape of the via hole opening in the resist coated on the insulating film;
A third step of forming a via hole by etching away the interlayer insulating film based on the via hole opening pattern;
A fourth step of subjecting the resist to a heat treatment to smooth the angle of the resist side wall of the via hole opening pattern;
A fifth step of depositing metal in the via hole and on the resist;
And a sixth step of removing the resist and lifting off the metal on the resist. Between the third step and the fourth step, there is provided a seventh step of exposing the resist to oxygen plasma to enlarge the via hole opening pattern and simultaneously reduce the thickness of the resist. The method for forming a via hole according to claim 1. 3. The via hole forming method according to claim 2, wherein a thickness of the resist after completion of the seventh step is 1.0 [mu] m or less and 0.5 [mu] m or more. 4. The via hole according to claim 1, wherein an angle formed between the resist side wall surface and the surface of the interlayer insulating film at the end of the fourth step is not less than 45 ° and not more than 75 °. 5. Forming method.

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