JP2000138227A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to realize simultaneously a lowered parasitic capacitance and leakage current among electrodes by forming a dielectric film to be a partial substrate of a base electrode in a manner in which selectively coating from an end face is made to an outside of a base-mesa. SOLUTION: A pattern for forming a base region is formed on a surface deposited by SiO2 film 80 with a photoresist 81, the SiO2 film 80 is etched with an RIE system, and a base region is formed with a part of a base layer 64, and a collector layer 63 etched. After the SiO2 film 80 is side etched, a SiO film 71 is vapor deposited from an oblique direction of max. 10 degrees from a normal line. The end of the base mesa and the end of the SiO film 71 are deposited in one point. A base electrode pattern is formed by a photoresist 82, the SiO2 film 80 is etched, and a base electrode 68 is formed with an electrode metal deposited and lifted off. The electrode can be formed on a dielectric film without itself being made to contact an ion implantation region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In electronic devices, high-speed performance is always required.
Integration (reduction in element area), low power consumption, and high reliability have been pursued. Among them, formation of a high resistance region by ion implantation is a very effective means from the viewpoint of reducing the element area, and is now a standard process.

FIG. 1 shows a sectional structure of a heterojunction bipolar transistor (HBT) according to a first conventional example. In order to reduce the base-collector capacitance, which has a large effect on high-frequency characteristics, the resistance of the collector layer and the sub-collector layer facing the parasitic region of the base electrode 17 is increased by ion implantation. With such a structure, the base-collector capacitance in a region required for the base lead-out electrode 21 can be reduced. However, since the base electrode is in direct contact with the ion-implanted region, the leakage current between the base and the collector increases. That is, usually, they are separated by a p / n junction, but trap levels are formed in the depletion layer by ion implantation, and the electrons and holes generated there are observed as a leak current. As described above, the reduction of the base-collector capacitance and the reduction of the leak current cannot be realized at the same time.

In the second conventional example of FIG. 2, in order to overcome the above two trade-offs, an increase in leak current is prevented by forming a part of the base electrode on a dielectric. However, the method of forming this structure is extremely complicated, difficult to control, and causes other problems such as an increase in base electrode contact resistance. FIG. 3 and FIG.
The method of forming the structure according to the conventional example of FIG.

First, a photoresist 33 is patterned as shown in FIG. Using the photoresist 33 as a mask, the semiconductor layer 32 (a part of the base layer and the collector layer) is etched to form a mesa shape (FIG. 3B).
A dielectric 36 is formed on the step by vapor deposition and lift-off (FIG. 3C). The thickness of the dielectric 36 is
It is necessary to set so that it is the same height as 4. At this time, from the positional relationship between the photoresist 33 and the mesa 34,
A gap 35 is always formed between the mesa 34 and the dielectric film 36. When such a gap 35 is formed, this mesa 3
When the base electrode is formed over the dielectric film 36 from above the electrode 4, the electrode falls into the gap 35, and the electrode is disconnected, or the base electrode is an undesired semiconductor layer (collector) on the end face of the mesa 34. Layer), which is likely to cause leakage current.

Therefore, it is necessary to fill the gap 35 and flatten it. Next, the process will be described. A resin film (for example, polyimide) 37 is applied on the entire surface (FIG. 3)
(D)). At this time, by applying a resin film having a relatively low viscosity, the gap 35 can be completely filled and the surface can be flattened. Next, the entire surface is etched back by a reactive ion etching method (RIE method).

Here, as shown in FIG. 3E, the surface of the mesa 34 (the surface of the base layer) and the resin 3 embedded in the gap 35 are formed.
It is necessary to adjust the etching so that the height of the dielectric film 36 and the height of the dielectric film 36 are exactly the same. That is, if the etching is insufficient, the residue of the resin 37 remains on the surface of the semiconductor mesa 34 (the surface of the base layer), and the next step (FIG. 3F)
Thus, when the base electrode is formed on the semiconductor mesa 34, a contact failure between the electrode and the semiconductor occurs. Conversely, if the etching is over, the mesa 34 and the dielectric 3
6, a step is formed between the resin and the resin to be filled in the gap between them.

However, in order to form an electrode on the base layer in the next step, it is necessary to surely expose the surface of the base layer at the time of etching back the resin film. The surface (base layer surface) is exposed to plasma, which causes an increase in contact resistance when an electrode is formed on the base layer, causing deterioration of device characteristics.

As described above, the method of simultaneously realizing the reduction of the base-collector parasitic capacitance and the reduction of the base leakage current causes a problem of increasing the base resistance.

[0010]

As described above, a simple method which simultaneously satisfies a low leakage current from the base electrode and a low collector capacitance and does not adversely affect other characteristics has been obtained. Not.

The present invention has been made in view of the above points, and has as its object to provide a method for simultaneously realizing a reduction in leakage current and a low capacity.

[0012]

In order to solve the above-mentioned problems, the present invention provides a first semiconductor layer of a first conductivity type formed on a semiconductor substrate, and a first semiconductor layer formed on the first semiconductor layer. A first step of depositing a first dielectric on the second semiconductor layer, wherein the first step comprises depositing a first dielectric on the second semiconductor layer. A second step of applying a photoresist to the substrate, a third step of opening a predetermined pattern of the photoresist, and the first step using the patterned photoresist as a mask.
A fourth step of exposing the surface of the second semiconductor layer by etching the dielectric of the second semiconductor layer and the first semiconductor layer by using the etched first dielectric as a mask. A fifth step of etching a part or all of the above, a sixth step of further etching the first dielectric, a seventh step of depositing a second dielectric over the entire surface, And an eighth step of removing the second dielectric deposited thereon. A method of manufacturing a semiconductor layer device, comprising:

In the present invention, it is desirable to have the following configuration.

(1) In the seventh step, the maximum inclination of the deposition direction of the second dielectric from the normal direction is defined as a deposition angle, and the deposition angle is measured from the lower end of the patterned photoresist. An angle with respect to a line direction is set to an angle equal to or larger than an angle facing a boundary between the first semiconductor layer and the second semiconductor layer that are etched and exposed, and the vapor deposition angle of the second dielectric is set. In the above, the etching amount of the first dielectric in the sixth step is set so that the first dielectric is not exposed from the lower end of the patterned photoresist.

(2) A ninth step of forming a continuous electrode on the second semiconductor layer and on the second dielectric is included.

(3) The second dielectric is SiO.

(4) The first semiconductor layer and the second semiconductor layer
Semiconductor layers constitute a heterojunction bipolar transistor.

(5) The first semiconductor layer forms a collector layer, and the second semiconductor layer forms a base layer.

That is, in order to solve the above problems, the present invention has devised a method of forming a dielectric serving as a base of an electrode. FIG. 4 shows the procedure. Here, a method of forming a base electrode on a base layer will be described as an example.

As shown in FIG. 4A, for example, SiO ₂ 44 is laminated on a portion where a collector layer 42 and a base layer 43 are sequentially laminated on a semiconductor substrate 41. Where S
iO ₂ acts as a spacer during the subsequent deposition lift-off. A high-resistance region 46 has already been formed by ion implantation to reduce the collector capacitance. A photoresist 45 is applied thereon and patterned. Using the photoresist pattern as a mask, to etch the SiO _2. The etching method takes into account pattern accuracy,
An etching method with high perpendicularity such as RIE is desirable. After the SiO ₂ is etched to expose the base layer 43, a part of the base layer 43 and a part of the collector layer 42 are etched (FIG. 4B).

Next, side etching is performed on the SiO ₂ 44 to recede from the photoresist end (FIG. 4).
(C)). This is the point. Next, a dielectric serving as a base of the electrode is formed by vapor deposition. At this time, vapor deposition is performed in an oblique direction. In addition, the maximum angle is set to an angle larger than the angle θ ₁ shown in FIG. The angle θ ₁ is determined by the amount of retreat x ₁ from the edge of the photoresist pattern at the pn junction boundary in the semiconductor mesa, the thickness t of the lift-off spacer SiO ₂ , and the pn from the upper surface of the semiconductor mesa.
Using the depth t ₁ to the junction, it is determined by tan θ ₁ = x ₁ / (t + t ₁ ).

By depositing the dielectric at an angle larger than θ ₁ determined as described above, the pn junction boundary can be covered with the dielectric, so that the leakage current when an electrode is formed thereon can be suppressed. You can do it. However, it is important in the present invention that the maximum vapor deposition angle is larger than θ ₁ determined above, but in order to smoothly perform the subsequent lift-off process, the angle at which the spacer SiO ₂ faces the photoresist end. It must be set to an angle smaller than theta _2. However, if the maximum deposition angle is large,
The area covered by the dielectric on the mesa increases. that is,
In other words, the contact area between the base electrode formed later and the base layer is reduced. That is, the contact resistance of the electrode is increased. Therefore, in consideration of flatness when the electrode traverses the mesa, the maximum deposition angle is desirably an angle facing the upper end of the semiconductor mesa from the photoresist end. That is, as shown in FIG. 5 (b), retraction amount x ₀ from the photoresist end of the mesa upper, against lift-off spacer SiO ₂ thickness t, theta represented by _{tan θ 0 = x 0 / t} 0 It is desirable to deposit the dielectric material by setting the angle of 最大 as the maximum angle.

FIG. 4D shows a case where the dielectric 47 is deposited at an angle θ ₀ . Because of the spacer SiO ₂ 44, the dielectric on the photoresist can be easily lifted off, and the dielectric film 47 can be selectively formed on the semiconductor mesa step as shown in FIG.

Thereafter, a photoresist pattern for forming a base electrode is formed, and an electrode metal is deposited and lifted off to form a base electrode 4 as shown in FIG.
8 can be formed. By using the above method, without contacting the electrode with the ion implantation region,
Since it is formed on the dielectric film, it is possible to greatly reduce the leak electrode. In addition, since the formation of the semiconductor mesa and the deposition of the dielectric film can be performed using the same mask, the positional relationship between the mesa and the dielectric film is always constant. It will be constant.

As described above, according to the present invention, a dielectric film is selectively formed on a step formed by a mesa without damaging the upper surface of the semiconductor mesa by plasma or the like as in the conventional example. And a manufacturing method capable of simultaneously reducing the leakage current from the electrode and the parasitic capacitance.

In the present invention, the positional relationship between the photoresist and the spacer and the semiconductor mesa and the deposition angle of the dielectric are important, and the material of the spacer and the dielectric is not limited.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, a method in which the present invention is applied to an InGaP / GaAs HBT wafer will be described. FIG. 6 shows the cross-sectional structure. 61 is a compound semiconductor substrate, a semi-insulating GaAs substrate, 62 is n ⁺
-Type GaAs collector contact layer, 63 is n-type GaAs
The collector layer 64 is a highly carbon doped p ⁺ -type G
aAs base layer, 65 is an n-type In _0.5 Ga _0.5 P emitter layer, and 66 is an n ⁺ -type In _x Ga _{1 -x} As (x = 0 → 0.
5) Emitter cap layers, which are sequentially laminated on a semi-insulating GaAs substrate 61. Here, for example,
n ⁺ -type GaAs collector contact layer 62 is 500 n
m, Si concentration 5E18 cm ⁻³ (E18 means × 10 ¹⁸ , the same applies hereinafter), n-type GaAs collector layer 63 is 500 nm, Si concentration 1E16 cm ⁻³ , p ⁺ -type GaAs.
The base layer 64 is 50 nm, the C concentration is 5E19 cm ⁻³ , the n-type In _0.5 Ga _0.5 P emitter layer 65 is 50 nm, the Si concentration is 5E17 cm ⁻³ , the n ⁺ -type In _x Ga _{1 -x} As layer 66 is 100 nm, and the Si concentration is 3E19 cm ^{−. Assume 3} .

First, a high melting point metal (for example, W, WSi, WN) is formed on the entire surface of the wafer by a method such as sputtering. Next, a photoresist is applied to the entire surface, and is exposed and developed to form a resist pattern so as to mask only a portion to be an emitter region. Subsequently, the high melting point metal is etched by reactive ion etching or the like using the photoresist as a mask. Thus, the emitter electrode 67 is formed.

Etching is performed using the emitter electrode 67 as a mask to expose the base layer 64. In this state, the photoresist is patterned so as to protect the element region, and ion implantation is performed to increase the resistance of the region 70 other than the element region. Subsequently, an SiO ₂ film 80 is deposited on the entire surface for 570.
nm. A pattern defining the base region is formed by the photoresist 81 (FIG. 7A).

Next, the SiO ₂ film 80 is etched by RIE, and then a part of the base layer 64 and a part of the collector layer 63 are etched in the manner described in Means for Solving the Problems. Here, 100 nm is etched. This defines the base region. Next, the SiO
_{After the second} film 80 is side-etched by 200 nm using ammonium fluoride, a SiO film 71 is deposited obliquely at a maximum of 10 ° from the normal direction. Then, as described in the means for solving the problem, as shown in FIG.
It is deposited so that the end of the base mesa and the end of the SiO film 71 coincide. The photoresist and the SiO film thereon are removed by a lift-off method. In this embodiment, the thickness of the SiO ₂ film 80, the etching amounts of the base layer 64 and the collector layer 63, and the deposition angle of the SiO film are set so as to satisfy the relationship described in the section for solving the problem. I have. These values can be set arbitrarily as long as they satisfy the relationship described in Means for Solving the Problems.

Next, a base electrode pattern is formed with a photoresist 82, the SiO ₂ film 80 is etched using ammonium fluoride, and then a base electrode 68 is formed by depositing and lifting off an electrode metal. Since the emitter electrode is formed in an eaves-like shape with respect to the emitter mesas 65 and 66 between the emitter electrode and the base electrode, "step disconnection" occurs automatically, so that no short circuit occurs (FIG. 7).
(C)). Further, as shown in FIG. 7D, a collector electrode pattern 83 is formed, and a collector electrode 69 is formed by etching, vapor deposition, and lift-off. Next, a SiN passivation film 72 is deposited by a plasma CVD method to protect the entire surface of the element.

Finally, the entire element is flattened with a resin 73 such as polyimide, BCB (benzocyclobutene), or an olefin resin, and a contact hole is opened on the electrode.
By forming the wiring electrode 74, an HBT can be manufactured.

The characteristics of the HBT thus manufactured are
A comparison is made with the HBT characteristics of the conventional structure shown in FIG.
The base-collector leakage current of a transistor having an emitter size of 5 μm square and a base electrode width of 1 μm was 1 μA in the transistor manufactured by the method according to the conventional example, while 1 pA in the transistor manufactured in this example. Level and could be greatly reduced.

Further, according to the method of the present invention, the SiO film 71, which is the base of a part of the base electrode, is formed so as to selectively cover the outside from the base mesa end face. The contact area is not sacrificed at all. Further, in the method of the present invention, since the outside of the base mesa is selectively covered with the SiO film 71, a dry etching method such as an etch-back method is not used.
The surface of the base layer is not exposed to plasma. Therefore, the method has no risk of increasing the base resistance and damaging the base layer.

In this embodiment, the present invention is applied to the etching mesa for separating the base and the collector. However, the present invention can be applied to any mesa step portion of the semiconductor layer. In the present invention, the deposition of the SiO film is described as an example, but the deposited dielectric film is not limited to the SiO film, but may be, for example, an SiO ₂ film.

[0036]

According to the above method, a semiconductor device capable of realizing a structure capable of simultaneously reducing the parasitic capacitance and the leak current between the electrodes without increasing the contact resistance of the electrodes or causing disconnection of the electrodes. Can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a cross-sectional structure of a first conventional example.

FIG. 2 is a diagram illustrating a cross-sectional structure of a second conventional example.

FIG. 3 is a process sectional view for explaining a manufacturing method of a second conventional example in the order of processes.

FIG. 4 is a process sectional view for explaining the manufacturing method of the present invention step by step.

FIG. 5 is a diagram illustrating a deposition angle of a dielectric film in the manufacturing method of the present invention.

FIG. 6 is a diagram showing a cross-sectional structure of the HBT according to the embodiment of the present invention.

FIG. 7 is a process sectional view for explaining the manufacturing method according to the example of the present invention in the order of processes.

[Explanation of symbols]

11: semi-insulating GaAs substrate 12: n ⁺ -type GaAs collector contact layer 13: n-type GaAs collector layer 14: p ⁺ -type GaAs base layer 15: n-type Al _x Ga _1-x As / n ⁺ -type In _x Ga _{1 -x}
As emitter layer 16: Emitter electrode 17: Base electrode 18: Collector electrode 19: Extraction electrode 20: Wiring electrode 21: High resistance region by ion implantation 22: Resin film made of polyimide, BCB, etc. 23: SiO film 24: Polyimide 31: Substrate 32: Epitaxial growth layer 33: Photoresist 34: Semiconductor mesa 35: Gaps 36: Dielectric film 37: Resin film such as polyimide 38: Electrode 41: Semiconductor substrate 42: Collector layer 43: Base layer 44: SiO ₂ film 45: Photoresist 46: High resistance region by ion implantation 47: SiO film 48: Base electrode 51: Semiconductor substrate or first semiconductor layer 52: Second semiconductor layer 53: SiO ₂ film 54: Photoresist 61: Semi-insulating property GaAs substrate 62: n ⁺ -type GaAs collector contact layer 63: n GaAs collector layer 64: p ⁺ -type GaAs base layer 65: n-type In _0.5 Ga _0.5 P emitter layer 66: n ⁺ -type In _x Ga _1-x As emitter contact layer 67: an emitter electrode 68: base electrode 69: the collector electrode 70 : High resistance region by ion implantation 71: SiO film 72: SiN film 73: BCB film 74: Wiring electrode 80: SiO ₂ film 81: Photoresist 82: Photoresist 83: Photoresist

Claims (6)

[Claims] 1. A semiconductor device comprising: a first semiconductor layer of a first conductivity type formed on a semiconductor substrate; and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer. A first step of depositing a first dielectric on the second semiconductor layer, a second step of applying a photoresist on the first dielectric, A third step of opening a predetermined pattern, a fourth step of etching the first dielectric using the patterned photoresist as a mask, and exposing a surface of the second semiconductor layer, and etching. A fifth step of etching part or all of the second semiconductor layer and the first semiconductor layer using the first dielectric thus formed as a mask, and further etching the first dielectric. The sixth step and the second dielectric A method of manufacturing a semiconductor device, comprising: a seventh step of vapor deposition on the entire surface; and an eighth step of removing the photoresist and the second dielectric deposited on the photoresist. . 2. In the seventh step, a maximum inclination of a deposition direction of the second dielectric from a normal direction is defined as a deposition angle, and the deposition angle is defined as a normal from a lower end of the patterned photoresist. An angle is set to be equal to or larger than an angle facing a boundary between the first semiconductor layer and the second semiconductor layer that are etched and exposed, and
At the deposition angle of the second dielectric, the etching amount of the first dielectric in the sixth step is set so that the first dielectric is not exposed from the lower end of the patterned photoresist. The method of manufacturing a semiconductor device according to claim 1, wherein: 3. The method according to claim 2, further comprising a ninth step of forming a continuous electrode on said second semiconductor layer and said second dielectric. 4. The method according to claim 2, wherein the second dielectric is SiO. 5. The method according to claim 3, wherein the first semiconductor layer and the second semiconductor layer form a heterojunction bipolar transistor. 6. The method according to claim 5, wherein the first semiconductor layer forms a collector layer, and the second semiconductor layer forms a base layer.