JP3833043B2 - Gradation wiring for display, driver for liquid crystal display, and stress test method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gradation wiring for a display, a driver for a liquid crystal display, and a stress test method thereof.
[0002]
[Prior art]
FIG. 10 is a wiring diagram of a grayscale voltage generator in a liquid crystal display driver according to the prior art. The gradation voltage generation unit includes reference voltage input terminals (IC pads) V1 to V9, a ladder resistor R, and a gradation wiring WW. The gradation wiring WW can be divided into a first half gradation wiring WA and a second half gradation wiring WB.
[0003]
The gradation wiring WW actually has, for example, 64 gradation wirings corresponding to 64 gradations, but here, for the sake of simplification of the drawing, an example in which there are 33 gradation wirings W1 to W33 is taken as an example. explain. A ladder resistor R is connected between the gradation wirings W1 to W33. The input terminal V1 is connected to the gradation wiring W1, the input terminal V2 is connected to the gradation wiring W5, the input terminal V3 is connected to the gradation wiring W9, the input terminal V4 is connected to the gradation wiring W13, and the input terminal V5 is connected to the gradation wiring W17, the input terminal V6 is connected to the gradation wiring W21, the input terminal V7 is connected to the gradation wiring W25, the input terminal V8 is connected to the gradation wiring W29, and the input terminal V9 is Connected to the gradation wiring W33.
[0004]
The gradation wirings W1 to W33 are connected to a liquid crystal panel (not shown), and the liquid crystal panel is driven by gradation voltages supplied from W1 to W33. A method for driving the liquid crystal panel will be described. For example, 0 V is applied to the input terminal V1, and 6 V is applied to the input terminal V9. Further, a voltage for interpolating between 0 to 6 V is applied to the input terminals V2 to V8. Then, the voltage generated in the gradation wirings W1 to W33 is divided by the ladder resistor R. As a result, a voltage between 0 and 6V that has been gamma corrected is output from the gradation wirings W1 to W33. The liquid crystal panel can be driven by applying any voltage selected from the gradation wirings W1 to W33 according to the image data to the liquid crystal panel.
[0005]
The gradation wirings W1 to W33 are connected to each other by a ladder resistor R, but foreign matter (dust) may be mixed between the gradation wirings in the manufacturing process of the liquid crystal display driver. When a foreign substance is mixed between the gradation wirings, the gradation wirings are short-circuited, and a prescribed gradation voltage is not output from the gradation wirings W1 to W33. When the gradation wiring is completely short-circuited, the defective LCD driver can be easily detected in the inspection process.
[0006]
However, even if foreign matter is mixed between the gradation wirings, the gradation wirings may not be completely short-circuited. In that case, it is difficult to detect a defect in the inspection process, and a defective liquid crystal display driver may be shipped. In such a case, the state of the foreign matter between the wirings may change during use by the user, and a failure may occur in the middle, making it impossible to output a normal gradation voltage. If normal gradation voltages are not output, line defects will occur in the pixel display on the liquid crystal panel.
[0007]
In order to avoid such an inconvenience, a stress test is performed at the time of testing the driver for the liquid crystal display. In the stress test, first, a stress voltage application process is performed, and then an inspection process is performed.
[0008]
The stress voltage application process will be described. In the stress voltage application step, first, for example, a stress voltage of 12 V (maximum rated voltage) is applied between the input terminals V1 and V2, and then, for example, a stress voltage of 12 V is also applied between the input terminals V2 and V3. Similarly, a stress voltage is applied between the input terminals V3 to V9. For example, when foreign matter is mixed between the gradation wirings, the insulation failure between the gradation wirings becomes remarkable by applying the stress voltage.
[0009]
After applying the stress voltage, an inspection process is performed. In the inspection process, for example, 0 V is applied to the input terminal V1, 6V is applied to the input terminal V9, and a voltage between 0 to 6V is applied to the input terminals V2 to V8, as in the normal driving of the liquid crystal panel. To do. Then, the output voltage of each gradation wiring of the gradation wirings W1 to W33 is measured, and when the output voltage is not within the range of the specified value, the driver for the liquid crystal display can be removed as a defective product.
[0010]
[Problems to be solved by the invention]
However, in the above stress voltage application step, only a 12V stress voltage is applied between the gradation wirings W1 and W5, and about 3V (between the gradation wiring W1 and the adjacent gradation wiring W2). Only a low voltage of 12V / 4) is applied. That is, a sufficiently large stress voltage cannot be applied between the gradation wirings, and the detection rate of the insulation failure between the gradation wirings is relatively low.
[0011]
In the stress voltage application step, first, a stress voltage is applied between the input terminals V1 and V2, then a stress voltage is applied between the input terminals V2 and V3, and similarly between each of the input terminals V3 to V9. It was necessary to repeat the voltage application process eight times in total by applying a stress voltage to the stress voltage application process, which required a long time.
[0012]
An object of the present invention is to provide a gradation wiring for a display, a driver for a liquid crystal display, and a stress test method thereof that can more reliably detect an insulation failure between gradation wirings.
[0013]
Another object of the present invention is to provide a gradation wiring for a display, a driver for a liquid crystal display, and a stress test method thereof that can detect an insulation failure between gradation wirings in a short time.
[0014]
[Means for Solving the Problems]
The gradation wiring for a display device according to the present invention includes wiring for each gradation in the first gradation area for outputting the voltage of the first gradation area when the total number of gradations of the display is divided into a plurality of parts. Wiring of each gradation of the second gradation area for outputting a voltage of a second gradation area different from the first gradation area, and wiring of each gradation of the first gradation area And wiring for each gradation of the second gradation area arranged alternately. Then, when inspecting such an insulation failure of the gradation wiring, the first potential is applied to the predetermined gradation wiring in the first gradation area and the predetermined gradation in the second gradation area is applied. By applying the second potential to the tonal wiring, a stress voltage higher than the reference input voltage is applied between the wirings.
[0015]
Since the present invention comprises the above technical means, the same potential (first potential) is applied to each wiring in the first gradation area, and the wiring is alternately arranged with each wiring in the first gradation area. The same potential (second potential different from the first gradation area) is applied to each wiring in the second gradation area, and each wiring in the first gradation area is connected to each wiring in the first gradation area. The difference voltage between the first potential and the second potential is equally applied to all the wirings in the second gradation area adjacent thereto. As a result, it is possible to apply a large stress voltage between the gradation wirings by applying the first potential and the second potential only once.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of the liquid crystal display according to the first embodiment. The liquid crystal display has a liquid crystal panel 1 and a liquid crystal display driver 2. The liquid crystal display driver 2 includes a D / A converter 3 that converts a digital gradation value input to the input terminal IN into an analog gradation value and outputs the analog gradation value to the output terminal OUT. The D / A converter 3 includes a gradation voltage generation unit 4 and a decoder 5.
[0017]
The gradation voltage generator 4 and the decoder 5 are connected to each other by, for example, 64 gradation wirings. The gradation value of each pixel of the liquid crystal panel 1 is input to the input terminal IN as a digital value. The gradation voltage generation unit 4 generates, for example, 64 gradation analog voltages and outputs them to the decoder 5 via 64 gradation wirings. The decoder 5 converts the digital gradation value input to the input terminal IN into an analog gradation value based on the analog gradation voltage value output from the gradation wiring of the gradation voltage generation unit 4, and outputs the analog gradation value. Output to OUT. The liquid crystal panel 1 inputs the analog gradation voltage of each pixel from the decoder 5 via the output terminal OUT. The liquid crystal display driver 2 drives the liquid crystal panel 1 by controlling the gradation value of each pixel of the liquid crystal panel 1. The liquid crystal panel 1 displays each pixel having a predetermined gradation value.
[0018]
FIG. 2 is a wiring diagram illustrating a configuration example of the gradation voltage generation unit 4 in the liquid crystal display according to the first embodiment. The gradation voltage generation unit 4 according to the present embodiment includes the first half gradation wiring WA and the second half gradation wiring WB in the gradation voltage generation section shown in FIG. It is.
[0019]
The gradation voltage generation unit 4 includes reference voltage input terminals (IC pads) V1 to V9, a first half gradation wiring WA, a second half gradation wiring WB, and ladder resistors R1 and R2. Hereinafter, the gradation wiring combining both the gradation wiring WA and the gradation wiring WB is referred to as a gradation wiring WW.
[0020]
The gradation wiring WW actually has, for example, 64 gradation wirings corresponding to 64 gradations, but here, for the sake of simplification of the drawing, an example in which there are 33 gradation wirings W1 to W33 is taken as an example. explain. The gradation wirings W1 to W33 are gradation wirings for outputting a voltage of each gradation. The gradation wiring W1 is a wiring for outputting a voltage indicating the minimum gradation value, and the gradation wiring W33 is a gradation wiring for outputting a voltage indicating the maximum gradation value.
[0021]
The gradation wiring WA in the first half part has 16 gradations for outputting the voltage of the gradation area whose half gradation value is smaller when the total number of gradations of the liquid crystal display is divided into two. Wirings W1-W16 are included. The gradation wiring WB in the latter half part has 17 gradations for outputting the voltage of the gradation area of about half of the larger gradation value when the total number of gradations of the liquid crystal display is divided into two. Wirings W17b to W33 are included.
[0022]
The first ladder resistor R1 is connected between the gradation wirings W1 to W16 of the first half gradation wiring WA, and the second ladder wiring W17 is connected between the gradation wirings W17b to W33 of the second gradation wiring WB. The ladder resistor R2 is connected. The input terminal V1 is connected to the gradation wiring W1 indicating the minimum gradation, the input terminal V2 is connected to the gradation wiring W5, the input terminal V3 is connected to the gradation wiring W9, and the input terminal V4 is connected to the gradation wiring W13. The input terminal V5 is connected to the gradation wirings W17a and W17b indicating intermediate gradation, the input terminal V6 is connected to the gradation wiring W21, the input terminal V7 is connected to the gradation wiring W25, and the input terminal V8. Is connected to the gradation wiring W29, and the input terminal V9 is connected to the gradation wiring W33 showing the maximum gradation.
[0023]
The gradation wirings W1 to W33 are connected to the liquid crystal panel 1 via the decoder 5 of FIG. The liquid crystal panel 1 can be driven by applying the following reference voltage to the input terminals V1 to V9. That is, for example, 0V is applied to the input terminal V1, and 6V is applied to the input terminal V9. Further, when a voltage for interpolating between 0 to 6 V is applied to the input terminals V2 to V8, the voltages of the gradation wirings W1 to W33 are divided by the ladder resistors R1 and R2, and gamma-corrected as shown in FIG. A voltage between 0 and 6V is output. In FIG. 3, the horizontal axis indicates the gradation value, and the vertical axis indicates the output voltage of the gradation wiring corresponding to the gradation value. The value of the reference voltage input to the input terminals V2 to V8 is determined according to the gamma characteristic shown in FIG.
[0024]
Although FIG. 2 illustrates the case where there are nine input terminals V1 to V9, the number of input terminals can be any number according to the characteristic curve of gamma correction. However, the input terminals V1 and V4 are connected to at least two gradation wirings W1 and W4 in the first half gradation wiring WA, and at least two gradation wirings W17a (W17b) in the second half gradation wiring WB. ) And W33 need to be connected to input terminals V5 and V9.
[0025]
When the above reference voltage is applied to the input terminals V1 to V9, the first ladder resistor R1 has a gradation with a large gradation value from the top to the bottom of the drawing, that is, from the gradation wiring W1 with a small gradation value. A current flows toward the wiring W17a. Since the lower left gradation wiring W17a is connected to the upper right gradation wiring W17b, the second ladder resistor R2 also increases from the gradation wiring W17b having a smaller gradation value from the top to the bottom of the figure. A current flows toward the gradation wiring W33 having gradation values. The direction of the current flowing through the first ladder resistor R1 and the direction of the current flowing through the second ladder resistor R2 are the same. As a result, voltages divided by the ladder resistors R1 and R2 appear in the gradation wirings W1 to W33, and specifically, voltage values of the respective gradations shown in FIG. 3 appear.
[0026]
Next, a stress test method will be described. The gradation wirings W1 to W33 are connected by ladder resistors R1 and R2, but foreign matter (dust) is mixed between the gradation wirings in the manufacturing process of the liquid crystal display driver 2 (FIG. 1). Insufficient insulation may occur between gradation wirings due to process variations. Although the liquid crystal display driver 2 with poor insulation is discarded as a defective product, the insulation failure between gradation wirings can be detected by the stress test described below. In the stress test, first, a stress voltage application process is performed, and then an inspection process is performed.
[0027]
The stress voltage application process will be described. In the stress voltage application step, for example, 0V is applied to the input terminals V1, V2, V3, and V4, and a stress voltage (maximum rated voltage) of, for example, 12V is applied to the input terminals V5, V6, V7, V8, and V9. By applying a stress voltage, for example, if there is an insulation failure between gradation wirings, the insulation failure between the gradation wirings becomes prominent.
[0028]
When the above stress voltage is applied, the same potential of 0V is applied to V1 to V4, so that even if the voltage is divided by R1, a gradation voltage of 0V appears in W1 to W13. On the other hand, since the same potential of 12V is applied to all of V5 to V9, even if the voltage is divided by R2, a gradation voltage of 12V appears in W17b to W33. Thus, 0V is applied to the input terminal V1, and 12V is applied to the input terminal V5. Therefore, a sufficiently high stress voltage of 12V can be applied between the gradation wiring W1 and the gradation wiring W17b. . Further, since 0V is applied to the gradation wiring W2 from the input terminals V1 and V2 via the first ladder resistor R1, a high stress voltage of 12V is also applied between the gradation wiring W2 and the gradation wiring W17b. Is applied. Similarly, a high stress voltage of 12 V can be applied between the gradation wirings except for the section shown later, and an insulation failure between the gradation wirings can be detected more reliably.
[0029]
That is, in the conventional gradation voltage generation unit shown in FIG. 10, only a stress voltage of 12V is applied between the gradation wirings W1 and W5, and about 3V (= 12V ÷ 4) is applied between the gradation wirings. Only a low voltage of) is applied. On the other hand, in the gradation voltage generation unit 4 according to the present embodiment, a high stress voltage of 12 V can be applied between the gradation wirings except for some sections, and insulation defects between the gradation wirings can be more reliably prevented. It becomes possible to detect.
[0030]
In the conventional gradation voltage generator shown in FIG. 10, first, a stress voltage is applied between the input terminals V1 and V2, and then a stress voltage is applied between the input terminals V2 and V3. The stress voltage application process must be repeated a total of 8 times by applying a stress voltage between the input terminals V3 to V9. In the grayscale voltage generator 4 according to the present embodiment, the input terminals V1 to V4 are used. The stress voltage application process can be performed in a short time by applying one stress voltage application process in which 0V is applied to the input terminals V5 to V9. Thereby, it is possible to detect an insulation failure between gradation wirings in a short time.
[0031]
In addition, the stress voltage application process of this Embodiment is not limited to applying 12V to the intermediate | middle reference voltage input terminal V5, You may apply 0V. That is, 0V may be applied to the input terminals V1 to V5, and 12V may be applied to the input terminals V6 to V9. However, when 12V is applied to the input terminals V5 to V9, a voltage drop occurs because a voltage of 12V is applied through the first ladder resistor R1 between the gradation wiring W13 and the gradation wiring W17a. A large stress voltage of 12 V cannot be applied only between the gradation wiring W13 and the gradation wiring W17a. In that case, if 0V is applied to the input terminals V1 to V4, 12V is applied to the input terminals V5 to V9, then 0V is applied to the input terminals V1 to V5, and 12V is applied to the input terminals V6 to V9, the above problems are eliminated. be able to. The other gradation voltage generation unit 4 for eliminating the inconvenience will be described later with reference to FIG.
[0032]
After applying the stress voltage, an inspection process is performed. In the inspection process, similarly to the normal driving of the liquid crystal panel, for example, 0V is applied to the input terminal V1, 6V is applied to the input terminal V9, and the voltage for interpolating between 0 to 6V to the input terminals V2 to V8. Apply. The output voltage of each gradation wiring of the gradation wirings W1 to W33 is measured, and when the output voltage is not within the specified value range, the liquid crystal display driver 2 can be removed as a defective product. The above-mentioned stress voltage application process accelerates the insulation failure between the gradation wirings, and this inspection process can more reliably detect the insulation failure between the gradation wirings.
[0033]
(Second Embodiment)
FIG. 4 is a wiring diagram illustrating a configuration example of the gradation voltage generation unit 4 according to the second embodiment. In the first embodiment shown in FIG. 2, in the latter half of the gradation wiring WB, the gradation wiring W17b having a small gradation value is provided on the upper side, and the gradation wiring W33 having a large gradation value is provided on the lower side. The gradation wirings W17b to W33 are arranged in the order of gradation values. However, in the gradation wiring WB in the latter half of the present embodiment, the gradation wiring W18 having a small gradation value is provided on the lower side and the gradation value is large. The gradation wiring W33 is provided on the upper side, and the gradation wirings W18 to W33 are arranged in order of gradation values. Also, the two gradation wirings 17a and 17b shown in FIG. The gradation wiring WA in the first half of the present embodiment is the same as the gradation wiring WA in the first half of the first embodiment.
[0034]
The gradation wiring WA in the first half includes 17 gradation wirings W1 to W17 for outputting the voltage of about half the gradation area having the smaller gradation value. The second half gradation wiring WB includes sixteen gradation wirings W18 to W33 for outputting the voltage of the gradation area of about half of the larger gradation value.
[0035]
The first ladder resistor R1 is connected between the gradation wirings W1 to W17 of the first half gradation wiring WA, and the second gradation wiring W18 of the second half gradation wiring WB is connected to the second gradation wiring W1. The ladder resistor R2 is connected. The connection between the input terminals V1 to V4 and the gradation wiring WA is the same as that in the first embodiment. The input terminal V5 is connected to the gradation wiring W17, the input terminal V6 is connected to the gradation wiring W21, the input terminal V7 is connected to the gradation wiring W25, the input terminal V8 is connected to the gradation wiring W29, and the input terminal V9 is connected to the gradation wiring W33.
[0036]
In such a configuration, the liquid crystal panel 1 can be driven by applying the same reference voltage as in the first embodiment to the input terminals V1 to V9. That is, for example, 0V is applied to the input terminal V1, 6V is applied to the input terminal V9, and a voltage that interpolates between 0 to 6V is applied to the input terminals V2 to V8. When the above reference voltage is applied to the input terminals V1 to V9, the first ladder resistor R1 has a gradation with a large gradation value from the top to the bottom of the drawing, that is, from the gradation wiring W1 with a small gradation value. A current flows toward the wiring W17. Since the second ladder resistor R2 is connected to the first ladder resistor R1 through the gradation wiring W17, the second ladder resistor R2 has a small gradation from the bottom to the top in the drawing. A current flows from the value gradation wiring W17 toward the gradation wiring W33 having a large gradation value. The direction of the current flowing through the first ladder resistor R1 is opposite to the direction of the current flowing through the second ladder resistor R2. As a result, voltages divided by the ladder resistors R1 and R2 appear in the gradation wirings W1 to W33, and specifically, voltage values of the respective gradations shown in FIG. 3 appear.
[0037]
Moreover, the stress test method can be performed by the same method as the first embodiment, and the same effect can be obtained. That is, a high stress voltage of 12 V can be applied between the gradation wirings, and an insulation failure between the gradation wirings can be detected more reliably, and a stress test can be performed in a short time.
[0038]
(Third embodiment)
FIG. 5 is a wiring diagram illustrating a configuration example of the gradation voltage generation unit 4 according to the third embodiment. In the third embodiment, the intermediate input terminal V5 in the first embodiment shown in FIG. 2 is divided into two input terminals V5A and V5B, and the other points are the same as in the first embodiment. It is the same.
[0039]
The gradation wiring having the smallest gradation value among the gradation wirings WB in the latter half is separated into the gradation wiring W17c and the gradation wiring W17d. One gradation wiring 17c is used only for the stress test, and the other gradation wiring W17d is used as a gradation wiring for actually outputting the gradation voltage. The first ladder resistor R1 is connected between the gradation wirings of the gradation wirings W1 to W17a, and the second ladder resistor R2 is connected between the gradation wirings of the gradation wirings W17d to W33. The input terminal V5A is connected to the gradation wirings W17a and W17c, and the input terminal V5B is connected to the gradation wiring W17d.
[0040]
The stress voltage application process will be described. In the stress voltage application step, for example, 0V is applied to the input terminals V1, V2, V3, V4, and V5A, and a stress voltage (maximum rated voltage) of, for example, 12V is applied to the input terminals V5B, V6, V7, V8, and V9. In the first embodiment of FIG. 2, a large stress voltage cannot be applied between the gradation wiring W13 and the gradation wiring W17a. However, according to the present embodiment, these gradations are not applied. Since 0 V having the same potential is applied to the input terminal V4 and the input terminal V5A to which the wirings W13 and W17a are connected, and 12 V is applied to the input terminals V5B and V6, between the gradation wiring W13 and the gradation wiring W17a. In addition, a stress voltage of 12 V can be applied between the gradation wirings. That is, a large stress voltage of 12 V can be applied between all the gradation wirings, and insulation failure between the gradation wirings can be detected more reliably.
[0041]
In the inspection process after applying the stress voltage and normal liquid crystal driving, the same voltage is applied to the input terminal V5A and the input terminal V5B, so that the present embodiment is the first embodiment ( A circuit equivalent to that in FIG. 2) can be configured and an equivalent operation can be performed.
[0042]
(Fourth embodiment)
FIG. 6 is a wiring diagram illustrating a configuration example of the gradation voltage generation unit 4 according to the fourth embodiment. In the present embodiment, the intermediate input terminal V5 in the second embodiment shown in FIG. 4 is divided into two input terminals V5A and V5B, and the other points are the same as in the second embodiment. It is.
[0043]
The gradation wiring having the largest gradation value among the gradation wirings WA in the first half is separated into the gradation wiring W17a and the gradation wiring W17c. One gradation wiring 17c is used only for the stress test, and the other gradation wiring W17a is used as a gradation wiring for actually outputting the gradation voltage. The first ladder resistor R1 is connected between the gradation lines W1 to W17a, and the second ladder resistor R2 is connected between the gradation lines W17c to W33. The input terminal V5A is connected to the gradation wiring W17a, and the input terminal V5B is connected to the gradation wiring W17c.
[0044]
In the stress voltage application step, for example, 0V is applied to the input terminals V1, V2, V3, V4, and V5A, and a stress voltage (maximum rated voltage) of, for example, 12V is applied to the input terminals V5B, V6, V7, V8, and V9. In the second embodiment (FIG. 4), a large stress voltage cannot be applied between the gradation wiring W13 and the gradation wiring W17. However, according to the present embodiment, these levels are not applied. Since 0 V having the same potential is applied to the input terminal V4 and the input terminal V5A to which the adjustment wirings W13 and W17a are connected, and 12 V is applied to the input terminals V5B and V6, the interval between the gradation wiring W13 and the gradation wiring W17 is applied. In FIG. 5, a stress voltage of 12 V can be applied between the gradation wirings. That is, a large stress voltage of 12 V can be applied between all the gradation wirings, and insulation failure between the gradation wirings can be detected more reliably.
[0045]
Note that when performing the inspection process after applying the stress voltage and normal liquid crystal driving, the same voltage is applied to the input terminal V5A and the input terminal V5B, so that this embodiment is the second embodiment ( A circuit equivalent to that in FIG. 4) can be configured and an equivalent operation can be performed.
[0046]
(Fifth embodiment)
FIG. 7 is a wiring diagram illustrating a configuration example of the gradation voltage generation unit 4 according to the fifth embodiment. In the present embodiment, a switch SW is provided between the intermediate input terminals V5A and V5B in the third embodiment shown in FIG. 5, and the other points are the same as in the third embodiment. .
[0047]
The switch SW can connect or disconnect between the input terminals V5A and V5B. In the present embodiment, as in the third embodiment (FIG. 5), the switch SW disconnects between the input terminals V5A and V5B during the stress voltage application process, and during the inspection process and normal liquid crystal panel driving. A switch SW connects between the input terminals V5A and V5B. Similarly, a switch SW may be provided between the terminals V5A and V5B of the fourth embodiment (FIG. 6).
[0048]
FIG. 8 is a circuit diagram showing the configuration of the switch SW. The switch SW includes a combination element of a P channel MOS transistor (transfer gate) 12 and an N channel MOS transistor (transfer gate) 13, and a NOT circuit (inverter) 11. The control terminal CTL is connected to the input terminal of the NOT circuit 11 and the gate of the N-channel transistor 13. The output terminal of the NOT circuit 11 is connected to the gate of the P-channel transistor 12. The sources / drains of the transistors 12 and 13 are connected to the input terminal V5A and the input terminal V5B, respectively.
[0049]
When a high level voltage is applied to the control terminal CTL, the source and drain of the transistors 12 and 13 are brought into conduction, and the input terminals V5A and V5B are connected. On the other hand, when a low level voltage is applied to the control terminal CTL, the source and drain of the transistors 12 and 13 are cut off and the input terminals V5A and V5B are disconnected.
[0050]
The switch SW is not limited to a configuration using a combination element of a P-channel and an N-channel MOS transistor (transfer gate), and may be configured by an N-channel MOS transistor (transfer gate) or only a P-channel. You may comprise by a MOS transistor (transfer gate).
[0051]
As described above in detail, according to the first to fifth embodiments, the first gradation area (for example, the first half gradation area) and the second gradation area (for example, the second half gradation area). ) Are arranged in a staggered manner, a sufficiently large stress voltage can be applied between the gradation wirings, and an insulation failure between the gradation wirings can be detected more reliably. Thereby, the defect rate due to deterioration in the market can be lowered, and the reliability can be improved. In addition, since a stress voltage can be applied between each gradation wiring by a single stress voltage application process, it is possible to detect an insulation failure between gradation wirings in a short time, and to reduce costs by shortening the process time. Can be planned.
[0052]
FIG. 9A is a cross-sectional view of the semiconductor substrate of the liquid crystal display driver 2 (FIG. 1). The first wiring layer 21 is a wiring layer of the decoder 5 (FIG. 1), and an insulating layer 22 is formed thereon. On the insulating layer 22, second wiring layers WA and WB are formed. The second wiring layer WA is the first half gradation wiring layer, and the second wiring layer WB is the second half gradation wiring layer. The second wiring layers WA and WB are alternately formed in the horizontal direction in the same layer. An insulating layer 24 is formed on the second wiring layers WA and WB.
[0053]
In FIG. 9A, the case where the first half gradation wiring WA and the second half gradation wiring WB are arranged in the same wiring layer has been described as an example. However, as shown in FIG. The gradation wiring WA in the part and the gradation wiring WB in the latter half may be arranged in different wiring layers.
[0054]
FIG. 9B is a cross-sectional view of another semiconductor substrate of the liquid crystal display driver 2 (FIG. 1). The first wiring layer 21 is a wiring layer of the decoder 5 (FIG. 1), and an insulating layer 22 is formed thereon. A second wiring layer (a first half gradation wiring layer) WA is formed on the insulating layer 22, and an insulating layer 24 is formed thereon. A third wiring layer (second half gradation wiring layer) WB is formed on the insulating layer 24, and an insulating layer 26 is formed thereon.
[0055]
FIG. 9C is a cross-sectional view of another semiconductor substrate of the liquid crystal display driver 2 (FIG. 1). The first wiring layer 21 is a wiring layer of the decoder 5 (FIG. 1), and an insulating layer 22 is formed thereon. On the insulating layer 22, the second wiring layer (first half gradation wiring layer) WA and the second wiring layer (second half gradation wiring layer) WB are alternately formed in the horizontal direction in the same layer. Is done. An insulating layer 24 is formed on the second wiring layers WA and WB. On the insulating layer 24, the third wiring layer (first half gradation wiring layer) WA and the third wiring layer (second half gradation wiring layer) WB are alternately formed in the horizontal direction in the same layer. Is done. An insulating layer 26 is formed on the third wiring layers WA and WB. Further, the wiring layers WA and WB are alternately formed in the vertical direction between different wiring layers.
[0056]
In the above embodiment, the case where the gradation wiring is divided into the first half gradation wiring WA and the second half gradation wiring WB has been described as an example. However, the gradation wiring may be divided into three or more. For example, in the gradation voltage generator shown in FIG. 10, the first region of the gradation wirings W1 to W4, the second region of the gradation wirings W5 to W8, the third region of the gradation wirings W9 to W12, and the floor. Dividing the control wirings W13 to W16 into fourth regions and the like, arranging the first regions and the second regions alternately in a comb shape, and forming the third regions and the fourth region in a comb shape. You may arrange alternately. In that case, it is preferable that the two regions arranged alternately are wiring regions in a gradation area where gradations continue to each other. Similarly to the gradation wiring WA in the first half, the latter half gradation wiring WB can be divided into four regions and arranged alternately.
[0057]
In addition, each of the above-described embodiments is merely an example of the embodiment for carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. It will not be. In other words, the present invention can be implemented in various forms without departing from the spirit or main features thereof.
[0058]
The various aspects of the present invention are summarized as follows.
(Supplementary note 1) Wiring of each gradation in the first gradation area for outputting the voltage of the first gradation area when dividing the total number of gradations of the display into a plurality of parts,
Wiring of each gradation of the second gradation area for outputting a voltage of a second gradation area different from the first gradation area, and wiring of each gradation of the first gradation area And wiring of each gradation in the second gradation area arranged alternately
A gradation wiring for a display, comprising:
(Supplementary note 2) The display-use gradation wiring according to supplementary note 1, wherein the second gradation area is a gradation area having a gradation following the gradation of the first gradation area.
[0059]
(Supplementary Note 3) The wiring for each gradation in the first gradation area is wiring in the gradation area in the first half when the total number of gradations of the display is divided into two, and the second floor 3. The gradation wiring for a display device according to appendix 2, wherein the gradation wiring in the gradation area is a wiring in a gradation area in the latter half portion when the total number of gradations of the display is divided into two.
(Supplementary Note 4) The gradation wiring for a display according to Supplementary Note 1, wherein the gradation wirings in the first and second gradation areas are wirings for outputting gradation voltages of a liquid crystal display. .
[0060]
(Additional remark 5) The 1st ladder resistance connected between the wiring of each gradation of the said 1st gradation area,
A second ladder resistor connected between the wirings of each gradation in the second gradation area;
The gradation wiring for a display device according to appendix 1, further comprising:
(Supplementary note 6) a first reference voltage input terminal connected to make the voltage of the wiring of each gradation in the first gradation area the same potential;
A second reference voltage input terminal connected to make the voltage of the wiring of each gradation in the second gradation area the same potential;
The gradation wiring for a display device according to appendix 5, further comprising:
[0061]
(Supplementary note 7) When a voltage is applied between the first and second reference voltage input terminals, the direction of the current flowing through the first ladder resistor is the same as the direction of the current flowing through the second ladder resistor. The gradation wiring for a display device according to appendix 6, which is characterized in that it exists.
(Supplementary note 8) When a voltage is applied between the first and second reference voltage input terminals, the direction of the current flowing through the first ladder resistor is opposite to the direction of the current flowing through the second ladder resistor. The gradation wiring for a display device according to appendix 6, which is characterized in that it exists.
[0062]
(Additional remark 9) The minimum gradation reference voltage input terminal connected to the wiring which shows the minimum gradation among the said wiring,
A maximum gradation reference voltage input terminal connected to the wiring indicating the maximum gradation of the wiring;
Two predetermined gradation reference voltage input terminals connected to a wiring having a predetermined same gradation among the wirings;
The gradation wiring for a display device according to appendix 1, further comprising:
(Additional remark 10) The minimum gradation reference voltage input terminal connected to the wiring which shows the minimum gradation among the said wiring,
A maximum gradation reference voltage input terminal connected to the wiring indicating the maximum gradation of the wiring;
Two intermediate gray scale reference voltage input terminals connected to a wiring showing an intermediate gray scale among the wirings;
The gradation wiring for a display device according to appendix 3, further comprising:
[0063]
(Additional remark 11) The gradation wiring for displays according to additional remark 9, further comprising a switching element for connecting or disconnecting the two predetermined gradation reference voltage input terminals. (Additional remark 12) The said switching element contains the combination element of the transfer gate of N channel and P channel, The gradation wiring for displays of Additional remark 11 characterized by the above-mentioned.
[0064]
(Supplementary note 13) The gradation wiring for display according to supplementary note 11, wherein the switching element includes a transfer gate having only an N channel.
(Supplementary note 14) The gradation wiring for display device according to supplementary note 11, wherein the switching element includes a transfer gate of only a P channel.
[0065]
(Supplementary note 15) The display device according to supplementary note 1, wherein each gradation wiring in the first gradation area and each gradation wiring in the second gradation area are arranged in the same layer. Gradation wiring.
(Supplementary note 16) The display floor according to supplementary note 1, wherein each gradation wiring in the first gradation area and each gradation wiring in the second gradation area are arranged in different layers. Adjustment wiring.
[0066]
(Supplementary Note 17) Wiring of each gradation in the first gradation area for outputting an analog gradation voltage of each gradation in the first gradation area when the total number of gradations of the liquid crystal display is divided into a plurality of Wiring for each gradation in the second gradation area for outputting an analog gradation voltage for each gradation in the second gradation area different from the first gradation area, Wiring for each gradation in the second gradation area arranged alternately with the wiring for each gradation in the gradation area;
A first ladder resistor connected between the wirings of each gradation in the first gradation area;
A second ladder resistor connected between the wirings of each gradation in the second gradation area;
A first reference voltage input terminal connected to set the voltage of the wiring in the first gradation area to the same potential;
A second reference voltage input terminal connected to set the voltage of the wiring in the second gradation area to the same potential;
A decoder for converting an input digital gradation value into an analog gradation value based on an analog gradation voltage value output from each gradation wiring in the first and second gradation areas; A driver for liquid crystal displays.
(Supplementary Note 18) Wiring of each gradation in the first gradation area for outputting the voltage of the first gradation area when the total number of gradations of the display is divided into a plurality, and the first gradation Wiring of each gradation in the second gradation area for outputting a voltage of the second gradation area different from the area, and alternately arranged with the wiring of each gradation in the first gradation area A stress test method for a driver for a liquid crystal display comprising a wiring for each gradation in a second gradation area,
By applying a first potential to the wiring of a predetermined gradation in the first gradation area and applying a second potential to the wiring of a predetermined gradation in the second gradation area, a reference input voltage Applying a higher stress voltage between the wires;
By applying a reference input voltage for each gradation to each of the predetermined gradation wirings in the first and second gradation areas and measuring the voltages output from the wirings for all gradations, it is possible to determine whether there is an abnormality in the output voltage. Step to inspect and
A stress test method for a driver for a liquid crystal display, comprising:
[0067]
【The invention's effect】
According to the present invention configured as described above, a sufficiently large stress voltage can be applied between the gradation wirings, and an insulation failure between the gradation wirings can be detected more reliably. In addition, since a stress voltage can be applied between the gradation wirings by a single stress voltage application step, an insulation failure between the gradation wirings can be detected in a short time.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a liquid crystal display according to a first embodiment.
FIG. 2 is a wiring diagram illustrating a configuration of a gradation voltage generation unit in the liquid crystal display according to the first embodiment.
FIG. 3 is a graph showing a relationship between a gradation value and a voltage.
FIG. 4 is a wiring diagram illustrating a configuration of a gradation voltage generation unit according to a second embodiment.
FIG. 5 is a wiring diagram showing a configuration of a gradation voltage generation unit according to a third embodiment.
FIG. 6 is a wiring diagram illustrating a configuration of a gradation voltage generation unit according to a fourth embodiment.
FIG. 7 is a wiring diagram showing a configuration of a gradation voltage generation unit according to a fifth embodiment.
FIG. 8 is a circuit diagram showing a configuration of a switch.
FIGS. 9A to 9C are cross-sectional views of a semiconductor substrate of a driver for a liquid crystal display.
FIG. 10 is a wiring diagram illustrating a configuration of a grayscale voltage generation unit according to the related art.
[Explanation of symbols]
1 LCD panel
2 LCD display driver
3 D / A converter
4 gradation voltage generator
5 Decoder
11 NOT circuit
12 P-channel MOS transistor
13 N-channel MOS transistor
21 First wiring layer
22, 24, 26 Insulating layer
V1 to V9 reference voltage input terminal
W1-W33 gradation wiring
WA First half gradation wiring
WB gradation wiring in the latter half
R1, R2, R Ladder resistance
SW switch

Claims (9)

Wiring of each gradation in the first gradation area for outputting the voltage of the first gradation area when the total number of gradations of the display is divided into a plurality of areas;
Wiring of each gradation of the second gradation area for outputting a voltage of a second gradation area different from the first gradation area, and wiring of each gradation of the first gradation area And a gradation wiring for a display, wherein the gradation wirings of the second gradation area are alternately arranged. The display-use gradation wiring according to claim 1, wherein the second gradation area is a gradation area having a gradation subsequent to the gradation of the first gradation area. 2. The gradation wiring for a display according to claim 1, wherein the wiring for each gradation in the first and second gradation areas is a wiring for outputting a gradation voltage of the liquid crystal display. A first ladder resistor connected between the wirings of each gradation in the first gradation area;
The display gradation wiring according to claim 1, further comprising a second ladder resistor connected between the wirings of each gradation in the second gradation area. A minimum gradation reference voltage input terminal connected to the wiring indicating the minimum gradation among the wirings;
A maximum gradation reference voltage input terminal connected to the wiring indicating the maximum gradation of the wiring;
The display gradation wiring according to claim 1, further comprising two predetermined gradation reference voltage input terminals connected to a wiring having a predetermined same gradation among the wirings. 2. The gradation wiring for a display according to claim 1, wherein the wiring for each gradation in the first gradation area and the wiring for each gradation in the second gradation area are arranged in the same layer. . 2. The gradation wiring for a display device according to claim 1, wherein the wiring for each gradation in the first gradation area and the wiring for each gradation in the second gradation area are arranged in different layers. Wiring of each gradation in the first gradation area for outputting an analog gradation voltage of each gradation in the first gradation area when the total number of gradations of the liquid crystal display is divided into a plurality;
Wiring of each gradation of the second gradation area for outputting an analog gradation voltage of each gradation of the second gradation area different from the first gradation area, wherein the first gradation Wiring of each gradation of the second gradation area arranged alternately with wiring of each gradation of the area;
A first ladder resistor connected between the wirings of each gradation in the first gradation area;
A second ladder resistor connected between the wirings of each gradation in the second gradation area;
A first reference voltage input terminal connected to set the voltage of the wiring in the first gradation area to the same potential;
A second reference voltage input terminal connected to set the voltage of the wiring in the second gradation area to the same potential;
A decoder for converting an input digital gradation value into an analog gradation value based on an analog gradation voltage value output from each gradation wiring in the first and second gradation areas; A driver for liquid crystal displays. The wiring of each gradation in the first gradation area for outputting the voltage of the first gradation area when the total number of gradations of the display is divided into a plurality is different from the first gradation area. Wiring for each gradation in the second gradation area for outputting the voltage in the second gradation area, and the second floor arranged alternately with the wiring for each gradation in the first gradation area. A stress test method for a driver for a liquid crystal display provided with wiring for each gradation in a gray scale area,
By applying a first potential to the wiring of a predetermined gradation in the first gradation area and applying a second potential to the wiring of a predetermined gradation in the second gradation area, a reference input voltage Applying a higher stress voltage between the wires;
By applying a reference input voltage for each gradation to each of the predetermined gradation wirings in the first and second gradation areas and measuring the voltages output from the wirings for all gradations, it is possible to determine whether there is an abnormality in the output voltage. A stress test method for a driver for a liquid crystal display.

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