JP3831355B2 - Gate driving method, gate driving circuit, and gate driving power IC - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gate driving method and a gate driving circuit, and more particularly to a MOS gate driving circuit applied to an inverter device and a power IC thereof.
[0002]
[Prior art]
In a conventional MOS gate driving power IC for an inverter device, when an abnormality occurs in the upper arm based on a floating potential or an abnormality of an external MOS gate power element, the abnormality is often not transmitted. Alternatively, a circuit configuration in which a floating potential reference signal is output to the outside and converted to a ground potential reference signal by a photocoupler is generally used. On the other hand, Patent Document 1 first shows an example (FIG. 7) in which a high voltage PMOS device is driven by a signal indicating abnormality of the upper arm and transmitted to the low side. Secondly, a technique (FIG. 2 and the like) has been proposed in which a current source is provided on the high side and the current signal is transmitted to the low side via a high voltage NMOS device.
[0003]
[Patent Document 1]
JP2003-32102A (FIGS. 7, 2, etc.)
[0004]
[Problems to be solved by the invention]
However, both the first and second prior arts described in Patent Document 1 may cause a malfunction due to the floating operation of the upper arm.
[0005]
An object of the present invention is to provide a gate driving method, a gate driving circuit, and a gate driving power IC that can prevent a malfunction due to a floating operation of an upper arm.
[0006]
[Means for Solving the Problems]
In a gate drive circuit, as is well known, the potential of the upper arm (high side) increases and rapidly fluctuates (floats) due to the switching operation of a main circuit such as an inverter to be driven. This floating potential is at the ground potential during the ON period of the IGBT which is the main switching element of the lower arm, and jumps to the power supply voltage of the inverter, for example, several hundred [V] at the moment when the IGBT is turned off. In addition, there is a parasitic capacitance in the switching element used to transmit the abnormality detection signal in the upper arm to the lower arm circuit. For this reason, it has been found that there is a possibility that a signal is transmitted to the lower arm circuit through this parasitic capacitance due to a large dV / dt when the floating potential jumps and erroneous detection is performed.
[0007]
Therefore, the present invention is characterized in that an abnormality detection signal for the upper arm is first transmitted to the lower arm circuit only when the floating potential is low, that is, only when the main switching element of the lower arm is ON.
[0008]
Specifically, the logical product of the abnormality detection signal of the upper arm and the signal indicating the ON state of the main switching element of the lower arm is taken and transmitted to the lower arm circuit. The signal representing the ON state of the main switching element of the lower arm is generated by a logical product of the period during which the on-gate signal is applied to the main switching element of the lower arm and the floating potential being lowered. Is desirable.
[0009]
This realizes a gate driving method and a gate driving circuit that can be expected to perform a highly reliable abnormality detection operation without picking up an error signal associated with the jump of the floating potential.
[0010]
The present invention not only transmits the abnormality detection signal to the lower arm circuit during the ON period of the main switching element of the lower arm, but also transmits the transmitted signal and the ON period of the main switching element of the lower arm. An abnormal signal is output to the outside based on a logical product with a signal representing.
[0011]
As a result, a gate driving method and a gate driving circuit that can expect a more reliable abnormality detection operation are realized.
[0012]
In the present invention, the signal indicating the ON state of the main switching element of the lower arm and the abnormality detection signal of the upper arm transmitted to the circuit for the lower arm of the gate drive circuit are input to the logic unit via a filter. It is characterized by that.
[0013]
As a result, a gate drive method and a gate drive circuit that can block, for example, a whisker-like erroneous detection signal caused by noise from the high-voltage circuit and prevent the possibility of malfunction more reliably are realized.
[0014]
In the power IC that drives a power converter such as an inverter, the present invention also includes an abnormality detection signal holding unit that detects and holds an abnormality of the upper arm, a low breakdown voltage switching element that is switched according to the output, A high breakdown voltage switching element connected in series to the low breakdown voltage switching element and controlled ON / OFF synchronously with the main switching element of the lower arm, and an abnormality detection signal for the upper arm when both of these two switching elements are turned ON. Is provided with a resistance element for transmitting to the lower arm circuit.
[0015]
The high breakdown voltage switching element used in this level conversion (level shift down) circuit is desirably a high breakdown voltage NMOS used in a level conversion (level shift up) circuit for an on / off signal for normal switching.
[0016]
As a result, it is possible to convert an abnormal signal of the upper arm to a signal level based on the ground potential with a relatively simple circuit configuration using an existing high-voltage device inside the power IC, and for gate driving having a stable upper arm abnormality detection function. A power IC can be realized.
[0017]
Other objects and features of the present invention will become apparent from the description of the following examples.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a functional block diagram showing one phase of a gate driving power IC and an inverter main circuit to be controlled according to an embodiment of the present invention. Inverter systems for home appliances, industrial use, EV (Electric Vehicle), and the like often use three-phase inverter bridges for motor drive. The DC power source 1 is connected to a series circuit of main switching elements (IGBTs) 21 and 22 of an upper arm and a lower arm showing one phase of a three-phase inverter. Here, IGBT is shown as the MOS gate element, but power MOS can also be used. A series connection point A of these IGBTs is connected to a one-phase terminal of a three-phase load 3 typified by a synchronous motor or an induction motor. The other two-phase circuits are omitted.
[0019]
The main IGBTs 21 and 22 are alternately turned ON / OFF from the gate driving power IC (gate driving circuit) 4 via the external buffers 51 and 52. In one embodiment, the power IC 4 is a PWM signal of several [V] level from the control signal generator 6 and receives the lower input signals 61 and 62 and receives power supplies 71 (Vcc) and 72 (Vct) of ten and several [V]. To output a PWM pulse train of several hundred [mA] level. This is amplified to several [A] levels by the external buffers 51 and 52 and supplied to the main IGBTs 21 and 22. These external buffers 51 and 52 amplify the output current level, but may be omitted depending on the current capability of the IC output and the input capacity of the MOS gate element to be driven. In this example, the main power source 1 has a level of several hundred [V].
[0020]
Next, functional blocks in the power IC 4 will be described. On the upper arm side, the upper input signal 61 is received by the input interface unit 41, and the potential level is shifted up by the level shift up circuit 42U. Then, the main IGBT (MOS gate element) 21 is driven through the upper arm drive circuit 431 and the external buffer 51. On the lower arm side, the lower input signal 62 is received by the input interface unit 41, passes through the lower arm drive circuit 432, and drives the main IGBT (MOS gate element) 22 via the external buffer 52.
[0021]
This power IC is provided with an abnormality detection function, and the upper and lower arm abnormality detection and holding units 441 and 442 detect and hold the abnormality, respectively. The upper arm abnormality detection and holding unit 441 detects / holds an abnormality such as an overcurrent of the main IGBT 21 of the upper arm and a decrease in the control power supply voltage. The held abnormality detection signal is shifted down in the signal potential level by the level shift down circuit 42D and transmitted to the fault output unit 45 of the lower arm. On the other hand, the abnormality detection signal detected / held by the lower arm abnormality detection and holding unit 442 is directly transmitted to the fault output unit 45.
[0022]
In this embodiment, the abnormality detection signal from the upper arm abnormality detection and holding unit 441 is sent to the fault output unit 45 via the level shift down circuit 42D only during the period when the floating potential at the point A is at the ground potential level. There is a feature in the transmitting portion, and the details will be described with reference to FIG.
[0023]
FIG. 2 is a configuration diagram showing a specific circuit of the level shift down circuit 42D in the gate driving power IC according to one embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same functional units, and the description will be made only when necessary. When an abnormality is detected by the upper arm abnormality detection / holding unit 441, the main IGBT element 21 is once shut off through the upper arm drive circuit 431. At the same time, this abnormality detection signal is held in the upper arm abnormality detection and holding unit 441, and in the held state, the low breakdown voltage PMOS switching element 11 in the level shift down circuit 42D is turned on. A Zener diode 12 is connected to the PMOS switching element 11 in parallel. Therefore, if the main IGBT 22 is now in the OFF period and the floating potential at the point A is a high potential of several hundred [V] level, this high potential reaches the drain of the high voltage NMOS switching element 13 and is blocked. .
[0024]
Generation of the gate signal of the high voltage NMOS switching element 13 will be described. An input signal 14 that is “H” during which an ON signal is applied to the lower arm IGBT is applied to the filter 15. On the other hand, the signal 16 indicating the level of the floating potential is compared with the output of the reference voltage generation unit 17 in the comparison unit 18. The output of the filter 15 and the output of the comparison unit 18 are input to the AND logic unit 19, and the gate signal of the high breakdown voltage NMOS switching element 13 is generated by the output of the AND logic unit 19. Therefore, when it is confirmed that the main IGBT 22 of the lower arm is in an ON period during the period in which the ON signal is applied to the main IGBT 22 of the lower arm and the floating potential is low, the high breakdown voltage NMOS switching element 13 Turns on.
[0025]
Now, during the period in which the main IGBT 22 of the lower arm is turned on and the high voltage NMOS switching element 13 that is turned on / off in synchronization with the main IGBT 22 is also turned on, the above-described abnormality detection and holding unit 441 from the upper arm is turned on. Assume that an abnormality detection signal is generated. Thus, when the low breakdown voltage PMOS switching element 11 is turned on, a current flows from the power supply 72 (Vct) for the upper arm circuit to the source follower resistor 23 through the low breakdown voltage PMOS switching element 11 and the high breakdown voltage NMOS switching element 13. . Therefore, the connection point between the source of the high voltage NMOS switching element 13 and the source follower resistor 23 is “H”. In this way, the abnormality detection signal for the upper arm is transmitted to the lower arm circuit unit.
[0026]
This signal becomes one input of the NAND logic unit 25 through the filter 24 that cuts whiskers. On the other hand, the output of the AND logic unit 19 is given to the other input of the NAND logic unit 25. That is, the abnormality detection signal transmitted from the upper arm circuit to the lower arm circuit is the fault output unit 45 only when the reliable ON state of the main switching element 22 of the lower arm can be reconfirmed in the lower arm circuit. To the outside of the power IC 4. Reference numeral 26 denotes a protective diode.
[0027]
The gate drive method, gate drive circuit or gate drive power IC according to this embodiment is summarized as follows. First, the upper arm gate drive signal based on the floating potential and the lower arm gate drive signal based on the ground potential are output to the main IGBTs 21 and 22 of the upper and lower arms connected in series according to the input signals 61 and 62. . Also, an abnormality detection unit 441 that detects an abnormality of the upper arm using the power supply 72 of the upper arm circuit based on the floating potential, and a gate having a transmission path for transmitting this abnormality detection signal to the lower arm circuit based on the ground potential The driving power IC 4 is assumed. Here, the abnormal signal holding unit 441 that holds the abnormality detection signal in the upper arm circuit and outputs it to the transmission path, the high breakdown voltage NMOS switching element 13 connected in the transmission path, and the high breakdown voltage NMOS switching when the floating potential decreases. The control part (14-19) which turns on the element 13 is provided. Then, when an abnormality detection signal is output to the low breakdown voltage PMOS 11 in the transmission path and the high breakdown voltage NMOS switching element 13 is turned on, the upper arm abnormality detection signal is supplied to the source follower resistor 23 of the lower arm circuit based on the ground potential. To communicate. In addition, it has a logical configuration that outputs (45) an abnormal signal to the outside by a logical product (25) of the potential signal of the source follower resistor 23 and a signal (19 outputs) indicating the ON state of the main IGBT 22 of the lower arm, A level shift down circuit 42D for outputting to the outside is provided.
[0028]
As described above, it is double-checked that the on-gate signal is applied to the main switching element of the lower arm, the abnormal signal of the upper arm is transmitted to the lower arm circuit, and the floating potential dV / dt is expected. This prevents double malfunctions.
[0029]
【The invention's effect】
According to the present invention, it is possible to realize a gate drive method, a gate drive circuit, or a gate drive power IC that can be expected to have a highly reliable abnormality detection operation without picking up an error signal associated with a rise in floating potential.
[0030]
Further, it is possible to provide a gate driving power IC that can be realized with a relatively simple circuit configuration using an existing high voltage device inside the IC and has a stable upper arm abnormality detection / output function.
[Brief description of the drawings]
FIG. 1 is a functional block diagram showing one phase of a gate driving power IC and an inverter main circuit to be controlled according to an embodiment of the present invention;
FIG. 2 is a specific circuit configuration diagram of a level shift down circuit in a gate driving power IC according to an embodiment of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... High voltage DC power supply, 21, 22 ... Upper and lower arm main switching element (main IGBT), 3 ... Three-phase load, 4 ... Gate drive circuit (power IC for gate drive), 41 ... Input interface part, 42U ... Level Shift-up circuit, 42D ... level shift-down circuit, 11 ... low voltage PMOS switching element, 12 ... protective zener diode, 13 ... high voltage NMOS switching element, 14 ... lower arm on signal, 15 ... filter, 16 ... floating potential, 17 ... Reference voltage generation unit, 18 ... comparison unit, 19 ... AND logic unit, 23 ... source follower resistance, 24 ... filter, 25 ... NAND logic unit, 26 ... protection diode, 431,432 ... upper and lower arm drive circuits, 441,442 ... Upper and lower arm abnormality detection and holding unit, 45 ... Fault output unit, 51, 52 External buffer, 6 ... (PWM) control signal generator, 61, 62 ... Vertical (PWM) control signal, 71 ... Control power supply (Vcc) for lower arm circuit based on ground potential, 72 ... For upper arm based on floating potential Control power supply (Vct) of the circuit, 8 ... external high voltage diode, 81 ... external pull-up resistor.

Claims (13)

The gate drive circuit outputs the gate drive signal of the upper arm based on the floating potential and the gate drive signal of the lower arm based on the ground potential to the main switching elements of the upper and lower arms connected in series. In the gate driving method having a function of detecting an abnormality of the upper arm using the power supply of the upper arm circuit and transmitting the abnormality signal to the ground potential reference circuit unit, the abnormality signal is transmitted by the upper arm circuit. A gate driving method comprising: a holding step; and a step of transmitting the held abnormal signal to the ground potential reference circuit unit during an ON period of the main switching element of the lower arm. The gate drive circuit outputs the gate drive signal of the upper arm based on the floating potential and the gate drive signal of the lower arm based on the ground potential to the main switching elements of the upper and lower arms connected in series. In the gate driving method having a function of detecting an abnormality of the upper arm using the power supply of the upper arm circuit and transmitting the abnormality signal to the ground potential reference circuit unit, the abnormality signal is transmitted by the upper arm circuit. A step of holding, a step of blocking the abnormal signal transmission path with a high voltage switching element during an off period of the main switching element of the lower arm, and a step of releasing the block during an on period of the main switching element of the lower arm. A gate driving method characterized by the above. The gate drive circuit outputs the gate drive signal of the upper arm based on the floating potential and the gate drive signal of the lower arm based on the ground potential to the main switching elements of the upper and lower arms connected in series. In the gate driving method having a function of detecting an abnormality of the upper arm using the power supply of the upper arm circuit and transmitting the abnormality signal to the ground potential reference circuit unit, the abnormality signal is transmitted by the upper arm circuit. A step of holding, a step of blocking the transmission path of the abnormal signal with a high voltage switching element during an off period of the main switching element of the lower arm, and a step of releasing the block during the on period of the main switching element of the lower arm. To the ground potential reference circuit unit, the transmitted signal, and the main switch of the lower arm. Gate drive method characterized by including the step of outputting an abnormality signal to the outside based on the logical product of the signal representing the on period of the quenching device. 4. The ON period of the main switching element according to claim 1, wherein the ON period of the main switching element is determined based on a logical product of an ON signal to the main switching element of the lower arm and a signal indicating a decrease in floating potential. The gate drive method. The gate drive circuit outputs the gate drive signal of the upper arm based on the floating potential and the gate drive signal of the lower arm based on the ground potential to the main switching elements of the upper and lower arms connected in series. In the gate drive circuit having an abnormality detection unit for detecting an abnormality of the upper arm using a power supply of the circuit for the upper arm in the inside and a transmission path for transmitting this abnormality detection signal to the circuit unit of the ground potential reference, An abnormality signal holding unit that holds the abnormality detection signal in a circuit and outputs it to the transmission path, a high-breakdown-voltage switching element connected in the transmission path, and the on / off of the main switching element of the lower arm synchronously with the on / off A gate drive circuit comprising a control unit that controls on / off of a high-breakdown-voltage switching element. The gate drive circuit outputs the gate drive signal of the upper arm based on the floating potential and the gate drive signal of the lower arm based on the ground potential to the main switching elements of the upper and lower arms connected in series. In the gate drive circuit having an abnormality detection unit for detecting an abnormality of the upper arm using a power supply of the circuit for the upper arm in the inside and a transmission path for transmitting this abnormality detection signal to the circuit unit of the ground potential reference, An abnormality signal holding unit that holds the abnormality detection signal in a circuit and outputs it to the transmission path, a high breakdown voltage switching element connected in the transmission path, and a control unit that turns on the high breakdown voltage switching element when the floating potential is lowered A gate drive circuit comprising: 7. The method according to claim 5, further comprising: a low breakdown voltage switching element that switches the transmission path according to an output of the abnormal signal holding unit; and a constant voltage element connected in parallel to the low breakdown voltage switching element. A gate drive circuit. 8. The gate drive circuit according to claim 5, wherein the high breakdown voltage switching element is a high breakdown voltage NMOS switching element. 9. The transmission path according to claim 5, wherein the transmission path includes a parallel body of a low breakdown voltage PMOS switching element and a constant voltage element, a high breakdown voltage NMOS switching element, and a series circuit of a source follower resistance element. Gate drive circuit. 10. The logic structure according to claim 9, further comprising: a logical configuration that outputs an abnormal signal to the outside by a logical product of a potential signal of the source follower resistance and a signal representing an ON state of the main switching element of the lower arm. Gate drive circuit. 11. The gate drive circuit according to claim 10, further comprising a filter in at least one of the logical product signal input units. The gate drive circuit outputs the gate drive signal of the upper arm based on the floating potential and the gate drive signal of the lower arm based on the ground potential to the main switching elements of the upper and lower arms connected in series. In the gate drive power IC having an abnormality detection unit for detecting an abnormality of the upper arm using the power supply of the upper arm circuit in the inside and a transmission path for transmitting the abnormality detection signal to the circuit unit of the ground potential reference, An abnormal signal holding unit for holding the abnormality detection signal in an arm circuit and outputting it to the transmission path, a high breakdown voltage switching element connected in the transmission path, and the high breakdown voltage switching when the main switching element of the lower arm is turned on A power IC for driving a gate, comprising a control unit for turning on an element. 13. The control unit according to claim 12, further comprising means for detecting an on state of the main switching element of the lower arm based on an on signal to the main switching element and / or a decrease in the floating potential. The gate drive power IC.

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