JP3830940B2 - Programmable even clock divider circuit with duty cycle correction and arbitrary phase shift - Google Patents

Description

The present invention relates to clock circuits for digital systems. More specifically, the present invention relates to a variable even clock divider circuit with duty cycle correction and arbitrary phase shift.

BACKGROUND OF THE INVENTION Digital circuits, such as board level systems and integrated circuit (IC) devices, including programmable logic devices (PLDs) and microprocessors, use clock signals for a variety of reasons. For example, a synchronization system uses a general purpose clock signal to synchronize various circuits across a board or IC device.

  However, as digital circuits become more complex, the clocking scheme for synchronous systems has become more complex. Many complex digital circuits such as PLDs and microprocessors have multiple clock signals at different frequencies. For example, in some microprocessors, internal circuitry is clocked at a first frequency by a first clock signal and input / output (I / O) circuitry is clocked at a second frequency by a second clock signal. There is something. In general, the second frequency is slower than the first frequency.

  A plurality of clock signals can be generated using a plurality of clock generation circuits. However, the clock generation circuit generally consumes a large amount of device or board space. Thus, most systems use one clock generation circuit to generate the first clock signal and use a dedicated circuit to derive the other clock signal from the first clock signal. For example, a clock divider is used to generate one or more clock signals having a lower clock frequency from the input clock signal.

  1A shows a conventional clock divider 100 that receives an input clock signal ICLK and generates a two-divided clock signal CLKD2, a four-divided clock signal CLKD4, an eight-divided clock signal CLKD8, and a sixteen-divided clock signal CLKD16. Show. (In this specification, the same reference numerals are used to refer to terminals, signal lines, and corresponding signals thereof.) Clock divider 100 includes a 4-bit counter 110. Input clock signal ICLK is applied to the clock terminal of 4-bit counter 110. 4-bit counter 110 drives clock signals CLKD2, CLKD4, CLKD8, and CLKD16 on output terminals O0, O1, O2, and O3, respectively. The output terminals O0 to O3 give the most significant bit from the least significant bit of the 4-bit counter 110, respectively.

  FIG. 1B is a timing diagram for clock divider 100. As can be easily seen from FIG. 1B, when the input clock signal ICLK has a clock period P, the divided clock signal CLKD2 has a clock period of 2P. Similarly, the four-divided clock signal CLKD4 has a period of 4P, and so on. Therefore, the frequency of the clock signal CLKD2 is half of the frequency of the input clock signal ICLK, the frequency of the clock signal CLKD4 is a quarter of the frequency of the signal ICLK, and so on.

The inclusion of a clock divider within an IC device generally suffers from timing penalties regardless of whether the clock divider is in use. FIG. 2A shows a first clock driver circuit in an IC that does not include a clock divider. Clock driver circuit 200 includes a driver 201 that receives an input clock signal from clock pad 202 and provides the signal to clock tree 203. FIG. 2B shows a second clock driver circuit 210 that includes an optional clock divider 204. The designer can either bypass the clock divider or include the clock divider 204 in the circuit under the control of the multiplexer 205.

  FIG. 2B demonstrates that there is an additional delay D210 in the circuit of FIG. 2B compared to the circuit of FIG. 2A, regardless of whether a clock divider is included in the clock path. If the clock divider is bypassed, there will be additional delay on the bypass line and propagation delay through multiplexer 205. If a clock divider is included in the circuit, additional propagation delays occur for both the multiplexer and the clock divider. In either case, the total delay through this clock driver circuit increases.

  When a clock divider such as that shown in FIG. 1 is placed in the clock driver circuit of FIG. 2B, it is flip-flop (via the 4-bit counter 110 of FIG. 1) via a multiplexer (such as multiplexer 205 of FIG. 2B). A) driven clock tree results. Clearly, neither flip-flops nor unbuffered multiplexers have the drive capability to drive large clock trees, and the resulting clock signal is unacceptably slow and has very high skew. Have. Thus, multiplexer 205 is generally buffered, for example as shown in FIGS. 3A and 3B.

  FIG. 3A shows a prior art clock driver circuit 320 that includes an inverting clock divider 314. Multiplex circuit 325 replaces multiplexer 205 and multiplex circuit 325 implements the logical equivalent of multiplexer 205 with the input signal from the clock divider inverted by inverter 306.

  One embodiment of multiplexing circuit 325, designated 325A in FIG. 3A, includes a tri-state driver 326 to which the output of inverting clock divider 314 is provided and a pass gate 327 to which a bypass clock signal is provided. including. By controlling the tristate control signal of the tristate driver 326 and the passgate control signal of the passgate 327, either the divided clock signal or the bypass clock signal is selected. However, it should be noted that in this embodiment, the bypass clock signal is not yet buffered, and another buffer (not shown) may be inserted behind the pass gate 327 for a heavily loaded clock signal. I want.

  FIG. 3B shows a prior art clock driver circuit 330 that includes a non-inverting clock divider 324. Multiplex circuit 335 replaces multiplexer 205 and multiplexer circuit 335 implements the logical equivalent of multiplexer 205 with the output signal buffered through buffer 309.

  One embodiment of multiplexing circuit 335, designated 335A in FIG. 3B, includes a first tri-state driver 336, to which the output of non-inverting clock divider 324 is provided, and a bypass clock signal thereto. Second tri-state driver 337. By controlling the tristate control signals of the tristate drivers 336 and 337, either the divided clock signal or the bypass clock signal is selected. The selected clock signal is then inverted and buffered by inverter 339.

  However, the clock driver circuit shown in FIGS. 3A and 3B has yet another potential delay that can be significant. Yet another delay D320 added by the clock divider of FIG. 3A is the delay through the clock divider 314 plus the delay through the tri-state driver 326. Still another delay D330 added by the clock divider of FIG. 3B is the delay through clock divider 324 plus the delay through tristate driver 336 and inverter 339.

  The delay through the clock driver circuit is an important parameter for IC designers. By using a circuit similar to that shown in FIGS. 3A and 3B, yet another delay due to the presence of the clock divider can be significant, eg, about 500 picoseconds. As with most timing parameters, this delay is generally specified as a worst-case value to ensure device operation under worst-case conditions. Thus, even when the clock divider is bypassed, the device specifications are based on the worst case scenario, namely the delay when the clock divider is included. Thus, the additional delay on the clock path due to the presence of the clock divider not only delays the clock signal, but also makes the IC device appear slower than it actually is.

  For these and other reasons, it would be advantageous to provide a clock divider circuit with reduced delay.

SUMMARY OF THE INVENTION The present invention provides a novel clock divider circuit that adds little further delay to a clock driver that includes the circuit. Further, according to one embodiment, the clock divider circuit of the present invention provides the ability to divide by any even number, rather than being limited to a power of two as is the case with many clock dividers. The delay through the clock divider circuit is the same regardless of which even number is selected as the divisor.

  In one embodiment of the invention, the clock divider circuit includes a state machine that receives an input clock signal and generates a set control signal and a reset control signal. The set control signal and the reset control signal are used to control the set pass gate and the reset pass gate, respectively, and selectively provide an input clock signal to the pull-up and pull-down gate terminals on the output node. The set control signal and the reset control signal are also supplied to a keeper circuit that maintains a value arranged at the output node.

  The advantage of this circuit is that the delays typical of prior art clock dividers (D-flip-flop delay, multiplexer delay, etc.) are shifted from the clock path to the path containing the set and reset control signals. It is. These delays are therefore not on the clock path, i.e. not on the critical path of the clock divider circuit.

  Another advantage is that by controlling the state machine functionality, any even number (up to the capacity limit built into the state machine) can be selected for the clock divider circuit as a divisor. Thus, the clock divider circuit of the present invention provides more flexibility than many known clock dividers.

In one embodiment, phase bits are provided. The phase bit allows the user to either start the clock divider circuit on the first rising edge of the input clock or delay the clock divider circuit by a predefined number of clock periods. Can be done.

  In another embodiment, the clock divider circuit may complete the latest high pulse if the user miscounts the number of clock periods and accidentally resets the clock during clock processing (e.g., latest Designed to clock at a data value of

  In accordance with another aspect of the invention, a clock driver circuit includes an input buffer, a bypass pass gate, and a clock divider circuit that can be tri-stated. Instead of using a multiplexer circuit to select between the bypass signal and the output of the clock divider circuit, the clock divider circuit can be tristated. Therefore, if the clock divider circuit is tri-stated and the bypass pass gate is on, the bypass signal is passed to the output of the clock driver circuit. When the clock divider circuit is active (not tristated) and the bypass pass gate is off, the divided clock signal is passed to the output of the clock driver circuit. Thus, further delays added by the multiplexer circuit used in conventional clock divider circuits are eliminated.

  The present invention is illustrated by way of illustration and not limitation in the following figures in which like reference numbers indicate like elements.

DETAILED DESCRIPTION OF THE DRAWINGS In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

  FIG. 4 shows a clock driver circuit 440 that includes a clock pad 402, an input buffer 401, a bypass pass gate PassB, and a clock divider circuit 434. Unlike prior art clock driver circuits, the clock driver circuit 440 does not include a multiplexer to select either the output of the clock divider circuit 434 or the bypass clock signal. Instead, the clock divider circuit 434 can be tri-stated internally. When the clock divider circuit 434 is tri-stated (ie, placed in high impedance) and the pass gate PassB is on, the bypass clock signal is passed through the clock tree 403. When the clock divider circuit 434 is in the active state and the pass gate PassB is off, the divided clock signal is passed through the clock tree 403.

  Circuit 434A of FIG. 4 illustrates one implementation of clock divider 434 that can be tri-stated. In this embodiment of the invention, the clock driver circuit that can be tri-stated includes a state machine 436, a pull-up circuit PUckt, a pull-down circuit PDckt, and a keeper circuit 439.

The state machine 436 receives the input clock signal CKIN of the clock divider and generates a set control signal and a reset control signal (QS and QR, respectively). When the control signal QS is low, the rising edge of the input clock CKIN is passed to the node “S” and thus to the output signal CKOUT. When the control signal QR is low, the rising edge of the input clock CKIN is passed to the node “R” and, therefore, is passed to the falling edge of the output signal CKOUT. Nodes S and R are preferably initialized to low and high values, respectively, by pull-down and pull-up (also not shown) gated by a reset signal (not shown). The state machine 436 keeps track of where the input signal CKIN is present in the “divided” clock period, generates appropriate voltage levels on QS and QR, and sets the output clock signal high at the appropriate time. And drive low. For example, if the divisor is 6, each of the control signals QS and QR pulses low with one CKIN clock period for every six.

  In one embodiment, the state machine only supports one divisor. In other embodiments, the state machine is programmable and supports multiple divisors.

  In some embodiments, the state machine and clock divider circuit form part of a programmable logic device (PLD), such as a field programmable gate array (FPGA) or programmable composite logic device (CPLD). . In one such embodiment, the state machine is implemented using programmable logic that is controlled by the user, performs a specific function in a specific design, and supports only one divisor.

  In another embodiment, the clock divider and state machine circuits are implemented in dedicated logic (ie, without user-controlled logic blocks). However, this dedicated logic can be designed to be programmable. For example, in some embodiments, the clock divider circuit is implemented with dedicated logic within a programmable logic device. The clock divider circuit includes a state machine that can be configured to support a number of arbitrary divisors. In one such embodiment, when the PLD is a CPLD, the state machine is controlled by logical values stored in FLASH memory using a typical programming process for CPLD. In this embodiment, the logical value is included in the CPLD configuration data file. In another such embodiment, if the PLD is an FPGA, the state machine is controlled by the logic value stored in the SRAM cell during normal configuration processing for the FPGA. In this embodiment, the logical value is loaded as part of the constituent bitstream.

  Returning to FIG. 4, the set control signal QS controls the set pass gate PassS, and this set pass gate PassS selectively provides the input clock signal CKIN to the pull-up PU. In the embodiment of FIG. 4, the set pass gate PassS is coupled to the input terminal of an inverter INVS that drives the gate of the pull-up PU. The reset control signal QR controls the reset pass gate PassR, and the reset pass gate PassR selectively provides the input clock signal CKIN to the pull-down PD.

  In the illustrated embodiment, the pull-up PU is a PMOS transistor, the pass gate PassS is a CMOS pass gate controlled by the set control signal QS and the same signal inverted by the inverter 437, and the pass gate PassR is reset. The CMOS pass gate is controlled by the control signal QR and the same signal inverted by the inverter 438, and the pull-down PD is an NMOS transistor. In other embodiments, other types of transistors and / or other circuits are used to implement pull-up PU, pull-down PD, and pass gates PassS and PassR. For example, the pass gates PassS and PassR can be realized as NMOS transistors, PMOS transistors, tristate drivers, etc., and the pull-up PU can be realized as an NMOS transistor when the inverter INVS is omitted.

  The set pass gate PassS, the inverters 437 and INVS, and the pull-up PU collectively constitute a pull-up circuit PUckt. The reset pass gate PassR, the inverter 438, and the pull-down PD collectively constitute a pull-down circuit PDckt.

Pull-up PU and pull-down PD are coupled in series between power high (VCC) and ground (GND). The node between pull-up PU and pull-down PD is coupled to the output terminal CKOUT of the clock divider.

  The set S and reset R control signals are also provided to a keeper circuit 439 coupled to the output terminal CKOUT. Keeper circuit 439 provides a weak output signal KOUT that enhances the signal on output terminal CKOUT so that when both pull-up PU and pull-down PD are off, the voltage level of the signal continues to be stored at the node. To do. One embodiment of the keeper circuit 439 will be described in detail below with reference to FIG. However, any keeper circuit is well known in the art and any keeper circuit can be used in the clock driver 434A as long as the output signal KOUT is weak enough to be overridden by both pull-up PU and pull-down PD. For example, a weak, cross-coupled latch with two inverters can be used as a weak keeper with one of the inverters also driving the signal CKOUT. This embodiment does not require signals S, R, and CDEN as inputs to the weak keeper.

  The set control signal QS and the reset control signal QR are preferably mutually exclusive. That is, preferably state machine 436 does not activate signals QS and QR at the same time. Thus, pull-up PU and pull-down PD are not both turned on at the same time, no current flows between VCC and GND, and can occur in the conventional clock divider circuit shown in FIGS. 3A and 3B. There is also no temporary contention by which the transistor controls the value on the output terminal of CKOUT.

  Note that the delay through the clock driver circuit 434A relative to the rising edge of the clock includes only the delay through the pass gate PassS, inverter INVS, and pull-up PU. The delay through the clock driver circuit 434A relative to the falling edge of the clock includes only the delay through the pass gate PassR and pull-down PD. Thus, the clock delay of clock driver circuit 440 is much shorter than the clock delay through, for example, clock driver circuits 320 and 330 of FIGS. 3A and 3B.

  The novel circuit configuration of FIG. 4 has further advantages. In conventional clock drivers, the clock signal follows the same path through the driver for both the rising and falling edges of the clock. Therefore, the circuit cannot be optimized for both ends. Rather, efforts must be made to make some compromise to provide acceptable performance at both ends of the clock. However, in the circuit shown in FIG. 4, the pull-up PU and pull-down PD are controlled separately. Thus, each of the control transistors can be optimized for the corresponding clock edge. That is, the rising edge of the output clock signal CKOUT is controlled by the pass gate PassS, the inverter INVS, and the pull-up PU, and the falling edge of the output clock signal CKOUT is controlled by the pass gate PassR and the pull-down PD. Therefore, the pass gate PassS, the inverter INVS, and the pull-up PU can be optimized to improve the performance of the rising edge of the output clock CKOUT, and the pass gate PassR and the pull-down PD can be optimized to reduce the falling edge of the output clock CKOUT. The performance can be improved. This optimization can be accomplished via well-known methods including, for example, computer-implemented circuit simulation.

For all of these reasons, the clock delay through the clock driver circuit 434A is significantly lower than the delay through the conventional clock driver circuit. As noted above, the delay added to a clock driver circuit using a conventional clock divider is typically about 500 picoseconds. However, using similar manufacturing techniques, the delay added when using clock divider 434A can be as little as 90 picoseconds.

Programmable Clock Divider FIGS. 5 and 8-15 collectively show a detailed schematic diagram of a programmable clock divider circuit 500 according to one embodiment of the present invention. 6 and 7 provide two exemplary timing diagrams for the clock divider circuit 500 in the divide-by-two mode and the divide-by-6 mode, respectively. Next, the operation of this embodiment will be described with reference to FIGS.

  The signals used in the clock divider circuit 500 include:

  • CKIN Input clock signal to the clock divider circuit.

  CKOUT output clock signal (eg, divided clock).

  • CDRST Resets (disables) the clock divider circuit when high, and releases (enables) the clock divider circuit when low.

  ・ CDEN Disables other control signals. When high, enable clock divider, turn off bypass circuit BPC, allow keeper circuit 560 to follow S and R control signals and keep CKOUT value stable, control RST signal Release the reset filter for. When low, the clock divider is disabled, the bypass circuit BPC is turned on, the keeper circuit 560 is tri-stated, and both the pull-up PU and pull-down PD are turned off. In one embodiment, signal CDEN is a value stored in a configuration memory cell, such as an SRAM configuration memory cell in an FPGA or a FLASH memory cell in a CPLD.

  CDDIV Input signals (CDDIV0, CDDIV1, and CDDIV2) that select the divisor for the programmable clock divider. In one embodiment, control signals CDDIV0-CDDIV2 are values stored in configuration memory cells, such as SRAM configuration memory cells in FPGA or FLASH memory cells in CPLD.

  CDP causes an arbitrary phase shift. When high, the clock divider output signal CKOUT rises on the first rising edge of the input clock signal CKIN after CDRST goes low. When low, the clock divider output signal is delayed by one output clock period (ie, one CKOUT period). For example, if the clock divider is configured to divide by 4, the CKOUT signal rises on the fifth rising edge of the CKIN signal after CDRST goes low.

  PUINIT This initialization signal is an input signal that goes high only while the PLD is powered on. This is mainly used to initialize the flip-flops of the entire PLD.

  The clock divider circuit of FIG. 5 includes a programmable control circuit 501, a pull-up circuit PUC, a pull-down circuit PDC, a keeper circuit 560, and a bypass circuit BPC.

FIG. 6 is a timing diagram illustrating the operation of the clock divider circuit of FIG. 5 in the two-divided mode. As long as the clock divider reset signal CDRST is high, the signals QS, QR, S, and R remain at their reset values (low, high, low, and high, respectively). The programmable control circuit 501 decodes the input signal CDDIV [2: 0] and derives a divisor of 2. When the clock divider reset signal CDRST goes low, the signal S goes high at the next rising edge of CKIN. The signal S then goes low again at the next falling edge of CKIN. The keeper signal KOUT remains high when the signal S goes low, so the signal CKOUT remains high after the signal S goes low.

  Next, signal R goes high at the next rising edge of CKIN (because the state machine has set signal QR low), causing CKOUT to go low. Signal R then goes low again at the next falling edge of CKIN. Keeper signal KOUT remains low when signal R goes low, and therefore signal CKOUT remains low after signal R goes low. This cycle is repeated until the clock divider reset signal CDRST goes high. If the clock divider is reset while signal CKOUT is high, a high pulse on signal CKOUT is completed.

  FIG. 7 is a timing diagram illustrating the operation of the clock divider circuit of FIG. 5 in the 6-divided mode. This timing diagram is similar to that of FIG. 6, but the signals QS and QR go low every sixth clock period instead of every other clock period, and the signals that depend on QS and QR result It differs in that it occurs less frequently.

The bypass circuit bypass circuit BPC provides a way to bypass and disable the clock divider function of the clock divider circuit. The pass gate PassB is located between the input clock terminal CKIN and the output clock terminal CKOUT. In the illustrated embodiment, the pass gate PassB is a CMOS pass gate with the PMOS control terminal coupled to CDEN and the NMOS control terminal coupled to the inverted signal generated by the inverter 544. When the clock divider enable signal CDEN is high, the pass gate is off. When the clock divider enable signal CDEN is low, the pass gate is on.

Programmable Control Circuit In the embodiment of FIG. 5, programmable control circuit 501 includes a synchronized reset generator 510, a decoder 520, and a state machine 530.

  The synchronized reset 510 provides an appropriately delayed version of the clock divider reset signal CDRST. The number of CKIN clock periods by which the reset signal is delayed by that amount is controlled by three control signals CDDIV0-CDDIV2.

  One embodiment of a synchronized reset 510 is shown in FIG. Synchronized reset 510 includes 16 sets of flip-flops 801-816 coupled in series. The Q outputs of the even number of flip-flops are supplied to an 8: 1 multiplexer 820 controlled by control signals CDDIV0 to CDDIV2. In the illustrated embodiment, the value of CDDIV corresponds to the value (divisor) to be divided of the clock divider, as shown in Table 1.

  The output of multiplexer 820 is a signal that mirrors clock divider reset signal CDRST, but is delayed by a selected number of CKIN clock periods. The output of multiplexer 820 drives the “0” data terminal of 2: 1 multiplexer 821. The “1” input terminal is driven by the CDRST signal, and one of the two inputs is selected by the control signal CDP as described above.

  The output of the multiplexer 821 is stored in the set flip-flop 817 that drives the NAND gate 823. The set terminal of the flip-flop 817 is driven by the signal PUINIT as described above. Another input to the NAND gate 823 is a reset control signal R from the pull-down circuit PDC. The NAND gate 823 is NANDed by inversion of the signal PUINIT (high only during power-up and initializes all flip-flops on the PLD) to generate the reset signal SYNRST.

  The R input to NAND gate 823 provides yet another capability. If the clock divider is reset while signal CKOUT is high, the feedback from reset control signal R ensures that the latest clock period on signal CKOUT is completed.

  FIG. 9 shows one embodiment of the decoder 520. The illustrated embodiment includes NOR gates 901-913, NAND gates 920-939, and inverters 950-957. Decoder 520 decodes signals CDDIV0-CDDIV2 and generates control signals DIV2-DIV14 and SMX_6-16 from these signals, which form the bus labeled "DIV" in FIGS. 9 and 5 . The decoder also generates control signals OFF2 to OFF16 from the signals CDDIV0 to CDDIV2, which form a bus labeled “OFF” in FIGS. All these signals are used to control the state machine 530. Decoding tables for decoder 520 are shown in Tables 2A and 2B, where “1” is high, “0” is low, and “x” is a don't care value.

  In addition, in the decoder 520, another reset signal RST is generated from the clock divider enable signal CDEN and the reset signal SYNRST. This reset signal is used to reset the set filter and the reset filter in the pull-up circuit and the pull-down circuit, respectively.

FIG. 10 (including FIGS. 10A and 10B) is a block diagram of one embodiment of state machine 530. The state machine 530 is controlled by the DIV and OFF buses from the decoder 520 to provide QS and QR control signals to the set and reset filters of the pull-up and pull-down circuits (respectively). State machine 530 includes seven subcells (logic blocks 531a-f and 532) connected in series as shown in FIG. Signals DIV14 to DIV2 control the serial connection between the blocks via multiplexers a to q and t to u. When the clock divider is activated (ie, when CDEN goes high), exactly one of the DIV signals DIV14-DIV2 goes high (see Table 2A). Thus, all but one of the subcells pass values from left to right along the chain. The selected subcell places its QS and QR values on the chain.

  For example, if the divisor is 6, the signal DIV6 is high. Therefore, the subcell 531f is a subcell in which the signal QS is arranged on the chain via the DS6 terminal. Similarly, value QR6FB is arranged on the dly6 (Ddelay6) terminal of subcell 531f, and signal QR2 is arranged on the DR6 terminal of subcell 531f. Next, the selected QS and QR values are passed through flip-flops 533 and 534, respectively. The set control signal QS is given by the flip-flop 533. The reset control signal QR is provided by the multiplexer 535, and the multiplexer 535 selects one of the values QR6dly, QR4dly, and QR2 based on the values of the signals SMX_6 to 16, DIV4, and DIV2.

  A chain of delays (Ddelay to Qdelay chain for the entire submachine of the state machine) provides automatic duty cycle correction capability. This circuit ensures that a low pulse on the QR signal always occurs midway between the low pulses on the QS signal (see, for example, the timing diagram of FIG. 7). As can be seen in FIG. 11, the delay on the chain of delay through each subcell is half of the delay on the chain from DSi to QSi and from DRi to QRi. Furthermore, the delay chain contributes to the formation of the QR control signal. Therefore, the duty cycle of the divided clock signal is always 50%.

  FIG. 11 is a block diagram of the first subcell 531 of the state machine of FIG. Subcell 531 includes reset flip-flops 1101 to 1102, set flip-flops 1110 to 1112, and NOR gates 1120 to 1123. The signal DSi is passed through the flip-flop 1101, the NOR gate 1120 (when the signal QS2B is low), the flip-flop 1102 and the NOR gate 1123 (when the signal QS2B is low) to the output terminal QSi. The signal Ddelay is passed through the flip-flop 1110 to the output terminal Qdelay. The signal DRi is passed through the flip-flop 1112 to the NOR gate 1121 and fed back to the output terminal QRiFB. When signal QR2B is low, NOR gate 1121 passes the inverted output of flip-flop 1112 to flip-flop 1111 and thus passes to NOR gate 1122 with signal QR2B as the other input. NOR gate 1122 provides output signal QRi.

  FIG. 12 is a block diagram of the second subcell 532 of the state machine of FIG. Subcell 532 is similar to subcell 531 except that signal QR4DLY is the output of flip-flop 1212.

  FIG. 13 is a block diagram of the set filter circuit 541. As can be seen in FIG. 5, the set filter circuit controls the pull-up PU on the clock output signal CKOUT. The set filter circuit receives the control signal QS from the state machine and filters the clock pulse on the input clock signal CKIN using the QS signal. That is, based on the value of the signal QS, the pulse on the signal CKIN is passed through the signal S or not passed through the signal S.

In the illustrated embodiment, the set filter circuit 541 includes a NOR gate 1301, an inverter 1302, a pass gate 1303, and a pull-down PD1. Passgate 1
303 is disposed between the input terminal CKIN and the output terminal S. NOR gate 1301 receives signals QS and RST as inputs and provides signal GNS, which controls the NMOS terminal of pass gate 1303. Signal GNS also drives inverter 1302, which controls the PMOS terminal of pass gate 1303 and also controls pull-down PD1. Pull-down PD1 is coupled between output terminal S and ground GND.

  FIG. 14 is a block diagram of the reset filter circuit 551. As can be seen in FIG. 5, the reset filter circuit controls the pull-down PD on the clock output signal CKOUT. The reset filter circuit receives a control signal QR from the state machine, and filters the clock pulse on the input clock signal CKIN using the QR signal. That is, based on the value of the signal QR, the pulse on the signal CKIN is passed through the signal R or not passed through the signal R.

  In the illustrated embodiment, the reset filter circuit 551 includes NOR gates 1401 and 1402, NAND gate 1406, inverters 1404 and 1405, pass gate 1403, pull-up PU2, and pull-down PD2. The pass gate 1403 is disposed between the input terminal CKIN and the output terminal R. The NOR gate 1401 receives the signals QR and RST as inputs and provides a signal GNR, which controls the NMOS terminal of the pass gate 1403. The signal GNR also drives the inverter 1405 that controls the PMOS terminal of the pass gate 1403 and also drives the first input of the NOR gate 1402. NOR gate 1402 controls pull-down PD2 coupled between output terminal R and ground GND. NAND gate 1406 receives signals CDEN and RST as inputs and provides signal PPUB. Signal PPUB controls pull-up PU2 coupled between output terminal R and power high VCC. Signal PPUB also drives an inverter 1404 that provides a second input to NOR gate 1402.

  FIG. 15 is a block diagram of the keeper circuit 560. Keeper circuit 560 includes pull-up PU3 and PU4 and pull-down PD4 and PD3 coupled in series between power high VCC and ground GND. Output terminal KOUT is coupled between pull-up PU4 and pull-down PD4. The clock divider enable signal CDEN directly drives the pull-down PD3 and drives the pull-up PU3 via the inverter 1501. Therefore, when signal CDEN is low, both pull-up PU3 and pull-down PD3 are off, and the signal at output terminal KOUT is tristated. Both pull-up PU4 and pull-down PD4 are driven by a signal SB. Signals SB and RB are provided by cross-coupled NOR gates 1502 and 1503, respectively. The other input to the NOR gate 1502 is the S signal from the set filter 541. The other input to the NOR gate 1503 is the R signal from the reset filter 551.

  In various embodiments of the present invention, novel structures have been described for clock driver circuits and clock divider circuits. The various embodiments of the structure and method of the present invention described above are merely illustrative of the principles of the invention and are not intended to limit the scope of the invention to the particular embodiments described. For example, with reference to this disclosure, those skilled in the art can define other state machines, keeper circuits, pass gates, inverters, pull-ups, pull-downs, clock dividers that can be tri-stated, buffers, multiplexers, etc. These alternative features can be used to form a method, circuit or system in accordance with the principles of the present invention. Accordingly, the invention is limited only by the following claims.

It is a block diagram of a conventional clock divider. FIG. 1B is a timing diagram for the clock divider of FIG. 1A. It is a block diagram of a conventional clock driver circuit that does not include a clock divider. 1 is a block diagram of a conventional clock driver circuit including an arbitrary clock divider. 1 is a block diagram of a conventional clock driver circuit including an inverting clock divider. 1 is a block diagram of a conventional clock driver circuit including a non-inverting clock divider. 1 is a block diagram of a first driver circuit including a clock divider that can be tri-stated according to a first embodiment of the present invention; FIG. FIG. 4 is a block diagram of a clock divider circuit according to a second embodiment of the present invention. FIG. 6 is a timing diagram illustrating the operation of the clock divider circuit of FIG. 5 in a two-divided mode. FIG. 6 is a timing diagram illustrating the operation of the clock divider circuit of FIG. FIG. 6 is a block diagram of an enable signal generator circuit that may be used with the clock divider circuit of FIG. FIG. 6 is a block diagram of a decoder circuit that can be used with the clock divider circuit of FIG. FIG. 6 is a block diagram of a state machine that can be used with the clock divider circuit of FIG. 5 (including FIGS. 10A and 10B). FIG. 6 is a block diagram of a state machine that can be used with the clock divider circuit of FIG. FIG. 6 is a block diagram of a state machine that can be used with the clock divider circuit of FIG. FIG. 11 is a block diagram of a first subcell of the state machine of FIG. 10. FIG. 11 is a block diagram of a second subcell of the state machine of FIG. 10. FIG. 6 is a block diagram of a set filter circuit that can be used with the clock divider circuit of FIG. FIG. 6 is a block diagram of a reset filter circuit that can be used with the clock divider circuit of FIG. FIG. 6 is a block diagram of a keeper circuit that can be used with the clock divider circuit of FIG.

Claims (8)

A clock input terminal;
A clock output terminal;
A state machine having an input terminal coupled to the clock input terminal, and further having a set output terminal and a reset output terminal;
A keeper circuit having an output terminal coupled to the clock output terminal;
A pull-up circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the set output terminal of the state machine, and an output terminal coupled to the clock output terminal;
A clock divider comprising: a data input terminal coupled to the clock input terminal; a control input terminal coupled to the reset output terminal of the state machine; and a pull-down circuit having an output terminal coupled to the clock output terminal. circuit. The pull-up circuit is
A pass gate coupled between the clock input terminal and a pass gate output terminal, the pass gate having a first gate terminal coupled to the set output terminal of the state machine, the pull-up circuit further comprising: ,
The clock divider circuit of claim 1 including a pull-up coupled between a power high and the clock output terminal, the pull-up having a gate terminal coupled to the pass gate output terminal. The pull-up circuit further includes a first inverter,
The pull-up is a PMOS transistor;
The clock divider circuit of claim 2, wherein the gate terminal of the pull-up is coupled to the pass gate output terminal via the first inverter. The pull-up circuit further includes a second inverter,
3. The clock divider circuit of claim 2, wherein the pass gate is a CMOS pass gate having a second gate terminal coupled to the set output terminal of the state machine via the second inverter. The pull-down circuit is
A pass gate coupled between the clock input terminal and a pass gate output terminal, the pass gate having a first gate terminal coupled to the reset output terminal of the state machine; and the pull-down circuit further comprises:
The clock divider circuit of claim 1 including a pull-down coupled between the clock output terminal and ground, the pull-down having a gate terminal coupled to the pass gate output terminal. The pull-down circuit further includes an inverter,
The pull-down is an NMOS transistor,
6. The clock divider circuit of claim 5, wherein the pass gate is a CMOS pass gate having a second gate terminal coupled to the reset output terminal of the state machine via the inverter.   The clock divider circuit of claim 1, wherein the state machine includes a programmable divisor selection circuit. The clock divider circuit of claim 7, wherein the clock divider circuit forms part of a programmable logic device (PLD).

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