JP3829701B2 - Pulse signal frequency control method and frequency control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pulse signal frequency control method and a pulse signal frequency control circuit for performing control to increase or decrease the frequency of a pulse signal used for rotation control of a pulse drive motor such as a stepping motor.
[0002]
[Prior art]
Conventionally, as a pulse signal output circuit, there is a circuit disclosed in JP-A-10-215167. As shown in FIG.ⁿ A frequency setting register 101 having at least (n + 1) bits for inputting the following frequency values; an adder circuit 102 capable of sequentially adding frequency values;^{n + 1}A flip-flop 103 that sequentially accumulates and holds frequency values by the adder circuit 102 each time a clock pulse signal having a frequency of every second is input, and outputs a carry signal that has been raised to the (n + 1) th bit; It has a configuration provided.
[0003]
Since this circuit outputs a pulse signal having the frequency set in the frequency setting register 101, it is output by setting the frequency set to the frequency setting register 101 at an arbitrary timing to the division. The frequency of the pulse signal can be increased. In addition, this circuit can reduce the frequency of the pulse signal to be output by setting the frequency setting register 101 to a frequency that is reduced by division at an arbitrary timing.
[0004]
The rotation control of the pulse drive type motor using this circuit will be described with reference to FIG. Acceleration increases from the initial frequency, which is the starting value, to the target value, which is a higher frequency than the starting value. Done. On the other hand, as in the case of acceleration, when the frequency is reduced by an arbitrary number of steps at the timing indicated by the arrow from the target value described above toward the starting value, the deceleration is performed along with the decrease in the frequency. Is called.
[0005]
Next, frequency change for acceleration / deceleration described above will be described. The frequency change for acceleration is performed at the frequency update timing for acceleration determined by the acceleration time from the start of acceleration to the end of acceleration and the number of acceleration stages. Further, the frequency change for deceleration is performed at the frequency update timing for deceleration described later, similarly to the frequency change for acceleration.
[0006]
An example of a frequency control circuit for a pulse signal that determines the frequency update timing for deceleration includes an acceleration / deceleration control circuit disclosed in Japanese Patent Application Laid-Open No. 2000-69776. This circuit is a circuit for setting a frequency reduction start time in advance, and as shown in FIG. 13, a frequency changing unit 201 that performs control related to the frequency of the output pulse signal, and a movement that performs control related to the number of designated pulse signals. The quantity processing unit 202 includes a deceleration point detection unit 203 that automatically detects a deceleration point.
[0007]
Next, the above-described deceleration point detection unit 203 will be described in detail with reference to FIG. The deceleration point detection unit 203 includes a multiplexer 203a, a deceleration point detection counter 203b, an adder 203c, and a deceleration point detection circuit 203d.
[0008]
The multiplexer 203a selects “−1” whose absolute value is a predetermined value while the acceleration flag indicating that the motor whose rotation is controlled by the acceleration / deceleration control circuit is accelerating is not input, While being input to the adder 203c, while the accelerating flag is being input, “−2” whose absolute value is twice the predetermined value is selected and input to the adder 203c.
[0009]
Similar to the drive amount detection counter 202a included in the movement amount processing unit 202, the deceleration point detection counter 203b is set as a predetermined drive amount to the setting unit 201a included in the frequency change unit 201 when an activation request is made to the frequency change unit 201. The set predetermined count value is transferred. The deceleration point detection counter 203b receives a pulse signal having a frequency value corresponding to the speed of the motor, and for each pulse of the pulse output signal, that is, simultaneously with the change of the drive amount detection counter 202a, the adder 203c. The output value of the deceleration point detection counter 203b is fed back to the adder 203c.
[0010]
The adder 203c adds the input value from the multiplexer 203a and the feedback value from the deceleration point detection circuit 203d. Specifically, as shown in FIG. 15, while the motor is accelerating and the accelerating flag is input to the multiplexer 203a, “−2” is input from the multiplexer 203a and this “−2” is added. Thus, “2” is subtracted from the feedback value from the deceleration point detection circuit 203d, and the value obtained by the subtraction is input to the deceleration point detection counter 203b. The adder 203c receives "-1" from the multiplexer 203a while the motor is driven at a constant speed and the accelerating flag is not input to the multiplexer 203a. “1” is subtracted from the feedback value, and the value obtained by the subtraction is input to the deceleration point detection counter 203b.
[0011]
Thus, when the value subtracted by the adder 203c is input to the deceleration point detection counter 203b, the deceleration point detection counter 203b is simultaneously with the change of the drive amount detection counter 202a when the motor is not accelerating. When the motor is accelerating from the predetermined count value, the value changes by “1”, and when the motor is accelerating, the driving amount detection counter 202a changes at the same time by “2”, which is twice the predetermined value. Become smaller.
[0012]
The deceleration point detection circuit 203d detects a deceleration point at the start of frequency reduction based on a comparison between “0”, which is a preset reference value, and the counter value Cd of the deceleration point detection counter. Specifically, the deceleration point detection circuit 203d detects a deceleration point when the counter value Cd of the deceleration point detection counter 203b is equal to or less than the reference value “0”, and outputs a deceleration request flag to the frequency changing unit 301. To do.
[0013]
[Problems to be solved by the invention]
In the above conventional pulse signal frequency control circuit (acceleration / deceleration control circuit disclosed in Japanese Patent Laid-Open No. 2000-69976), although the pulse signal during acceleration is counted, the acceleration end timing is output. Since the rising edge and falling edge of the pulse signal are irrelevant, the preset acceleration end timing may not match the actual acceleration end timing.
[0014]
This will be described with reference to FIG. For example, when the pulse signal is counted by the rising edge, before the counted pulse signal is output, more specifically, the acceleration section is completed before one cycle of the counted pulse signal is completed. The actual acceleration end timing may be earlier than the preset acceleration end timing.
[0015]
Since the deceleration point (deceleration start timing) is also detected by counting the pulse signal as described above, the preset deceleration point and the actual deceleration point are similar to the acceleration end timing. If the actual deceleration point (deceleration start timing) is earlier than the preset deceleration point (deceleration start timing), as shown in FIG. Since a long pulse signal is output, the actual operation time becomes longer than the preset operation time.
[0016]
Furthermore, linear interpolation in which two motors are used to drive independently in each of the X-axis direction and the Y-axis direction will be described with reference to FIGS. Note that, as shown in FIG. 17, the linear interpolation is a synchronous control of the multi-axis motor so that the locus of coordinates is a straight line, and simultaneous activation and simultaneous stop are performed. In this linear interpolation, the combined target frequency in the X-axis direction and the Y-axis direction, the activation frequency and the target frequency in the X-axis direction and the Y-axis direction are set. In this linear interpolation, in theory, if simultaneous activation is performed, the operation is completed simultaneously as shown in FIG.
[0017]
However, as described above, when the preset deceleration point and the actual deceleration point do not coincide with each other, the actual operation time is different from the preset operation time, as shown in FIG. In addition, the end of the operation in the X-axis direction and the end of the operation in the Y-axis direction do not coincide with each other, and it is impossible to pass on a preset locus.
[0018]
The present invention has been made paying attention to the above points, and the object of the present invention is to provide a frequency control method and a frequency control for a pulse signal capable of making an actual operation time coincide with a preset operation time. It is to provide a circuit.
[0019]
[Means for Solving the Problems]
  In order to solve the above-described problem, the pulse signal frequency control method according to claim 1 is configured such that the activation value and a target value higher than the activation value are preset, and the pulse signal is maintained until the preset frequency increase ends. The frequency control method of the pulse signal that increases the frequency of the signal from the starting value toward the target value, and decreases and returns to the starting value after a certain period of frequency of one period or more of the pulse signal has elapsed. BecauseWhen the frequency fixed period is one cycle or more of the pulse signal,Based on a correction period consisting of a period of fixed frequency in the pulse signal including the end of frequency increase,When the correction period elapses from the preset frequency decrease start time, the frequency decrease start timeCorrection is executed.
[0020]
  In the frequency control method of the pulse signal according to claim 2, a starting value and a target value higher than the starting value are preset,The frequency of the pulse signal is increased from the activation value toward the target value until the preset frequency increase ends, and the activation value is reached after a certain frequency period of one or more periods of the pulse signal or less than one period has elapsed. A method for controlling the frequency of a pulse signal that is reduced and restored to a frequency signal, and when the constant frequency period is less than one cycle of the pulse signal, the correction includes a period that is a constant frequency period in the pulse signal including the end of the frequency increase. Based on the period, when the correction period elapses from the pulse edge immediately after the end of the frequency increase in the pulse signal including the end of the frequency increase, the start of the frequency decreaseCorrection is executed.
[0021]
  The frequency control method for a pulse signal according to claim 3 is:Claim 1In the frequency control method for a pulse signal described in the above, it is determined whether the end of the frequency increase is after a half cycle of the pulse signal or before the half cycle has elapsed, and the end of the frequency increase is after the half cycle of the pulse signal has elapsed. The correction period is a period from the end of the frequency increase in the pulse signal including the end of the frequency increase to the pulse edge that is the boundary with the next pulse signal, and the end of the frequency increase is in the pulse signal. When the half period has not elapsed, the correction period is a period obtained by adding a half period of the pulse signal to a period from the end of the frequency increase to the pulse edge in the pulse signal immediately after the end of the frequency increase. Like to do.
[0023]
  Claim 4The frequency control method of the described pulse signal isClaims 1 to 3In the frequency control method for a pulse signal according to any one of the above, the frequency value of the pulse signal at the end of the frequency increase is stored, and the frequency of the pulse signal is decreased from the stored frequency value toward the activation value. I try to let them.
[0024]
  Claim 5The frequency control method of the described pulse signal isClaims 1 to 3In the frequency control method for a pulse signal according to any one of the above, when the pulse signal has a preparation period of less than a half cycle before the first pulse edge, a half cycle of the pulse signal after returning to the activation value After the elapse of time, the output of the pulse signal is regulated.
[0025]
  Claim 6The described pulse signal frequency control circuit is preset with a starting value and a target value higher than the starting value, and increases the frequency of the pulse signal from the starting value toward the target value until the preset frequency increase ends. And a pulse signal frequency control circuit for reducing and returning to a starting value after a certain frequency period of one cycle or more or less than one cycle has elapsed. In the case where the period is equal to or longer than the period, a measuring unit is provided for measuring a correction period including a period that is a constant frequency period in the pulse signal including the end of frequency increase, and the constant frequency period is equal to or longer than one period of the pulse signal. Further, the correction is performed so that the frequency reduction starts when the correction period elapses from the preset frequency reduction start.
[0026]
  Claim 7The pulse signal frequency control circuit described isClaim 6In the pulse signal frequency control circuit described above, there is provided second measuring means for measuring the correction period when the fixed frequency period is less than one cycle of the pulse signal, and the fixed frequency period is less than one cycle of the pulse signal. In some cases, the correction is executed such that the frequency reduction starts when the correction period further elapses from the pulse edge immediately after the end of the frequency increase.
[0027]
  Claim 8The pulse signal frequency control circuit described isClaim 7DescribedPulse signal frequency control circuitThe measuring means is used as the second measuring means.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
A frequency control method for a pulse signal according to the first embodiment of the present invention will be described with reference to FIGS. In this pulse signal frequency control method, a starting value and a target value higher than the starting value are set in advance, and the frequency of the pulse signal is changed from the starting value to the target value until the preset frequency increase end t1. A method of increasing the frequency and returning to a starting value after a certain frequency period of one or more cycles of the pulse signal has elapsed, wherein the pulse signal includes a frequency constant period in the pulse signal including the end t1 of the frequency increase. Based on the correction period TA, the correction for making the frequency reduction start time constant is executed.
[0029]
Of the frequency control method of this pulse signal, the method is the same as that of the prior art except for the method of executing the correction that makes the frequency reduction start time constant, and the explanation of the same points as the prior art is omitted.
[0030]
That is, as shown in FIG.ⁿ A frequency setting register 1 having at least (n + 1) bits for inputting the following frequency values, an adding circuit 2 capable of sequentially adding frequency values, and 2^{n + 1}A flip-flop 3 that sequentially accumulates and holds frequency values by the adder circuit 2 every time a clock pulse signal having a frequency of every second is input, and outputs a carry signal that has been raised to the (n + 1) th bit; The pulse signal output circuit is provided, and the frequency setting register 1 is set to a frequency that is increased and divided at an arbitrary timing to increase the frequency of the pulse signal to be output. Regarding the method of reducing the frequency of the pulse signal to be output by setting a frequency that is reduced at an arbitrary timing, the pulse signal output disclosed in Japanese Patent Laid-Open No. 10-215167 already described as the prior art It is the same as the method.
[0031]
Also, as shown in FIGS. 3 and 4, a frequency changing unit 4 for controlling the frequency of the output pulse signal, a movement amount processing unit 5 for controlling the number of designated pulse signals, and automatically detecting a deceleration point The deceleration point detection unit 6 includes a multiplexer 6a, a deceleration point detection counter 6b, an adder 6c, and a deceleration point detection circuit 6d. As already described in the prior art, the method of making the frequency of the pulse signal constant from the start value to the target value and increasing the frequency until the end of the preset frequency increase and then making the frequency of the pulse signal constant is disclosed in Japanese Patent Application Laid-Open No. 2000-2000. This is the same as the method using the acceleration / deceleration control circuit disclosed in Japanese Patent No. 69776. Reference numeral 7 denotes a counter described later.
[0032]
Hereinafter, a detailed description will be given with reference to FIGS. 2A shows a theoretical pulse signal sequence that should be output in accordance with preset conditions, and FIG. 2B shows, for comparison, Japanese Patent Application No. Hei 10-10, which is a prior art. The pulse signal sequence output by the acceleration / deceleration control circuit disclosed in Japanese Patent No. 239850 is shown, and FIG. 10C shows the pulse signal sequence output by the pulse signal frequency control method of this embodiment.
[0033]
This figure shows three periods theoretically derived by the prior art disclosed in Japanese Patent Laid-Open No. 2000-69776, that is, a frequency increase period, a constant frequency period, and a frequency decrease period. Note that the fixed frequency period is one or more cycles of the pulse signal.
[0034]
Further, as shown in FIGS. 9A to 9C, the frequency increase end time t1, which is the end of the frequency increase period, may not coincide with the pulse edge of the pulse signal. For this reason, in the pulse signal including the frequency increase end time t1, a period before the frequency increase end time t1 in the same pulse signal has a longer period corresponding to the frequency increase. The period after t1 is a part of the constant frequency period.
[0035]
Therefore, as shown in FIG. 5B, in the conventional technique, the frequency constant period is shortened by the period of the frequency constant period in the same pulse signal, and the frequency reduction start time, which is the start time of the frequency reduction period, is also reduced. This is faster than the theoretical pulse signal sequence (FIG. 5A) that should be output in accordance with preset conditions. Therefore, as already described, as a problem of the prior art, the frequency is reduced, that is, a pulse signal having a long cycle is output, and the end of the frequency reduction that is the end of the output of the pulse signal. Is delayed.
[0036]
On the other hand, the pulse signal sequence output by the pulse signal frequency control method of the present embodiment is further reduced from the start of frequency reduction set in advance by the conventional technique disclosed in Japanese Patent Application Laid-Open No. 2000-69976. As shown in FIG. 5B, correction is performed so that the actual frequency decrease start time t2 is obtained when a correction period TA consisting of a period of constant frequency has elapsed in the pulse signal including the frequency increase end time t1. is doing. Therefore, in the pulse signal frequency control method of the present embodiment, the actual frequency reduction start time t2 can be made constant, and the frequency reduction end time, which is the pulse signal output end time, is output in accordance with preset conditions. This agrees with the theoretical pulse signal train (FIG. 5A) that should be performed.
[0037]
In order to execute the frequency control method of the pulse signal, when the constant frequency period is longer than the pulse signal of one cycle, the period that is the constant frequency period in the pulse signal including the end t1 of the pulse frequency increase, that is, the correction period As a measuring means for measuring TA, a counter 7 is provided as shown in FIG.
[0038]
The counter 7 counts up from the time t1 when the frequency increase ends to the next rising pulse edge, starts counting down from the preset frequency decrease start time, and returns to “0” to start the actual frequency decrease. Time t2 is set. Note that the measuring means is not limited to a counter that counts up and down.
[0039]
By the way, according to the pulse signal control method of the present embodiment, the frequency increase period and the frequency decrease period of the pulse signal are symmetrical.
[0040]
In such a frequency control method of the pulse signal, when a correction period TA consisting of a period of a constant frequency has elapsed in the pulse signal including the frequency increase end time t1 from the preset frequency decrease start time. By executing the correction at the actual frequency decrease start time t2, the frequency decrease start time can be made constant, and thus the actual operation time can be made to coincide with the preset operation time. There is an effect.
[0041]
Next, a pulse signal frequency control method according to a second embodiment of the present invention will be described with reference to FIGS. Only differences from the pulse signal frequency control method of the first embodiment will be described. The method of the pulse signal of this embodiment is basically the same as the frequency control method of the pulse signal of the first embodiment, but the time t1 when the frequency increase ends is after the half cycle of the pulse signal or the half cycle has elapsed. When the preset frequency increase end time t1 is after a half cycle of the pulse signal, the correction period TA is changed to a pulse edge that is a boundary between the frequency increase end time t1 and the next pulse signal. When the frequency increase end time t1 is before the half cycle of the pulse signal, the correction period TA is changed from the frequency increase end time t1 to immediately after the frequency increase end time t1 and the pulse in the pulse signal. The period up to the edge is set to a period obtained by adding a half cycle of the pulse signal in the constant frequency period T1.
[0042]
5 (a) to 5 (c) and FIGS. 6 (a) to 6 (c) are similar to FIGS. 1 (a) to 1 (c), the theoretical pulse signal train and the conventional acceleration / deceleration control circuit. 2 shows a pulse signal sequence output by the frequency signal control method and a pulse signal sequence output by the frequency control method of the pulse signal of this embodiment.
[0043]
5 (d) and 6 (d) show that the pulse signal sequence shown in FIGS. 5 (a) to (c) and FIGS. 6 (a) to (c) is “H” at the end of frequency increase t2. ”Or“ L ”. In other words, since the pulse signal sequences shown in FIGS. 5A to 5C and FIGS. 6A to 6C are considered to start at the rising pulse edge, FIG. 5D and FIG. When the polarity determination signal shown in FIG. 6 (d) is “L”, it indicates that the frequency increase time t1 is after the half cycle of the pulse signal, and the polarity determination shown in FIGS. 5 (d) and 6 (d). When the signal is “H”, it indicates that the frequency increase time t1 is before the half cycle of the pulse signal. Note that the pulse signal train is not limited to one that starts with a rising pulse edge.
[0044]
Since the pulse signal sequence shown in FIGS. 5A to 5C is “L” at the end of the frequency increase, the polarity determination signal shown in FIG. 5D is also “L”. Thus, it can be recognized that the time t1 when the frequency increase ends is after the half cycle of the pulse signal has elapsed. Based on this recognition, the correction period TA is set to a period from the time t1 when the frequency increase ends to the pulse edge that is the boundary with the next pulse signal. Then, the correction is performed such that the time when the correction period TA has elapsed from the preset frequency decrease start time is set to the actual frequency decrease start time t2.
[0045]
On the other hand, since the pulse signal sequence shown in FIGS. 6A to 6C is “H” at the time t1 when the frequency increase ends, the polarity determination signal shown in FIG. It can be recognized that the time t1 when the frequency increase ends is before the half cycle of the pulse signal. Based on this recognition, the correction period TA is set to a period obtained by adding a half cycle in a constant frequency period to the period from the end of frequency increase t1 to the pulse edge which is the boundary with the next pulse signal. Then, the correction is performed such that the time when the correction period TA has elapsed from the preset frequency decrease start time is set to the actual frequency decrease start time t2.
[0046]
By the way, according to the pulse signal control method of the present embodiment, the frequency increase period and the frequency decrease period of the pulse signal are symmetric as in the case of the pulse signal control method of the first embodiment.
[0047]
In such a pulse signal frequency control method, in addition to the effect of the pulse signal frequency control method of the first embodiment, when the frequency increase end time t1 is before the half cycle of the pulse signal, the correction period TA is set. A period in which a half period of a known pulse signal is added to a period from the end of frequency increase t1 to the pulse edge immediately after the end of frequency increase t1, and the frequency in the pulse signal including the end of frequency increase t1 Since it is not the period from the end t1 of the increase to the pulse edge that is the boundary with the next pulse signal, when measuring the period of the frequency constant in the pulse signal including the end t1 of the frequency increase, A measurement period can be made into a half cycle or less.
[0048]
Next, a frequency control method for a pulse signal according to a third embodiment of the present invention will be described with reference to FIG. Only the differences from the pulse signal frequency control method of the second embodiment will be described. The frequency control method of the pulse signal of the present embodiment is basically the same as the frequency control method of the pulse signal of the second embodiment, but the frequency value of the pulse signal at the end of frequency increase t1 is stored and stored. The frequency of the pulse signal is decreased from the measured frequency value toward the starting value. That is, the configuration (pulse signal frequency control circuit) that executes the frequency control method of the pulse signal of the present embodiment includes the dedicated register 8 as a storage unit that stores the frequency value of the pulse signal at the time t1 when the frequency increase ends. Yes.
[0049]
The configuration for executing the pulse signal frequency control method of the present embodiment is similar to the configuration for executing the pulse signal frequency control method of the first embodiment, and the pulse signal output circuit shown in FIG. Have. Since this type of pulse signal output circuit has an adder circuit 2 capable of sequentially adding frequency values, the flip-flop 3 of this pulse signal output circuit has an internal value and frequency during the frequency increase period. The internal value will be different during the decrease period.
[0050]
However, in the configuration for executing the pulse signal frequency control method of this embodiment, the dedicated register 8 stores the frequency value of the pulse signal at the time t1 when the frequency increase ends, and the actual frequency decrease after the correction is executed. At the start time t2, the frequency value stored in the dedicated register 4 is written back to the flip-flop 3, so that the internal value during the frequency increase period and the internal value during the frequency decrease period can be made the same. As a result, in the configuration for executing the frequency control method of the pulse signal of the present embodiment, the frequency of the pulse signal can be decreased from the frequency value of the pulse signal at the end of frequency increase t1 toward the starting value. is there.
[0051]
In addition, the configuration for executing the frequency control method of the pulse signal of the present embodiment needs to invert the output polarity of the pulse signal from the flip-flop 3 after the start of the frequency reduction, so that the well-known output inversion having an inverter A circuit (not shown) is provided after the flip-flop 3.
[0052]
By the way, according to the pulse signal control method of the present embodiment, the frequency increase period and the frequency decrease period of the pulse signal are symmetric as in the case of the pulse signal control method of the first embodiment.
[0053]
In this pulse signal frequency control method, in addition to the effect of the pulse signal frequency control method of the first embodiment, the frequency value of the pulse signal at the end of frequency increase t1 is stored, and from the stored frequency value Since the frequency of the pulse signal is decreased toward the starting value, the frequency of the pulse signal can be decreased to the same degree as the increase when the frequency of the pulse signal is increased.
[0054]
Next, a pulse signal frequency control method according to a fourth embodiment of the present invention will be described with reference to FIG. Only differences from the pulse signal frequency control method of the first embodiment will be described. The frequency control method of the pulse signal according to the first embodiment is a method applied when the fixed frequency period is one period or more of the pulse signal. The correction period TA described above is further applied from the preset frequency reduction start time. The correction of the actual frequency decrease start time t2 is executed when the time elapses, while the pulse signal frequency control method of the present embodiment is applied when the fixed frequency period is less than one cycle of the pulse signal. In this method, when the above-described correction period TA has further elapsed from the pulse edge immediately after the frequency increase end time t1 in the pulse signal including the frequency increase end time t1, the correction is performed so that the actual frequency decrease start time t2 is reached. To do.
[0055]
FIGS. 7A and 7B respectively show a pulse signal sequence output by the conventional acceleration / deceleration control circuit and a pulse signal sequence output by the pulse signal frequency control method of the present embodiment. .
[0056]
In order to execute the frequency control method of the pulse signal, a second period is measured when the constant frequency period is less than one period of the pulse signal in the pulse signal including the frequency increase end time t1. As the measurement means, a second counter similar to the measurement means described above is provided.
[0057]
This second measuring means measures the period of the pulse signal including the frequency increase end time t1, which is a constant frequency period, when the constant frequency period is less than one cycle of the pulse signal. The pulse signal including the time t1 does not operate at the same time as the measurement unit that measures the period of the fixed frequency period when the fixed frequency period is one cycle or more of the pulse signal.
[0058]
Accordingly, both the second measuring means and the above-described measuring means are provided, and the frequency increase end time t1 is included regardless of whether the frequency constant period is one cycle or more and less than one cycle of the pulse signal. When the pulse signal is configured to measure a period with a constant frequency, as shown in FIG. 9, the counter 7 as the measuring means and the second counter 9 as the second measuring means may be shared. In that case, the number of parts can be reduced and the mounting area of the parts can also be reduced.
[0059]
By the way, according to the pulse signal control method of the present embodiment, the frequency increase period and the frequency decrease period of the pulse signal are symmetric as in the case of the pulse signal control method of the first embodiment.
[0060]
In such a frequency control method of the pulse signal, when the frequency constant period is less than one cycle of the pulse signal, the pulse signal further includes a pulse edge immediately after the frequency increase end time t1 in the pulse signal including the frequency increase end time t1. By executing a correction that makes the frequency reduction start time t2 when the correction period TA has elapsed, the frequency reduction start time can be made constant, so that the actual operation time matches the preset operation time. The effect that it can be made can be produced.
[0061]
In the configuration for executing the pulse signal frequency control method of the present embodiment, a dedicated register 4 is provided as a storage means for storing the frequency value of the pulse signal at the end of frequency increase t1 for decreasing the frequency of the pulse signal, As in the pulse signal frequency control method of the third embodiment, the frequency value of the pulse signal at the end of frequency increase t1 is stored, and the frequency of the pulse signal is decreased from the stored frequency value toward the starting value. The frequency value of the pulse signal at the end of the frequency increase t1 may be stored. At that time, the frequency of the pulse signal is set to the same level as the increase in the frequency of the pulse signal. Can be reduced.
[0062]
Next, a frequency control method for a pulse signal according to a fifth embodiment of the present invention will be described with reference to FIG. Only differences from the pulse signal frequency control method of the fourth embodiment will be described. The frequency control method of the pulse signal of this embodiment is basically the same as the frequency control method of the pulse signal of the third embodiment, but the pulse signal is the first pulse edge as shown in FIG. In the case of having a preparation period TB less than half a cycle before, after returning to the starting value, the output of the pulse signal is regulated after the half cycle of the pulse signal has elapsed, as shown in FIG. I am doing so.
[0063]
Note that the case where the pulse signal has a preparatory period TB of less than a half cycle before the first pulse edge means, for example, that the drive is performed with the first rising pulse edge when performing rotation control of a stepping motor, servometer, or the like. As described above, this indicates a case where the preparation period TB is less than a half cycle before the first pulse edge.
[0064]
Specifically, among the preset number of pulse signals, the mask signal becomes “H” as shown in FIG. In the section where the mask signal is “H”, the output of the pulse signal is restricted, and the frequency increase period and the frequency decrease period of the pulse signal are not symmetrical.
[0065]
According to such a pulse signal control method, in addition to the effect of the pulse signal frequency control method of the fourth embodiment, when the pulse signal has a preparatory period TB of less than a half cycle before the first pulse edge, it is activated. Since the output of the pulse signal is regulated after the half cycle of the pulse signal has elapsed after returning to the value, it is not necessary to output an unnecessary pulse signal corresponding to the preparation period TB.
[0066]
【The invention's effect】
  According to the frequency control method of the pulse signal according to claim 1,When the frequency fixed period is one cycle or more of the pulse signal, the time when the correction period has passed since the start of the frequency decrease set based on the number of pulse signals at the time of the frequency increase is the time when the actual frequency decrease starts. By executing the correction to perform, it is possible to make the frequency reduction start time constant, so that the actual operation time isIt is possible to match the preset operation time.
[0067]
  According to the pulse signal frequency control method of claim 2.When the fixed frequency period is less than one cycle of the pulse signal, the time when the correction period elapses from the pulse edge immediately after the end of the frequency increase in the pulse signal including the end of the frequency increase is the start time of the frequency decrease. By executing the correction, the start of the circumferential frequency reduction can be made constant,Therefore, the actual operation time can be matched with the preset operation time..
[0068]
  According to the frequency control method of a pulse signal according to claim 3,Claim 1In addition to the effects of the frequency control method of the pulse signal described above, when the end of the frequency increase is before the half cycle of the pulse signal, the correction period is set from the end of the frequency increase to the pulse edge immediately after the end of the frequency increase. The period is a period obtained by adding a half cycle of a known pulse signal to the period from the end of the frequency increase to the pulse edge that is the boundary with the next pulse signal, including the end of the frequency increase. Therefore, when measuring a period of a constant frequency in a pulse signal including the end of frequency increase, the measurement period can be set to a half cycle or less.
[0070]
  Claim 4According to the frequency control method of the described pulse signal,Claims 1 to 3In addition to the effect of the frequency control method for the pulse signal described in any of the above, the frequency value of the pulse signal at the end of the frequency increase is stored, and the frequency of the pulse signal is decreased from the stored frequency value toward the starting value. Therefore, the frequency of the pulse signal can be reduced to the same extent as the increase in the frequency of the pulse signal.
[0071]
  Claim 5According to the frequency control method of the described pulse signal,Claims 1 to 3In addition to the effect of the frequency control method of the pulse signal described in any of the above, when the pulse signal has a preparatory period of less than a half cycle before the first pulse edge, the pulse signal half Since the output of the pulse signal is regulated after the elapse of the cycle, it is not necessary to output an unnecessary pulse signal corresponding to the preparation period.
[0072]
  Claim 6The frequency control circuit for a pulse signal described above uses a measuring means to measure a correction period consisting of a period of a constant frequency in a pulse signal including the end of frequency increase when the constant frequency period is one cycle or more of the pulse signal. When the fixed frequency period is one cycle or more of the pulse signal, the time when the correction period elapses after the start of the frequency decrease set based on the number of pulse signals at the time of the frequency increase is set as the frequency decrease start time. Since the correction is executed, the frequency reduction start time is constant, and the actual operation time can be matched with the preset operation time.
[0073]
  Claim 7The frequency control circuit of the described pulse signal isClaim 6In addition to the effect of the frequency control circuit for the pulse signal described above, when the fixed frequency period is less than one cycle of the pulse signal, the correction period is measured by the second measuring means, and the fixed frequency period is one cycle of the pulse signal. In the case where the frequency decrease is less than the frequency edge, the correction at the start of the frequency decrease is executed after the correction period has passed since the pulse edge immediately after the end of the frequency increase.BecomeThe actual operation time can be matched with a preset operation time.Claim 8The frequency control circuit of the described pulse signal isClaim 7In addition to the effect of the frequency control circuit for the pulse signal described, the measuring means is used as the second measuring means, so that it is not necessary to provide two measuring means.
[Brief description of the drawings]
FIG. 1 is a pulse signal sequence output by a pulse signal frequency control circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a pulse signal output circuit having the same as above.
FIG. 3 is a block diagram of the internal configuration of the above.
FIG. 4 is a block diagram of a deceleration point detection unit included in the above.
FIG. 5 is a pulse signal train output when the end of frequency increase is before the half cycle of the pulse signal has elapsed by the pulse signal frequency control circuit of the second embodiment of the present invention.
FIG. 6 is a pulse signal sequence output when the end of the frequency increase is after a half period of the pulse signal has elapsed by the pulse signal frequency control circuit described above.
FIG. 7 is an operation explanatory diagram of a frequency control circuit for a pulse signal according to a third embodiment of the present invention.
FIG. 8 is a pulse signal train output by a pulse signal frequency control circuit according to a fourth embodiment of the present invention.
FIG. 9 is a block diagram of an internal configuration when a counter as a measurement unit and a second counter as a second measurement unit are shared.
FIG. 10 is a pulse signal string output by a pulse signal frequency control circuit according to a fifth embodiment of the present invention.
FIG. 11 is a block diagram of a pulse signal output circuit disclosed in Japanese Patent Laid-Open No. 10-215167.
FIG. 12 is an explanatory diagram of rotation control of a pulse drive type motor using the circuit described above.
FIG. 13 is a block diagram of an acceleration / deceleration control circuit disclosed in Japanese Patent Application Laid-Open No. 2000-69776.
FIG. 14 is a block diagram of a deceleration point detection unit included in the above.
FIG. 15 is an explanatory diagram of rotation control of a pulse drive type motor using the circuit described above.
FIG. 16 is an explanatory diagram showing that a preset acceleration end timing does not coincide with an actual acceleration end timing.
FIG. 17 is an explanatory diagram showing linear interpolation that is driven independently in each of the X-axis direction and the Y-axis direction.
FIG. 18 is an explanatory diagram showing an ideal case where the end of operation in the X-axis direction matches the end of operation in the Y-axis direction.
FIG. 19 is an explanatory diagram showing that the end of operation in the X-axis direction and the end of operation in the Y-axis direction do not match.
[Explanation of symbols]
Counter 7
Dedicated register (memory means) 8
Second counter 9
Correction period TA
Preparation period TB
At the end of frequency increase t1
When frequency actually decreases t2

Claims (8)

The starting value and a target value higher than the starting value are preset, and the frequency of the pulse signal is increased from the starting value toward the target value until the preset frequency increase ends, and at least one cycle of the pulse signal Or a frequency control method for a pulse signal that is reduced to a starting value and restored after a certain frequency period less than one period has elapsed, and the frequency is determined when the certain frequency period is one period or more of the pulse signal. Based on a correction period consisting of a period of a constant frequency in the pulse signal including the end of the increase, a correction is made so that the frequency decrease start time is when the correction period has further passed from a preset frequency decrease start time. A frequency control method for a pulse signal, which is executed . The starting value and a target value higher than the starting value are preset, and the frequency of the pulse signal is increased from the starting value toward the target value until the preset frequency increase ends, and at least one cycle of the pulse signal Or a frequency control method for a pulse signal that is reduced to a starting value and returned after a certain frequency period less than one period has elapsed, and the frequency is determined when the certain frequency period is less than one period of the pulse signal. Based on a correction period consisting of a period with a constant frequency in the pulse signal including the end of the increase, the correction period further elapses from the pulse edge immediately after the end of the frequency increase in the pulse signal including the end of the frequency increase. A frequency control method for a pulse signal, wherein correction is performed so that the frequency reduction starts at the start of the frequency reduction . It is determined whether the end of the frequency increase is after a half cycle of the pulse signal or before the half cycle has elapsed, and when the end of the frequency increase is after the half cycle of the pulse signal has elapsed, the correction period is set to the frequency In the pulse signal including the end of the increase, the period from the end of the frequency increase to the pulse edge that is the boundary with the next pulse signal, and when the end of the frequency increase is before the half cycle of the pulse signal, the correction 2. The frequency of the pulse signal according to claim 1, wherein the period is a period obtained by adding a half cycle of the pulse signal to a period from the end of the frequency increase to immediately after the end of the frequency increase and to the pulse edge in the pulse signal. Control method. Storing the frequency value of the pulse signal when the frequency increases ends, toward the frequency value thereof stored to the starting value, according to any one of claims 1 to 3 to reduce the frequency of the pulse signal Pulse signal frequency control method. When the pulse signal has a preparation period of less than a half cycle before the first pulse edge, the claims from after a half period of said pulse signal has returned to the starting value, to regulate the output of the pulse signal The frequency control method of the pulse signal in any one of Claim 1 thru | or 3 .   The start value and a target value higher than the start value are preset, and the frequency of the pulse signal is increased from the start value toward the target value until the preset frequency increase ends, and at least one cycle of the pulse signal Or a frequency control circuit for a pulse signal that is reduced to a starting value and restored after a certain frequency period of less than one cycle has elapsed, and the frequency increases when the certain frequency period is one period or more of the pulse signal. Provided with a measuring means for measuring a correction period consisting of a period of a constant frequency in the pulse signal including the end time, and when the frequency constant period is more than one period of the pulse signal, a preset frequency reduction start time Further, the frequency control circuit for the pulse signal is characterized in that the correction is performed so that the frequency reduction starts when the correction period elapses. A second measuring means for measuring the correction period when the fixed frequency period is less than one cycle of the pulse signal; and when the frequency increase ends when the fixed frequency period is less than one cycle of the pulse signal. 7. The frequency control circuit for a pulse signal according to claim 6 , wherein correction is performed such that the time when the correction period elapses from the immediately following pulse edge is the start of frequency reduction. 8. A frequency control circuit for a pulse signal according to claim 7 , wherein the measuring means is used as the second measuring means.

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