JPS626880Y2 - - Google Patents

Description

[Detailed description of the invention] The invention is based on a microprocessor (in the specification).
It is called CPU. ) for controlling pulse oscillation for controlling a pulse motor driver.

Figure 1 is a circuit diagram of a conventional example, where 1' is the CPU, 2'
is a timer LSI. Timer LSI2' is a CPU
This is a dedicated LSI that can generate or stop pulses of a specified frequency by applying data from 1'. First, when data is input to timer LSI 2' to generate pulses with a specified frequency that changes from time to time or a constant value from CPU 1', timer LSI 2' responds to the pulse 3' (pulse 3') with a specified frequency according to the CPU data. (hereinafter referred to as generated pulse).
will occur. Next, the timer LSI
The CPU 1' counts the number of generated pulses 3' generated from the pulse 2', and when a predetermined number of pulses is reached, the timer LSI 2' stops generating pulses. This allows generation of a specified number of pulses and control of frequency changes. Now, what has been a problem in the past is that in order to generate the specified number of pulses from timer LSI 2', the CPU
1' must always count the pulses 3' generated by the timer LSI 2'. However, the CPU 1' itself is operated by the reference clock 4' with a certain fixed frequency T, and therefore the minimum frequency at which to count the generated pulses 3' is fixed, and the pulses 3' that have a frequency T shorter than that of the reference clock 4' are determined. Pulse 3' cannot be counted. This relationship is shown in FIG. Here, as shown in Figure 2 a,
The state of the generated pulse 3' is checked by reading by the CPU 1'. For example, when the generated pulse 3' shifts from the H state to the L state, the reference clock 4'
Since the generated pulse 3' has a longer period, it can be counted accurately, but if the generated pulse 3' has a shorter period than the reference clock 4', as shown in b in the same figure, it cannot be counted accurately. . next,
The necessity of counting pulses in CPU 1' will be explained. When driving the pulse motor 5' while controlling its speed and stop position using a motor driver, as shown in Fig. 3, at time T ₀ and frequency ₀ ,
Start pulse oscillation with . Then, the frequency of the generated pulse 3' is linearly increased and accelerated until time _T1 , and the maximum speed is reached at time _T1 . Next, this speed is maintained until time T ₂ , and the frequency is linearly lowered from time T ₂ to time T ₃ to reduce the speed. At time T ₃ , the oscillation of timer LSI 2' is stopped and the target position is accurately reached. To stop the pulse motor 5', the total number of pulses output from time T ₀ to T ₃ must match the target number of pulses. While 3' is occurring, the number must be constantly counted and confirmed. And this work is done by CPU
1' must be performed directly.

In controlling such a pulse motor drive,
In the conventional method where the CPU 1' counts the generated pulses 3' one by one, as mentioned above, if the frequency of the generated pulses 3' becomes higher than the frequency of the reference clock 4', the number of pulses is counted. This will result in overrunning the stop position. Therefore, if the stopping position is to be made accurate, the maximum speed of the pulse motor 5' will be limited to the frequency T of the reference clock 4', making it impossible to increase the speed of the pulse motor drive.

The present invention was developed in view of the drawbacks of the conventional example, and its purpose is to count the generated pulses in groups of 2 ⁿ (n = integer) at high frequencies, and to An object of the present invention is to provide a pulse oscillation circuit for controlling a pulse motor that can count generated pulses no matter how high their frequency is by performing correction in .

The present invention will be described in detail below with reference to illustrated embodiments.
In FIG. 4, 1 is a CPU, 2 is a timer LSI, and 6 is a frequency dividing circuit. First, the CPU 1 inputs data to the timer LSI 2 so as to generate a pulse of a specified frequency. In response to this, timer LSI 2 changes the frequency of generated pulse 3 between times T ₀ and _{T 1} as shown in Figure 3.
The frequency is increased continuously from ₀ to ₁ , the frequency is held at ₁ from time T ₁ to T ₂ , and the frequency is continuously decreased from ₁ to ₀ from time T ₂ to _{T 3} . In FIG. 3, it becomes impossible to count the generated pulses 3 when the frequency T of the reference clock 4 is exceeded. Therefore, as a method of counting generated pulse 3,
As shown in FIG. 4, the frequency dividing line 6 of the frequency dividing circuit 6
a, 6b, 6c and CPU1 selection lines 1a, 1
By doing an AND with b and 1c, the frequency-divided pulse 7 having the optimum frequency for the generated pulse 3 is selected and input to the CPU 1. That is, the frequency of the generated pulse 3 is equal to 2 of the frequency T of the reference clock 4 in FIG.
The frequency of the time-divided pulse 7, which increases by 2 times, 4 times, and 8 times, is converted to 2 ⁿ (n = integer) frequency by dividing by 2, 4, and 8. I'm going. Such a selection must be programmed into CPU1 in advance. Now,
Immediately before the pulse motor 5 stops, if there is a difference between the sum of the generated pulses 3 indirectly counted by the frequency divided pulse 7 and the predetermined number of pulses to be generated by the timer LSI 2, only that difference occurs. The correction pulse 8 is output, and the pulse motor 5 is activated by matching the two pulses.
stop accurately. Note that the frequency-divided pulse 7a may be programmed so that the generated pulse 3 exceeds the frequency T of the reference clock 4, but the frequency-divided pulse 7a can be used from the beginning to generate the generated pulse 3. It is also possible to count the number and output the correction pulse 8 at the end. In addition,
In this example, only up to 8 frequency divisions are described, but of course the number is not limited to this, and 2 ⁿ frequency divisions (n >
(an integer of 3 or more) can be adopted.

As mentioned above, this invention provides a frequency divider circuit controlled by the CPU, and selects the frequency divider circuit with the optimum frequency for the generated pulses generated by the timer LSI.
Since the input is made to the CPU, even if the generated pulses are generated at a higher frequency than the CPU's reference clock, the number of generated pulses can be accurately counted, and the accurate stop position can be maintained. It has become possible to drive a pulse motor at a high frequency (in other words, at high speed), which was previously impossible to achieve.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional pulse oscillation circuit, Figures 2a and b are comparison diagrams showing the relationship between generated pulses and the CPU reference clock, and Figure 3 is a time-frequency relationship diagram in pulse motor drive. FIG. 4 is a block circuit diagram of the present invention, and FIG. 5 is a pulse frequency comparison diagram, where 1 is a CPU, 2 is a timer LSI, 6 is a frequency dividing circuit, 3 is a generated pulse, and 7 is a frequency divided pulse.

Claims (1)

[Scope of utility model registration request] A timer LSI for controlling the pulse motor drive circuit whose number of generated pulses and changes in frequency are controlled by the CPU, and a timer LSI that receives input of the pulses generated from the timer LSI and provides the optimal frequency-divided pulse for the generated pulses according to instructions from the CPU. occurs and the CPU
A CPU that counts the number of pulses generated by the timer LSI by counting the number of divided pulses, and controls the number of pulses generated by the timer LSI and frequency changes. Pulse oscillation circuit for pulse motor control.