JP3827314B2 - Inductive device manufacturing method - Google Patents

Inductive device manufacturing method Download PDF

Info

Publication number
JP3827314B2
JP3827314B2 JP2003406831A JP2003406831A JP3827314B2 JP 3827314 B2 JP3827314 B2 JP 3827314B2 JP 2003406831 A JP2003406831 A JP 2003406831A JP 2003406831 A JP2003406831 A JP 2003406831A JP 3827314 B2 JP3827314 B2 JP 3827314B2
Authority
JP
Japan
Prior art keywords
conductor pattern
strip
shaped conductor
laminated
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003406831A
Other languages
Japanese (ja)
Other versions
JP2004304157A (en
Inventor
稔 高谷
隆 楫野
恒 小更
正美 佐々木
和彦 伊藤
敏一 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP2003406831A priority Critical patent/JP3827314B2/en
Priority to US10/799,717 priority patent/US7167071B2/en
Priority to KR1020040017295A priority patent/KR100739889B1/en
Priority to EP04006266A priority patent/EP1460654B1/en
Priority to CNB2004100397915A priority patent/CN1277280C/en
Publication of JP2004304157A publication Critical patent/JP2004304157A/en
Application granted granted Critical
Publication of JP3827314B2 publication Critical patent/JP3827314B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04BMECHANICALLY-DRIVEN CLOCKS OR WATCHES; MECHANICAL PARTS OF CLOCKS OR WATCHES IN GENERAL; TIME PIECES USING THE POSITION OF THE SUN, MOON OR STARS
    • G04B19/00Indicating the time by visual means
    • G04B19/06Dials
    • G04B19/16Shiftable dials, e.g. indicating alternately from 1 to 12 and from 13 to 24
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H01F41/041Printed circuit coils
    • H01F41/046Printed circuit coils structurally combined with ferromagnetic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F17/0013Printed inductances with stacked layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F17/0033Printed inductances with the coil helically wound around a magnetic core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F5/00Coils
    • H01F5/06Insulation of windings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/4902Electromagnet, transformer or inductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Manufacturing Cores, Coils, And Magnets (AREA)

Description

本発明は、コイル、トランス、コモンモードチョークコイル等の磁気誘導現象を利用したインダクティブデバイスの製造方法に係り、とくに高性能、狭公差の素子を量産性良く作成出来るインダクティブデバイスの製造方法に関する。 The present invention, coils, transformers, the method for manufacturing an inductive device using a magnetic induction phenomenon such as common mode choke coils, in particular high performance, a manufacturing method of inductive devices the elements of narrow tolerance good mass productivity can be created.

従来、この種のインダクティブデバイスの製法として、大別して下記の工法が挙げられる。
(1)巻線工法
磁性又は非磁性コアに線材を巻回するものであり、最も一般的な工法である。
(2)ビルドアップで形成する方法
下記特許文献1で示すように、ヘリカルの一部を成すコイル導体を形成した絶縁基板と絶縁層とを交互に積層してヘリカルコイルを形成するものである。
(3)本出願人提案の下記特許文献2(未公開であり、公知技術ではない)の方法
Conventionally, as a method for producing this type of inductive device, the following methods are roughly classified.
(1) Winding method A wire is wound around a magnetic or nonmagnetic core, and is the most common method.
(2) Method of forming by build-up As shown in Patent Document 1 below, a helical coil is formed by alternately laminating an insulating substrate and an insulating layer on which a coil conductor forming a part of a helical is formed.
(3) Method of the following patent document 2 (unpublished and not a known technique) proposed by the present applicant

特開2002−134321号公報JP 2002-134321 A 特願2002−262372号Japanese Patent Application No. 2002-262372

上記工法にはそれぞれ以下の問題点がある。
(1)巻線工法
a. コイルとしての性能は良いが、公差が大きくなる不具合な傾向がある。
b. 巻線作業が必要であり、量産性に乏しく、コスト高になる。
(2)ビルドアップで形成する方法
a. 巻数が増える場合、積層数が多くなることに起因して公差が大きくなる。
b. 巻数が増える場合、積層数が多くなり、量産性が低下する。
(3)本出願人提案の特許文献2の方法
製造過程で集合基板を用いるが、この場合、下記の問題点がある。
a. コア基板及び絶縁層の厚さがばらつき、集合基板における素子配列のX方向及びY方向ピッチが一定にならない。
b. これにより歩留まりの低下(コイル導体同士がうまく接続されないことに起因するオープン不良)及びコイル内径のばらつきに起因するインダクタンス値のばらつきが発生する。
c. コア基板及び/又は絶縁層が有機材料の場合は上記の問題が特に顕著であり、また新にそり及び割れの問題が発生する。
d. コア基板両面の帯状導体間の裏表のアライメントが困難であり、歩留まりの低下、またインダクタンス公差の増大を来す。
Each of the above methods has the following problems.
(1) Winding method a. Although the performance as a coil is good, there is a tendency that the tolerance increases.
b. Winding work is required, resulting in poor mass production and high cost.
(2) Method of forming by build-up a. When the number of turns increases, the tolerance increases due to the increase in the number of layers.
b. When the number of windings increases, the number of stacked layers increases and mass productivity decreases.
(3) Method of Patent Document 2 proposed by the applicant The collective substrate is used in the manufacturing process, but in this case, there are the following problems.
a. The thicknesses of the core substrate and the insulating layer vary, and the pitches in the X direction and Y direction of the element arrangement on the collective substrate are not constant.
b. This causes a decrease in yield (open failure due to poor connection between coil conductors) and a variation in inductance value due to a variation in coil inner diameter.
c. In the case where the core substrate and / or the insulating layer is an organic material, the above problem is particularly remarkable, and new problems of warpage and cracking occur.
d. It is difficult to align the front and back between the strip conductors on both sides of the core substrate, resulting in a decrease in yield and an increase in inductance tolerance.

本発明は、上記の点に鑑み、高性能、狭公差のインダクティブデバイスを提供することを第1の目的とするとともに、そのインダクティブデバイスを高い歩留まりで量産性良く作製出来るインダクティブデバイスの製造方法を提供することを第2の目的とするものである。   In view of the above points, the present invention has a first object to provide an inductive device with high performance and narrow tolerance, and also provides a method for manufacturing an inductive device capable of producing the inductive device with high yield and high productivity. This is the second purpose.

本発明のその他の目的や新規な特徴は後述の実施の形態において明らかにする。   Other objects and novel features of the present invention will be clarified in embodiments described later.

上記目的を達成するために、本願請求項1の発明に係るインダクティブデバイスの製造方法は、芯材を有する有機コア基板の表裏面に複数の帯状導体パターンを形成し、これをプリプレグ又は接着シートの絶縁層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴としている。
In order to achieve the above object, an inductive device manufacturing method according to the invention of claim 1 of the present invention forms a plurality of strip-like conductor patterns on the front and back surfaces of an organic core substrate having a core material, which is formed on a prepreg or an adhesive sheet. A laminating process in which a plurality of sheets are pressed and integrated through an insulating layer;
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the multilayer slice into individual chips so as to have at least one helical coil composed of the strip-like conductor pattern and the bridged conductor pattern .

本願請求項の発明に係るインダクティブデバイスの製造方法は、芯材を有する有機コア基板の表裏面に複数の帯状導体パターン及び該複数の帯状導体パターンを覆う絶縁層を形成し、これを接着層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴としている。
In the inductive device manufacturing method according to the second aspect of the present invention, a plurality of strip-shaped conductor patterns and an insulating layer covering the plurality of strip-shaped conductor patterns are formed on the front and back surfaces of an organic core substrate having a core material, and the adhesive layer is formed. A stacking process in which a plurality of sheets are pressed and integrated through
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the multilayer slice into individual chips so as to have at least one helical coil composed of the strip-like conductor pattern and the bridged conductor pattern.

本願請求項の発明に係るインダクティブデバイスの製造方法は、芯材を有する有機コア基板の片面に複数の帯状導体パターンを形成し、これをプリプレグ又は接着シートの絶縁層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴としている。
In the inductive device manufacturing method according to claim 3 of the present application, a plurality of strip-like conductor patterns are formed on one side of an organic core substrate having a core material, and a plurality of these are laminated via an insulating layer of a prepreg or an adhesive sheet. A laminating process for pressing and integrating;
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the multilayer slice into individual chips so as to have at least one helical coil composed of the strip-like conductor pattern and the bridged conductor pattern.

本願請求項の発明に係るインダクティブデバイスの製造方法は、芯材を有する有機コア基板の片面に複数の帯状導体パターン及び該帯状導体パターンを覆う絶縁層を形成し、これを接着層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴としている。
In the inductive device manufacturing method according to claim 4 of the present application, a plurality of strip-shaped conductor patterns and an insulating layer covering the strip-shaped conductor patterns are formed on one surface of an organic core substrate having a core material. A lamination process in which a plurality of sheets are stacked and pressed to be integrated;
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the multilayer slice into individual chips so as to have at least one helical coil composed of the strip-like conductor pattern and the bridged conductor pattern.

本願請求項の発明に係るインダクティブデバイスの製造方法は、請求項2,3又は4において、前記絶縁層を研磨処理して厚さを調整することを特徴としている。 The inductive device manufacturing method according to claim 5 of the present invention is characterized in that, in claim 2, 3 or 4 , the insulating layer is polished to adjust the thickness.

本願請求項の発明に係るインダクティブデバイスの製造方法は、請求項3又は4において、前記芯材を有する有機コア基板の前記帯状導体パターンの無い面を研磨処理して厚さを調整することを特徴としている。 The method for manufacturing an inductive device according to the invention of claim 6 is characterized in that, in claim 3 or 4 , the thickness of the organic core substrate having the core material is adjusted by polishing the surface without the strip-like conductor pattern. It is a feature.

本願請求項の発明に係るインダクティブデバイスの製造方法は、請求項1,2,3,4,5又は6において、前記スライス工程の後、スライス面を研磨処理して厚さを調整することを特徴としている。 The inductive device manufacturing method according to the invention of claim 7 is the method of claim 1, 2 , 3, 4, 5 or 6 , wherein after the slicing step, the slice surface is polished to adjust the thickness. It is a feature.

本願請求項の発明に係るインダクティブデバイスの製造方法は、請求項1,2,3,4,5,6又は7において、前記芯材を有する有機コア基板は、前記帯状導体パターンが転写されて設けられていることを特徴としている。 The inductive device manufacturing method according to claim 8 of the present application is the method according to claim 1, 2 , 3, 4, 5, 6 or 7 , wherein the organic conductor substrate having the core material is transferred with the strip-shaped conductor pattern. It is characterized by being provided.

本願請求項の発明に係るインダクティブデバイスの製造方法は、表裏面に複数の帯状導体パターンを形成した無機焼結体コア基板を、プリプレグ又は接着シートの絶縁層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴としている。
In the inductive device manufacturing method according to the invention of claim 9 of the present application, a plurality of inorganic sintered core substrates each having a plurality of strip-like conductor patterns formed on the front and back surfaces are stacked and pressed through an insulating layer of a prepreg or an adhesive sheet. Integrated lamination process;
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the multilayer slice into individual chips so as to have at least one helical coil composed of the strip-like conductor pattern and the bridged conductor pattern.

本願請求項10の発明に係るインダクティブデバイスの製造方法は、表裏面に複数の帯状導体パターンを形成した無機焼結体コア基板の前記表裏面に前記複数の帯状導体パターンを覆う絶縁層を形成し、これを、接着層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴としている。
In the inductive device manufacturing method according to the invention of claim 10 of the present application, an insulating layer covering the plurality of strip-shaped conductor patterns is formed on the front and back surfaces of the inorganic sintered body core substrate in which a plurality of strip-shaped conductor patterns are formed on the front and back surfaces. , A laminating step in which a plurality of sheets are pressed and integrated through an adhesive layer,
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the multilayer slice into individual chips so as to have at least one helical coil composed of the strip-like conductor pattern and the bridged conductor pattern.

本願請求項11の発明に係るインダクティブデバイスの製造方法は、片面に複数の帯状導体パターンを形成した無機焼結体コア基板を、プリプレグ又は接着シートの絶縁層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴としている。
In the inductive device manufacturing method according to the invention of claim 11 of the present application, a plurality of inorganic sintered core substrates each having a plurality of strip-like conductor patterns formed on one side are pressed and laminated together via an insulating layer of a prepreg or an adhesive sheet. Laminating process
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the multilayer slice into individual chips so as to have at least one helical coil composed of the strip-like conductor pattern and the bridged conductor pattern.

本願請求項12の発明に係るインダクティブデバイスの製造方法は、片面に複数の帯状導体パターンを形成した無機焼結体コア基板の前記片面に前記複数の帯状導体パターンを覆う絶縁層を形成し、これを、接着層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴としている。
In the inductive device manufacturing method according to the invention of claim 12 of the present application, an insulating layer that covers the plurality of strip-shaped conductor patterns is formed on the one surface of the inorganic sintered body core substrate in which the plurality of strip-shaped conductor patterns are formed on one surface. A stacking process in which a plurality of sheets are pressed and integrated through an adhesive layer,
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the multilayer slice into individual chips so as to have at least one helical coil composed of the strip-like conductor pattern and the bridged conductor pattern.

本願請求項13の発明に係るインダクティブデバイスの製造方法は、芯材を有する有機コア基板の表裏面に複数の帯状導体パターンを形成したものと、無機焼結体コア基板とを接着性絶縁層を介して交互に複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴としている。
In the inductive device manufacturing method according to the invention of claim 13 of the present invention, an adhesive insulating layer is formed by bonding a plurality of strip-shaped conductor patterns on the front and back surfaces of an organic core substrate having a core material and an inorganic sintered body core substrate. A stacking process in which a plurality of sheets are alternately stacked and pressed and integrated,
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the multilayer slice into individual chips so as to have at least one helical coil composed of the strip-like conductor pattern and the bridged conductor pattern.

本願請求項14の発明に係るインダクティブデバイスの製造方法は、請求項9,10,11,12又は13において、前記絶縁層を研磨処理して厚さを調整することを特徴としている。 The inductive device manufacturing method according to claim 14 of the present application is characterized in that, in claim 9, 10, 11, 12 or 13 , the insulating layer is polished to adjust the thickness.

本願請求項15の発明に係るインダクティブデバイスの製造方法は、請求項11又は12において、前記無機焼結体コア基板の前記帯状導体パターンの無い面を研磨処理して厚さを調整することを特徴としている。 A method for manufacturing an inductive device according to the invention of claim 15 of the present application is characterized in that, in claim 11 or 12 , the surface of the inorganic sintered core substrate without the strip-like conductor pattern is polished to adjust the thickness. It is said.

本願請求項16の発明に係るインダクティブデバイスの製造方法は、請求項9,10,11,12,13,14又は15において、前記スライス工程の後、スライス面を研磨処理して厚さを調整することを特徴としている。 The inductive device manufacturing method according to claim 16 of the present application is the method of claim 9, 10, 11, 12, 13 , 14 or 15 , wherein after the slicing step, the slice surface is polished to adjust the thickness. It is characterized by that.

本願請求項17の発明に係るインダクティブデバイスの製造方法は、請求項9,10,11,12,13,14,15又は16において、前記無機焼結体は、多孔質セラミックであることを特徴としている。 An inductive device manufacturing method according to claim 17 of the present application is characterized in that, in claim 9, 10, 11, 12, 13 , 14, 15 , or 16 , the inorganic sintered body is a porous ceramic. Yes.

本願請求項18の発明に係るインダクティブデバイスの製造方法は、請求項9,10,11,12,13,14,15又は16において、前記無機焼結体は、磁性体であることを特徴としている。 An inductive device manufacturing method according to claim 18 of the present application is characterized in that, in claim 9, 10, 11, 12, 13 , 14, 15 , or 16 , the inorganic sintered body is a magnetic body. .

本発明によれば、高性能、狭公差のインダクティブデバイスを高い歩留まりで量産性良く作製可能である。   According to the present invention, a high performance, narrow tolerance inductive device can be manufactured with high yield and high productivity.

また、コア基板として無機焼結体コア基板を用いる場合、コア基板の温度による収縮、反り等による変形が小さく、寸法安定性に優れているので、特に積層時における位置ずれを抑えることができ、歩留まりが良好となり、コスト削減を実現できる。また、無機焼結体コア基板として多孔質セラミックを用いる場合、切削性が良く、有機基板のみと比べて基板の強度が高く、ハンドリングが良好となる。さらに、無機焼結体コア基板として磁性体を用いる場合、透磁率を高くすることができるので、トランスを構成する場合等においてヘリカルコイル相互の結合を強くすることができる利点がある。   Also, when using an inorganic sintered body core substrate as the core substrate, the deformation due to shrinkage, warpage, etc. due to the temperature of the core substrate is small and excellent in dimensional stability. Yield is improved and cost reduction can be realized. Further, when a porous ceramic is used as the inorganic sintered body core substrate, the machinability is good, the strength of the substrate is higher than that of only the organic substrate, and the handling is good. Furthermore, when a magnetic material is used as the inorganic sintered body core substrate, the magnetic permeability can be increased, and thus there is an advantage that the coupling between the helical coils can be strengthened when a transformer is formed.

以下、本発明を実施するための最良の形態として、インダクティブデバイスの製造方法の実施の形態を図面に従って説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an inductive device manufacturing method will be described below with reference to the drawings as the best mode for carrying out the present invention.

図1及び図2で本発明の第1の実施の形態を説明する。まず、図1(A)のように、帯状導体作製工程では、芯材を有する有機コア基板1を用意し、その基板1に複数個所形成された表裏アライメント用スルーホール9を利用して、基板1の表裏面に複数の平行帯状導体パターン2を形成する。   A first embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 1A, in the band-shaped conductor manufacturing process, an organic core substrate 1 having a core material is prepared, and through use of front and back alignment through holes 9 formed in a plurality of locations on the substrate 1, A plurality of parallel strip conductor patterns 2 are formed on the front and back surfaces of 1.

芯材を有する有機コア基板1は、ガラスクロス、ケプラー等の樹脂クロス、フッ素樹脂(商品名:テフロン)の多孔質シート等の芯材に樹脂を含浸させたものであり、樹脂板を芯材で補強したものである。また、樹脂に例えば線膨張係数の制御や電気的特性の向上を目的として、球状シリカフィラーを添加したもの、チタン酸バリウム等の強誘電体粉末を添加したもの、フェライト粉末を添加したもの(複合フェライト)等も好ましく用いられる。樹脂の種類は高周波コイル等の高周波部品にはビニルベンジル樹脂のような高Q、低誘電率材が好ましい。   An organic core substrate 1 having a core material is obtained by impregnating a resin with a core material such as a resin cloth such as glass cloth or Kepler, or a porous sheet of fluororesin (trade name: Teflon). Reinforced with. In addition, for the purpose of controlling the linear expansion coefficient and improving electrical characteristics, for example, a resin added with a spherical silica filler, a ferroelectric powder such as barium titanate, or a ferrite powder (composite) Ferrite) and the like are also preferably used. The type of resin is preferably a high-Q, low-dielectric constant material such as vinylbenzyl resin for high-frequency parts such as a high-frequency coil.

前記複数の平行帯状導体パターン2の形成は、サブトラクティブ法、セミアディティブ法、転写などのフルアディティブ法等による導体層のパターニング方法で行う。前記サブトラクティブ法は導体層上に帯状導体パターン2に対応したレジスト層を形成し、レジスト層で被覆されていない導体層をエッチングにより除去する方法であり、プリント配線基板の製法で最も一般的な方法である。また、前記セミアディティブ法は下地導体層上にレジスト層を形成して、帯状導体パターン2に対応した下地導体層部分を露出させ、電気めっきにより帯状導体パターン2となる導体層を所望の厚さに形成後、不要な下地導体層部分を除去する方法である。   The plurality of parallel strip conductor patterns 2 are formed by a conductor layer patterning method using a subtractive method, a semi-additive method, a full additive method such as transfer, or the like. The subtractive method is a method in which a resist layer corresponding to the strip-shaped conductor pattern 2 is formed on a conductor layer, and a conductor layer not covered with the resist layer is removed by etching, which is the most common method for producing a printed wiring board. Is the method. The semi-additive method forms a resist layer on the underlying conductor layer, exposes the underlying conductor layer portion corresponding to the strip-shaped conductor pattern 2, and forms a conductor layer to be the strip-shaped conductor pattern 2 by electroplating with a desired thickness. This is a method of removing an unnecessary underlying conductor layer portion after the formation.

次に、図1(B)のように、積層工程では、芯材を有する有機コア基板1の表裏面に複数の平行帯状導体パターン2を形成したものを、層間絶縁層(プリプレグ、接着シート)3を介して複数枚積み重ね(但し、導体パターン2が露出しないように最下層と最上層にも絶縁層を設ける)、加熱、加圧して積層一体化し、積層基板10を得る。層間絶縁層3及び最下層と最上層の絶縁層の材質はコア基板1と同様でもよく、層間絶縁層3には芯材はあっても無くともよい。   Next, as shown in FIG. 1B, in the laminating step, a plurality of parallel strip conductor patterns 2 formed on the front and back surfaces of the organic core substrate 1 having a core material are used as an interlayer insulating layer (prepreg, adhesive sheet). A plurality of layers are stacked through 3 (however, an insulating layer is also provided on the lowermost layer and the uppermost layer so that the conductive pattern 2 is not exposed), and heated and pressurized to be laminated and integrated to obtain a laminated substrate 10. The material of the interlayer insulating layer 3 and the lowermost and uppermost insulating layers may be the same as that of the core substrate 1, and the interlayer insulating layer 3 may or may not have a core material.

前記積層工程では、層間絶縁層3となるプリプレグ又は接着シートと基板1を交互に積み重ねて、熱プレスもしくは真空プレスで一括積層するが、基板1は上から見て正確に重なるようにアライメントを行う必要がある。アライメントの方法としては、ピンアライメント、画像によるアライメント、基板1の外形寸法を正確に出してこの内の少なくとも2辺を高精度に形成されたアライメントの型に押し当てる等によってなされる。プリプレグとしては、例えばガラスクロス入りビニルベンジル樹脂、接着シートとしては適度に流動性を有する(導体パターン2の凹凸を吸収できる)日立化成社製接着フィルムGF3600等が好適に使用できる。なお、層間絶縁層3となるプリプレグ又は接着シートの厚みは出来るだけ薄い方が、積層方向のピッチ精度の向上の為には好ましい。   In the laminating step, the prepreg or adhesive sheet to be the interlayer insulating layer 3 and the substrate 1 are alternately stacked and stacked together by hot press or vacuum press, and alignment is performed so that the substrate 1 is accurately overlapped when viewed from above. There is a need. As an alignment method, pin alignment, alignment by an image, an external dimension of the substrate 1 is accurately obtained, and at least two sides thereof are pressed against an alignment mold formed with high accuracy. As the prepreg, for example, a vinylbenzyl resin containing glass cloth, and as the adhesive sheet, an adhesive film GF3600 manufactured by Hitachi Chemical Co., Ltd. having moderate fluidity (can absorb the irregularities of the conductor pattern 2) can be preferably used. Note that it is preferable that the thickness of the prepreg or the adhesive sheet as the interlayer insulating layer 3 is as thin as possible in order to improve the pitch accuracy in the stacking direction.

前記積層工程の後、図1(C)のようにスライス工程において、前記積層工程で得た積層基板をマルチワイヤーソー、マルチブレードソー等の切断手段で帯状導体パターン2を横断する切断線Pで切断し、積層スライス体20を作製する。   After the laminating step, in the slicing step as shown in FIG. 1C, the laminated substrate obtained in the laminating step is cut along a cutting line P that crosses the strip-shaped conductor pattern 2 with a cutting means such as a multi-wire saw or a multi-blade saw. It cut | disconnects and the lamination | stacking slice body 20 is produced.

次に、図2(A)のように、架橋導体形成工程にて積層スライス体20の切断面に露出した帯状導体パターン2の端部同士(基板1の表側のパターンと裏側パターン)を接続する架橋導体パターン21を表裏両面にそれぞれ形成する。ここで、架橋導体パターン21は基板表裏1の帯状導体パターン2と共にヘリカルコイルを構成するものであり、架橋導体パターン21の形成は、帯状導体パターン2の場合と同様の、サブトラクティブ法、セミアディティブ法、あるいはフルアディティブ法等による導体層のパターニングで行うことができる。   Next, as shown in FIG. 2A, the ends of the strip-like conductor pattern 2 exposed on the cut surface of the laminated slice body 20 in the bridged conductor forming step (the front side pattern and the back side pattern of the substrate 1) are connected. Cross-linked conductor patterns 21 are formed on both the front and back surfaces. Here, the bridging conductor pattern 21 constitutes a helical coil together with the strip-shaped conductor pattern 2 on the front and back of the substrate 1, and the formation of the bridging conductor pattern 21 is the same as in the case of the strip-shaped conductor pattern 2. The patterning of the conductor layer can be performed by the method or the full additive method.

そして、架橋導体パターン21の形成後の積層スライス体20の表裏面を覆うように、図2(B)の保護層形成工程にて保護層25を設ける。保護層25はエポキシ、ビニルベンジル、ポリイミド等の樹脂やこれに石英等のフィラーを入れたものが好ましく、熱膨張等に配慮すると有機コア基板1と同様の材質がより好ましい。保護層25には後工程で形成する端子電極とヘリカルコイル間の接続のために、ヘリカルコイル端部となる架橋導体パターン21の端部を露出させるビアホール26を形成する。ビアホール26の形成方法はレーザー加工、サンドブラスト加工、あるいはダイサーで直線状の溝を形成する工法等が好ましく用いられる。また、保護層25に感光性のエポキシ又はポリイミド樹脂を用いてフォトリソグラフィー法にてビアホール26を形成するのも、位置精度または、量産性を考慮した場合好ましい。   And the protective layer 25 is provided in the protective layer formation process of FIG.2 (B) so that the front and back of the lamination | stacking slice body 20 after formation of the bridge | crosslinking conductor pattern 21 may be covered. The protective layer 25 is preferably a resin such as epoxy, vinyl benzyl, polyimide, or the like, and a filler such as quartz added thereto, and a material similar to the organic core substrate 1 is more preferable in consideration of thermal expansion. In the protective layer 25, via holes 26 for exposing the end portions of the bridging conductor pattern 21 serving as the end portions of the helical coils are formed for connection between the terminal electrodes and the helical coils to be formed in a later step. As a method for forming the via hole 26, laser processing, sandblasting, or a method of forming a linear groove with a dicer is preferably used. In addition, it is preferable to form the via hole 26 by a photolithography method using a photosensitive epoxy or polyimide resin for the protective layer 25 in consideration of positional accuracy or mass productivity.

その後、図2(C)の端子電極形成工程にて前記架橋導体パターン21の端部に接続する端子電極30を帯状導体パターン2や架橋導体パターン21の形成に準ずる工法、例えばサブトラクティブ法、セミアディティブ法、フルアディティブ法等で形成する。   Thereafter, in the terminal electrode forming step of FIG. 2C, the terminal electrode 30 connected to the end portion of the bridged conductor pattern 21 is a method similar to the formation of the strip-like conductor pattern 2 or the bridged conductor pattern 21, such as a subtractive method, It is formed by the additive method or the full additive method.

そして、図2(D)のチップ分離工程において、ダイシングソー等の切断手段にて1個(又は複数個)のヘリカルコイルを有するインダクティブデバイスの個品チップ40に切断線Q1,Q2で切断、分離する。   Then, in the chip separation step of FIG. 2 (D), a cutting means such as a dicing saw cuts and separates the individual chip 40 of the inductive device having one (or plural) helical coils along the cutting lines Q1 and Q2. To do.

チップ40に分離後、端子電極30のバレル電気めっき処理により、例えば、ニッケル、錫の順に電気めっき層を形成する。   After separation into chips 40, for example, an electroplating layer is formed in the order of nickel and tin by barrel electroplating treatment of the terminal electrode 30.

なお、電気めっき処理は、チップ分離前に、端子電極形成工程の端子電極30の形成に引き続いて実施してもよい。   Note that the electroplating treatment may be performed subsequent to the formation of the terminal electrode 30 in the terminal electrode formation step before chip separation.

前記帯状導体パターン2及び架橋導体パターン21の種類は、金、銀、銅、アルミ等が挙げられるが、電気抵抗及び量産時のコストを考慮すると銅が好ましい。   Examples of the types of the strip-like conductor pattern 2 and the bridged conductor pattern 21 include gold, silver, copper, and aluminum, but copper is preferable in consideration of electric resistance and cost during mass production.

この第1の実施の形態によれば、次の通りの効果を得ることができる。   According to the first embodiment, the following effects can be obtained.

(1)下記の理由でインダクティブデバイスのインダクタンス値が狭公差である。
a. 芯材を有する有機コア基板1であるため、基板の硬化収縮が小さく、寸法安定性に優れ、基板厚さバラツキが少なくなり、基板両面に帯状導体パターン2を形成したことと相俟ってヘリカルコイルの内径が一定となる。
b. 芯材を有する有機コア基板1の平面方向(厚さと垂直の方向)の収縮が小さく、コイルピッチ精度が良好である。
(1) The inductance value of the inductive device has a narrow tolerance for the following reasons.
a. Since the organic core substrate 1 has a core material, the curing shrinkage of the substrate is small, the dimensional stability is excellent, the variation in the substrate thickness is small, and the band-like conductor pattern 2 is formed on both sides of the substrate. The inner diameter of the coil is constant.
b. Shrinkage in the plane direction (direction perpendicular to the thickness) of the organic core substrate 1 having the core material is small, and the coil pitch accuracy is good.

(2)下記の理由で歩留まりが良い。
芯材を有する有機コア基板1は上述のように厚さバラツキが少なく、基板平面方向の収縮が小さいため、芯材を有する有機コア基板1に形成されたインダクティブデバイスとなる素子のX方向及びY方向の配列ピッチの精度が良い。
(2) Yield is good for the following reasons.
Since the organic core substrate 1 having the core material has a small thickness variation and small shrinkage in the plane direction of the substrate as described above, the X direction and the Y direction of the element to be an inductive device formed on the organic core substrate 1 having the core material The accuracy of the direction arrangement pitch is good.

(3)下記の理由で量産性に優れる。
a. 歩留まりが良好である。
b. 芯材を有する有機コア基板1を用いているため、基板強度が良好であり工程内の基板の割れを防止出来る。
(3) Excellent in mass productivity for the following reasons.
a. Yield is good.
b. Since the organic core substrate 1 having the core material is used, the substrate strength is good and the substrate can be prevented from cracking in the process.

図3及び図4で本発明の第2の実施の形態を説明する。まず、図3(A)のように、帯状導体作製工程では、コア基板1Aを用意し、その基板1Aの片面に複数の平行帯状導体パターン2を形成する。   A second embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 3A, in the strip conductor manufacturing process, a core substrate 1A is prepared, and a plurality of parallel strip conductor patterns 2 are formed on one surface of the substrate 1A.

コア基板1Aは樹脂板、あるいはガラスクロス、ケプラー等の樹脂クロス、フッ素樹脂(商品名:テフロン)の多孔質シート等の芯材に樹脂を含浸させてなる、樹脂板を芯材で補強したものを使用できる。また、主材質である樹脂に例えば線膨張係数の制御や電気的特性の向上を目的として、球状シリカフィラーを添加したもの、チタン酸バリウム等の強誘電体粉末を添加したもの、フェライト粉末を添加したもの(複合フェライト)等も好ましく用いられる。樹脂の種類は高周波コイル等の高周波部品にはビニルベンジル樹脂のような高Q、低誘電率材が好ましい。また、コア基板1Aとして、石英、ガラス、アルミナ、フェライト等の無機質の基板を用いても良い。さらに、高周波での用途でない場合はパーマロイ基板、及びパーマロイの薄いシートを薄い絶縁層を介して積層したもののような、金属製の基板を用いることもできる。但し、金属製基板の場合、帯状導体パターン2を設ける側に絶縁性の接着シートを設けておく。   The core substrate 1A is a resin plate, or a resin cloth such as a glass cloth or Kepler, or a core material such as a porous sheet of fluororesin (trade name: Teflon), in which the resin plate is reinforced with a core material. Can be used. In addition, for the purpose of controlling the linear expansion coefficient and improving electrical characteristics, for example, the resin that is the main material is added with spherical silica filler, the addition of ferroelectric powder such as barium titanate, and the addition of ferrite powder Those obtained (composite ferrite) are also preferably used. The type of resin is preferably a high-Q, low-dielectric constant material such as vinylbenzyl resin for high-frequency parts such as a high-frequency coil. Further, as the core substrate 1A, an inorganic substrate such as quartz, glass, alumina, or ferrite may be used. Further, when not used at a high frequency, a metal substrate such as a permalloy substrate and a thin sheet of permalloy laminated with a thin insulating layer may be used. However, in the case of a metal substrate, an insulating adhesive sheet is provided on the side where the strip-shaped conductor pattern 2 is provided.

前記複数の平行帯状導体パターン2の形成は、前述の第1の実施の形態と同様の工法で行うことができる。   The formation of the plurality of parallel strip conductor patterns 2 can be performed by the same method as in the first embodiment.

次に、図3(B)のように、積層工程では、コア基板1Aの片面に複数の平行帯状導体パターン2を形成したものを、層間絶縁層(プリプレグ、接着シート)3を介して複数枚積み重ね(但し、導体パターン2が露出しないように最上層にも絶縁層を設ける)、加熱、加圧して積層一体化し、積層基板10Aを得る。コア基板1Aが有機材質であるとき、層間絶縁層3の材質はコア基板1Aと同様でよい。層間絶縁層3が樹脂層の場合、芯材はあっても無くともよい。また、層間絶縁層3に無機材質を用いる場合は、両側に薄い絶縁性接着シートを挟んで積層する。ここで用いる接着シートとしては適度に流動性のある(導体パターン2の凹凸を吸収できる)日立化成社製接着フィルムGF3600等が好適に使用できる。積層工程のその他の条件は前述の第1の実施の形態と同様でよい。   Next, as shown in FIG. 3B, in the laminating step, a plurality of parallel strip-like conductor patterns 2 formed on one side of the core substrate 1A are provided via an interlayer insulating layer (prepreg, adhesive sheet) 3. Stacking (however, an insulating layer is also provided on the uppermost layer so that the conductor pattern 2 is not exposed), heating and pressurizing are performed to integrate and obtain a laminated substrate 10A. When the core substrate 1A is an organic material, the material of the interlayer insulating layer 3 may be the same as that of the core substrate 1A. When the interlayer insulating layer 3 is a resin layer, the core material may or may not be present. Moreover, when using an inorganic material for the interlayer insulation layer 3, it laminates | stacks on both sides on both sides of a thin insulating adhesive sheet. As the adhesive sheet used here, an adhesive film GF3600 manufactured by Hitachi Chemical Co., Ltd., which has moderate fluidity (can absorb the irregularities of the conductor pattern 2), and the like can be suitably used. Other conditions for the lamination process may be the same as those in the first embodiment.

前記積層工程の後、図3(C)のようにスライス工程において、前記積層工程で得た積層基板をマルチワイヤーソー、マルチブレードソー等の切断手段で帯状導体パターン2を横断する切断線Pで切断し、積層スライス体20Aを作製する。   After the laminating step, in the slicing step as shown in FIG. 3C, the laminated substrate obtained in the laminating step is cut along a cutting line P that crosses the strip-shaped conductor pattern 2 by a cutting means such as a multi-wire saw or a multi-blade saw. Cut to produce a laminated slice 20A.

次に、図4(A)のように、架橋導体形成工程にて積層スライス体20Aの切断面に露出した帯状導体パターン2の端部同士(上下1組のコア基板1Aのパターン同士)を接続する架橋導体パターン21を形成する。ここで、架橋導体パターン21は対をなす2枚のコア基板1Aの帯状導体パターン2と共にヘリカルコイルを構成するものであり、架橋導体パターン21の形成は、帯状導体パターン2の場合と同様の、サブトラクティブ法、セミアディティブ法、あるいはフルアディティブ法等による導体層のパターニングで行うことができる。   Next, as shown in FIG. 4A, the ends of the strip-like conductor pattern 2 exposed on the cut surface of the laminated slice body 20A in the bridged conductor forming step (the patterns of the upper and lower sets of core substrate 1A) are connected to each other. The bridge | crosslinking conductor pattern 21 to be formed is formed. Here, the bridging conductor pattern 21 constitutes a helical coil together with the strip-shaped conductor pattern 2 of the two core substrates 1A that make a pair, and the formation of the bridging conductor pattern 21 is the same as in the case of the strip-shaped conductor pattern 2. The conductive layer can be patterned by a subtractive method, a semi-additive method, a full additive method, or the like.

以後、図4(B)の保護層形成工程、同図(C)の端子電極形成工程及び同図(D)のチップ分離工程は第1の実施の形態と同様に行うことができる。但し、チップ分離工程において、第1の実施の形態では層間絶縁層の部分を切断したが、この第2の実施の形態ではコア基板1Aの厚みの中間位置を切断線Q1で切断する。その他は、第1の実施の形態と同一又は相当部分に同一の符号を付して詳細は省略する。   Thereafter, the protective layer forming step in FIG. 4B, the terminal electrode forming step in FIG. 4C, and the chip separating step in FIG. 4D can be performed in the same manner as in the first embodiment. However, in the chip separation step, the portion of the interlayer insulating layer is cut in the first embodiment, but in the second embodiment, the intermediate position of the thickness of the core substrate 1A is cut along the cutting line Q1. In other respects, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and details thereof are omitted.

この第2の実施の形態によれば、コア基板1Aの片面のみに帯状導体パターン2を形成すればよく、工程の簡素化が図れる。また、基板両面に帯状導体パターン2を形成した場合に問題となる、表裏の導体パターンのアライメントのずれに起因する歩留まり低下を避けることができる。   According to the second embodiment, the strip-shaped conductor pattern 2 may be formed only on one surface of the core substrate 1A, and the process can be simplified. In addition, it is possible to avoid a decrease in yield due to misalignment between the front and back conductor patterns, which becomes a problem when the strip-like conductor patterns 2 are formed on both surfaces of the substrate.

なお、第2の実施の形態における積層工程での積層方法としては、コア基板の片面に平行帯状導体パターンを形成したものを、当該平行帯状導体パターンを形成している面を交互に反転して積層することも可能である。   In addition, as a laminating method in the laminating step in the second embodiment, a method in which a parallel strip conductor pattern is formed on one side of a core substrate is alternately reversed on a surface on which the parallel strip conductor pattern is formed. It is also possible to laminate.

図5及び図6で本発明の第3の実施の形態を説明する。まず、図5(A)のように、帯状導体作製工程では、芯材を有する有機コア基板1を用意し、その有機コア基板1に複数個所形成された表裏アライメント用スルーホール9を利用して、有機コア基板1の表裏面に複数の平行帯状導体パターン2を形成する。この工程は第1の実施の形態と同様である。   A third embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 5A, in the band-shaped conductor manufacturing process, an organic core substrate 1 having a core material is prepared, and front and back alignment through holes 9 formed in a plurality of locations on the organic core substrate 1 are used. A plurality of parallel strip conductor patterns 2 are formed on the front and back surfaces of the organic core substrate 1. This step is the same as in the first embodiment.

次に、図5(B)のように、第1積層工程では、前記帯状導体作製工程で平行帯状導体パターン2が表裏に形成された有機コア基板1に対して、その表裏に層間絶縁層(プリプレグ、あるいは接着シート)4を重ねて加圧、加熱等を施して積層一体化し、基板表裏が層間絶縁層4で覆われた積層体5を作製する。層間絶縁層4は、プリプレグとしては、例えばビニルベンジル樹脂を用いたもの、あるいは、接着シートとしては適度に流動性を有する(導体パターン2の凹凸を吸収できる)もの、例えば日立化成社製接着フィルムGF3600等が好適に使用できる。なお、積層体5上下面は互いに平行な平面に形成され、また積層体5の厚み精度を出すために、必要に応じて研磨処理を施すことも好ましい。   Next, as shown in FIG. 5B, in the first laminating step, an interlayer insulating layer (on the front and back sides) is formed on the organic core substrate 1 on which the parallel strip-like conductor patterns 2 are formed on the front and back sides in the strip conductor manufacturing step. A prepreg 4 or an adhesive sheet) 4 is stacked and subjected to pressurization, heating, and the like to be laminated and integrated to produce a laminate 5 in which the substrate front and back are covered with the interlayer insulating layer 4. The interlayer insulating layer 4 is, for example, one using a vinyl benzyl resin as a prepreg, or one having moderate fluidity as an adhesive sheet (can absorb the irregularities of the conductor pattern 2), for example, an adhesive film manufactured by Hitachi Chemical Co., Ltd. GF3600 etc. can be used conveniently. Note that the upper and lower surfaces of the laminated body 5 are formed in planes parallel to each other, and it is also preferable to perform a polishing treatment as necessary in order to increase the thickness accuracy of the laminated body 5.

その後、図5(C)のように、第2積層工程において、積層体5と接着層となる接着シート6とを交互に積み重ねて、熱プレスもしくは真空プレスで一括積層し積層基板10Bを作製する。その際、積層体5は上から見て正確に重なるようにアライメントを行う必要がある。アライメントの方法は第1の実施の形態と同様に行うことができる。   Thereafter, as shown in FIG. 5C, in the second laminating step, the laminate 5 and the adhesive sheet 6 serving as an adhesive layer are alternately stacked, and are laminated together by heat press or vacuum press to produce a laminate substrate 10B. . In that case, it is necessary to align so that the laminated body 5 may overlap correctly seeing from the top. The alignment method can be performed in the same manner as in the first embodiment.

この第2積層工程において使用する接着シート6の材質はプレス時に出来るだけ流動性のないものが好ましい。このために、例えば接着シートの樹脂の硬化度を上げる等の手法が適用出来る。この接着シート6には、流動性の少ない日立化成社製接着フィルムGF3500等が好適に使用できる。なお、接着シート6の厚みは出来るだけ薄い方が積層方向のピッチ精度の向上の為(架橋導体パターン21の位置合わせの為)には好ましい。さらに、接着シート6として導電性を有するものを使用しても良い。例を挙げると真鍮またはアルミ基板の表裏面に薄く接着剤を塗布したもの等がある。これにより工程内の基板及び積層体の機械的強度をさらに向上させることが可能で、またピッチ精度も良くなる。   The material of the adhesive sheet 6 used in the second laminating step is preferably a material having as little fluidity as possible at the time of pressing. For this purpose, for example, a technique such as increasing the degree of curing of the resin of the adhesive sheet can be applied. For the adhesive sheet 6, an adhesive film GF3500 manufactured by Hitachi Chemical Co., Ltd. with little fluidity can be suitably used. The adhesive sheet 6 is preferably as thin as possible for improving the pitch accuracy in the stacking direction (for aligning the cross-linked conductor pattern 21). Further, a conductive sheet may be used as the adhesive sheet 6. For example, a thin adhesive is applied to the front and back surfaces of a brass or aluminum substrate. As a result, the mechanical strength of the substrate and the laminate in the process can be further improved, and the pitch accuracy is improved.

以後、図5(D)のスライス工程、図6(A)の架橋導体形成工程、同図(B)の保護層形成工程、同図(C)の端子電極形成工程及び同図(D)のチップ分離工程は第1の実施の形態と同様に行うことができる。第1の実施の形態と同一又は相当部分に同一の符号を付して詳細は省略する。   Thereafter, the slicing step in FIG. 5D, the bridging conductor forming step in FIG. 6A, the protective layer forming step in FIG. 5B, the terminal electrode forming step in FIG. 5C, and the FIG. The chip separation step can be performed in the same manner as in the first embodiment. The same reference numerals are given to the same or corresponding parts as in the first embodiment, and the details are omitted.

この第3の実施の形態によれば、第1積層工程では層間絶縁層4をできるだけ薄くし、当該層間絶縁層形成後の積層体5の厚み精度を高くし(必要ならばグラインダー等による研削、研磨を行い)、かつ第2積層工程では接着シート6をできるだけ薄くかつプレス時の流動性が少ないものを用いることで、積層基板10Bに含まれるインダクティブデバイスとなる素子の積層方向のピッチ精度が良好となり、図6(A)の架橋導体形成工程における架橋導体パターン21と帯状導体パターン2間の位置ずれが発生しにくくなり、いっそうの歩留まり向上を図り得る。なお、その他の作用効果は第1の実施の形態と同様である。   According to the third embodiment, in the first stacking step, the interlayer insulating layer 4 is made as thin as possible, and the thickness accuracy of the stacked body 5 after forming the interlayer insulating layer is increased (if necessary, grinding with a grinder, etc. Polishing is performed), and in the second lamination step, the adhesive sheet 6 is made as thin as possible and the fluidity at the time of pressing is low, so that the pitch accuracy in the laminating direction of the element that becomes the inductive device included in the laminated substrate 10B is good. Thus, it is difficult for positional deviation between the cross-linked conductor pattern 21 and the strip-shaped conductor pattern 2 in the cross-linked conductor forming step of FIG. 6A to occur, and the yield can be further improved. Other functions and effects are the same as those of the first embodiment.

上記第3の実施の形態は、コア基板片面のみに帯状導体パターンを形成した場合にも適用可能である。この場合、第2の実施の形態と同様に、対をなす上下のコア基板の帯状導体パターン同士を架橋導体パターンで接続後、コア基板の厚み中間位置を切断すればよい。但し、接着層は絶縁性のものに限定される。   The third embodiment can also be applied to the case where a strip conductor pattern is formed only on one side of the core substrate. In this case, similarly to the second embodiment, after connecting the strip-like conductor patterns of the upper and lower core substrates forming a pair with the bridging conductor pattern, the intermediate thickness position of the core substrate may be cut. However, the adhesive layer is limited to an insulating layer.

図7及び図8で本発明の第4の実施の形態を説明する。まず、図7(A)の帯状導体作製工程では、コア基板7となるプリプレグを用意するとともに、導電性を有する転写用基板に平行帯状導体パターン2をパターンメッキ法で所定厚みで形成しておく。そして、前記転写用基板にプリプレグを重ねて加圧(真空プレス)、加熱し、プリプレグを硬化した後、前記転写用基板を剥離する。これにより、図7(A)のようにコア基板7の片面に平行帯状導体パターン2が転写で形成される。なお、コア基板7は平行帯状導体パターン2を転写するために、転写時においては、半硬化状態となっている樹脂シートやプリプレグを硬化したものである。例えば、ガラスクロス、ケプラー等の樹脂クロス、フッ素樹脂(商品名:テフロン)の多孔質シート等の芯材に樹脂を含浸させたものであり、樹脂板を芯材で補強したものである。また、樹脂に例えば線膨張係数の制御や電気的特性の向上を目的として、球状シリカフィラーを添加したもの、チタン酸バリウム等の強誘電体粉末を添加したもの、フェライト粉末を添加したもの(複合フェライト)等も好ましく用いられる。樹脂の種類は高周波コイル等の高周波部品にはビニルベンジル樹脂のような高Q、低誘電率材が好ましい。この帯状導体作製工程では転写によって平行帯状導体パターン2を転写時に半硬化状態のコア基板7の片面に設けることで、コア基板7の導体パターン2を転写した面を平滑にすることができる。ここで、「平滑」とはRmaxが10μm以下、好ましくは5μm以下、最も好ましくは2μm以下の表面状態を示す。   A fourth embodiment of the present invention will be described with reference to FIGS. First, in the strip conductor manufacturing step of FIG. 7A, a prepreg to be the core substrate 7 is prepared, and the parallel strip conductor pattern 2 is formed with a predetermined thickness on the transfer substrate having conductivity by a pattern plating method. . Then, the prepreg is overlaid on the transfer substrate, pressurized (vacuum press) and heated to cure the prepreg, and then the transfer substrate is peeled off. Thereby, as shown in FIG. 7A, the parallel strip-like conductor pattern 2 is formed on one surface of the core substrate 7 by transfer. In addition, in order to transfer the parallel strip | belt-shaped conductor pattern 2, the core board | substrate 7 hardens | cures the resin sheet and prepreg which are in the semi-hardened state at the time of transcription | transfer. For example, a resin cloth such as glass cloth or Kepler, or a porous material such as a fluororesin (trade name: Teflon) porous sheet is impregnated with resin, and a resin plate is reinforced with a core material. In addition, for the purpose of controlling the linear expansion coefficient and improving electrical characteristics, for example, a resin added with a spherical silica filler, a ferroelectric powder such as barium titanate, or a ferrite powder (composite) Ferrite) and the like are also preferably used. The type of resin is preferably a high-Q, low-dielectric constant material such as vinylbenzyl resin for high-frequency parts such as a high-frequency coil. In this strip conductor manufacturing step, the parallel strip conductor pattern 2 is provided on one side of the core substrate 7 in a semi-cured state during transfer by transfer, so that the surface of the core substrate 7 onto which the conductor pattern 2 is transferred can be smoothed. Here, “smooth” indicates a surface state in which Rmax is 10 μm or less, preferably 5 μm or less, and most preferably 2 μm or less.

次に、図7(B)の基板厚さ調整工程では、研磨処理により、コア基板7の導体パターン2を転写した面の反対面を研削、研磨して基板厚みを予め定めた一定厚さに調整する。   Next, in the substrate thickness adjusting step of FIG. 7B, the surface opposite to the surface to which the conductor pattern 2 of the core substrate 7 is transferred is ground and polished by a polishing process so that the substrate thickness is a predetermined constant thickness. adjust.

次に、図7(C)のように、積層工程では、コア基板7の片面に複数の平行帯状導体パターン2を形成したものを、接着層となるできるだけ薄い絶縁性接着シート8を介して複数枚積み重ね(但し、導体パターン2が露出しないように最上層にも接着シート8を設ける)、加熱、加圧して積層一体化し、積層基板10Cを得る。前記接着シート8の材質は流動性の少ない日立化成社製接着フィルムGF3500等が好適に使用できる。   Next, as shown in FIG. 7C, in the laminating step, a plurality of parallel strip-like conductor patterns 2 formed on one side of the core substrate 7 are provided via an insulating adhesive sheet 8 that is as thin as possible as an adhesive layer. Sheet stacking (however, the adhesive sheet 8 is also provided on the uppermost layer so that the conductor pattern 2 is not exposed), heating and pressurization are performed to integrate the layers, thereby obtaining a multilayer substrate 10C. As the material of the adhesive sheet 8, an adhesive film GF3500 manufactured by Hitachi Chemical Co., Ltd. having a low fluidity can be preferably used.

以後、図7(D)のスライス工程、図8(A)の架橋導体形成工程、同図(B)の保護層形成工程、同図(C)の端子電極形成工程及び同図(D)のチップ分離工程は第2の実施の形態と同様に行うことができ、第2の実施の形態と同一又は相当部分に同一の符号を付して詳細は省略する。   Thereafter, the slicing step in FIG. 7D, the bridging conductor forming step in FIG. 8A, the protective layer forming step in FIG. 7B, the terminal electrode forming step in FIG. The chip separation step can be performed in the same manner as in the second embodiment, and the same reference numerals are given to the same or corresponding parts as in the second embodiment, and the details are omitted.

この第4の実施の形態の場合、コア基板7の片面に転写で帯状導体パターン2を設け、かつその帯状導体パターン2を配置した側の面を平滑にし、あわせて基板厚さ調整工程にてコア基板厚みを高精度で一定厚みに管理することができる。   In the case of the fourth embodiment, the belt-like conductor pattern 2 is provided by transfer on one surface of the core substrate 7, and the surface on which the belt-like conductor pattern 2 is arranged is smoothed, and at the same time, in the substrate thickness adjusting step The core substrate thickness can be controlled to a constant thickness with high accuracy.

また、コア基板7の両面が平滑となるため、接着シート8として薄く、しかも流動性の少ないものを使用でき、積層工程でのプレス圧も少なくできる。このため、積層方向のピッチ精度が極めて良好であり、第2の実施の形態の作用効果に加えて、積層基板10Cに含まれるインダクティブデバイスとなる素子の積層方向のピッチ精度を極めて良好なものにでき、図8(A)の架橋導体形成工程における架橋導体パターン21と帯状導体パターン2間の位置ずれが発生しにくくなり、いっそうの歩留まり向上を図り得る。   Moreover, since both surfaces of the core substrate 7 are smooth, the adhesive sheet 8 can be thin and less fluid, and the pressing pressure in the laminating process can be reduced. For this reason, the pitch accuracy in the stacking direction is extremely good, and in addition to the effects of the second embodiment, the pitch accuracy in the stacking direction of the element that is an inductive device included in the stacked substrate 10C is extremely good. In addition, misalignment between the cross-linked conductor pattern 21 and the strip-shaped conductor pattern 2 in the cross-linked conductor forming step in FIG. 8A is less likely to occur, and the yield can be further improved.

上記第4の実施の形態における積層工程での積層方法としては、コア基板の片面に平行帯状導体パターンを形成したものを、当該平行帯状導体パターンを形成している面を交互に反転して積層することも可能である。   As a laminating method in the laminating step in the fourth embodiment, the parallel strip conductor pattern formed on one side of the core substrate is laminated by alternately inverting the plane on which the parallel strip conductor pattern is formed. It is also possible to do.

なお、前述の第1、第2又は第3の実施の形態においても、第4の実施の形態と同様に、転写により帯状導体パターンをコア基板面に形成し、当該コア基板の帯状導体パターン配置側の面を平滑にした構成が可能である。   In the first, second, or third embodiment described above, similarly to the fourth embodiment, a strip-shaped conductor pattern is formed on the core substrate surface by transfer, and the strip-shaped conductor pattern arrangement of the core substrate is performed. A configuration with a smooth side surface is possible.

図1及び図2で本発明の第5の実施の形態を説明する。この第5の実施の形態は芯材を有する有機コア基板の代わりに無機焼結体コア基板を用いるものである。まず、図1(A)のように、帯状導体作製工程では、無機焼結体コア基板1を用意し、その基板1に複数個所形成された表裏アライメント用スルーホール9を利用して、基板1の表裏面に複数の平行帯状導体パターン2を形成する。この場合、コア基板1の焼結後に導体パターン2を形成してもよいし、未焼成コア基板に導体ペーストを設けておき、コア基板1の焼成と同時に導体パターン2を形成してもよい。   A fifth embodiment of the present invention will be described with reference to FIGS. In the fifth embodiment, an inorganic sintered body core substrate is used instead of an organic core substrate having a core material. First, as shown in FIG. 1A, in the band-shaped conductor manufacturing process, an inorganic sintered body core substrate 1 is prepared, and the substrate 1 is formed using the front and back alignment through holes 9 formed in a plurality of locations on the substrate 1. A plurality of parallel strip-like conductor patterns 2 are formed on the front and back surfaces. In this case, the conductor pattern 2 may be formed after the core substrate 1 is sintered, or a conductor paste may be provided on the unfired core substrate, and the conductor pattern 2 may be formed simultaneously with the firing of the core substrate 1.

無機焼結体コア基板1は、磁気特性に配慮してフェライト等の磁性体を用いたり、製造時の切削性が良好な多孔質セラミック等を用いることができる。   The inorganic sintered body core substrate 1 can be made of a magnetic material such as ferrite in consideration of magnetic characteristics, or can be made of a porous ceramic having good machinability during production.

前記複数の平行帯状導体パターン2の形成は、サブトラクティブ法、セミアディティブ法、フルアディティブ法等による導体層のパターニング方法で行う。   The plurality of parallel strip conductor patterns 2 are formed by a conductor layer patterning method using a subtractive method, a semi-additive method, a full additive method, or the like.

次に、図1(B)のように、積層工程では、無機焼結体コア基板1の表裏面に複数の平行帯状導体パターン2を形成したものを、層間絶縁層(プリプレグ、接着シート)3を介して複数枚積み重ね(但し、導体パターン2が露出しないように最下層と最上層にも絶縁層を設ける)、加熱、加圧して積層一体化し、積層基板10を得る。層間絶縁層3には芯材はあっても無くともよい。   Next, as shown in FIG. 1B, in the laminating step, a plurality of parallel strip conductor patterns 2 formed on the front and back surfaces of the inorganic sintered body core substrate 1 are formed as an interlayer insulating layer (prepreg, adhesive sheet) 3. A plurality of layers are stacked (provided that an insulating layer is also provided on the lowermost layer and the uppermost layer so that the conductive pattern 2 is not exposed), heated and pressurized to be laminated and integrated to obtain a laminated substrate 10. The interlayer insulating layer 3 may or may not have a core material.

前記積層工程では、層間絶縁層3となるプリプレグ又は接着シートと基板1を交互に積み重ねて、熱プレスもしくは真空プレスで一括積層するが、基板1は上から見て正確に重なるようにアライメントを行う必要がある。アライメントの方法としては、ピンアライメント、画像によるアライメント、基板1の外形寸法を正確に出してこの内の少なくとも2辺を高精度に形成されたアライメントの型に押し当てる等によってなされる。プリプレグとしては、例えばガラスクロス入りビニルベンジル樹脂、接着シートとしては適度に流動性を有する(導体パターン2の凹凸を吸収できる)日立化成社製接着フィルムGF3600等が好適に使用できる。なお、層間絶縁層3となるプリプレグ又は接着シートの厚みは出来るだけ薄い方が、積層方向のピッチ精度の向上の為には好ましい。   In the laminating step, the prepreg or adhesive sheet to be the interlayer insulating layer 3 and the substrate 1 are alternately stacked and stacked together by hot press or vacuum press, and alignment is performed so that the substrate 1 is accurately overlapped when viewed from above. There is a need. As an alignment method, pin alignment, alignment by an image, an external dimension of the substrate 1 is accurately obtained, and at least two sides thereof are pressed against an alignment mold formed with high accuracy. As the prepreg, for example, a vinylbenzyl resin containing glass cloth, and as the adhesive sheet, an adhesive film GF3600 manufactured by Hitachi Chemical Co., Ltd. having moderate fluidity (can absorb the irregularities of the conductor pattern 2) can be preferably used. Note that it is preferable that the thickness of the prepreg or the adhesive sheet as the interlayer insulating layer 3 is as thin as possible in order to improve the pitch accuracy in the stacking direction.

前記積層工程の後、図1(C)のようにスライス工程において、前記積層工程で得た積層基板をマルチワイヤーソー、マルチブレードソー等の切断手段で帯状導体パターン2を横断する切断線Pで切断し、積層スライス体20を作製する。   After the laminating step, in the slicing step as shown in FIG. 1C, the laminated substrate obtained in the laminating step is cut along a cutting line P that crosses the strip-shaped conductor pattern 2 with a cutting means such as a multi-wire saw or a multi-blade saw. It cut | disconnects and the lamination | stacking slice body 20 is produced.

次に、図2(A)のように、架橋導体形成工程にて積層スライス体20の切断面に露出した帯状導体パターン2の端部同士(基板1の表側のパターンと裏側パターン)を接続する架橋導体パターン21を表裏両面にそれぞれ形成する。ここで、架橋導体パターン21は基板表裏1の帯状導体パターン2と共にヘリカルコイルを構成するものであり、架橋導体パターン21の形成は、帯状導体パターン2の場合と同様の、サブトラクティブ法、セミアディティブ法、あるいはフルアディティブ法等による導体層のパターニングで行うことができる。   Next, as shown in FIG. 2A, the ends of the strip-like conductor pattern 2 exposed on the cut surface of the laminated slice body 20 in the bridged conductor forming step (the front side pattern and the back side pattern of the substrate 1) are connected. Cross-linked conductor patterns 21 are formed on both the front and back surfaces. Here, the bridging conductor pattern 21 constitutes a helical coil together with the strip-shaped conductor pattern 2 on the front and back of the substrate 1, and the formation of the bridging conductor pattern 21 is the same as in the case of the strip-shaped conductor pattern 2. The patterning of the conductor layer can be performed by the method or the full additive method.

そして、架橋導体パターン21の形成後の積層スライス体20の表裏面を覆うように、図2(B)の保護層形成工程にて保護層25を設ける。保護層25はエポキシ、ビニルベンジル、ポリイミド等の樹脂やこれに石英等のフィラーを入れたものが好ましい。保護層25には後工程で形成する端子電極とヘリカルコイル間の接続のために、ヘリカルコイル端部となる架橋導体パターン21の端部を露出させるビアホール26を形成する。ビアホール26の形成方法はレーザー加工、サンドブラスト加工、あるいはダイサーで直線状の溝を形成する工法等が好ましく用いられる。また、保護層25に感光性のエポキシ又はポリイミド樹脂を用いてフォトリソグラフィー法にてビアホール26を形成するのも、位置精度または、量産性を考慮した場合好ましい。   And the protective layer 25 is provided in the protective layer formation process of FIG.2 (B) so that the front and back of the lamination | stacking slice body 20 after formation of the bridge | crosslinking conductor pattern 21 may be covered. The protective layer 25 is preferably a resin such as epoxy, vinyl benzyl, polyimide, or the like, and a filler such as quartz added thereto. In the protective layer 25, via holes 26 for exposing the end portions of the bridging conductor pattern 21 serving as the end portions of the helical coils are formed for connection between the terminal electrodes and the helical coils to be formed in a later step. As a method for forming the via hole 26, laser processing, sandblasting, or a method of forming a linear groove with a dicer is preferably used. In addition, it is preferable to form the via hole 26 by a photolithography method using a photosensitive epoxy or polyimide resin for the protective layer 25 in consideration of positional accuracy or mass productivity.

その後、図2(C)の端子電極形成工程にて前記架橋導体パターン21の端部に接続する端子電極30を帯状導体パターン2や架橋導体パターン21の形成に準ずる工法、例えばサブトラクティブ法、セミアディティブ法、フルアディティブ法等で形成する。   Thereafter, in the terminal electrode forming step of FIG. 2C, the terminal electrode 30 connected to the end portion of the bridged conductor pattern 21 is a method similar to the formation of the strip-like conductor pattern 2 or the bridged conductor pattern 21, such as a subtractive method, It is formed by the additive method or the full additive method.

そして、図2(D)のチップ分離工程において、ダイシングソー等の切断手段にて1個(又は複数個)のヘリカルコイルを有するインダクティブデバイスの個品チップ40に切断線Q1,Q2で切断、分離する。   Then, in the chip separation step of FIG. 2 (D), a cutting means such as a dicing saw cuts and separates the individual chip 40 of the inductive device having one (or plural) helical coils along the cutting lines Q1 and Q2. To do.

チップ40に分離後、端子電極30のバレル電気めっき処理により、例えば、ニッケル、錫の順に電気めっき層を形成する。   After separation into chips 40, for example, an electroplating layer is formed in the order of nickel and tin by barrel electroplating treatment of the terminal electrode 30.

なお、電気めっき処理は、チップ分離前に、端子電極形成工程の端子電極30の形成に引き続いて実施してもよい。   Note that the electroplating treatment may be performed subsequent to the formation of the terminal electrode 30 in the terminal electrode formation step before chip separation.

前記帯状導体パターン2及び架橋導体パターン21の種類は、金、銀、銅、アルミ等が挙げられるが、電気抵抗及び量産時のコストを考慮すると銅が好ましい。   Examples of the types of the strip-like conductor pattern 2 and the bridged conductor pattern 21 include gold, silver, copper, and aluminum, but copper is preferable in consideration of electric resistance and cost during mass production.

この第5の実施の形態によれば、次の通りの効果を得ることができる。   According to the fifth embodiment, the following effects can be obtained.

(1)下記の理由でインダクティブデバイスのインダクタンス値が狭公差である。
a. 無機焼結体コア基板1であるため、基板の硬化収縮が小さく、寸法安定性に優れ、基板厚さバラツキが少なくなり、基板両面に帯状導体パターン2を形成したことと相俟ってヘリカルコイルの内径が一定となる。
b. 無機焼結体コア基板1の平面方向(厚さと垂直の方向)の収縮が小さく、コイルピッチ精度が良好である。
(1) The inductance value of the inductive device has a narrow tolerance for the following reasons.
a. Since it is an inorganic sintered body core substrate 1, the helical coil is coupled with the fact that the substrate has small curing shrinkage, excellent dimensional stability, less substrate thickness variation, and the formation of the strip-like conductor pattern 2 on both surfaces of the substrate. The inner diameter is constant.
b. Shrinkage in the plane direction (direction perpendicular to the thickness) of the inorganic sintered body core substrate 1 is small, and the coil pitch accuracy is good.

(2)下記の理由で歩留まりが良い。
無機焼結体コア基板1は上述のように厚さバラツキが少なく、基板平面方向の収縮が小さいため、無機焼結体コア基板1に形成されたインダクティブデバイスとなる素子のX方向及びY方向の配列ピッチの精度が良い。
(2) Yield is good for the following reasons.
As described above, the inorganic sintered body core substrate 1 has a small thickness variation and a small shrinkage in the plane direction of the substrate. Therefore, the elements in the X direction and the Y direction of the element to be an inductive device formed on the inorganic sintered body core substrate 1 The accuracy of the arrangement pitch is good.

(3)下記の理由で量産性に優れる。
a. 歩留まりが良好である。
b. 無機焼結体コア基板1を用いているため、基板強度が良好であり工程内の基板の割れを防止出来る。
(3) Excellent in mass productivity for the following reasons.
a. Yield is good.
b. Since the inorganic sintered body core substrate 1 is used, the substrate strength is good and the substrate can be prevented from cracking in the process.

図3及び図4で本発明の第6の実施の形態を説明する。まず、図3(A)のように、帯状導体作製工程では、無機焼結体コア基板1Aを用意し、その無機焼結体コア基板1Aの片面に複数の平行帯状導体パターン2を形成する。   A sixth embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 3A, in the band-shaped conductor manufacturing step, an inorganic sintered body core substrate 1A is prepared, and a plurality of parallel band-shaped conductor patterns 2 are formed on one surface of the inorganic sintered body core substrate 1A.

無機焼結体コア基板1Aは、フェライトやセラミック等であり、高周波コイル等の高周波部品には高Q、低誘電率材が好ましい。   The inorganic sintered body core substrate 1A is made of ferrite, ceramic, or the like, and a high-Q, low-dielectric constant material is preferable for high-frequency components such as a high-frequency coil.

前記複数の平行帯状導体パターン2の形成は、前述の第1の実施の形態と同様の工法で行うことができる。   The formation of the plurality of parallel strip conductor patterns 2 can be performed by the same method as in the first embodiment.

次に、図3(B)のように、積層工程では、無機焼結体コア基板1Aの片面に複数の平行帯状導体パターン2を形成したものを、層間絶縁層(プリプレグ、接着シート)3を介して複数枚積み重ね(但し、導体パターン2が露出しないように最上層にも絶縁層を設ける)、加熱、加圧して積層一体化し、積層基板10Aを得る。層間絶縁層3が樹脂層の場合、芯材はあっても無くともよい。また、層間絶縁層3に無機材質を用いる場合は、両側に薄い絶縁性接着シートを挟んで積層する。ここで用いる接着シートとしては適度に流動性のある(導体パターン2の凹凸を吸収できる)日立化成社製接着フィルムGF3600等が好適に使用できる。積層工程のその他の条件は前述の第1の実施の形態と同様でよい。   Next, as shown in FIG. 3B, in the laminating step, an interlayer insulating layer (prepreg, adhesive sheet) 3 is formed by forming a plurality of parallel strip conductor patterns 2 on one side of the inorganic sintered core substrate 1A. A plurality of layers are stacked (however, an insulating layer is also provided on the uppermost layer so that the conductor pattern 2 is not exposed), heated and pressed to be laminated and integrated to obtain a laminated substrate 10A. When the interlayer insulating layer 3 is a resin layer, the core material may or may not be present. Moreover, when using an inorganic material for the interlayer insulation layer 3, it laminates | stacks on both sides on both sides of a thin insulating adhesive sheet. As the adhesive sheet used here, an adhesive film GF3600 manufactured by Hitachi Chemical Co., Ltd., which has moderate fluidity (can absorb the irregularities of the conductor pattern 2), and the like can be suitably used. Other conditions for the lamination process may be the same as those in the first embodiment.

前記積層工程の後、図3(C)のようにスライス工程において、前記積層工程で得た積層基板をマルチワイヤーソー、マルチブレードソー等の切断手段で帯状導体パターン2を横断する切断線Pで切断し、積層スライス体20Aを作製する。   After the laminating step, in the slicing step as shown in FIG. 3C, the laminated substrate obtained in the laminating step is cut along a cutting line P that crosses the strip-shaped conductor pattern 2 by a cutting means such as a multi-wire saw or a multi-blade saw. Cut to produce a laminated slice 20A.

次に、図4(A)のように、架橋導体形成工程にて積層スライス体20Aの切断面に露出した帯状導体パターン2の端部同士(上下1組のコア基板1Aのパターン同士)を接続する架橋導体パターン21を形成する。ここで、架橋導体パターン21は対をなす2枚のコア基板1Aの帯状導体パターン2と共にヘリカルコイルを構成するものであり、架橋導体パターン21の形成は、帯状導体パターン2の場合と同様の、サブトラクティブ法、セミアディティブ法、あるいはフルアディティブ法等による導体層のパターニングで行うことができる。   Next, as shown in FIG. 4A, the ends of the strip-like conductor pattern 2 exposed on the cut surface of the laminated slice body 20A in the bridged conductor forming step (the patterns of the upper and lower sets of core substrate 1A) are connected to each other. The bridge | crosslinking conductor pattern 21 to be formed is formed. Here, the bridging conductor pattern 21 constitutes a helical coil together with the strip-shaped conductor pattern 2 of the two core substrates 1A that make a pair, and the formation of the bridging conductor pattern 21 is the same as in the case of the strip-shaped conductor pattern 2. The conductive layer can be patterned by a subtractive method, a semi-additive method, a full additive method, or the like.

以後、図4(B)の保護層形成工程、同図(C)の端子電極形成工程及び同図(D)のチップ分離工程は第1の実施の形態と同様に行うことができる。但し、チップ分離工程において、第1の実施の形態では層間絶縁層の部分を切断したが、この第6の実施の形態ではコア基板1Aの厚みの中間位置を切断線Q1で切断する。その他は、第1の実施の形態と同一又は相当部分に同一の符号を付して詳細は省略する。   Thereafter, the protective layer forming step in FIG. 4B, the terminal electrode forming step in FIG. 4C, and the chip separating step in FIG. 4D can be performed in the same manner as in the first embodiment. However, in the chip separation step, the portion of the interlayer insulating layer is cut in the first embodiment, but in the sixth embodiment, the intermediate position of the thickness of the core substrate 1A is cut along the cutting line Q1. In other respects, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and details thereof are omitted.

この第6の実施の形態によれば、無機焼結体コア基板1Aの片面のみに帯状導体パターン2を形成すればよく、工程の簡素化が図れる。また、基板両面に帯状導体パターン2を形成した場合に問題となる、表裏の導体パターンのアライメントのずれに起因する歩留まり低下を避けることができる。   According to the sixth embodiment, the strip-like conductor pattern 2 may be formed only on one surface of the inorganic sintered body core substrate 1A, and the process can be simplified. In addition, it is possible to avoid a decrease in yield due to misalignment between the front and back conductor patterns, which becomes a problem when the strip-like conductor patterns 2 are formed on both surfaces of the substrate.

なお、第6の実施の形態における積層工程での積層方法としては、コア基板の片面に平行帯状導体パターンを形成したものを、当該平行帯状導体パターンを形成している面を交互に反転して積層することも可能である。   In addition, as a laminating method in the laminating step in the sixth embodiment, a method in which a parallel strip conductor pattern is formed on one side of a core substrate, and a surface on which the parallel strip conductor pattern is formed are alternately inverted. It is also possible to laminate.

図5及び図6で本発明の第7の実施の形態を説明する。まず、図5(A)のように、帯状導体作製工程では、無機焼結体コア基板1を用意し、その無機焼結体コア基板1に複数個所形成された表裏アライメント用スルーホール9を利用して、無機焼結体コア基板1の表裏面に複数の平行帯状導体パターン2を形成する。この工程は第1の実施の形態と同様である。   A seventh embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 5A, in the band-shaped conductor manufacturing process, an inorganic sintered body core substrate 1 is prepared, and front and back alignment through holes 9 formed in a plurality of locations on the inorganic sintered body core substrate 1 are used. Then, a plurality of parallel strip conductor patterns 2 are formed on the front and back surfaces of the inorganic sintered body core substrate 1. This step is the same as in the first embodiment.

次に、図5(B)のように、第1積層工程では、前記帯状導体作製工程で平行帯状導体パターン2が表裏に形成された無機焼結体コア基板1に対して、その表裏に層間絶縁層(プリプレグ、あるいは接着シート)4を重ねて加圧、加熱等を施して積層一体化し、基板表裏が層間絶縁層4で覆われた積層体5を作製する。層間絶縁層4は、プリプレグとしては、例えばビニルベンジル樹脂を用いたもの、あるいは、接着シートとしては適度に流動性を有する(導体パターン2の凹凸を吸収できる)もの、例えば日立化成社製接着フィルムGF3600等が好適に使用できる。なお、積層体5上下面は互いに平行な平面に形成され、また積層体5の厚み精度を出すために、必要に応じて研磨処理を施すことも好ましい。   Next, as shown in FIG. 5B, in the first laminating step, the inorganic sintered core substrate 1 on which the parallel strip-shaped conductor pattern 2 is formed on the front and back in the strip-shaped conductor manufacturing step, the interlayer is formed on the front and back. An insulating layer (prepreg or adhesive sheet) 4 is stacked and pressurized, heated, etc., and laminated and integrated to produce a laminate 5 in which the substrate front and back are covered with the interlayer insulating layer 4. The interlayer insulating layer 4 is, for example, one using a vinyl benzyl resin as a prepreg, or one having moderate fluidity as an adhesive sheet (can absorb the irregularities of the conductor pattern 2), for example, an adhesive film manufactured by Hitachi Chemical Co., Ltd. GF3600 etc. can be used conveniently. Note that the upper and lower surfaces of the laminated body 5 are formed in planes parallel to each other, and it is also preferable to perform a polishing treatment as necessary in order to increase the thickness accuracy of the laminated body 5.

その後、図5(C)のように、第2積層工程において、積層体5と接着層となる接着シート6とを交互に積み重ねて、熱プレスもしくは真空プレスで一括積層し積層基板10Bを作製する。その際、積層体5は上から見て正確に重なるようにアライメントを行う必要がある。アライメントの方法は第1の実施の形態と同様に行うことができる。   Thereafter, as shown in FIG. 5C, in the second laminating step, the laminate 5 and the adhesive sheet 6 serving as an adhesive layer are alternately stacked, and are laminated together by heat press or vacuum press to produce a laminate substrate 10B. . In that case, it is necessary to align so that the laminated body 5 may overlap correctly seeing from the top. The alignment method can be performed in the same manner as in the first embodiment.

この第2積層工程において使用する接着シート6の材質はプレス時に出来るだけ流動性のないものが好ましい。このために、例えば接着シートの樹脂の硬化度を上げる等の手法が適用出来る。この接着シート6には、流動性の少ない日立化成社製接着フィルムGF3500等が好適に使用できる。なお、接着シート6の厚みは出来るだけ薄い方が積層方向のピッチ精度の向上の為(架橋導体パターン21の位置合わせの為)には好ましい。さらに、接着シート6として導電性を有するものを使用しても良い。例を挙げると真鍮またはアルミ基板の表裏面に薄く接着剤を塗布したもの等がある。これにより工程内の基板及び積層体の機械的強度をさらに向上させることが可能で、またピッチ精度も良くなる。   The material of the adhesive sheet 6 used in the second laminating step is preferably a material having as little fluidity as possible at the time of pressing. For this purpose, for example, a technique such as increasing the degree of curing of the resin of the adhesive sheet can be applied. For the adhesive sheet 6, an adhesive film GF3500 manufactured by Hitachi Chemical Co., Ltd. with little fluidity can be suitably used. The adhesive sheet 6 is preferably as thin as possible for improving the pitch accuracy in the stacking direction (for aligning the cross-linked conductor pattern 21). Further, a conductive sheet may be used as the adhesive sheet 6. For example, a thin adhesive is applied to the front and back surfaces of a brass or aluminum substrate. As a result, the mechanical strength of the substrate and the laminate in the process can be further improved, and the pitch accuracy is improved.

以後、図5(D)のスライス工程、図6(A)の架橋導体形成工程、同図(B)の保護層形成工程、同図(C)の端子電極形成工程及び同図(D)のチップ分離工程は第1の実施の形態と同様に行うことができる。第5の実施の形態と同一又は相当部分に同一の符号を付して詳細は省略する。   Thereafter, the slicing step in FIG. 5D, the bridging conductor forming step in FIG. 6A, the protective layer forming step in FIG. 5B, the terminal electrode forming step in FIG. 5C, and the FIG. The chip separation step can be performed in the same manner as in the first embodiment. The same reference numerals are given to the same or corresponding parts as those in the fifth embodiment, and the details are omitted.

この第7の実施の形態によれば、第1積層工程では層間絶縁層4をできるだけ薄くし、当該層間絶縁層形成後の積層体5の厚み精度を高くし(必要ならばグラインダー等による研削、研磨を行い)、かつ第2積層工程では接着シート6をできるだけ薄くかつプレス時の流動性が少ないものを用いることで、積層基板10Bに含まれるインダクティブデバイスとなる素子の積層方向のピッチ精度が良好となり、図6(A)の架橋導体形成工程における架橋導体パターン21と帯状導体パターン2間の位置ずれが発生しにくくなり、いっそうの歩留まり向上を図り得る。なお、その他の作用効果は第5の実施の形態と同様である。   According to the seventh embodiment, in the first stacking step, the interlayer insulating layer 4 is made as thin as possible, and the thickness accuracy of the stacked body 5 after forming the interlayer insulating layer is increased (if necessary, grinding with a grinder, etc. Polishing is performed), and in the second lamination step, the adhesive sheet 6 is made as thin as possible and the fluidity at the time of pressing is low, so that the pitch accuracy in the laminating direction of the element that becomes the inductive device included in the laminated substrate 10B is good. Thus, it is difficult for positional deviation between the cross-linked conductor pattern 21 and the strip-shaped conductor pattern 2 in the cross-linked conductor forming step of FIG. 6A to occur, and the yield can be further improved. Other effects are the same as in the fifth embodiment.

上記第7の実施の形態は、無機焼結体コア基板片面のみに帯状導体パターンを形成した場合にも適用可能である。この場合、第2の実施の形態と同様に、対をなす上下のコア基板の帯状導体パターン同士を架橋導体パターンで接続後、コア基板の厚み中間位置を切断すればよい。但し、接着層は絶縁性のものに限定される。   The seventh embodiment can also be applied to the case where a band-like conductor pattern is formed only on one surface of the inorganic sintered body core substrate. In this case, similarly to the second embodiment, after connecting the strip-like conductor patterns of the upper and lower core substrates forming a pair with the bridging conductor pattern, the intermediate thickness position of the core substrate may be cut. However, the adhesive layer is limited to an insulating layer.

図10で本発明の第8の実施の形態を説明する。図10(A)の帯状導体作製工程のように、芯材を有する有機コア基板1の表裏面に複数の平行帯状導体パターン2を形成する。前記コア基板1は、ガラスクロス、ケプラー等の樹脂クロス、フッ素樹脂(商品名:テフロン)の多孔質シート等の芯材に樹脂を含浸させてなる樹脂板を芯材で補強したものを使用できる。また、主材質である樹脂に例えば線膨張係数の制御や電気的特性の向上を目的として、球状シリカフィラーを添加したもの、チタン酸バリウム等の強誘電体粉末を添加したもの、フェライト粉末を添加したもの(複合フェライト)等も好ましく用いられる。樹脂の種類は高周波コイル等の高周波部品にはビニルベンジル樹脂のような高Q、低誘電率材が好ましい。   The eighth embodiment of the present invention will be described with reference to FIG. Like the strip | belt-shaped conductor preparation process of FIG. 10 (A), the some parallel strip | belt-shaped conductor pattern 2 is formed in the front and back of the organic core board | substrate 1 which has a core material. The core substrate 1 may be made by reinforcing a resin plate made by impregnating a resin with a core material such as a glass cloth, a resin cloth such as a Kepler, or a porous sheet of fluororesin (trade name: Teflon). . In addition, for the purpose of controlling the linear expansion coefficient and improving electrical characteristics, for example, the resin that is the main material is added with spherical silica filler, the addition of ferroelectric powder such as barium titanate, and the addition of ferrite powder Those obtained (composite ferrite) are also preferably used. The type of resin is preferably a high-Q, low-dielectric constant material such as vinylbenzyl resin for high-frequency parts such as a high-frequency coil.

前記複数の平行帯状導体パターン2の形成は、前述の第1の実施の形態と同様の工法で行うことができる。   The formation of the plurality of parallel strip conductor patterns 2 can be performed by the same method as in the first embodiment.

次に、図10(B)のように、積層工程では、芯材を有する有機コア基板1の表裏面に複数の平行帯状導体パターン2を形成したものと無機焼結体コア基板50とを、接着性層間絶縁層(接着シート)51を介して交互に複数枚積み重ね、加熱、加圧して積層一体化し、積層基板60を得る。   Next, as shown in FIG. 10B, in the laminating step, the inorganic sintered body core substrate 50 having a plurality of parallel strip conductor patterns 2 formed on the front and back surfaces of the organic core substrate 1 having a core material, A plurality of sheets are alternately stacked via an adhesive interlayer insulating layer (adhesive sheet) 51, and heated and pressed to be laminated and integrated to obtain a laminated substrate 60.

前記積層工程の後、図10(C)のようにスライス工程において、前記積層工程で得た積層基板60をマルチワイヤーソー、マルチブレードソー等の切断手段で帯状導体パターン2を横断する切断線Pで切断し、積層スライス体70を作製する。   After the laminating step, in the slicing step as shown in FIG. 10C, a cutting line P crossing the strip-shaped conductor pattern 2 with the cutting means such as a multi-wire saw and a multi-blade saw in the laminating step in the laminating step. The laminated sliced body 70 is produced by cutting.

次に、図10(D)のように、架橋導体形成工程にて積層スライス体70の切断面に露出した帯状導体パターン2の端部同士を接続する架橋導体パターン21を形成する。ここで、架橋導体パターン21は無機焼結体コア基板50を挟んで対をなす2枚の有機コア基板1の帯状導体パターン2と共にヘリカルコイルを構成するものであり、架橋導体パターン21の形成は、帯状導体パターン2の場合と同様の、サブトラクティブ法、セミアディティブ法、あるいはフルアディティブ法等による導体層のパターニングで行うことができる。   Next, as shown in FIG. 10D, a bridged conductor pattern 21 that connects the ends of the strip-like conductor pattern 2 exposed on the cut surface of the laminated slice 70 in the bridged conductor forming step is formed. Here, the bridging conductor pattern 21 constitutes a helical coil together with the strip-like conductor pattern 2 of the two organic core substrates 1 that are paired with the inorganic sintered body core substrate 50 interposed therebetween. The conductive layer can be patterned by the subtractive method, the semi-additive method, the full-additive method, or the like, as in the case of the strip-shaped conductor pattern 2.

以後の工程は、第1の実施の形態における図2(B),(C),(D)と同様に行うことができる。但し、チップ分離工程において、第1の実施の形態では層間絶縁層の部分を切断したが、この第8の実施の形態では有機コア基板の厚みの中間位置(図10(D)の仮想線S)を切断する。   The subsequent steps can be performed in the same manner as in FIGS. 2B, 2C, and 2D in the first embodiment. However, in the chip separation step, the portion of the interlayer insulating layer is cut in the first embodiment, but in the eighth embodiment, the intermediate position of the thickness of the organic core substrate (the virtual line S in FIG. 10D). ).

この第8の実施の形態の場合も、前述した第5の実施の形態と同様の効果が得られる。   In the case of the eighth embodiment, the same effects as those of the fifth embodiment described above can be obtained.

図9はコア基板の表裏に形成する帯状導体パターンの例であり、同図(A)は各実施の形態で例示した平行帯状導体パターン2を示す。また、図9(B)は帯状導体パターン2の変形例であり、端子電極の強度アップの為に基板端部に帯状導体パターンの接続端部となる幅広導体28を埋め込んだ例である。図9(C)はインダクティブデバイスが低インダクタンス品の場合で、帯状導体パターン2の中間のものを斜めに配置した別の変形例である。   FIG. 9 shows an example of a strip-shaped conductor pattern formed on the front and back of the core substrate, and FIG. 9A shows the parallel strip-shaped conductor pattern 2 exemplified in each embodiment. FIG. 9B shows a modified example of the strip-shaped conductor pattern 2 in which a wide conductor 28 serving as a connection end portion of the strip-shaped conductor pattern is embedded in the end portion of the substrate in order to increase the strength of the terminal electrode. FIG. 9C shows another modification in which the inductive device is a low-inductance product, and the middle one of the strip-shaped conductor pattern 2 is arranged obliquely.

以下、本発明を実施例で詳述する。   Hereinafter, the present invention will be described in detail with reference to examples.

図1及び図2参照:下記に各工程の詳細を示す。   See FIG. 1 and FIG. 2: The details of each step are shown below.

(1)帯状導体作製工程
芯材を有する有機コア基板としてガラスクロス入りビニルベンジル樹脂基板(76mm角、厚さ350μm)を用意した。次に有機コア基板の表裏面にそれぞれ平行帯状導体パターンをセミアディティブ工法で銅めっきで作成した。パターンは、導体幅:35μm(端部は100μm)、導体間隔:20μm、導体高さ:35μmとした。なお、表裏のアライメントは直径0.2mmの穴を前記基板の2カ所にドリルで開けてアライメントマークとして行った。
(1) Band-shaped conductor manufacturing process A glass cloth-containing vinylbenzyl resin substrate (76 mm square, thickness 350 μm) was prepared as an organic core substrate having a core material. Next, parallel strip conductor patterns were formed on the front and back surfaces of the organic core substrate by copper plating by a semi-additive method, respectively. In the pattern, the conductor width was 35 μm (the end was 100 μm), the conductor interval was 20 μm, and the conductor height was 35 μm. The front and back alignment was performed as an alignment mark by drilling holes with a diameter of 0.2 mm at two locations on the substrate.

(2)積層工程
上記で帯状導体パターンを作製した有機コア基板と層間絶縁層を交互に積み重ね真空プレスで加熱、加圧して一括積層し積層基板とした。コア基板の積層の枚数はプレス後の厚さが76mmになるように設定した(138枚)。層間絶縁層は200μm厚ガラスクロス入りビニルベンジル樹脂プリプレグを用いた。アライメントは各基板の四隅に直径5mmの穴を平行電極パターンに対して一定の位置に開けてピンアライメントにて行った。
(2) Lamination process The organic core board | substrate and interlayer insulation layer which produced the strip | belt-shaped conductor pattern above were piled up alternately, and it heated and pressurized with the vacuum press, and was laminated | stacked collectively, and it was set as the laminated board. The number of laminated core substrates was set so that the thickness after pressing was 76 mm (138 sheets). As the interlayer insulating layer, a vinylbenzyl resin prepreg containing 200 μm thick glass cloth was used. The alignment was performed by pin alignment with holes having a diameter of 5 mm formed at the four corners of each substrate at fixed positions with respect to the parallel electrode pattern.

(3)スライス工程
マルチワイヤーソーで切断後の厚みが0.45mmになるように前記積層基板を切断し、積層スライス体とした。その後、スライス面の両面を50μmずつ研磨処理し、積層スライス体の厚さを350μmに調整した。
(3) Slicing step The laminated substrate was cut so that the thickness after cutting with a multi-wire saw was 0.45 mm to obtain a laminated sliced body. Thereafter, both sides of the sliced surface were polished by 50 μm, and the thickness of the laminated sliced body was adjusted to 350 μm.

(4)架橋導体形成工程
架橋導体パターンはセミアディティブ工法で銅めっきで作成した。パターンは、導体幅:35μm(端部は100μm)、導体間隔:20μm、導体高さ:35μmとした。
(4) Bridged conductor formation process The bridged conductor pattern was created by copper plating by a semi-additive method. In the pattern, the conductor width was 35 μm (the end was 100 μm), the conductor interval was 20 μm, and the conductor height was 35 μm.

(5)保護層形成工程
50μm厚ビニルベンジル樹脂で保護層を形成した。ビアホールはサンドブラスト法で保護層に形成した。
(5) Protective layer formation process The protective layer was formed with 50-micrometer-thick vinyl benzyl resin. Via holes were formed in the protective layer by sandblasting.

(6)端子電極形成工程
セミアディティブ法によって銅の端子電極を形成した。チップ分離後端子電極上にバレルめっきでニッケル層1μm、その上に錫層2μm形成した。
(6) Terminal electrode formation process The copper terminal electrode was formed by the semi-additive method. After chip separation, a nickel layer of 1 μm was formed on the terminal electrode by barrel plating, and a tin layer of 2 μm was formed thereon.

(7)チップ分離工程
ダイシングで切断した。
(7) Chip separation step Dicing was performed.

(8)歩留まりについて
スライス基板を10枚作製した場合の歩留まりは、工程内歩留まり100%であり、基板1枚当たり約1万個、基板10枚で計約10万個作製したうち100個をサンプルとして特性検査を行ったときの特性検査歩留まり65%(主な不良原因はパターンずれによる断線)、一貫歩留まり65%であった。
工程内歩留まり={(基板投入枚数−ウエハアウト基板枚数)/(基板投入枚数)}×100(%)
(ウエハアウト基板枚数:割れ、外観不良等の理由で工程内で除去した基板枚数)
特性検査の判定基準はインダクタンス値:基準値±2%、1GHzでのQ≧45、直流抵抗Rdc:基準値±30%とした。また良品のインダクタンス値(L値)バラツキは3σ/Xで3.2%であった(但し、σ:標準偏差、X:平均値)。
(一貫歩留まり)=(工程内歩留まり)×(特性検査歩留まり)
(8) Yield Yield when 10 sliced substrates are manufactured is 100% in process yield, about 10,000 pieces per substrate, about 100 out of a total of about 100,000 produced with 10 substrates When the characteristic inspection was performed, the characteristic inspection yield was 65% (the main cause of failure was disconnection due to pattern deviation), and the consistent yield was 65%.
Yield in process = {(number of substrates loaded−number of substrates out of wafer) / (number of substrates loaded)} × 100 (%)
(Number of wafer-out substrates: Number of substrates removed in the process due to cracks, poor appearance, etc.)
The determination criteria for the characteristic inspection were inductance value: reference value ± 2%, Q ≧ 45 at 1 GHz, DC resistance Rdc: reference value ± 30%. Moreover, the inductance value (L value) variation of non-defective products was 3.2% at 3σ / X (where σ: standard deviation, X: average value).
(Consistent yield) = (in-process yield) x (characteristic inspection yield)

比較例1
実施例1でコア基板に芯材クロスを入れない場合、歩留まりは工程内歩留まり20%(不良原因は工程内の割れ)、検査歩留まり20%(主な不良原因はパターンずれによる断線)、一貫歩留まり4%である。また良品のインダクタンス値バラツキは3σ/Xで6.7%であった。
Comparative Example 1
When the core material cloth is not inserted into the core substrate in Example 1, the yield is 20% in the process (the cause of failure is cracking in the process), the inspection yield is 20% (the main cause of failure is disconnection due to pattern deviation), and the consistent yield. 4%. The inductance value variation of the non-defective product was 6.7% at 3σ / X.

図3及び図4参照、下記以外は実施例1と同じ。   3 and 4, the same as Example 1 except for the following.

(1)帯状導体作製工程
パターニングは片面のみに行った。
(1) Strip conductor manufacturing process Patterning was performed only on one side.

(2)積層工程
層間絶縁層は50μm厚クロスなしビニルベンジル樹脂プリプレグを用いた。
(2) Laminating process As the interlayer insulating layer, a vinylbenzyl resin prepreg having a thickness of 50 μm and having no cloth was used.

(3)歩留まりについて
スライス基板を10枚作製した場合の歩留まりは、工程内歩留まり100%、検査歩留まり72%(主な不良原因はパターンずれによる断線)、一貫歩留まり72%である。また良品のインダクタンス値バラツキは3σ/Xで2.1%であった。実施例1に比べての歩留まりの改善は上下の対をなす帯状導体パターン同士のアライメント精度の向上に起因する。
(3) Yield When 10 slice substrates are manufactured, the yield is 100% in the process, the inspection yield is 72% (the main cause of failure is disconnection due to pattern deviation), and the consistent yield is 72%. The inductance value variation of non-defective products was 2.1% at 3σ / X. The improvement in yield compared to Example 1 is due to the improvement in alignment accuracy between the strip-like conductor patterns that form a pair in the upper and lower sides.

なお、実施例2における積層工程での積層方法としては、コア基板の片面に平行帯状導体パターンを形成したものを、当該平行帯状導体パターンを形成している面を交互に反転して積層することも可能である。   In addition, as a lamination | stacking method in the lamination | stacking process in Example 2, what formed the parallel strip | belt-shaped conductor pattern in the single side | surface of a core substrate is laminated | stacked by alternately inverting the surface in which the said parallel strip | belt-shaped conductor pattern is formed. Is also possible.

図5及び図6参照、下記以外は実施例1と同じ。   5 and FIG. 6, the same as Example 1 except for the following.

(1)第1積層工程、
ガラスクロス入りビニルベンジル樹脂基板を100μm厚ビニルベンジル樹脂プリプレグで挟み込んで積層した。両面を40μmずつ削り、基板を含む積層体の厚さを470μmに調整した(積層体厚みの精度出しの為)。
(1) 1st lamination process,
A glass cloth-containing vinylbenzyl resin substrate was sandwiched and laminated by a 100 μm-thick vinylbenzyl resin prepreg. Both sides were cut by 40 μm, and the thickness of the laminate including the substrate was adjusted to 470 μm (to increase the accuracy of the laminate thickness).

(2)第2積層工程
エポキシ接着シートは厚さ20μmでプレス時に殆ど流動しないタイプ(日立化成社製接着フィルムGF3500)を使用した。
(2) Second Laminating Step The epoxy adhesive sheet was 20 μm thick and used a type that hardly flows during pressing (adhesive film GF3500 manufactured by Hitachi Chemical Co., Ltd.).

(3)歩留まりについて
スライス基板を10枚作製した場合の歩留まりは、工程内歩留まり100%、検査歩留まり83%(主な不良原因はパターンずれによる断線)、一貫歩留まり83%である。また良品のインダクタンス値バラツキは3σ/Xで1.5%であった。実施例1に比べての歩留まりの改善は、図5及び図6の断面図の縦方向のピッチの精度の向上に起因する。
(3) Yield When 10 sliced substrates are manufactured, the yield is 100% in the process, the inspection yield is 83% (the main cause of failure is disconnection due to pattern deviation), and the consistent yield is 83%. The inductance value variation of the non-defective product was 1.5% at 3σ / X. The improvement in yield compared to Example 1 is attributed to the improvement in the accuracy of the pitch in the vertical direction of the cross-sectional views of FIGS.

下記以外は実施例3と同じ。   Same as Example 3 except for the following.

(1)帯状導体作製工程
パターニングは片面のみに行った。
(1) Strip conductor manufacturing process Patterning was performed only on one side.

(2)第1積層工程、
ガラスクロス入りビニルベンジル樹脂基板の帯状導体作製面に100μm厚ビニルベンジル樹脂プリプレグを積層した。プリプレグ側の面を40μm削り、積層体厚みの精度出しを行った。
(2) first lamination step,
A 100 μm-thick vinylbenzyl resin prepreg was laminated on the surface of the belt-like conductor production surface of the glass cloth-containing vinylbenzyl resin substrate. The surface on the prepreg side was shaved by 40 μm to obtain an accurate thickness of the laminate.

(3)歩留まりについて
スライス基板を10枚作製した場合の歩留まりは、工程内歩留まり100%、検査歩留まり86%(主な不良原因はパターンずれによる断線)、一貫歩留まり86%である。また良品のインダクタンス値バラツキは3σ/Xで1.4%であった。実施例1に比べての歩留まりの改善は、積層体縦方向のピッチの精度の向上に起因する。
(3) Yield When 10 slice substrates are manufactured, the yield is 100% in the process, the inspection yield is 86% (the main cause of failure is disconnection due to pattern shift), and the consistent yield is 86%. Moreover, the inductance value variation of the non-defective product was 1.4% at 3σ / X. The improvement in yield compared to Example 1 is attributed to the improvement in the accuracy of the pitch in the longitudinal direction of the laminate.

なお、実施例4における積層工程での積層方法としては、コア基板の片面に平行帯状導体パターンを形成したものを、当該平行帯状導体パターンを形成している面を交互に反転して積層することも可能である。   In addition, as a laminating method in the laminating process in Example 4, the one in which the parallel strip conductor pattern is formed on one surface of the core substrate is laminated by alternately inverting the surface on which the parallel strip conductor pattern is formed. Is also possible.

図7及び図8参照   See FIG. 7 and FIG.

(1)帯状導体作製工程
転写用基板としての0.1mm厚(76mm角)のステンレス薄板(SUS304材)を用い、その上に平行帯状導体パターンをパターンメッキ法で形成した。パターンは導体幅:35μm(端部は100μm)、導体間隔:20μm、高さ:35μmとした。コア基板は150μm厚ガラスクロス入りビニルベンジル樹脂基板を用いた。このコア基板は、半硬化状(Bステージ状)のガラスクロス入りビニルベンジル樹脂プリプレグを上記転写用基板上に重ね、真空プレスにて加圧、加熱し、プリプレグを硬化した後、転写用基板を剥離し、帯状導体パターンを転写して作製した。
(1) Band-shaped conductor manufacturing process A 0.1 mm thick (76 mm square) stainless steel thin plate (SUS304 material) was used as a transfer substrate, and a parallel band-shaped conductor pattern was formed thereon by a pattern plating method. The pattern had a conductor width: 35 μm (the end was 100 μm), a conductor interval: 20 μm, and a height: 35 μm. As the core substrate, a vinylbenzyl resin substrate containing 150 μm thick glass cloth was used. For this core substrate, a semi-cured (B-stage) glass benzyl resin prepreg containing glass cloth is stacked on the above-mentioned transfer substrate, pressurized and heated with a vacuum press to cure the prepreg, and then the transfer substrate is It peeled and produced by transferring a strip | belt-shaped conductor pattern.

(2)基板厚さ調整工程
帯状導体パターンのない面を研磨処理し、コア基板の厚さを400μmに調整した。
(2) Substrate thickness adjustment step The surface without the strip-shaped conductor pattern was polished to adjust the thickness of the core substrate to 400 μm.

(3)積層工程
厚さ10μmのビニルベンジル樹脂製接着シートで真空プレスを行った。
(3) Lamination process Vacuum pressing was performed with an adhesive sheet made of vinylbenzyl resin having a thickness of 10 μm.

(4)歩留まりについて
スライス基板を10枚作製した場合の歩留まりは、工程内歩留まり100%、検査歩留まり90%(主な不良原因はパターンずれによる断線)、一貫歩留まり90%であった。また良品のインダクタンス値バラツキは3σ/Xで1.2%であった。実施例1に比べての歩留まりの改善は上下の対をなす帯状導体パターン同士のアライメント精度の向上及び図7及び図8における縦方向のピッチの精度の向上に起因する。
(4) Yield When 10 slice substrates were produced, the yield was 100% in the process, the inspection yield was 90% (the main cause of failure was disconnection due to pattern deviation), and the consistent yield was 90%. The inductance value variation of the non-defective product was 1.2% at 3σ / X. The improvement in yield compared to Example 1 is attributed to the improvement in alignment accuracy between the upper and lower strip-like conductor patterns and the improvement in pitch accuracy in the vertical direction in FIGS.

なお、実施例5における積層工程での積層方法としては、コア基板の片面に平行帯状導体パターンを形成したものを、当該平行帯状導体パターンを形成している面を交互に反転して積層することも可能である。   In addition, as a lamination | stacking method in the lamination | stacking process in Example 5, what formed the parallel strip | belt-shaped conductor pattern in the single side | surface of a core board | substrate is laminated | stacked by alternately inverting the surface in which the said parallel strip | belt-shaped conductor pattern is formed. Is also possible.

図10参照:下記に各工程の詳細を示す。   See FIG. 10: Details of each step are shown below.

(1)帯状導体作製工程
芯材を有する有機コア基板としてガラスクロス入りビニルベンジル樹脂基板(70mm角、厚さ200μm)を用意した。次に有機コア基板の表裏面にそれぞれ平行帯状導体パターンをセミアディティブ工法で銅めっきにて作製した。パターンは、導体幅:35μm、導体間隔:20μm、導体高さ:30μmとした。なお、表裏のアライメントは、直径0.2mmの穴を前記基板の2箇所にドリルで開けてアライメントマークとして行った。
(1) Band-shaped conductor manufacturing process A vinyl cloth resin substrate with glass cloth (70 mm square, thickness 200 μm) was prepared as an organic core substrate having a core material. Next, parallel strip conductor patterns were respectively formed on the front and back surfaces of the organic core substrate by copper plating by a semi-additive method. The pattern was conductor width: 35 μm, conductor spacing: 20 μm, and conductor height: 30 μm. The front and back alignment was performed as an alignment mark by drilling holes with a diameter of 0.2 mm at two locations on the substrate.

(2)積層工程
上記で帯状導体パターンを作製した有機コア基板と無機焼結体コア基板とを接着性層間絶縁層(接着シート)を介して交互に複数枚積み重ね、加熱、加圧して積層一体化し、積層基板とした。コア基板の積層の枚数はプレス後の厚さが40mmになるように設定した(80枚)。層間絶縁層は50μmのエポキシ系接着シートを用いた。無機焼結体コア基板は、フェライト(Ni−Co系)を用いた。アライメントは、各基板の四隅に直径5mmの穴を平行電極パターンに対して一定の位置に開けてピンアライメントにて行った。
(2) Laminating step A plurality of organic core substrates and inorganic sintered core substrates with the band-shaped conductor patterns prepared above are alternately stacked via an adhesive interlayer insulating layer (adhesive sheet), and heated and pressed to laminate them. To obtain a laminated substrate. The number of laminated core substrates was set so that the thickness after pressing was 40 mm (80 sheets). The interlayer insulating layer was a 50 μm epoxy adhesive sheet. Ferrite (Ni-Co series) was used for the inorganic sintered body core substrate. Alignment was performed by pin alignment with holes having a diameter of 5 mm formed at four corners of each substrate at fixed positions with respect to the parallel electrode pattern.

(3)スライス工程
マルチワイヤーソーで切断後の厚みが0.45mmになるように前記積層基板を切断し、積層スライス体とした。その後、スライス面の両面を50μmずつ研磨処理し、積層スライス体の厚さを350μmに調整した。
(3) Slicing step The laminated substrate was cut so that the thickness after cutting with a multi-wire saw was 0.45 mm to obtain a laminated sliced body. Thereafter, both sides of the sliced surface were polished by 50 μm, and the thickness of the laminated sliced body was adjusted to 350 μm.

(4)架橋導体形成工程
架橋導体パターンは、セミアディティブ工法で銅めっきにて作製した。パターンは、導体幅:35μm、導体間隔20μm、導体高さ:30μmとした。
(4) Bridged conductor formation process The bridged conductor pattern was produced by copper plating by a semi-additive method. The pattern was a conductor width: 35 μm, a conductor interval of 20 μm, and a conductor height: 30 μm.

(5)保護層形成工程
50μm厚ビニルベンジル樹脂で保護層を形成した。ビアホールはサンドブラスト法で保護層に形成した。
(5) Protective layer formation process The protective layer was formed with 50-micrometer-thick vinyl benzyl resin. Via holes were formed in the protective layer by sandblasting.

(6)端子電極形成工程
セミアディティブ工法によって銅の端子電極を形成した。チップ分離後端子電極上にバレルめっきでニッケル層1μm、その上に錫層2μm形成した。
(6) Terminal electrode formation process The copper terminal electrode was formed by the semi-additive construction method. After chip separation, a nickel layer of 1 μm was formed on the terminal electrode by barrel plating, and a tin layer of 2 μm was formed thereon.

(7)チップ分離工程
ダイシングで切断した。
(7) Chip separation step Dicing was performed.

(8)歩留まりについて
スライス基板を10枚作製した場合の歩留まりは、工程内歩留まり100%、検査歩留まり88%(主な不良原因はパターンずれによる断線)、一貫歩留まり88%である。また、良品のインダクタンス値バラツキは3σ/Xで1.3%であった。実施例1に比べて歩留まりの改善は、図10断面図の、縦方向のピッチ精度の向上に起因する。
(8) Yield When 10 slice substrates are manufactured, the yield is 100% in the process, the inspection yield is 88% (the main cause of failure is disconnection due to pattern deviation), and the consistent yield is 88%. Moreover, the inductance value variation of the non-defective product was 1.3% at 3σ / X. The improvement in yield compared to Example 1 is attributed to the improvement in pitch accuracy in the vertical direction in the cross-sectional view of FIG.

(9)インダクタンス値について
50MHzにおけるインダクタンス値は、実施例1のコイルと比較しておよそ10倍となった。これは、無機焼結体コア基板(Ni−Co系フェライト)を使用したことにより、透磁率が高くなったことに起因する。
(9) Inductance value The inductance value at 50 MHz was about 10 times that of the coil of Example 1. This is due to the increase in the magnetic permeability due to the use of the inorganic sintered body core substrate (Ni-Co ferrite).

各実施例及び比較例の基板、電極(帯状導体パターン)、接着方法(積層方法)、歩留まりを以下の表1にまとめて示す。   Table 1 below collectively shows the substrates, electrodes (strip-shaped conductor patterns), adhesion methods (lamination methods), and yields of the examples and comparative examples.

Figure 0003827314
Figure 0003827314

また、実施例1と実施例6のインダクタンス値を対比したものを以下の表2に示す。   Table 2 below shows a comparison of the inductance values of Example 1 and Example 6.

Figure 0003827314
Figure 0003827314

以上本発明の実施の形態及び実施例について説明してきたが、本発明はこれに限定されることなく請求項の記載の範囲内において各種の変形、変更が可能なことは当業者には自明であろう。   Although the embodiments and examples of the present invention have been described above, it is obvious to those skilled in the art that the present invention is not limited thereto and various modifications and changes can be made within the scope of the claims. I will.

本発明の第1及び第5の実施の形態における工程の前半部分を示す断面図及び平面図である。It is sectional drawing and a top view which show the first half part of the process in the 1st and 5th embodiment of this invention. 第1及び第5の実施の形態における工程の後半部分を示す断面図及び平面図である。It is sectional drawing and a top view which show the latter half part of the process in 1st and 5th embodiment. 第2及び第6の実施の形態における工程の前半部分を示す断面図及び平面図である。It is sectional drawing and the top view which show the first half part of the process in 2nd and 6th Embodiment. 第2及び第6の実施の形態における工程の後半部分を示す断面図及び平面図である。It is sectional drawing and a top view which show the latter half part of the process in 2nd and 6th Embodiment. 第3及び第7の実施の形態における工程の前半部分を示す断面図及び平面図である。It is sectional drawing and a top view which show the first half part of the process in 3rd and 7th Embodiment. 第3及び第7の実施の形態における工程の後半部分を示す断面図及び平面図である。It is sectional drawing and a top view which show the latter half part of the process in 3rd and 7th Embodiment. 第4の実施の形態における工程の前半部分を示す断面図及び平面図である。It is sectional drawing and a top view which show the first half part of the process in 4th Embodiment. 第4の実施の形態における工程の後半部分を示す断面図及び平面図である。It is sectional drawing and a top view which show the latter half part of the process in 4th Embodiment. 各実施の形態における帯状導体パターンの変形例を示す平面図及び底面図である。It is the top view and bottom view which show the modification of the strip | belt-shaped conductor pattern in each embodiment. 第8の実施の形態における工程を示す断面図及び平面図である。It is sectional drawing and the top view which show the process in 8th Embodiment.

符号の説明Explanation of symbols

1,1A,7,50 コア基板
2 平行帯状導体パターン
3 層間絶縁層
5 積層体
8 絶縁性接着シート
9 表裏アライメント用スルーホール
10,10A,10B,10C,60 積層基板
20,20A,70 積層スライス体
21 架橋導体パターン
25 保護層
26 ビアホール
30 端子電極
40 チップ
1, 1A, 7, 50 Core substrate 2 Parallel strip conductor pattern 3 Interlayer insulating layer 5 Laminate 8 Insulating adhesive sheet 9 Front / back alignment through hole 10, 10A, 10B, 10C, 60 Laminated substrate 20, 20A, 70 Laminated slice Body 21 Cross-linked conductor pattern 25 Protective layer 26 Via hole 30 Terminal electrode 40 Chip

Claims (18)

芯材を有する有機コア基板の表裏面に複数の帯状導体パターンを形成し、これをプリプレグ又は接着シートの絶縁層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴とするインダクティブデバイスの製造方法。
A laminating step of a plurality of band-shaped conductor patterns formed on front and rear surfaces of the organic core board having a core, which is pressed integrally stacked plurality through an insulating layer of prepreg or adhesive sheet,
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the laminated slice into individual chips so as to have at least one helical coil composed of the strip-shaped conductor pattern and the bridged conductor pattern.
芯材を有する有機コア基板の表裏面に複数の帯状導体パターン及び該複数の帯状導体パターンを覆う絶縁層を形成し、これを接着層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴とするインダクティブデバイスの製造方法。
A laminating step of forming a plurality of strip conductor patterns and an insulating layer covering the plurality of strip conductor patterns on the front and back surfaces of the organic core substrate having a core material, and stacking and pressurizing the plurality of strips via an adhesive layer; ,
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the laminated slice into individual chips so as to have at least one helical coil composed of the strip-shaped conductor pattern and the bridged conductor pattern.
芯材を有する有機コア基板の片面に複数の帯状導体パターンを形成し、これをプリプレグ又は接着シートの絶縁層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴とするインダクティブデバイスの製造方法。
A laminating step of forming a plurality of strip-like conductor patterns on one side of an organic core substrate having a core material, and stacking and compressing a plurality of them through an insulating layer of a prepreg or an adhesive sheet ; and
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the laminated slice into individual chips so as to have at least one helical coil composed of the strip-shaped conductor pattern and the bridged conductor pattern.
芯材を有する有機コア基板の片面に複数の帯状導体パターン及び該帯状導体パターンを覆う絶縁層を形成し、これを接着層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴とするインダクティブデバイスの製造方法。
A laminating step of forming an insulating layer covering the plurality of band-shaped conductor patterns and the belt-shaped conductor pattern on one surface of the organic core board having a core material is pressed integrally stacked plurality via an adhesive layer so,
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the laminated slice into individual chips so as to have at least one helical coil composed of the strip-shaped conductor pattern and the bridged conductor pattern.
前記絶縁層を研磨処理して厚さを調整することを特徴とする請求項2,3又は4記載のインダクティブデバイスの製造方法。 The method for manufacturing an inductive device according to claim 2, wherein the insulating layer is polished to adjust the thickness. 前記芯材を有する有機コア基板の前記帯状導体パターンの無い面を研磨処理して厚さを調整することを特徴とする請求項3又は4記載のインダクティブデバイスの製造方法。 5. The method for manufacturing an inductive device according to claim 3 , wherein the thickness of the organic core substrate having the core material is adjusted by polishing a surface without the strip-like conductor pattern. 前記スライス工程の後、スライス面を研磨処理して厚さを調整することを特徴とする請求項1,2,3,4,5又は6記載のインダクティブデバイスの製造方法。 The slice after the step, the manufacturing method of the inductive device of claim 2, 3, 4, 5 or 6, wherein the adjusting the thickness by polishing the slice plane. 前記芯材を有する有機コア基板は、前記帯状導体パターンが転写されて設けられている請求項1,2,3,4,5,6又は7記載のインダクティブデバイスの製造方法。 The inductive device manufacturing method according to claim 1, 2, 3, 4, 5, 6 or 7 , wherein the organic core substrate having the core material is provided by transferring the strip-shaped conductor pattern. 表裏面に複数の帯状導体パターンを形成した無機焼結体コア基板を、プリプレグ又は接着シートの絶縁層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴とするインダクティブデバイスの製造方法。
A lamination process in which a plurality of inorganic sintered body core substrates having a plurality of strip-like conductor patterns formed on the front and back surfaces are stacked and pressed together via an insulating layer of a prepreg or an adhesive sheet ; and
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the laminated slice into individual chips so as to have at least one helical coil composed of the strip-shaped conductor pattern and the bridged conductor pattern.
表裏面に複数の帯状導体パターンを形成した無機焼結体コア基板の前記表裏面に前記複数の帯状導体パターンを覆う絶縁層を形成し、これを、接着層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴とするインダクティブデバイスの製造方法。
An insulating layer that covers the plurality of strip-shaped conductor patterns is formed on the front and back surfaces of the inorganic sintered body core substrate on which the plurality of strip-shaped conductor patterns are formed on the front and back surfaces, and a plurality of these layers are pressed over the adhesive layer and pressed. Integrated lamination process;
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the laminated slice into individual chips so as to have at least one helical coil composed of the strip-shaped conductor pattern and the bridged conductor pattern.
片面に複数の帯状導体パターンを形成した無機焼結体コア基板を、プリプレグ又は接着シートの絶縁層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴とするインダクティブデバイスの製造方法。
A lamination step in which a plurality of inorganic sintered body core substrates, each having a plurality of strip-like conductor patterns formed on one side, are pressed and integrated through an insulating layer of a prepreg or an adhesive sheet ; and
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the laminated slice into individual chips so as to have at least one helical coil composed of the strip-shaped conductor pattern and the bridged conductor pattern.
片面に複数の帯状導体パターンを形成した無機焼結体コア基板の前記片面に前記複数の帯状導体パターンを覆う絶縁層を形成し、これを、接着層を介して複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴とするインダクティブデバイスの製造方法。
An insulating layer covering the plurality of strip-shaped conductor patterns is formed on the one surface of the inorganic sintered core substrate having a plurality of strip-shaped conductor patterns formed on one side, and a plurality of the layers are pressed and integrated through an adhesive layer. Laminating process to
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the laminated slice into individual chips so as to have at least one helical coil composed of the strip-shaped conductor pattern and the bridged conductor pattern.
芯材を有する有機コア基板の表裏面に複数の帯状導体パターンを形成したものと、無機焼結体コア基板とを接着性絶縁層を介して交互に複数枚重ねて加圧し一体化する積層工程と、
前記積層工程で得られた積層基板を、前記帯状導体パターンを横断する向きで切断するスライス工程と、
前記スライス工程で得られた積層スライス体の切断面に露出した前記帯状導体パターンの端部同士を接続する架橋導体パターンを当該切断面に形成する架橋導体形成工程と、
前記帯状導体パターン及び前記架橋導体パターンからなるヘリカルコイルを少なくとも1個以上有するように、前記積層スライス体を個品チップに分離する分離工程とを備えることを特徴とするインダクティブデバイスの製造方法。
Laminating process in which a plurality of strip conductor patterns formed on the front and back surfaces of an organic core substrate having a core material and an inorganic sintered body core substrate are alternately stacked and pressed together via an adhesive insulating layer When,
A slicing step of cutting the laminated substrate obtained in the laminating step in a direction crossing the strip-shaped conductor pattern;
A bridging conductor forming step for forming a bridging conductor pattern on the cut surface that connects ends of the strip-shaped conductor pattern exposed on the cut surface of the laminated slice obtained in the slicing step; and
And a separation step of separating the laminated slice into individual chips so as to have at least one helical coil composed of the strip-shaped conductor pattern and the bridged conductor pattern.
前記絶縁層を研磨処理して厚さを調整することを特徴とする請求項9,10,11,12又は13記載のインダクティブデバイスの製造方法。 14. The method of manufacturing an inductive device according to claim 9, wherein the thickness of the insulating layer is adjusted by polishing. 前記無機焼結体コア基板の前記帯状導体パターンの無い面を研磨処理して厚さを調整することを特徴とする請求項11又は12記載のインダクティブデバイスの製造方法。 The method for manufacturing an inductive device according to claim 11 or 12 , wherein a surface of the inorganic sintered core substrate without the strip-like conductor pattern is polished to adjust the thickness. 前記スライス工程の後、スライス面を研磨処理して厚さを調整することを特徴とする請求項9,10,11,12,13,14又は15記載のインダクティブデバイスの製造方法。 16. The method of manufacturing an inductive device according to claim 9 , wherein the thickness of the sliced surface is adjusted by polishing after the slicing step. 前記無機焼結体は、多孔質セラミックである請求項9,10,11,12,13,14,15又は16記載のインダクティブデバイスの製造方法。 The method for manufacturing an inductive device according to claim 9 , wherein the inorganic sintered body is a porous ceramic. 前記無機焼結体は、磁性体である請求項9,10,11,12,13,14,15又は16記載のインダクティブデバイスの製造方法。 The method for manufacturing an inductive device according to claim 9 , wherein the inorganic sintered body is a magnetic body.
JP2003406831A 2003-03-17 2003-12-05 Inductive device manufacturing method Expired - Fee Related JP3827314B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2003406831A JP3827314B2 (en) 2003-03-17 2003-12-05 Inductive device manufacturing method
US10/799,717 US7167071B2 (en) 2003-03-17 2004-03-15 Inductive device and method for producing the same
KR1020040017295A KR100739889B1 (en) 2003-03-17 2004-03-15 Inductive device manufacturing method
EP04006266A EP1460654B1 (en) 2003-03-17 2004-03-16 Inductive device and method for producing the same
CNB2004100397915A CN1277280C (en) 2003-03-17 2004-03-17 Inductor and producing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003071196 2003-03-17
JP2003406831A JP3827314B2 (en) 2003-03-17 2003-12-05 Inductive device manufacturing method

Publications (2)

Publication Number Publication Date
JP2004304157A JP2004304157A (en) 2004-10-28
JP3827314B2 true JP3827314B2 (en) 2006-09-27

Family

ID=32829000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003406831A Expired - Fee Related JP3827314B2 (en) 2003-03-17 2003-12-05 Inductive device manufacturing method

Country Status (5)

Country Link
US (1) US7167071B2 (en)
EP (1) EP1460654B1 (en)
JP (1) JP3827314B2 (en)
KR (1) KR100739889B1 (en)
CN (1) CN1277280C (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4682606B2 (en) * 2004-12-07 2011-05-11 ソニー株式会社 Inductance element, manufacturing method thereof, and wiring board
TW200826745A (en) * 2006-08-07 2008-06-16 Messier Bugatti Power control for densification of one or more porous articles
JP4609466B2 (en) * 2007-09-05 2011-01-12 Tdk株式会社 Manufacturing method of multilayer electronic component
US8023269B2 (en) * 2008-08-15 2011-09-20 Siemens Energy, Inc. Wireless telemetry electronic circuit board for high temperature environments
JP5304476B2 (en) * 2009-06-23 2013-10-02 株式会社村田製作所 Electronic component manufacturing method and manufacturing apparatus
US8093982B2 (en) * 2010-03-25 2012-01-10 Qualcomm Incorporated Three dimensional inductor and transformer design methodology of glass technology
TW201232573A (en) * 2011-01-28 2012-08-01 Bing-Li Lai Plasma choking method and plasma choke coil
JP6215518B2 (en) * 2011-08-26 2017-10-18 ローム株式会社 Magnetic metal substrate and inductance element
KR20130076246A (en) 2011-12-28 2013-07-08 삼성전기주식회사 Common mode filter and manufacturing method thereof
JP5674077B2 (en) * 2012-09-25 2015-02-25 株式会社村田製作所 Inductor element
US20150332839A1 (en) * 2012-12-21 2015-11-19 Robert Bosch Gmbh Inductive charging coil device
DE102013114155B4 (en) * 2013-12-16 2015-10-22 Infineon Technologies Ag Method for producing a chip arrangement and chip arrangements
CN103887034B (en) * 2014-02-27 2016-01-27 浙江晶盛机电股份有限公司 A kind of processing method of CUSP field generator for magnetic coil
US10121585B2 (en) * 2014-06-23 2018-11-06 Cyntec Co., Ltd. Method of manufacturing magnetic core elements
US9954510B2 (en) * 2014-11-28 2018-04-24 Samsung Electro-Mechanics Co., Ltd. Common mode filter
CN105551712B (en) * 2016-03-11 2017-07-18 深圳市固电电子有限公司 A kind of chip ceramic electrical sensor and preparation method thereof
JP6394840B2 (en) 2016-06-21 2018-09-26 日産自動車株式会社 Inductor
KR102450597B1 (en) 2017-09-29 2022-10-07 삼성전기주식회사 Coil component and method for manufacturing the same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3992691A (en) * 1975-07-02 1976-11-16 Cubic Corporation Electronic circuit board flat coil inductor
JPS5821807A (en) 1981-07-31 1983-02-08 Tdk Corp Manufacture of chip inductor
JPH03177376A (en) * 1989-12-04 1991-08-01 Japan Gore Tex Inc Ceramic board
US5349743A (en) * 1991-05-02 1994-09-27 At&T Bell Laboratories Method of making a multilayer monolithic magnet component
JP3642110B2 (en) 1996-06-11 2005-04-27 松下電器産業株式会社 Manufacturing method of electronic parts
JPH1145809A (en) 1997-07-24 1999-02-16 Taiyo Yuden Co Ltd Laminated inductance element and manufacture therefor
US6135078A (en) * 1997-11-18 2000-10-24 Denso Corporation Variable valve timing control apparatus for an internal combustion engine
DE19817852B4 (en) 1998-04-22 2009-04-16 Theodor Dr. Doll Use production of inductors with microtechniques
GB2348321A (en) 1999-03-23 2000-09-27 Mitel Semiconductor Ltd A laminated transformer and a method of its manufacture
JP2001023822A (en) * 1999-07-07 2001-01-26 Tdk Corp Laminated ferrite chip inductor array and manufacture thereof
WO2001090809A1 (en) * 2000-05-24 2001-11-29 Schott Donnelly Llc Electrochromic devices
JP2001345212A (en) * 2000-05-31 2001-12-14 Tdk Corp Laminated electronic part
JP2002124415A (en) 2000-10-17 2002-04-26 Tdk Corp Printed circuit board for high frequency and its manufacturing method
US6864774B2 (en) * 2000-10-19 2005-03-08 Matsushita Electric Industrial Co., Ltd. Inductance component and method of manufacturing the same
JP2002134321A (en) 2000-10-23 2002-05-10 Tdk Corp High-frequency coil and its manufacturing method
JP2002324729A (en) 2001-02-22 2002-11-08 Tdk Corp Electronic component and its manufacturing method
JP2002262372A (en) 2001-03-01 2002-09-13 Matsushita Electric Ind Co Ltd Remote control method, remote controller and remote control object device
US6387747B1 (en) * 2001-05-31 2002-05-14 Chartered Semiconductor Manufacturing Ltd. Method to fabricate RF inductors with minimum area
JP2003077726A (en) 2001-08-30 2003-03-14 Fdk Corp Chip type inductor and manufacturing method thereof
JP2003197426A (en) 2001-12-25 2003-07-11 Tdk Corp Composite electronic component containing inductance element
JP2003197427A (en) 2001-12-25 2003-07-11 Tdk Corp Inductance element

Also Published As

Publication number Publication date
KR20040082290A (en) 2004-09-24
JP2004304157A (en) 2004-10-28
EP1460654A1 (en) 2004-09-22
US20050151613A1 (en) 2005-07-14
CN1277280C (en) 2006-09-27
EP1460654B1 (en) 2011-10-05
CN1530972A (en) 2004-09-22
KR100739889B1 (en) 2007-07-13
US7167071B2 (en) 2007-01-23

Similar Documents

Publication Publication Date Title
JP3827314B2 (en) Inductive device manufacturing method
JP4010920B2 (en) Inductive element manufacturing method
JP3800540B2 (en) Inductance element manufacturing method, multilayer electronic component, multilayer electronic component module, and manufacturing method thereof
KR100755088B1 (en) Multilayered substrate and manufacturing method thereof
EP1067568B1 (en) Lamination type coil component and method of producing the same
CN108288534B (en) Inductance component
WO2006098406A1 (en) Method for manufacturing circuit forming board
US9440378B2 (en) Planar electronic device and method for manufacturing
KR101832587B1 (en) Inductor and manufacturing method of the same
JPH07122430A (en) Laminated printed coil and manufacture thereof
JP4010919B2 (en) Inductive element manufacturing method
JP2004128130A (en) Coil component and its manufacturing method
JPH1131632A (en) Method for manufacturing solid-state composite component
JP7127840B2 (en) Inductor and its manufacturing method
JP4825012B2 (en) Wiring board manufacturing method
JP2010050390A (en) Method for manufacturing stacked coil component
JPH06215947A (en) Multilayer inductor
JPH11288832A (en) Laminated inductor component and manufacture thereof
JP2006196567A (en) Method for manufacturing circuit formation substrate
JP2005276878A (en) Inductive device and its manufacturing method
JP2006253246A (en) Method of manufacturing multilayer ceramic substrate
JP2005051097A (en) Method for manufacturing laminated electronic part
JP2005085786A (en) Common mode choke coil, its manufacturing process and common mode choke coil array
JP2002271028A (en) Coil-incorporated multi-layer substrate and its manufacturing method, and manufacturing method for laminated coil
JP2000353618A (en) Laminated chip coil

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060313

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060323

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060517

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060628

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060703

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060703

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090714

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100714

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110714

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120714

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees