JP3825565B2 - Integration type A / D conversion calibration method and integration type A / D converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integral type A / D conversion calibration method and an integral type A / D converter that can calibrate variations in integral constants.
[0002]
[Prior art]
The integration type A / D converter first inputs the converted voltage, integrates it for a predetermined period, obtains the integrated voltage, then inputs the reference voltage, and the integrated voltage becomes the original integration with the same time constant. It integrates in the reverse direction until it reaches the previous voltage (inverse integration), and performs A / D conversion based on the count number of the integration time of the inverse integration, among which the conversion time is particularly short and highly accurate. An example of the / D converter is shown in FIG.
[0003]
In FIG. 4, 1 is an input terminal to which the converted voltage Vin (> 0) is input, 2 is an input terminal to which the reference voltage Vr (> 0) is input, 3 is a buffer as a voltage follower constituted by an operational amplifier, and 4 is an integration 5 is a comparator that compares the integrated voltage Vc of the integrator 4 with the reference value Va, 6 is a control circuit that performs on / off switching of the analog switches S1 to S11, and 7 is a clock that is output from the control circuit 6. A counter for counting 8 is an arithmetic unit for calculating an A / D conversion value (digital value) from the count value of the counter 7. The integrator 4 includes two resistors R1 and R2 that determine an integration constant, a capacitor C1, and an operational amplifier 41.
[0004]
In this A / D converter, the conversion is performed by on / off controlling the switches S1 to S11 as shown in FIG. First, the switches S3, S6 to S8, and S10 are turned on, and the other switches are turned off. As a result, the circuit is switched as shown in FIG. 6A, and the voltage Vc of the capacitor C1 becomes Vc = Va and is initialized.
[0005]
Next, the switches S1, S4, S7, and S10 are turned on, and the other switches are turned off. As a result, the circuit is switched as shown in FIG. 6B, and the measured voltage Vin is integrated into the capacitor C1 for a predetermined time T1 (take-in integration). At this time, the voltage Vc of the capacitor C1 decreases at a slope determined by the measured voltage Vin and the integration constant C1 · R. However, R = R1 + R2.
[0006]
Next, the switches S2, S5, S6, and S10 are turned on, and the other switches are turned off. Thereby, the circuit is switched as shown in FIG. Then, reverse integration is performed with the reference voltage Vr until the integration voltage Vc reaches the voltage at initialization (Vc = Va) (measurement integration). This time is T2.
[0007]
In the above, the voltage to be measured Vin can be represented by the digital value N1 if the clock generated during the period of time T2 is counted by the counter 7, and in principle, this allows the A / D conversion. Is possible.
[0008]
However, since the clock to be counted has a finite time per cycle, the digital value N1 represents the number of clocks from the start of time T2 to immediately after the output voltage Vo of the comparator 5 is inverted, and the output voltage Vo The time between the inversion and the next edge at which the clock triggers the counter 7 is an A / D conversion error.
[0009]
That is, the start point of the time T2 can be intentionally matched with the counter trigger edge of the clock, but this is not possible at the end point, and a sampling error E occurs.
[0010]
In order to reduce this error E (maximum error of less than 1 clock), the resistance is then switched from (R1 + R2 = R) to R1 (= R / n), and the error E is integrated. However, 1 / n = R1 / (R1 + R2).
[0011]
That is, the switches S2, S5, S6, S9, S11 are turned on, the other switches are turned off, the circuit is switched as shown in FIG. 6 (d), and the integration is continued for a certain time T3 by the reference voltage Vr. Perform (take-in integration). At this time, the integration constant is C1 · R / n, and the integration with the reference voltage Vr is performed with a steep slope. The change width of the integrated voltage during the time T3 at this time represents the content n · Ve multiplied by n, where Ve is the voltage corresponding to the error E described above.
[0012]
Next, by turning on the switches S2, S4, S7, and S10 and turning off the other switches, the circuit is switched as shown in FIG. 6E, and the voltage integrated in the capacitor C1 is inversely integrated. (Measurement integration) Assuming that the time from the start of the reverse integration until the voltage Vc of the capacitor C1 decreases and the output Vo of the comparator 5 is inverted (Vc = Vo) is T4, and the count value of the counter 7 during that time is N2, N2 = N · Ve.
[0013]
Therefore, the digital value N of the input voltage Vin is
N = n · N1-N2 (1)
The sampling error E described above is corrected and reduced. The count value N2 includes the same sampling error as when the count value N1 is obtained. However, since this error is already 1 / n, the same processing may be repeated if necessary. (For details of the above, see Japanese Patent Application Nos. 8-034406 and 9-334809).
[0014]
[Problems to be solved by the invention]
By the way, in the above-described integral type A / D circuit, if the values of the two resistors R1 and R2 are varied, the variation appears in n in the equation (1), which greatly affects the A / D converted digital value. It will be. The values of these resistors can be adjusted when they are externally attached, but it is inevitable that the values will fluctuate afterwards due to usage conditions such as temperature and humidity, changes over time, etc. Further, when these resistors are incorporated in a one-chip IC, the adjustment cannot be performed at all, and in either case, it is a major factor causing an error in A / D conversion.
[0015]
The present invention has been made in view of the above points. The object of the present invention is to investigate the ratio of two integration constants and adjust the integration time during A / D conversion based on the result, thereby integrating An integral A / D calibration method and an integral A / D circuit that can calibrate variations in constants.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the first invention performs A / D conversion on the measured voltage using only the second integration constant or using the first and second integration constants, and thereafter In the integration type A / D conversion method for performing A / D conversion for reducing the sampling error of the A / D conversion using the first and second integration constants, the first integration constant is used. A reference voltage is inputted for a predetermined first period to obtain an integration voltage, and then the second period until the integration voltage becomes the original voltage using the second integration constant and the reference voltage. The second integration in the A / D conversion performed by the first and second integration constants based on the ratio and obtaining the ratio between the design value and the actual value in the second period. It was configured to calibrate the constant integration period.
[0017]
According to a second invention, in the first invention, the second period is obtained from a clock count number, and based on a ratio between a design value and an actual value of the count number, the second integration constant is used thereafter. The clock period for obtaining the integration period is adjusted.
[0018]
According to a third invention, in the second invention, a frequency divider is provided on an output side of the oscillator for generating the clock, and the first and second periods are obtained by the count number of the output clock of the frequency divider, Thereafter, when counting of the integration period performed by the second integration constant is performed, the count value of the second period is used as the frequency division ratio of the frequency divider.
[0019]
According to a fourth aspect of the present invention, the measured voltage is A / D converted using only the second integration constant or using the first and second integration constants, and thereafter the first and second integrations are performed. Integral A / D converter for performing A / D conversion for reducing sampling error of A / D conversion using a constant, a frequency divider for setting a clock cycle for counting an integration period And the second integration constant in the A / D conversion performed by the first and second integration constants, with the frequency division ratio of the frequency divider when using the first integration constant being a fixed value. The frequency division ratio of the frequency divider when using the circuit is changed in accordance with the ratio between the design value and the actual value of the ratio between the first integral constant and the second integral constant.
[0020]
In a fifth aspect based on the fourth aspect, the frequency dividing ratio of the frequency divider when using the second integral constant is the integrated voltage obtained by integrating a reference voltage with the first integral constant. Is set by the number of clocks at the fixed frequency division ratio during the period until the original voltage is integrated in the reverse direction using the second integration constant and the reference voltage.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1A is a circuit diagram of an A / D converter used in the first embodiment of the present invention. Although this is the same as that shown in FIG. 4, the control circuit 6, the counter 7, the arithmetic unit 8 and the like are omitted. FIG. 1B is an explanatory diagram of the control operation.
[0022]
In the present embodiment, as shown in FIG. 1B and FIG. 2A, after a resistor is initialized with only R1, the reference voltage Vr is determined for a predetermined time similarly with the resistor only R1. Integrate by Ta (first integration), then switch the resistance to “R1 + R2”, and perform reverse integration (second integration) with the same reference voltage Vr until the integration voltage Vc returns to Va. This time is Tb. As a result,
R1 / (R1 + R2) = Ta / Tb (2)
The relationship is obtained. If the ratio between R1 and R2 is different from the original value due to manufacturing variations, the time Ta is constant and the error appears in Tb.
[0023]
When the times Ta and Tb are counted by the counter, a count value Na corresponding to the time Ta and a count value Nb corresponding to the time Tb are obtained.
R1 / (R1 + R2) = Na / Nb (3)
The relationship is obtained. Note that the sampling error described above occurs in Na and Nb during digital conversion, but is ignored here.
[0024]
On the other hand, the time Tb can be set in advance at the time of design as its original value (value without error) corresponding to the time Ta, the count value is Nb ′, and the count clock at that time If the cycle is Tclk,
Tb = Nb · Tclk
= Nb ′ · {(Nb / Nb ′) Tclk}
= Nb '· Tclk' (4)
However, Tclk ′ = (Nb / Nb ′) Tclk
It becomes. That is, the time Tb is equal to the time counted by the ideal count value Nb ′ by the clock having the clock cycle Tclk ′.
[0025]
From the above, the clock period of the integration period for integration (first integration) using only the resistor R1 is Tclk, and the clock period of the integration period for reverse integration (second integration) using the resistor “R1 + R2” is Assuming Tclk ′, the clock count value in the latter is Nb ′, which is an ideal value.
[0026]
Therefore, even if the ratio between the resistors R1 and R2 varies, the integration period using only the resistor R1 is counted with the clock having the cycle Tclk, and the integration period using the resistor “R1 + R2” is counted with the clock having the cycle Tclk ′. When counting, the error is cancelled.
[0027]
Therefore, the resistor “R1 + R2” is used in the A / D conversion in which the integration using the resistor R1 and the inverse integration using the resistor “R1 + R2” are performed, that is, the A / D conversion for correcting the sampling error. The integration period is counted with a clock having a cycle Tclk ′.
[0028]
In the A / D conversion of the measured voltage Vin performed immediately after the first integration and the second integration (T1 and T2 in FIG. 1B), the resistor “R1 + R2” is used for both integration and inverse integration. Therefore, since there is no influence due to the variation in the ratio of the resistors R1 and R2, it is not always necessary to use the clock having the period Tclk ′, but it can also be used.
[0029]
However, in the A / D conversion of the voltage to be measured Vin, the integration using the resistor R1 and the inverse integration using the resistor “R1 + R2” are performed (in this method, the inverse integration period becomes longer, so the resolution can be increased. ), The integration period using the resistor “R1 + R2” is counted with a clock having a cycle Tclk ′.
[0030]
[Second Embodiment]
As described above, it was found that in the case of integration using the resistor “R1 + R2,” the counter 7 should be operated by switching the clock cycle to be used from Tclk to Tclk ′. Therefore, in the second embodiment, R1 / (R1 + R2) = 1/10 as an example of the ideal value of the integration constant ratio, and the period of the clock to be counted is counted when integrating by the resistor R1. The frequency dividing ratio of the frequency divider is adjusted to be different from that at the time of integration counting by “R1 + R2.”
[0031]
FIG. 3 is a diagram showing the configuration of the second embodiment. Reference numeral 9 denotes a fixed-frequency clock oscillator, and reference numeral 10 denotes a frequency divider. Others are the same as those shown in FIG.
[0032]
First, during the first integration using the resistor R1, the clock cycle is Tclk and integration is performed by the number of clocks Na = 10. Then, the resistor is switched to “R1 + R2” until the integration voltage Vc returns to the start voltage of the first integration. The second integration is performed to obtain the clock number Nb during that time. If the number of clocks Nb at this time is Nb = 100, the ratio of the resistors R1 and R2 will not vary, but if Nb ≠ 100, there will be variation.
[0033]
Therefore, the frequency division ratio of the frequency divider 10 can be set in the range of “50 to 150” with the ideal value “100” as the center value and considering a margin of ± 50%.
[0034]
As described above, when there is no variation in the ratio between the resistors R1 and R2, since Nb = 100, “100” is set as the frequency dividing ratio of the frequency divider 10. Further, for example, when Nb = 94, it indicates that the value of “R1 + R2” is smaller than the ideal value “100” and smaller than the ideal value. Therefore, the clock cycle is reduced, that is, the frequency division ratio is “94”. Should be set. If the second integration is performed by the output clock of the frequency divider 10 using this frequency division ratio, the count number Nb = 100. On the other hand, when Nb = 121, it indicates that the value of “R1 + R2” is larger than the ideal value “100” and is larger than the ideal value. Therefore, the clock cycle is increased, that is, the frequency division ratio is set to “121”. do it.
[0035]
In this way, by using the count value Nb of the integration period Tb of the second integration as it is for setting the frequency dividing ratio of the frequency divider 10, the variation of the resistors R1 and R2 can be canceled immediately. .
[0036]
That is, if the first integration and the second integration are performed prior to the original A / D conversion and the count value Nb is obtained by the second integration, the dividing ratio is set to “ 100 ”and when dividing using the resistor“ R1 + R ”(during A / D conversion of the measured voltage using different integration constants or A / D conversion for sampling error correction), the division ratio is counted. By setting the value to Nb, A / D conversion can be performed without being affected by variations in the resistances R1 and R2.
[0037]
【The invention's effect】
From the above, according to the present invention, even if the integration constant varies not only at the time of manufacture, but also afterwards due to temperature change or change over time, the influence of the variation can be canceled, Fine adjustment at the time of mass production is not necessary, and IC can be further promoted.
[Brief description of the drawings]
FIG. 1A is a circuit diagram of the main part of an integrating A / D converter used in the first embodiment, and FIG. 1B is an explanatory diagram of switch switching.
FIGS. 2A to 2C are circuits of the main part of an integrating A / D converter switched by switch switching shown in FIG. 1B.
FIG. 3 is an explanatory diagram of a second embodiment.
FIG. 4 is a circuit diagram of a conventional integrating A / D converter.
5 is an operation explanatory diagram of the A / D converter of FIG. 4. FIG.
6 is a circuit of a main part of the integral type A / D converter switched by switch switching shown in FIG. 4;
[Explanation of symbols]
1, 2: input terminal, 3: buffer, 4: integrator, 41: operational amplifier, 5: comparator, 6: control circuit, 7: counter, 8: arithmetic unit, 9: oscillator, 10: frequency divider.

Claims (5)

A / D conversion of the measured voltage using only the second integration constant or using the first and second integration constants, and then using the first and second integration constants In the integration type A / D conversion method for performing A / D conversion for reducing the sampling error of A / D conversion,
Using the first integration constant, a reference voltage is input for a predetermined first period to obtain an integration voltage, and then using the second integration constant and the reference voltage, the integration voltage is restored to the original voltage. Integrate in the reverse direction for the second period until it reaches the voltage,
A ratio between the design value and the actual value in the second period is obtained, and based on the ratio, the integration period by the second integration constant in the A / D conversion performed by the first and second integration constants is calibrated. An integration type A / D conversion calibration method characterized by the above. The second period is obtained from the count number of the clock, and the period of the clock for obtaining the integration period performed by the second integration constant is adjusted based on the ratio between the design value and the actual value of the count number. The integration type A / D conversion calibration method according to claim 1, wherein: A frequency divider is provided on the output side of the oscillator for generating the clock, the first and second periods are obtained from the count of the output clock of the frequency divider, and the integration performed by the second integration constant thereafter 3. The integral A / D conversion calibration method according to claim 2, wherein when the period is counted, the count value of the second period is used as a frequency division ratio of the frequency divider. A / D conversion of the measured voltage using only the second integration constant or using the first and second integration constants, and then using the first and second integration constants In an integrating A / D converter that performs A / D conversion for reducing sampling error of A / D conversion,
A frequency divider for setting a cycle of a clock for counting the integration period, wherein the frequency division ratio of the frequency divider when using the first integration constant is a fixed value, The division ratio of the frequency divider when using the second integration constant in the A / D conversion performed by the integration constant is expressed as the design value of the ratio between the first integration constant and the second integration constant. An integral type A / D converter characterized by being changed according to a ratio to an actual value. The frequency division ratio of the frequency divider when using the second integration constant is
The fixed voltage during the period until the integrated voltage obtained by integrating the reference voltage with the first integration constant is integrated in the reverse direction until the original voltage is obtained using the second integration constant and the reference voltage. 5. The integral type A / D converter according to claim 4, wherein the integral type A / D converter is set according to the number of clocks at a frequency division ratio.

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