JP3821148B2 - Electro-optical device drive circuit, electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to a drive circuit of an electro-optical device that prevents generation of a useless region in a formation region with a high-quality display, an electro-optical device incorporating the drive circuit, and an electron using the electro-optical device Regarding equipment.

A driving circuit of a conventional electro-optical device, for example, a liquid crystal device, includes a data line driving circuit that supplies an image signal, a scanning signal, and the like to a data line and a scanning line arranged in an image display area at a predetermined timing, and a scanning circuit. It is composed of a line drive circuit, a sampling circuit, and the like. Among these, the data line driving circuit generally includes a plurality of latch circuits (shift register circuits), and sequentially shifts the transfer signal supplied at the beginning of the horizontal scanning period according to the clock signal, and performs sampling control thereof. Similarly, the scanning line driving circuit includes a plurality of latch circuits, and sequentially shifts the transfer signal supplied at the beginning of the vertical scanning period in accordance with the clock signal, and outputs this signal as the scanning signal. Is output as The sampling circuit is composed of a sampling switch provided for each data line, samples an image signal supplied from the outside according to a sampling control signal, and supplies it to each data line.

  In addition, a buffer circuit is interposed between the latch circuit and the sampling circuit to shape the transfer signal to obtain the above-described sampling control signal, and the driving capability of the latch circuit is sufficient to drive the sampling switch. A configuration that can sufficiently cope with the load of the sampling switch is also adopted even if it is not.

  On the other hand, a drive circuit built-in type electro-optical device in which these drive circuits are provided on a substrate constituting the electro-optical device has been developed. In this type of electro-optical device, the elements constituting the drive circuit are manufactured in a common process with the switching elements for driving the pixels from the viewpoint of improving the efficiency of the manufacturing process. For example, an element constituting a driving circuit in a liquid crystal device using liquid crystal as an electro-optic material is constituted by a thin film transistor (hereinafter referred to as “TFT”) for driving a liquid crystal pixel. Such an electro-optical device with a built-in drive circuit is advantageous in reducing the size and cost of the entire device as compared with an electro-optical device in which a drive circuit is formed on a separate substrate and externally attached. is there.

  In recent years, not only electro-optical devices but also display devices in general have become high-definition, such as XGA (1024 x 768 dots), SXGA (1280 x 1024 dots), UXGA (1600 x 1200 dots), etc. Accordingly, there is a need to increase the dot frequency of the electro-optical device. Here, in the electro-optical device with a built-in drive circuit, when the dot frequency is increased, the sampling capability of the sampling switch described above is insufficient, the operation delay of elements constituting the drive circuit, and the like occur. As a result of the image signal to be written to the data line being written also to the previous data line, so-called ghost and crosstalk occur, and the quality of the display image is degraded. In order to solve this problem, if the performance of the sampling switch and the constituent elements of the drive circuit itself is increased, the cost will increase significantly.

  Recently, therefore, one system of image signals is distributed to a plurality of systems and is expanded on the time axis (serial-parallel conversion). On the other hand, the sampling circuit simultaneously samples a plurality of systems of image signals to generate a plurality of data lines. Technology has been developed that can be supplied simultaneously. According to this technique, the sampling time by each sampling switch is double the number of simultaneously driven data lines in accordance with the number of simultaneously driven data lines, so that the drive frequency in the drive circuit is substantially reduced. Further, the number of data lines is reduced to the reciprocal of the data lines that are driven simultaneously. For this reason, it is possible to cope with a higher dot frequency without improving the performance of the sampling switch, the drive circuit components, the pixel drive elements, and the like.

  When a plurality of data lines are simultaneously driven in this way, it is necessary to supply the same sampling control signal to a plurality of sampling switches simultaneously. For this reason, it is necessary to increase the drive capability of the buffer circuit interposed between the latch circuit and the sampling switch in accordance with the total load of the plurality of sampling switches.

  Here, as a measure for increasing the drive capability of the buffer circuit, first, it is conceivable to increase the size of the logic circuit that constitutes the buffer circuit, for example, the element that constitutes the inverter. However, in this measure, if the constituent elements of the driving circuit are simply increased in size, it will be necessary to increase the driving capability of the latch circuit that will drive the constituent elements. This results in a contradiction with the general demand in the technical field of the electro-optical device for reducing the power consumption of the shift register circuit. Therefore, a configuration is adopted in which a plurality of inverters are connected in multiple stages in series to constitute a buffer circuit, and the driving capability of the buffer circuit is increased step by step for each stage. That is, the buffer circuit employs a configuration in which the element size constituting the inverter at the stage on the latch circuit side is small and the element size constituting the inverter at the stage on the sampling switch side is large.

  However, if a buffer circuit composed of inverters connected in multiple stages in series is provided in the electro-optical device with a built-in driving circuit, the buffer circuit is enlarged in the substrate region. An increase in ineffective use area becomes a problem. In particular, since the region where the buffer circuit is formed is usually a region interposed between the image signal line and the shift register circuit, it is long in a direction intersecting with the extending direction of the data line. Therefore, in the configuration in which each stage of inverter is formed from elements extending in the longitudinal direction in the direction of extension of the data line and this is simply connected in a plurality of stages in the direction of extension of the data line, The proportion of the ineffective use area will be significantly increased. Finally, since the data line driving circuit is formed outside one end of the image display area, the non-image display area is expanded, and the entire apparatus can be reduced in size and weight, and the image display area in the same apparatus size can be reduced. This leads to a result that contradicts the general demand for the electro-optical device, that is, an increase in size.

  The present invention has been made in view of the above-described circumstances, and an object thereof is an electro-optical device such as a liquid crystal device that has a built-in driving circuit and simultaneously drives a plurality of data lines. A drive circuit for an electro-optical device capable of efficiently downsizing the entire device by efficiently using a substrate region, an electro-optical device incorporating the drive circuit, and an electronic apparatus having the electro-optical device It is to provide.

In order to solve the above problems, the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to the intersections of the plurality of scanning lines and the plurality of data lines. In the electro-optical device drive circuit for driving the electro-optical device, the drive circuit includes a shift register circuit and a phase adjustment that limits a signal width of a transfer signal supplied from the shift register circuit to a predetermined width. And a buffer circuit that outputs the transfer signal, the signal width of which is limited by the phase adjustment circuit, as a sampling control signal. The buffer circuit intersects with the direction in which the data line extends. A plurality of stages constituted by a plurality of logic circuits connected in parallel are connected in series, and the channel width of the transistors constituting the logic circuit is: Serial characterized wider than the channel width of the transistor included in the logic circuit included in the preceding stage including a logic circuit.
And driving an electro-optical device including a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. In the drive circuit of the electro-optical device, the drive circuit includes a shift register circuit, and a buffer circuit that outputs a sampling control signal based on a transfer signal supplied from the shift register circuit. Including a plurality of logic circuits arranged in a direction intersecting with the extending direction of the data lines and connected in parallel, and each transistor constituting the plurality of logic circuits has a channel width direction of the transistors. The data lines are arranged in the extending direction.

  In the driving circuit of the electro-optical device, the buffer circuit includes a stage configured by a plurality of logic circuits arranged in a direction intersecting with the extending direction of the data lines and connected in parallel. Furthermore, it is desirable to connect a plurality of the stages in series.

  Furthermore, it is desirable that the channel width of the transistors constituting the logic circuit is wider than the channel width of the transistors constituting the logic circuit included in the preceding stage including the logic circuit.

  With this configuration, the size of the transistors constituting the logic circuit increases step by step for each stage, so that the drive capability of the entire buffer circuit can be increased. For this reason, it is possible to increase the number of samplings that can be simultaneously driven by the sampling control signal. On the other hand, since the size of the transistor constituting the first stage logic circuit may be relatively small, the driving capability of the latch circuit that supplies a transfer signal to this transistor may be low. For this reason, in a shift register circuit including a plurality of latch circuits, the circuit scale is reduced and power consumption is reduced. Furthermore, since the signal width of the transfer signal (the time during which the signal is at the active level) is limited to a predetermined period by the phase adjustment circuit, duplication of transfer signals output before and after the latch circuit is reduced. . For this reason, the situation where the same image signal is sampled simultaneously on data lines that should be driven by different sampling control signals is prevented, so that the occurrence of crosstalk, ghosts, etc. can be suppressed in advance. .

  As the number of stages connected in series increases, the total delay time by the transistors constituting these logic circuits also increases. Therefore, in practice, the total delay time will not adversely affect the displayed image, and the dot frequency, required specifications, and image quality will be comprehensively taken into consideration. It is desirable to determine the number of stages of series connection.

  Note that in a configuration in which the circuits are connected in series, it is desirable that the number of logic circuits connected in parallel in one stage is equal to all other stages. With this configuration, the logic circuit is arranged in a matrix in the extending direction of the data lines and in the intersecting direction, so that the buffer circuit can be easily designed. Furthermore, if the logic circuits for each stage are connected in parallel in the direction crossing the extending direction of the data lines, the board area can be fully used.

  Further, in the configuration in which the logic circuits are arranged in a matrix, it is desirable that among the logic circuits in all stages, the logic circuits located in the same column share the power supply wiring formed in the extending direction of the data lines. This is because not only the design of the buffer circuit is facilitated, but also the substrate area is effectively utilized for the shared power supply wiring. In order to share the power supply wiring in the logic circuits located in the same row in this way, it is possible to have a configuration in which two power supply wirings are arranged facing each other in a comb-tooth shape. In particular, in this configuration, among the logic circuits in the same stage, one power supply wiring is shared by adjacent logic circuits, so that the wiring of the power supply wiring is greatly simplified.

  On the other hand, in the drive circuit according to the present invention, it is desirable that the drive circuit is serial-parallel converted and supplied via a plurality of image signal lines. According to this, since the image signal is converted into a plurality of systems, a margin is substantially generated in the time axis, so that a sampling switch with relatively low performance can be used even when the dot peripheral number is high. It becomes possible.

In order to achieve the above object, the electro-optical device according to the present invention is characterized by including the drive circuit. According to the present invention, since the substrate can be efficiently used, high-quality image display can be achieved along with downsizing of the entire apparatus and enlargement of the image display area in the same size apparatus.

  Here, in the present invention, the substrate is provided with pixel electrodes arranged in a matrix, the pixel electrodes and the data lines, and scanning signals supplied to the scanning lines. Therefore, it is desirable to further include a transistor that opens and closes. According to this configuration, since the on-pixel and the off-pixel can be electrically separated by the transistor, high-definition and high-definition display with high contrast and no crosstalk is possible.

  Further, in order to achieve the above object, the electric apparatus according to the present invention is characterized by including the above electro-optical device, so that high-quality display without ghost and crosstalk becomes possible.

  Embodiments of the present invention will be described below with reference to the drawings.

<Liquid crystal device>
First, a liquid crystal device will be described as an example of an electro-optical device according to the present invention. As will be described later, the configuration of the liquid crystal device is such that the TFT array substrate and the counter substrate are attached to each other with the electrode forming surfaces facing each other and with a certain gap, and the liquid crystal is sandwiched between the gaps. It has become. Among them, the image display area of the TFT array substrate has an equivalent circuit as shown in FIG.
As shown in this figure, m scanning lines 3a are formed in parallel along the X direction, while n data lines 6a are formed in parallel along the Y direction. Has been. At each intersection of the scanning line 3a and the data line 6a, the gate of the TFT 30 is connected to the scanning line 3a, the source of the TFT 30 is connected to the data line 6a, and the drain of the TFT 30 is connected to the pixel electrode. 9a. Each pixel is composed of a pixel electrode 9a, a counter electrode (described later) formed on the counter substrate, and a liquid crystal sandwiched between the two electrodes. As a result, the scanning line 3a and the data line 6a Corresponding to each intersection, they are arranged in a matrix.

Here, in the liquid crystal device according to the present embodiment, in particular, the image signals S1, S2,..., Sn sampled on the data line 6a are image signals that supply the image signals S1, S2,. Serial-parallel conversion circuit (not shown) in the processing circuit is serial-parallel converted in advance and distributed to 12 systems, and simultaneously supplied to each group of 12 data lines 6a adjacent to each other. It is what is done. In general, if the dot frequency is relatively low (or if the sampling capability in a sampling circuit described later is relatively high), the serial-parallel conversion number is a small value such as “3” or “6”. It may be set to. Conversely, if the dot frequency is relatively high (or if the sampling capability is relatively low), a large value such as “24” may be set. In addition, since the number of serial-parallel conversions is a multiple of 3 because the color image signal is composed of signals related to three colors, control and circuit configuration for video display are simplified. Is preferable. Furthermore, in the case of a high dot frequency such as recent XGA, SXGA, UXGA, etc., in view of the existing TFT manufacturing technology, a large value such as “12” in this embodiment and “24” in addition to this. It is preferable to set to.

  Further, scanning signals G1, G2,..., Gm are applied to the scanning line 3a to which the gate of the TFT 30 is connected in a pulse-by-line manner. For this reason, when a scanning signal is supplied to a certain scanning line 3a, the TFT 30 connected to the scanning line 3a is turned on, so that the image signals S1, S2,..., Sn supplied from the data line 6a at a predetermined timing. Are sequentially written in the corresponding pixels and then held for a predetermined period.

  Here, since the orientation and order of liquid crystal molecules change according to the voltage level applied to each pixel, gradation display by light modulation becomes possible. For example, in the normally white mode, the amount of light passing through the liquid crystal is limited as the applied voltage increases. In the normally black mode, the amount of light that passes through the liquid crystal is reduced as the applied voltage increases. Then, light having contrast according to the image signal is emitted for each pixel. For this reason, a predetermined display is possible.

  In order to prevent the held image signal from leaking, the storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, since the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time when the source voltage is applied, the holding characteristics are improved, and as a result, a high contrast ratio is realized. Become.

  Next, the drive circuit of the liquid crystal device according to this embodiment will be described. FIG. 2 is a block diagram showing the configuration of the TFT array substrate, in particular, the configuration of the drive circuit formed around the outside of the image display area.

  As shown in this figure, the TFT array substrate 10 is provided with an image display unit 100a that is an intersection region of the scanning lines 3a and the data lines 6a. A drive circuit 200 including a drive circuit 104 and a sampling circuit 301 is provided. That is, the present embodiment is a TFT active matrix driving type liquid crystal device with a built-in driving circuit in which a driving circuit 200 is formed on the TFT array substrate 10.

  Of the driving circuit 200, the scanning line driving circuit 104 supplies the scanning signals G1, G2,..., Gm to the scanning line 3a in a pulse-sequential manner in one vertical scanning period. On the other hand, the data line driving circuit 101 has sampling control signals X1, X2,..., Xn in one horizontal scanning period, that is, in a period in which the scanning line driving circuit 104 supplies a scanning signal to one scanning line 3a. Are sequentially supplied to the sampling control signal line 114.

  The sampling circuit 301 includes a sampling switch 302 for each data line 6a, samples the image signal supplied to the image signal line 115 in accordance with the sampling control signals X1, X2,. It is supplied to the line 6a. Here, in the present embodiment, since one image signal is serial-parallel converted into 12 image signals VID1 to VID12 as described above, they are connected to 12 adjacent data lines 6a. 12 sampling switches 302 are simultaneously driven by the same sampling control signal, and image signals VID1 to VID12 are sampled and supplied to each of the 12 data lines 6a.

<Data line drive circuit>
Next, details of the data line driving circuit 101 will be described. FIG. 3 is a block diagram showing a configuration of the data line driving circuit 101. As shown in FIG. 3, the data line driving circuit 101 includes a shift register circuit 400 that sequentially outputs transfer signals, and a buffer circuit 500 that shapes the waveform of the sequentially output transfer signals. Among these, the shift register circuit 400 includes a plurality of stages of latch circuits 401 connected in series, and each latch circuit 401 actually has an input signal according to the clock signal CLX and its inverted clock signal CLX ′. A delay flip-flop circuit that takes in and holds is used.

Further, the data line driving circuit 101 is provided with a phase adjustment circuit 402. The phase adjustment circuit 402 includes NAND circuits 403 provided corresponding to the outputs of the latch circuits 401, and the odd-numbered NAND circuits 403 counted from the left in the drawing are input from the corresponding latch circuits 401. The NAND circuit 403 of the even-numbered stage counted from the left is input from the corresponding latch circuit 401, while the negative AND signal of the transfer signal ST _2i-1 (where i is a natural number) and the phase adjustment signal ENB1. The NAND signal of the transfer signal ST _2i and the phase adjustment signal ENB 2 is supplied to the buffer circuit 500 via the wiring 404.

  The buffer circuit 500 is provided corresponding to each NAND circuit 403 and includes three stages of inverters 501 to 503 connected in series. The output signal from the phase adjustment circuit 402 is subjected to waveform shaping or the like, and the sampling control signal line As 114, it outputs as a sampling control signal. Here, as will be described later, each of the inverters 501 to 503 is formed so that the size of the TFTs constituting the inverters 501 to 503 increases as the latter stage is reached. Therefore, the input impedance is kept low.

  Next, the operation of the data line driving circuit 101 configured as described above will be described. FIG. 4 is a timing chart for explaining the operation of the data line driving circuit 101. As shown in FIG. 3, when the start pulse SP is supplied from an external image signal processing circuit in synchronization with the image signals VID1 to VID12 at the beginning of one horizontal scanning period, it is positioned at the leftmost end in FIG. The latch circuit 401 starts the transfer operation based on the X-side reference clock signal CLX (and its inverted clock signal CLX ′), outputs the transfer signal ST1, and counts the transfer signal from the left to the second stage. To the latch circuit 401. Next, the second-stage latch circuit 401 shifts the transfer signal ST1 by a half cycle of the clock signal CLX and outputs it as the transfer signal ST2, and counts the transfer signal from the left and outputs it to the third-stage latch circuit 401. This is supplied to the latch circuit 401. Subsequently, the same transfer operation is repeated in each stage of the latch circuit 401. As a result, transfer signals ST1, ST2,..., STn are sequentially output in one horizontal scanning period.

  Further, the transfer signals ST1, ST2,..., STn sequentially output in this way are limited by the phase adjustment circuit 402 to the pulse width of the phase adjustment signal ENB1 or ENB2, and then shaped by the buffer circuit 500, Sampling control signals X1, X2,..., Xn are supplied to a sampling circuit 301 formed of transistors or the like.

  In the present embodiment, the pulse intervals of the sampling control signals X1, X2,..., Xn that follow each other are temporally separated as shown in FIG. The occurrence of crosstalk, ghosts and the like due to the overlap of these signal pulses is prevented in advance. That is, if the sampling control signals X1, X2,..., Xn overlap, an image signal that should be sampled on a data line of a certain group is also applied to a data line of a group located before and after that group. However, according to the present embodiment, the pulses of the sampling control signals X1, X2,..., Xn are temporally isolated and output. Therefore, occurrence of crosstalk, ghost, etc. is prevented in advance.

  In addition, the drive capability of the buffer circuit 500 is much greater than the drive capability of the latch circuit 401 and the phase adjustment circuit 402. Therefore, even if the driving capability of the latch circuit 401 and the phase adjustment circuit 402 is low, the twelve sampling switches 302 can be driven simultaneously well by the sampling control signals X1, X2,..., Xn output from the buffer circuit 500. It will be.

<Layout of data line driving circuit>
Here, a circuit layout of the data line driving circuit 101 will be described. FIG. 5 is a plan view showing a layout of a main circuit of the data line driving circuit 101. In this figure, the output signal of the phase adjustment circuit 402 supplied via the wiring 404 is first subjected to waveform shaping or the like by the buffer circuit 500 and output as a sampling control signal via the sampling control signal line 114. Secondly, the twelve sampling switches 302 are driven and controlled according to the sampling control signal, and the image signals VID1 to VID12 supplied to the twelve image signal lines 115 are sampled by the twelve sampling switches. Thus, the configuration supplied to the corresponding 12 data lines 6a is shown.
Further, as shown in FIG. 5, the buffer circuit 500 is provided with an area where the latch circuit 401 and the phase adjustment circuit 402 are formed, and 12 lines supplied with 12 systems of serial-parallel converted image signals VID1 to VID12. Are formed between the image signal line 115 and the region where the image signal line 115 is formed.

<Buffer circuit layout>
Next, details of the buffer circuit 500 will be described with reference to FIGS. 6 is a plan view showing the layout of the buffer circuit 500, FIG. 7 is a circuit diagram in which the layout of FIG. 6 is simplified, and FIG. 8 is an equivalent circuit diagram showing the configuration of the buffer circuit 500. It is. As shown in these drawings, in the buffer circuit 500, the inverters 501 to 503 are configured by serially connecting three stages in the extending direction (Y direction) of the data line 6a. In 503, seven inverters are connected in parallel in the extending direction (X direction) of the scanning line 3a. That is, the first-stage inverter 501 is connected in parallel with inverters 511-517, the second-stage inverter 502 is connected with inverters 521-527, and the third-stage inverter 503 is connected with inverters 531-537 in parallel. It is.

  Further, each of these inverters 511 to 517, 521 to 527, and 531 to 537 is configured as a complementary TFT in which a P-channel TFT and an N-channel TFT having a channel width direction formed in the Y direction are combined. . That is, in each of the inverters 511 to 517, 521 to 527, and 531 to 537, a P-channel TFT and an N-channel TFT are connected in series between the lead wirings 601a and 602a.

  The channel lengths of these TFTs are substantially the same throughout. Therefore, the inverters 511 to 517, 521 to 527, and 531 to 537 constituting the buffer circuit 500 are arranged in a matrix of 3 rows and 7 columns in terms of layout.

  Here, the channel width L1 of the TFT constituting the first stage inverter 501 (inverters 511 to 517), the channel width L2 of the TFT constituting the second stage inverter 502 (inverters 521 to 527), and the first The channel width L3 of the TFT constituting the third-stage inverter 503 (inverters 531 to 537) is L1 <L2 <L3. As described above, since the first to third stage inverters 501 to 503 are the same number (7) of inverters connected in parallel, the on-resistance is determined by the channel width. Inverter 501, inverter 502> inverter 503>.

  Therefore, when viewed as a whole in the buffer circuit 500, the input impedance is increased while the output impedance is decreased. For this reason, the size of the TFT constituting the latch circuit 401 for outputting the transfer signal or the phase adjustment circuit 402 for narrowing the pulse width of the transfer signal can be reduced. While a reduction in power consumption of 400 is achieved, it is possible to drive and control a large number (12) of sampling switches 302 at the same time.

  On the other hand, the high-voltage (Vcc) wiring 601 and the low-voltage (GND) wiring 602 are respectively arranged so as to extend through the TFT element array substrate 10 in the X direction, but in the region where the buffer circuit 500 is formed. In particular, as shown by a thick line in FIG. 7, a lead-out wiring 601a is extended from the high-voltage wiring 601 and a lead-out wiring 602a is extended from the low-voltage wiring 602 in the Y direction and is comb-toothed. It is formed to face.

Here, the inverters adjacent to each other in the X direction share one channel region and have a continuous shape that is folded back. Therefore, the TFT channel type constituting the inverter for one stage is shown in FIG. In FIG. 7, P, N, N, P, P, N, N,... For this reason, inverters adjacent to each other in the same stage not only have the same channel region, but also share the lead-out wiring connected to the common region. For example, the inverters 511 and 512 not only share an N channel type channel region, but also share a lead wiring 602a connected to the drain region of the shared region. Further, for example, the inverters 522 and 523 not only share a channel region that is a P-channel type, but also share a lead-out wiring 601a that is connected to the source region in the shared region. That is, in other words, the respective inverters are arranged so as to be symmetric with respect to the lead wiring 601a or 602a.

On the other hand, in each TFT constituting the first-stage inverters 511 to 517, a wiring 404 for supplying a transfer signal with a narrowed pulse width is extended in a comb shape to serve as a gate electrode. . On the other hand, wirings connected to the source region of the P-channel TFT and the drain region of the N-channel TFT constituting the first-stage inverters 511 to 517 serve as outputs of the inverters 511 to 517 through contact holes. The gate electrodes of the TFTs constituting the second stage inverters 521 to 527 are connected in common and extended in a comb shape. Similarly, wirings connected to the source region of the P-channel TFT and the drain region of the N-channel TFT constituting the second stage inverters 521 to 527 are output from the inverters 521 to 527 through the contact holes. As a gate electrode of each TFT constituting the third-stage inverters 531 to 537, extending in a comb shape. Then, the source region of the P-channel TFT and the drain region of the N-channel TFT constituting the third stage inverters 531 to 537 are commonly connected as outputs of the inverters 531 to 537 through the contact holes, This is the sampling control signal line 114. Then, as shown in FIG. 9, the buffer circuit 500 has a latch circuit in the shift register circuit 400 in the X direction at a pitch that matches the total width (ΔW) of the twelve data lines 6a that are driven simultaneously. Arranged corresponding to 401.

  According to such a buffer circuit 500, since a plurality of inverters are connected in parallel to form a single-stage inverter, a region whose length is normally in the X direction is efficiently used and It is possible to improve the driving capability by the inverter of the minute. Further, since the channel widths L1 to L3 of the TFTs constituting the inverters 501 to 503 are increased stepwise, the entire buffer circuit 500 can cope with a high load, and the number of sampling switches 302 that can be driven simultaneously can be increased. Become.

  In addition, among the inverters for one stage connected in parallel, the inverters adjacent to each other in the X direction share the P channel region or the N channel region. Compared with the case where the channel region is formed for each TFT. Thus, the substrate area is efficiently used. Further, in the shared channel region, since the drain region or the source region is also shared, the lead-out wiring from the power supply wiring can be shared.

In addition, the first to third stage inverters 501 to 503 are all composed of the same number (seven) of inverters connected in parallel, and the complementary TFTs constituting these inverters all have channel lengths. Are substantially the same (channel widths differ from stage to stage), so that inverters 511 to 517, 521 to 527, and 531 to 537 are arranged in a matrix in the X direction and the Y direction. Therefore, each inverter can be efficiently arranged in a region extending in the X direction between the shift register circuit 400 (the latch circuit 401 and the phase adjustment circuit 402) and the plurality of image signal lines 115. At the same time, it becomes easy to share the lead-out wiring from the power supply wiring between the inverters at different stages adjacent in the Y direction. For example, in the inverters 511, 521, 531, the lead wiring 601
a and 602a can be shared. Therefore, in the present embodiment, the lead-out wirings 601a and 602a are shared not only between the inverters adjacent to each other in the X direction as described above, but also between the inverters adjacent to each other in the Y direction. It will be used extremely efficiently.

  Furthermore, in this embodiment, the size adjustment of the TFTs constituting each inverter can be performed relatively easily. For example, the channel length can be adjusted by increasing or decreasing the number of inverters connected in parallel in one stage, and the channel width can be adjusted by changing the interval between the shift register circuit 400 and the plurality of image signal lines 115. It is possible by widening. In particular, it is very advantageous in terms of device design that the channel width of the final stage inverter that determines the driving capability of the buffer circuit 500 can be easily adjusted. In addition, since a plurality of inverters for one stage are connected in parallel in the X direction regardless of the size adjustment of the TFT, the driving ability is improved along with the efficient use of the substrate region.

  In the buffer circuit 500 described above, the number of direct inverter stages is three, but it is needless to say that other stages may be used. Similarly, in the above-described buffer circuit 500, the number of parallel inverters in one stage is seven, but it goes without saying that other numbers may be used.

  By the way, as a specific configuration example of the sampling switch 302 constituting the sampling circuit 301, for example, as shown in FIG. 10A, the sampling switch 302 may be configured by an N-channel TFT 302a, or FIG. As shown in FIG. 3, the TFT may be constituted by a P-channel TFT 302b, or the TFTs 302a and 302b may be complementary as shown in FIG. In the configuration shown in FIG. 3, it is assumed that the N-channel TFT 302a shown in FIG. 10A is used. Therefore, when the P-channel TFT is used, the sampling control signal 114a is used. It is necessary to generate the sampling control signal 114b whose level is inverted with respect to the above. Further, in the case where the complementary TFT is used, a signal line for supplying the sampling control signals 114a and 114b is also required.

  Further, each sampling switch 302 constituting the sampling circuit 301 is preferably an N-channel TFT or a P-channel TFT manufactured by a common process with the TFT 30 in the pixel portion, and the complement of both from the viewpoint of manufacturing efficiency and the like. It consists of molds.

  As described above, according to the present embodiment, since the buffer circuit 500 is laid out so as to efficiently use the area of the TFT array substrate 10, the entire liquid crystal device can be reduced in size and the image in the same size device can be obtained. Not only can the display area be increased in size, but also high-quality image display can be achieved in response to high dot frequencies.

<Overall configuration of liquid crystal device>
Next, the overall configuration of the liquid crystal device according to the above-described embodiment will be described with reference to FIGS. 11 and 12. Here, FIG. 11 is a perspective view showing the configuration of the liquid crystal device 100, and FIG. 12 is a cross-sectional view taken along the line AA 'in FIG.

  As shown in these drawings, the liquid crystal device 100 is made of a transparent material such as glass on which pixel electrodes 9a and the like are formed, TFT array substrate 10 made of semiconductor, quartz, and the like, and glass on which counter electrodes 23 and the like are formed. The counter substrate 20 is bonded to the counter substrate 20 with a sealant 52 mixed with spacers SP so that the electrode forming surfaces face each other, and a liquid crystal 50 as an electro-optic material is sealed in the gap. It has a structure. The sealing material 52 is formed along the periphery of the counter substrate 20, but a part thereof is opened to enclose the liquid crystal 50. For this reason, after the liquid crystal 50 is sealed, the opening is sealed with the sealing material SR.

  Here, the data line driving circuit 101 and the sampling circuit 301 (not shown in FIGS. 11 and 12) described above are formed on the opposite surface of the TFT array substrate 10 and on the outer side of the sealing material 52, and the Y direction. The data line 6a extending in the direction is driven. Further, a plurality of external circuit connection terminals 102 are formed on one side, and various signals such as image signals VID1 to VID12 that are serial-parallel converted by the external circuit are input. Further, two scanning line driving circuits 104 are formed on two sides adjacent to the one side, and the scanning line 3a extending in the X direction is driven from both sides. Note that if the delay of the scanning signal supplied to the scanning line 3a does not become a problem, a configuration in which the scanning line driving circuit 104 is formed only on one side may be employed. In addition, in the TFT array substrate 10, in order to reduce the load of writing the image signal to the data line 6a, the precharge for precharging each data line 6a to a predetermined potential at the timing preceding the sampling of the image signal. A circuit may be formed.

  On the other hand, the counter electrode 23 of the counter substrate is electrically connected to the TFT array substrate 10 by a conductive material provided in at least one of the four corners of the bonded portion. In addition, the counter substrate 20 is provided with a color filter arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal device 100, and secondly, for example, chromium. A light shielding film such as resin black in which a metal material such as nickel or nickel, carbon, titanium, or the like is dispersed in a photoresist is provided. In the case of color light modulation, a light shielding film is provided on the counter substrate 20 without forming a color filter. In addition, a backlight for irradiating the liquid crystal device 10 with light as needed is provided on the back side of one of the substrates.

  In addition, the opposing surfaces of the TFT array substrate 10 and the counter substrate 20 are each provided with an alignment film (not shown) that is rubbed in a predetermined direction, and the back surface thereof is polarized according to the alignment direction. Each plate (not shown) is provided. However, if a polymer dispersion type liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 50, the above-described alignment film, polarizing plate, etc. are not required. This is advantageous in terms of reducing power consumption.

  Instead of forming part or all of the peripheral circuits such as the drive circuit 200 on the TFT array substrate 10, for example, a driving IC chip mounted on a film using a TAB (Tape Automated Bonding) technique is used. It may be configured to be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position of the array substrate 10, or the driving IC chip itself may be TFT using COG (Chip On Grass) technology. Although it may be configured to be electrically and mechanically connected to a predetermined position of the array substrate 10 through an anisotropic conductive film, as described above, the effect of the liquid crystal device according to the present embodiment is most apparent. This is a case where the drive circuit 200 is formed on the TFT array substrate 10.

<Others>
In the embodiment, a transparent insulating substrate such as glass is used as the TFT array substrate 10 constituting the liquid crystal device, a silicon thin film is formed on the substrate, and a source, drain, channel is formed on the thin film. In the above description, the TFTs forming the pixel switching elements (TFTs 30) and the TFTs constituting the driving circuit 200 are formed. However, the present invention is not limited to this.

  For example, the TFT array substrate 10 is composed of a semiconductor substrate, and the switching elements of the pixels and the constituent elements of the drive circuit 200 are formed by insulated gate field effect transistors in which the source, drain, and channel are formed on the surface of the semiconductor substrate. You may do it. Thus, when a semiconductor substrate is used as the TFT array substrate 10, it cannot be used as a transmissive type, and therefore, the pixel electrode 9a is formed of aluminum or the like and used as a reflective type. Alternatively, the TFT array substrate 10 may be a transparent substrate, and the pixel electrode 9a may be formed of aluminum or the like to be a reflective type.

  Furthermore, in the above-described embodiment, the switching element of the pixel has been described as a three-terminal element typified by a TFT, but may be configured by a two-terminal element such as a diode. However, when a two-terminal element is used as a pixel switching element, the scanning line 3a is formed on one substrate, the data line 6a is formed on the other substrate, and the two-terminal element is connected to the scanning line 3a or the data line. It is necessary to form between either one of 6a and the pixel electrode 9a. In this case, the pixel includes a pixel electrode 9a to which the two-terminal element is connected, a signal line (one of the data line 6a or the scanning line 3a) formed on the counter substrate 20, and the liquid crystal 50 sandwiched between them. It will be composed of.

  Further, the present invention is not limited to an active matrix liquid crystal device, and can also be applied to a passive type using STN (Super Twisted Nematic) liquid crystal. In this case, the pixel is composed of the scanning line 3a acting as an electrode, the data line 6a also acting as an electrode, and the liquid crystal 50 sandwiched between these electrodes.

  Furthermore, as an electro-optic material, in addition to liquid crystal, an electroluminescence element or the like can be used for a display device that performs display by the electro-optic effect. That is, the present invention can be applied to all electro-optical devices having a configuration similar to that of the liquid crystal device described above.

<Electronic equipment>
Next, the case where the above-described liquid crystal device is applied to various electronic devices will be described. In this case, as shown in FIG. 13, the electronic apparatus mainly includes a display information output source 1000, a display information processing circuit 1002, a drive circuit 1004, a liquid crystal device 100, a clock generation circuit 1008, and a power supply circuit 1010. Has been. Among these, the display information output source 1000 includes a memory such as a ROM (Read Only Memory) and a RAM (Random Access Memory), a storage unit such as an optical disk device, a tuning circuit that tunes and outputs an image signal, and the like. Based on a clock signal from the generation circuit 1008, display information such as an image signal in a predetermined format is output to the display information processing circuit 1002. The display information processing circuit 1002 includes various processing circuits such as the above-described serial-parallel conversion circuit, amplification / polarity inversion circuit, rotation circuit, gamma correction circuit, and clamp circuit. The digital signal is sequentially generated from the display information input based on the above and is output to the drive circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the liquid crystal device 100 and includes an inspection circuit used for inspection after manufacture in addition to the drive circuit 200 described above. The power supply circuit 1010 supplies predetermined power to the above-described circuits.

  Next, some examples in which the above-described liquid crystal device is used in a specific electronic device will be described.

<Part 1: Projector>
First, a projector using the liquid crystal device 100 as a light valve will be described. FIG. 14 is a plan view showing the configuration of the projector. As shown in this figure, a lamp unit 1102 made of a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by three mirrors 1106 and two dichroic mirrors 1108 disposed therein, and light valves 100R, 100G corresponding to the primary colors and 100B, respectively.

  Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal device 100 described above, and is driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). It is. In addition, B light has a long optical path compared to other R colors and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124. Led.

  The light modulated by the light valves 100R, 100G, and 100B is incident on the dichroic prism 1112 from three directions. In the dichroic prism 1112, the R and B light beams are refracted at 90 degrees, while the G light beam goes straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen 1120 via the projection lens 1114.

  Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 1108, it is not necessary to provide a color filter as described above.

<Part 2: Mobile computer>
Next, an example in which this liquid crystal device is applied to a mobile personal computer will be described. FIG. 15 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal device 100 described above.

  In addition to the electronic devices described with reference to FIGS. 14 and 15, the electronic devices include a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, and a word processor. , Workstations, mobile phones, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the liquid crystal device and the electro-optical device according to the embodiments can be applied to these various electronic devices.

It is an equivalent circuit diagram which shows the structure of an image display area | region among the TFT array substrates which comprise the liquid crystal device which concerns on embodiment of this invention. It is a block diagram which shows the structure of the TFT array substrate in the liquid crystal device. 2 is a block diagram illustrating a detailed configuration of a data line driving circuit in the liquid crystal device. FIG. 4 is a timing chart for explaining the operation of the data line driving circuit in the liquid crystal device. 4 is a plan view showing a layout of a data line driving circuit in the liquid crystal device. FIG. 4 is a plan view showing a layout of a buffer circuit in the liquid crystal device. FIG. 2 is a circuit diagram illustrating a detailed configuration of a buffer circuit in the liquid crystal device. FIG. 3 is a block diagram illustrating a detailed configuration of a buffer circuit in the liquid crystal device. FIG. FIG. 3 is a block diagram showing an arrangement of buffer circuits in the liquid crystal device. (1)-(3) is a circuit diagram which shows the switch structure of the sampling circuit in the liquid crystal device, respectively. It is a perspective view which shows the structure of the liquid crystal device. 2 is a partial cross-sectional view for explaining the structure of the liquid crystal device. FIG. It is a block diagram which shows schematic structure of the electronic device to which the liquid crystal device is applied. It is sectional drawing which shows the structure of the projector which is an example of the electronic device to which the liquid crystal device is applied. It is a perspective view which shows the structure of the personal computer which is an example of the electronic device to which the liquid crystal device is applied.

Explanation of symbols

3a ... Scanning line 3b ... Capacitance line 6a ... Data line 9a ... Pixel electrode 10 ... TFT array substrate 20 ... Counter substrate 30 ... TFT
50 ... Liquid crystal 52 ... Sealing material 70 ... Storage capacitor 101 ... Data line driving circuit 104 ... Scanning line driving circuit 114 ... Sampling control signal line 115 ... Image signal line 301 ... Sampling circuit 302 ... Sampling switch 400 ... Shift register circuit 401 ... Latch Circuit 402 ... Phase adjustment circuit 403 ... NAND circuit 500 ... Buffer circuit 501 ... Inverter (first stage)
502 ... Inverter (second stage)
503 ... Inverter (third stage)
601 ... High voltage wiring 602 ... Low voltage wiring

Claims (3)

Electricity for driving an electro-optical device comprising a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines In the drive circuit of the optical device,
The drive circuit is
A shift register circuit;
A phase adjustment circuit that limits a signal width of a transfer signal supplied from the shift register circuit to a predetermined width;
A buffer circuit that outputs the transfer signal, the signal width of which is limited by the phase adjustment circuit, as a sampling control signal;
Have
The buffer circuit is
A plurality of stages constituted by a plurality of logic circuits arranged in a direction intersecting with the extending direction of the data lines and connected in parallel are configured by connecting in series.
A drive circuit of an electro-optical device, wherein a channel width of a transistor constituting the logic circuit is wider than a channel width of a transistor constituting a logic circuit included in a stage preceding the stage including the logic circuit.   An electro-optical device comprising the drive circuit for the electro-optical device according to claim 1. The electro-optical device according to claim 2 is provided.
Electronic equipment characterized by

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